1 /* ppc-dis.c -- Disassemble PowerPC instructions 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <stdio.h> 25 #include "dis-asm.h" 26 #include "elf-bfd.h" 27 #include "elf/ppc.h" 28 #include "opintl.h" 29 #include "opcode/ppc.h" 30 31 /* This file provides several disassembler functions, all of which use 32 the disassembler interface defined in dis-asm.h. Several functions 33 are provided because this file handles disassembly for the PowerPC 34 in both big and little endian mode and also for the POWER (RS/6000) 35 chip. */ 36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, 37 ppc_cpu_t); 38 39 struct dis_private 40 { 41 /* Stash the result of parsing disassembler_options here. */ 42 ppc_cpu_t dialect; 43 } private; 44 45 #define POWERPC_DIALECT(INFO) \ 46 (((struct dis_private *) ((INFO)->private_data))->dialect) 47 48 struct ppc_mopt { 49 const char *opt; 50 ppc_cpu_t cpu; 51 ppc_cpu_t sticky; 52 }; 53 54 struct ppc_mopt ppc_opts[] = { 55 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), 56 0 }, 57 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), 58 0 }, 59 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 60 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 61 0 }, 62 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 63 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 64 0 }, 65 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 66 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), 67 0 }, 68 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), 69 0 }, 70 { "603", (PPC_OPCODE_PPC), 71 0 }, 72 { "604", (PPC_OPCODE_PPC), 73 0 }, 74 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), 75 0 }, 76 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 77 0 }, 78 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 79 0 }, 80 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 81 0 }, 82 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 83 0 }, 84 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) 85 , 0 }, 86 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 87 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 88 | PPC_OPCODE_A2), 89 0 }, 90 { "altivec", (PPC_OPCODE_PPC), 91 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, 92 { "any", 0, 93 PPC_OPCODE_ANY }, 94 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 95 0 }, 96 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 97 0 }, 98 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 99 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), 100 0 }, 101 { "com", (PPC_OPCODE_COMMON), 102 0 }, 103 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), 104 0 }, 105 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 106 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 107 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 108 | PPC_OPCODE_E500), 109 0 }, 110 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 111 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 112 | PPC_OPCODE_E500MC), 113 0 }, 114 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 115 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 116 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 117 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 118 0 }, 119 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 122 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 123 | PPC_OPCODE_POWER7), 124 0 }, 125 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 126 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 127 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 128 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 129 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 130 0 }, 131 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 132 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 133 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 134 | PPC_OPCODE_E500), 135 0 }, 136 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 137 0 }, 138 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 139 0 }, 140 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 141 | PPC_OPCODE_POWER5), 142 0 }, 143 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 144 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 145 0 }, 146 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 147 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 148 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 149 0 }, 150 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 151 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 152 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM 153 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), 154 0 }, 155 { "ppc", (PPC_OPCODE_PPC), 156 0 }, 157 { "ppc32", (PPC_OPCODE_PPC), 158 0 }, 159 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), 160 0 }, 161 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), 162 0 }, 163 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), 164 0 }, 165 { "pwr", (PPC_OPCODE_POWER), 166 0 }, 167 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 168 0 }, 169 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 170 0 }, 171 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 172 | PPC_OPCODE_POWER5), 173 0 }, 174 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 175 | PPC_OPCODE_POWER5), 176 0 }, 177 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 178 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 179 0 }, 180 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 181 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 182 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 183 0 }, 184 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 185 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 186 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM 187 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), 188 0 }, 189 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 190 0 }, 191 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 192 PPC_OPCODE_SPE }, 193 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 194 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 195 0 }, 196 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), 197 PPC_OPCODE_VLE }, 198 { "vsx", (PPC_OPCODE_PPC), 199 PPC_OPCODE_VSX }, 200 { "htm", (PPC_OPCODE_PPC), 201 PPC_OPCODE_HTM }, 202 }; 203 204 /* Switch between Booke and VLE dialects for interlinked dumps. */ 205 static ppc_cpu_t 206 get_powerpc_dialect (struct disassemble_info *info) 207 { 208 ppc_cpu_t dialect = 0; 209 210 dialect = POWERPC_DIALECT (info); 211 212 /* Disassemble according to the section headers flags for VLE-mode. */ 213 if (dialect & PPC_OPCODE_VLE 214 && info->section->owner != NULL 215 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour 216 && elf_object_id (info->section->owner) == PPC32_ELF_DATA 217 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) 218 return dialect; 219 else 220 return dialect & ~ PPC_OPCODE_VLE; 221 } 222 223 /* Handle -m and -M options that set cpu type, and .machine arg. */ 224 225 ppc_cpu_t 226 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) 227 { 228 unsigned int i; 229 230 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 231 if (strcmp (ppc_opts[i].opt, arg) == 0) 232 { 233 if (ppc_opts[i].sticky) 234 { 235 *sticky |= ppc_opts[i].sticky; 236 if ((ppc_cpu & ~*sticky) != 0) 237 break; 238 } 239 ppc_cpu = ppc_opts[i].cpu; 240 break; 241 } 242 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) 243 return 0; 244 245 ppc_cpu |= *sticky; 246 return ppc_cpu; 247 } 248 249 /* Determine which set of machines to disassemble for. */ 250 251 static void 252 powerpc_init_dialect (struct disassemble_info *info) 253 { 254 ppc_cpu_t dialect = 0; 255 ppc_cpu_t sticky = 0; 256 char *arg; 257 struct dis_private *priv = calloc (sizeof (*priv), 1); 258 259 if (priv == NULL) 260 priv = &private; 261 262 switch (info->mach) 263 { 264 case bfd_mach_ppc_403: 265 case bfd_mach_ppc_403gc: 266 dialect = ppc_parse_cpu (dialect, &sticky, "403"); 267 break; 268 case bfd_mach_ppc_405: 269 dialect = ppc_parse_cpu (dialect, &sticky, "405"); 270 break; 271 case bfd_mach_ppc_601: 272 dialect = ppc_parse_cpu (dialect, &sticky, "601"); 273 break; 274 case bfd_mach_ppc_a35: 275 case bfd_mach_ppc_rs64ii: 276 case bfd_mach_ppc_rs64iii: 277 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64; 278 break; 279 case bfd_mach_ppc_e500: 280 dialect = ppc_parse_cpu (dialect, &sticky, "e500"); 281 break; 282 case bfd_mach_ppc_e500mc: 283 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc"); 284 break; 285 case bfd_mach_ppc_e500mc64: 286 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64"); 287 break; 288 case bfd_mach_ppc_e5500: 289 dialect = ppc_parse_cpu (dialect, &sticky, "e5500"); 290 break; 291 case bfd_mach_ppc_e6500: 292 dialect = ppc_parse_cpu (dialect, &sticky, "e6500"); 293 break; 294 case bfd_mach_ppc_titan: 295 dialect = ppc_parse_cpu (dialect, &sticky, "titan"); 296 break; 297 case bfd_mach_ppc_vle: 298 dialect = ppc_parse_cpu (dialect, &sticky, "vle"); 299 break; 300 default: 301 dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY; 302 } 303 304 arg = info->disassembler_options; 305 while (arg != NULL) 306 { 307 ppc_cpu_t new_cpu = 0; 308 char *end = strchr (arg, ','); 309 310 if (end != NULL) 311 *end = 0; 312 313 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0) 314 dialect = new_cpu; 315 else if (strcmp (arg, "32") == 0) 316 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; 317 else if (strcmp (arg, "64") == 0) 318 dialect |= PPC_OPCODE_64; 319 else 320 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); 321 322 if (end != NULL) 323 *end++ = ','; 324 arg = end; 325 } 326 327 info->private_data = priv; 328 POWERPC_DIALECT(info) = dialect; 329 } 330 331 #define PPC_OPCD_SEGS 64 332 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; 333 #define VLE_OPCD_SEGS 32 334 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; 335 336 /* Calculate opcode table indices to speed up disassembly, 337 and init dialect. */ 338 339 void 340 disassemble_init_powerpc (struct disassemble_info *info) 341 { 342 int i; 343 unsigned short last; 344 345 i = powerpc_num_opcodes; 346 while (--i >= 0) 347 { 348 unsigned op = PPC_OP (powerpc_opcodes[i].opcode); 349 350 powerpc_opcd_indices[op] = i; 351 } 352 353 last = powerpc_num_opcodes; 354 for (i = PPC_OPCD_SEGS; i > 0; --i) 355 { 356 if (powerpc_opcd_indices[i] == 0) 357 powerpc_opcd_indices[i] = last; 358 last = powerpc_opcd_indices[i]; 359 } 360 361 i = vle_num_opcodes; 362 while (--i >= 0) 363 { 364 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); 365 unsigned seg = VLE_OP_TO_SEG (op); 366 367 vle_opcd_indices[seg] = i; 368 } 369 370 last = vle_num_opcodes; 371 for (i = VLE_OPCD_SEGS; i > 0; --i) 372 { 373 if (vle_opcd_indices[i] == 0) 374 vle_opcd_indices[i] = last; 375 last = vle_opcd_indices[i]; 376 } 377 378 if (info->arch == bfd_arch_powerpc) 379 powerpc_init_dialect (info); 380 } 381 382 /* Print a big endian PowerPC instruction. */ 383 384 int 385 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 386 { 387 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); 388 } 389 390 /* Print a little endian PowerPC instruction. */ 391 392 int 393 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 394 { 395 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); 396 } 397 398 /* Print a POWER (RS/6000) instruction. */ 399 400 int 401 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) 402 { 403 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); 404 } 405 406 /* Extract the operand value from the PowerPC or POWER instruction. */ 407 408 static long 409 operand_value_powerpc (const struct powerpc_operand *operand, 410 unsigned long insn, ppc_cpu_t dialect) 411 { 412 long value; 413 int invalid; 414 /* Extract the value from the instruction. */ 415 if (operand->extract) 416 value = (*operand->extract) (insn, dialect, &invalid); 417 else 418 { 419 if (operand->shift >= 0) 420 value = (insn >> operand->shift) & operand->bitm; 421 else 422 value = (insn << -operand->shift) & operand->bitm; 423 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 424 { 425 /* BITM is always some number of zeros followed by some 426 number of ones, followed by some number of zeros. */ 427 unsigned long top = operand->bitm; 428 /* top & -top gives the rightmost 1 bit, so this 429 fills in any trailing zeros. */ 430 top |= (top & -top) - 1; 431 top &= ~(top >> 1); 432 value = (value ^ top) - top; 433 } 434 } 435 436 return value; 437 } 438 439 /* Determine whether the optional operand(s) should be printed. */ 440 441 static int 442 skip_optional_operands (const unsigned char *opindex, 443 unsigned long insn, ppc_cpu_t dialect) 444 { 445 const struct powerpc_operand *operand; 446 447 for (; *opindex != 0; opindex++) 448 { 449 operand = &powerpc_operands[*opindex]; 450 if ((operand->flags & PPC_OPERAND_NEXT) != 0 451 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 452 && operand_value_powerpc (operand, insn, dialect) != 0)) 453 return 0; 454 } 455 456 return 1; 457 } 458 459 /* Find a match for INSN in the opcode table, given machine DIALECT. 460 A DIALECT of -1 is special, matching all machine opcode variations. */ 461 462 static const struct powerpc_opcode * 463 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) 464 { 465 const struct powerpc_opcode *opcode; 466 const struct powerpc_opcode *opcode_end; 467 unsigned long op; 468 469 /* Get the major opcode of the instruction. */ 470 op = PPC_OP (insn); 471 472 /* Find the first match in the opcode table for this major opcode. */ 473 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; 474 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; 475 opcode < opcode_end; 476 ++opcode) 477 { 478 const unsigned char *opindex; 479 const struct powerpc_operand *operand; 480 int invalid; 481 482 if ((insn & opcode->mask) != opcode->opcode 483 || (dialect != (ppc_cpu_t) -1 484 && ((opcode->flags & dialect) == 0 485 || (opcode->deprecated & dialect) != 0))) 486 continue; 487 488 /* Check validity of operands. */ 489 invalid = 0; 490 for (opindex = opcode->operands; *opindex != 0; opindex++) 491 { 492 operand = powerpc_operands + *opindex; 493 if (operand->extract) 494 (*operand->extract) (insn, dialect, &invalid); 495 } 496 if (invalid) 497 continue; 498 499 return opcode; 500 } 501 502 return NULL; 503 } 504 505 /* Find a match for INSN in the VLE opcode table. */ 506 507 static const struct powerpc_opcode * 508 lookup_vle (unsigned long insn) 509 { 510 const struct powerpc_opcode *opcode; 511 const struct powerpc_opcode *opcode_end; 512 unsigned op, seg; 513 514 op = PPC_OP (insn); 515 if (op >= 0x20 && op <= 0x37) 516 { 517 /* This insn has a 4-bit opcode. */ 518 op &= 0x3c; 519 } 520 seg = VLE_OP_TO_SEG (op); 521 522 /* Find the first match in the opcode table for this major opcode. */ 523 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; 524 for (opcode = vle_opcodes + vle_opcd_indices[seg]; 525 opcode < opcode_end; 526 ++opcode) 527 { 528 unsigned long table_opcd = opcode->opcode; 529 unsigned long table_mask = opcode->mask; 530 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); 531 unsigned long insn2; 532 const unsigned char *opindex; 533 const struct powerpc_operand *operand; 534 int invalid; 535 536 insn2 = insn; 537 if (table_op_is_short) 538 insn2 >>= 16; 539 if ((insn2 & table_mask) != table_opcd) 540 continue; 541 542 /* Check validity of operands. */ 543 invalid = 0; 544 for (opindex = opcode->operands; *opindex != 0; ++opindex) 545 { 546 operand = powerpc_operands + *opindex; 547 if (operand->extract) 548 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); 549 } 550 if (invalid) 551 continue; 552 553 return opcode; 554 } 555 556 return NULL; 557 } 558 559 /* Print a PowerPC or POWER instruction. */ 560 561 static int 562 print_insn_powerpc (bfd_vma memaddr, 563 struct disassemble_info *info, 564 int bigendian, 565 ppc_cpu_t dialect) 566 { 567 bfd_byte buffer[4]; 568 int status; 569 unsigned long insn; 570 const struct powerpc_opcode *opcode; 571 bfd_boolean insn_is_short; 572 573 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 574 if (status != 0) 575 { 576 /* The final instruction may be a 2-byte VLE insn. */ 577 if ((dialect & PPC_OPCODE_VLE) != 0) 578 { 579 /* Clear buffer so unused bytes will not have garbage in them. */ 580 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; 581 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 582 if (status != 0) 583 { 584 (*info->memory_error_func) (status, memaddr, info); 585 return -1; 586 } 587 } 588 else 589 { 590 (*info->memory_error_func) (status, memaddr, info); 591 return -1; 592 } 593 } 594 595 if (bigendian) 596 insn = bfd_getb32 (buffer); 597 else 598 insn = bfd_getl32 (buffer); 599 600 /* Get the major opcode of the insn. */ 601 opcode = NULL; 602 insn_is_short = FALSE; 603 if ((dialect & PPC_OPCODE_VLE) != 0) 604 { 605 opcode = lookup_vle (insn); 606 if (opcode != NULL) 607 insn_is_short = PPC_OP_SE_VLE(opcode->mask); 608 } 609 if (opcode == NULL) 610 opcode = lookup_powerpc (insn, dialect); 611 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) 612 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); 613 614 if (opcode != NULL) 615 { 616 const unsigned char *opindex; 617 const struct powerpc_operand *operand; 618 int need_comma; 619 int need_paren; 620 int skip_optional; 621 622 if (opcode->operands[0] != 0) 623 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 624 else 625 (*info->fprintf_func) (info->stream, "%s", opcode->name); 626 627 if (insn_is_short) 628 /* The operands will be fetched out of the 16-bit instruction. */ 629 insn >>= 16; 630 631 /* Now extract and print the operands. */ 632 need_comma = 0; 633 need_paren = 0; 634 skip_optional = -1; 635 for (opindex = opcode->operands; *opindex != 0; opindex++) 636 { 637 long value; 638 639 operand = powerpc_operands + *opindex; 640 641 /* Operands that are marked FAKE are simply ignored. We 642 already made sure that the extract function considered 643 the instruction to be valid. */ 644 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 645 continue; 646 647 /* If all of the optional operands have the value zero, 648 then don't print any of them. */ 649 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) 650 { 651 if (skip_optional < 0) 652 skip_optional = skip_optional_operands (opindex, insn, 653 dialect); 654 if (skip_optional) 655 continue; 656 } 657 658 value = operand_value_powerpc (operand, insn, dialect); 659 660 if (need_comma) 661 { 662 (*info->fprintf_func) (info->stream, ","); 663 need_comma = 0; 664 } 665 666 /* Print the operand as directed by the flags. */ 667 if ((operand->flags & PPC_OPERAND_GPR) != 0 668 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 669 (*info->fprintf_func) (info->stream, "r%ld", value); 670 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 671 (*info->fprintf_func) (info->stream, "f%ld", value); 672 else if ((operand->flags & PPC_OPERAND_VR) != 0) 673 (*info->fprintf_func) (info->stream, "v%ld", value); 674 else if ((operand->flags & PPC_OPERAND_VSR) != 0) 675 (*info->fprintf_func) (info->stream, "vs%ld", value); 676 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 677 (*info->print_address_func) (memaddr + value, info); 678 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 679 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 680 else if ((operand->flags & PPC_OPERAND_FSL) != 0) 681 (*info->fprintf_func) (info->stream, "fsl%ld", value); 682 else if ((operand->flags & PPC_OPERAND_FCR) != 0) 683 (*info->fprintf_func) (info->stream, "fcr%ld", value); 684 else if ((operand->flags & PPC_OPERAND_UDI) != 0) 685 (*info->fprintf_func) (info->stream, "%ld", value); 686 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 687 && (((dialect & PPC_OPCODE_PPC) != 0) 688 || ((dialect & PPC_OPCODE_VLE) != 0))) 689 (*info->fprintf_func) (info->stream, "cr%ld", value); 690 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) 691 && (((dialect & PPC_OPCODE_PPC) != 0) 692 || ((dialect & PPC_OPCODE_VLE) != 0))) 693 { 694 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 695 int cr; 696 int cc; 697 698 cr = value >> 2; 699 if (cr != 0) 700 (*info->fprintf_func) (info->stream, "4*cr%d+", cr); 701 cc = value & 3; 702 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); 703 } 704 else 705 (*info->fprintf_func) (info->stream, "%d", (int) value); 706 707 if (need_paren) 708 { 709 (*info->fprintf_func) (info->stream, ")"); 710 need_paren = 0; 711 } 712 713 if ((operand->flags & PPC_OPERAND_PARENS) == 0) 714 need_comma = 1; 715 else 716 { 717 (*info->fprintf_func) (info->stream, "("); 718 need_paren = 1; 719 } 720 } 721 722 /* We have found and printed an instruction. 723 If it was a short VLE instruction we have more to do. */ 724 if (insn_is_short) 725 { 726 memaddr += 2; 727 return 2; 728 } 729 else 730 /* Otherwise, return. */ 731 return 4; 732 } 733 734 /* We could not find a match. */ 735 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); 736 737 return 4; 738 } 739 740 void 741 print_ppc_disassembler_options (FILE *stream) 742 { 743 unsigned int i, col; 744 745 fprintf (stream, _("\n\ 746 The following PPC specific disassembler options are supported for use with\n\ 747 the -M switch:\n")); 748 749 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 750 { 751 col += fprintf (stream, " %s,", ppc_opts[i].opt); 752 if (col > 66) 753 { 754 fprintf (stream, "\n"); 755 col = 0; 756 } 757 } 758 fprintf (stream, " 32, 64\n"); 759 } 760