1 /* ppc-dis.c -- Disassemble PowerPC instructions 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <stdio.h> 25 #include "dis-asm.h" 26 #include "elf-bfd.h" 27 #include "elf/ppc.h" 28 #include "opintl.h" 29 #include "opcode/ppc.h" 30 31 /* This file provides several disassembler functions, all of which use 32 the disassembler interface defined in dis-asm.h. Several functions 33 are provided because this file handles disassembly for the PowerPC 34 in both big and little endian mode and also for the POWER (RS/6000) 35 chip. */ 36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, 37 ppc_cpu_t); 38 39 struct dis_private 40 { 41 /* Stash the result of parsing disassembler_options here. */ 42 ppc_cpu_t dialect; 43 } private; 44 45 #define POWERPC_DIALECT(INFO) \ 46 (((struct dis_private *) ((INFO)->private_data))->dialect) 47 48 struct ppc_mopt { 49 const char *opt; 50 ppc_cpu_t cpu; 51 ppc_cpu_t sticky; 52 }; 53 54 struct ppc_mopt ppc_opts[] = { 55 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), 56 0 }, 57 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), 58 0 }, 59 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 60 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 61 0 }, 62 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 63 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 64 0 }, 65 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 66 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), 67 0 }, 68 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), 69 0 }, 70 { "603", (PPC_OPCODE_PPC), 71 0 }, 72 { "604", (PPC_OPCODE_PPC), 73 0 }, 74 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), 75 0 }, 76 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 77 0 }, 78 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 79 0 }, 80 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 81 0 }, 82 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 83 0 }, 84 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) 85 , 0 }, 86 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 87 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 88 | PPC_OPCODE_A2), 89 0 }, 90 { "altivec", (PPC_OPCODE_PPC), 91 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, 92 { "any", 0, 93 PPC_OPCODE_ANY }, 94 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 95 0 }, 96 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 97 0 }, 98 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 99 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), 100 0 }, 101 { "com", (PPC_OPCODE_COMMON), 102 0 }, 103 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), 104 0 }, 105 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 106 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 107 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 108 | PPC_OPCODE_E500), 109 0 }, 110 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 111 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 112 | PPC_OPCODE_E500MC), 113 0 }, 114 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 115 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 116 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 117 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 118 0 }, 119 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 122 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 123 | PPC_OPCODE_POWER7), 124 0 }, 125 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 126 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 127 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 128 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 129 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 130 0 }, 131 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 132 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 133 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 134 | PPC_OPCODE_E500), 135 0 }, 136 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 137 0 }, 138 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 139 0 }, 140 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 141 | PPC_OPCODE_POWER5), 142 0 }, 143 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 144 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 145 0 }, 146 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 147 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 148 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 149 0 }, 150 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 151 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 152 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM 153 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), 154 0 }, 155 { "ppc", (PPC_OPCODE_PPC), 156 0 }, 157 { "ppc32", (PPC_OPCODE_PPC), 158 0 }, 159 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), 160 0 }, 161 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), 162 0 }, 163 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), 164 0 }, 165 { "pwr", (PPC_OPCODE_POWER), 166 0 }, 167 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 168 0 }, 169 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 170 0 }, 171 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 172 | PPC_OPCODE_POWER5), 173 0 }, 174 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 175 | PPC_OPCODE_POWER5), 176 0 }, 177 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 178 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 179 0 }, 180 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 181 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 182 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 183 0 }, 184 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 185 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 186 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM 187 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX), 188 0 }, 189 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 190 0 }, 191 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 192 PPC_OPCODE_SPE }, 193 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 194 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 195 0 }, 196 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), 197 PPC_OPCODE_VLE }, 198 { "vsx", (PPC_OPCODE_PPC), 199 PPC_OPCODE_VSX }, 200 { "htm", (PPC_OPCODE_PPC), 201 PPC_OPCODE_HTM }, 202 }; 203 204 /* Switch between Booke and VLE dialects for interlinked dumps. */ 205 static ppc_cpu_t 206 get_powerpc_dialect (struct disassemble_info *info) 207 { 208 ppc_cpu_t dialect = 0; 209 210 dialect = POWERPC_DIALECT (info); 211 212 /* Disassemble according to the section headers flags for VLE-mode. */ 213 if (dialect & PPC_OPCODE_VLE 214 && info->section->owner != NULL 215 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour 216 && elf_object_id (info->section->owner) == PPC32_ELF_DATA 217 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) 218 return dialect; 219 else 220 return dialect & ~ PPC_OPCODE_VLE; 221 } 222 223 /* Handle -m and -M options that set cpu type, and .machine arg. */ 224 225 ppc_cpu_t 226 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) 227 { 228 unsigned int i; 229 230 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 231 if (strcmp (ppc_opts[i].opt, arg) == 0) 232 { 233 if (ppc_opts[i].sticky) 234 { 235 *sticky |= ppc_opts[i].sticky; 236 if ((ppc_cpu & ~*sticky) != 0) 237 break; 238 } 239 ppc_cpu = ppc_opts[i].cpu; 240 break; 241 } 242 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) 243 return 0; 244 245 ppc_cpu |= *sticky; 246 return ppc_cpu; 247 } 248 249 /* Determine which set of machines to disassemble for. */ 250 251 static void 252 powerpc_init_dialect (struct disassemble_info *info) 253 { 254 ppc_cpu_t dialect = 0; 255 ppc_cpu_t sticky = 0; 256 char *arg; 257 struct dis_private *priv = calloc (sizeof (*priv), 1); 258 259 if (priv == NULL) 260 priv = &private; 261 262 switch (info->mach) 263 { 264 case bfd_mach_ppc_403: 265 case bfd_mach_ppc_403gc: 266 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403); 267 break; 268 case bfd_mach_ppc_405: 269 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405); 270 break; 271 case bfd_mach_ppc_601: 272 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601); 273 break; 274 case bfd_mach_ppc_a35: 275 case bfd_mach_ppc_rs64ii: 276 case bfd_mach_ppc_rs64iii: 277 dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64); 278 break; 279 case bfd_mach_ppc_e500: 280 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 281 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 282 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 283 | PPC_OPCODE_E500); 284 break; 285 case bfd_mach_ppc_e500mc: 286 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 287 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 288 | PPC_OPCODE_E500MC); 289 break; 290 case bfd_mach_ppc_e500mc64: 291 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 292 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 293 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 294 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); 295 break; 296 case bfd_mach_ppc_e5500: 297 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 298 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 299 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 300 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 301 | PPC_OPCODE_POWER7); 302 break; 303 case bfd_mach_ppc_e6500: 304 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 305 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 306 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 307 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 308 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); 309 break; 310 case bfd_mach_ppc_titan: 311 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 312 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN); 313 break; 314 case bfd_mach_ppc_vle: 315 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE); 316 break; 317 default: 318 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 319 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 320 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX 321 | PPC_OPCODE_ANY); 322 } 323 324 arg = info->disassembler_options; 325 while (arg != NULL) 326 { 327 ppc_cpu_t new_cpu = 0; 328 char *end = strchr (arg, ','); 329 330 if (end != NULL) 331 *end = 0; 332 333 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0) 334 dialect = new_cpu; 335 else if (strcmp (arg, "32") == 0) 336 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; 337 else if (strcmp (arg, "64") == 0) 338 dialect |= PPC_OPCODE_64; 339 else 340 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); 341 342 if (end != NULL) 343 *end++ = ','; 344 arg = end; 345 } 346 347 info->private_data = priv; 348 POWERPC_DIALECT(info) = dialect; 349 } 350 351 #define PPC_OPCD_SEGS 64 352 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; 353 #define VLE_OPCD_SEGS 32 354 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; 355 356 /* Calculate opcode table indices to speed up disassembly, 357 and init dialect. */ 358 359 void 360 disassemble_init_powerpc (struct disassemble_info *info) 361 { 362 int i; 363 unsigned short last; 364 365 i = powerpc_num_opcodes; 366 while (--i >= 0) 367 { 368 unsigned op = PPC_OP (powerpc_opcodes[i].opcode); 369 370 powerpc_opcd_indices[op] = i; 371 } 372 373 last = powerpc_num_opcodes; 374 for (i = PPC_OPCD_SEGS; i > 0; --i) 375 { 376 if (powerpc_opcd_indices[i] == 0) 377 powerpc_opcd_indices[i] = last; 378 last = powerpc_opcd_indices[i]; 379 } 380 381 i = vle_num_opcodes; 382 while (--i >= 0) 383 { 384 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); 385 unsigned seg = VLE_OP_TO_SEG (op); 386 387 vle_opcd_indices[seg] = i; 388 } 389 390 last = vle_num_opcodes; 391 for (i = VLE_OPCD_SEGS; i > 0; --i) 392 { 393 if (vle_opcd_indices[i] == 0) 394 vle_opcd_indices[i] = last; 395 last = vle_opcd_indices[i]; 396 } 397 398 if (info->arch == bfd_arch_powerpc) 399 powerpc_init_dialect (info); 400 } 401 402 /* Print a big endian PowerPC instruction. */ 403 404 int 405 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 406 { 407 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); 408 } 409 410 /* Print a little endian PowerPC instruction. */ 411 412 int 413 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 414 { 415 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); 416 } 417 418 /* Print a POWER (RS/6000) instruction. */ 419 420 int 421 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) 422 { 423 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); 424 } 425 426 /* Extract the operand value from the PowerPC or POWER instruction. */ 427 428 static long 429 operand_value_powerpc (const struct powerpc_operand *operand, 430 unsigned long insn, ppc_cpu_t dialect) 431 { 432 long value; 433 int invalid; 434 /* Extract the value from the instruction. */ 435 if (operand->extract) 436 value = (*operand->extract) (insn, dialect, &invalid); 437 else 438 { 439 if (operand->shift >= 0) 440 value = (insn >> operand->shift) & operand->bitm; 441 else 442 value = (insn << -operand->shift) & operand->bitm; 443 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 444 { 445 /* BITM is always some number of zeros followed by some 446 number of ones, followed by some number of zeros. */ 447 unsigned long top = operand->bitm; 448 /* top & -top gives the rightmost 1 bit, so this 449 fills in any trailing zeros. */ 450 top |= (top & -top) - 1; 451 top &= ~(top >> 1); 452 value = (value ^ top) - top; 453 } 454 } 455 456 return value; 457 } 458 459 /* Determine whether the optional operand(s) should be printed. */ 460 461 static int 462 skip_optional_operands (const unsigned char *opindex, 463 unsigned long insn, ppc_cpu_t dialect) 464 { 465 const struct powerpc_operand *operand; 466 467 for (; *opindex != 0; opindex++) 468 { 469 operand = &powerpc_operands[*opindex]; 470 if ((operand->flags & PPC_OPERAND_NEXT) != 0 471 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 472 && operand_value_powerpc (operand, insn, dialect) != 0)) 473 return 0; 474 } 475 476 return 1; 477 } 478 479 /* Find a match for INSN in the opcode table, given machine DIALECT. 480 A DIALECT of -1 is special, matching all machine opcode variations. */ 481 482 static const struct powerpc_opcode * 483 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) 484 { 485 const struct powerpc_opcode *opcode; 486 const struct powerpc_opcode *opcode_end; 487 unsigned long op; 488 489 /* Get the major opcode of the instruction. */ 490 op = PPC_OP (insn); 491 492 /* Find the first match in the opcode table for this major opcode. */ 493 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; 494 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; 495 opcode < opcode_end; 496 ++opcode) 497 { 498 const unsigned char *opindex; 499 const struct powerpc_operand *operand; 500 int invalid; 501 502 if ((insn & opcode->mask) != opcode->opcode 503 || (dialect != (ppc_cpu_t) -1 504 && ((opcode->flags & dialect) == 0 505 || (opcode->deprecated & dialect) != 0))) 506 continue; 507 508 /* Check validity of operands. */ 509 invalid = 0; 510 for (opindex = opcode->operands; *opindex != 0; opindex++) 511 { 512 operand = powerpc_operands + *opindex; 513 if (operand->extract) 514 (*operand->extract) (insn, dialect, &invalid); 515 } 516 if (invalid) 517 continue; 518 519 return opcode; 520 } 521 522 return NULL; 523 } 524 525 /* Find a match for INSN in the VLE opcode table. */ 526 527 static const struct powerpc_opcode * 528 lookup_vle (unsigned long insn) 529 { 530 const struct powerpc_opcode *opcode; 531 const struct powerpc_opcode *opcode_end; 532 unsigned op, seg; 533 534 op = PPC_OP (insn); 535 if (op >= 0x20 && op <= 0x37) 536 { 537 /* This insn has a 4-bit opcode. */ 538 op &= 0x3c; 539 } 540 seg = VLE_OP_TO_SEG (op); 541 542 /* Find the first match in the opcode table for this major opcode. */ 543 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; 544 for (opcode = vle_opcodes + vle_opcd_indices[seg]; 545 opcode < opcode_end; 546 ++opcode) 547 { 548 unsigned long table_opcd = opcode->opcode; 549 unsigned long table_mask = opcode->mask; 550 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); 551 unsigned long insn2; 552 const unsigned char *opindex; 553 const struct powerpc_operand *operand; 554 int invalid; 555 556 insn2 = insn; 557 if (table_op_is_short) 558 insn2 >>= 16; 559 if ((insn2 & table_mask) != table_opcd) 560 continue; 561 562 /* Check validity of operands. */ 563 invalid = 0; 564 for (opindex = opcode->operands; *opindex != 0; ++opindex) 565 { 566 operand = powerpc_operands + *opindex; 567 if (operand->extract) 568 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); 569 } 570 if (invalid) 571 continue; 572 573 return opcode; 574 } 575 576 return NULL; 577 } 578 579 /* Print a PowerPC or POWER instruction. */ 580 581 static int 582 print_insn_powerpc (bfd_vma memaddr, 583 struct disassemble_info *info, 584 int bigendian, 585 ppc_cpu_t dialect) 586 { 587 bfd_byte buffer[4]; 588 int status; 589 unsigned long insn; 590 const struct powerpc_opcode *opcode; 591 bfd_boolean insn_is_short; 592 593 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 594 if (status != 0) 595 { 596 /* The final instruction may be a 2-byte VLE insn. */ 597 if ((dialect & PPC_OPCODE_VLE) != 0) 598 { 599 /* Clear buffer so unused bytes will not have garbage in them. */ 600 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; 601 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 602 if (status != 0) 603 { 604 (*info->memory_error_func) (status, memaddr, info); 605 return -1; 606 } 607 } 608 else 609 { 610 (*info->memory_error_func) (status, memaddr, info); 611 return -1; 612 } 613 } 614 615 if (bigendian) 616 insn = bfd_getb32 (buffer); 617 else 618 insn = bfd_getl32 (buffer); 619 620 /* Get the major opcode of the insn. */ 621 opcode = NULL; 622 insn_is_short = FALSE; 623 if ((dialect & PPC_OPCODE_VLE) != 0) 624 { 625 opcode = lookup_vle (insn); 626 if (opcode != NULL) 627 insn_is_short = PPC_OP_SE_VLE(opcode->mask); 628 } 629 if (opcode == NULL) 630 opcode = lookup_powerpc (insn, dialect); 631 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) 632 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); 633 634 if (opcode != NULL) 635 { 636 const unsigned char *opindex; 637 const struct powerpc_operand *operand; 638 int need_comma; 639 int need_paren; 640 int skip_optional; 641 642 if (opcode->operands[0] != 0) 643 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 644 else 645 (*info->fprintf_func) (info->stream, "%s", opcode->name); 646 647 if (insn_is_short) 648 /* The operands will be fetched out of the 16-bit instruction. */ 649 insn >>= 16; 650 651 /* Now extract and print the operands. */ 652 need_comma = 0; 653 need_paren = 0; 654 skip_optional = -1; 655 for (opindex = opcode->operands; *opindex != 0; opindex++) 656 { 657 long value; 658 659 operand = powerpc_operands + *opindex; 660 661 /* Operands that are marked FAKE are simply ignored. We 662 already made sure that the extract function considered 663 the instruction to be valid. */ 664 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 665 continue; 666 667 /* If all of the optional operands have the value zero, 668 then don't print any of them. */ 669 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) 670 { 671 if (skip_optional < 0) 672 skip_optional = skip_optional_operands (opindex, insn, 673 dialect); 674 if (skip_optional) 675 continue; 676 } 677 678 value = operand_value_powerpc (operand, insn, dialect); 679 680 if (need_comma) 681 { 682 (*info->fprintf_func) (info->stream, ","); 683 need_comma = 0; 684 } 685 686 /* Print the operand as directed by the flags. */ 687 if ((operand->flags & PPC_OPERAND_GPR) != 0 688 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 689 (*info->fprintf_func) (info->stream, "r%ld", value); 690 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 691 (*info->fprintf_func) (info->stream, "f%ld", value); 692 else if ((operand->flags & PPC_OPERAND_VR) != 0) 693 (*info->fprintf_func) (info->stream, "v%ld", value); 694 else if ((operand->flags & PPC_OPERAND_VSR) != 0) 695 (*info->fprintf_func) (info->stream, "vs%ld", value); 696 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 697 (*info->print_address_func) (memaddr + value, info); 698 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 699 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 700 else if ((operand->flags & PPC_OPERAND_FSL) != 0) 701 (*info->fprintf_func) (info->stream, "fsl%ld", value); 702 else if ((operand->flags & PPC_OPERAND_FCR) != 0) 703 (*info->fprintf_func) (info->stream, "fcr%ld", value); 704 else if ((operand->flags & PPC_OPERAND_UDI) != 0) 705 (*info->fprintf_func) (info->stream, "%ld", value); 706 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 707 && (((dialect & PPC_OPCODE_PPC) != 0) 708 || ((dialect & PPC_OPCODE_VLE) != 0))) 709 (*info->fprintf_func) (info->stream, "cr%ld", value); 710 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) 711 && (((dialect & PPC_OPCODE_PPC) != 0) 712 || ((dialect & PPC_OPCODE_VLE) != 0))) 713 { 714 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 715 int cr; 716 int cc; 717 718 cr = value >> 2; 719 if (cr != 0) 720 (*info->fprintf_func) (info->stream, "4*cr%d+", cr); 721 cc = value & 3; 722 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); 723 } 724 else 725 (*info->fprintf_func) (info->stream, "%d", (int) value); 726 727 if (need_paren) 728 { 729 (*info->fprintf_func) (info->stream, ")"); 730 need_paren = 0; 731 } 732 733 if ((operand->flags & PPC_OPERAND_PARENS) == 0) 734 need_comma = 1; 735 else 736 { 737 (*info->fprintf_func) (info->stream, "("); 738 need_paren = 1; 739 } 740 } 741 742 /* We have found and printed an instruction. 743 If it was a short VLE instruction we have more to do. */ 744 if (insn_is_short) 745 { 746 memaddr += 2; 747 return 2; 748 } 749 else 750 /* Otherwise, return. */ 751 return 4; 752 } 753 754 /* We could not find a match. */ 755 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); 756 757 return 4; 758 } 759 760 void 761 print_ppc_disassembler_options (FILE *stream) 762 { 763 unsigned int i, col; 764 765 fprintf (stream, _("\n\ 766 The following PPC specific disassembler options are supported for use with\n\ 767 the -M switch:\n")); 768 769 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 770 { 771 col += fprintf (stream, " %s,", ppc_opts[i].opt); 772 if (col > 66) 773 { 774 fprintf (stream, "\n"); 775 col = 0; 776 } 777 } 778 fprintf (stream, " 32, 64\n"); 779 } 780