1// i386 register table. 2// Copyright 2007, 2008 3// Free Software Foundation, Inc. 4// 5// This file is part of the GNU opcodes library. 6// 7// This library is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 3, or (at your option) 10// any later version. 11// 12// It is distributed in the hope that it will be useful, but WITHOUT 13// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15// License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with GAS; see the file COPYING. If not, write to the Free 19// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20// 02110-1301, USA. 21 22// Make %st first as we test for it. 23st, FloatReg|FloatAcc, 0, 0, 11, 33 24// 8 bit regs 25al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval 26cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval 27dl, Reg8, 0, 2, Dw2Inval, Dw2Inval 28bl, Reg8, 0, 3, Dw2Inval, Dw2Inval 29ah, Reg8, 0, 4, Dw2Inval, Dw2Inval 30ch, Reg8, 0, 5, Dw2Inval, Dw2Inval 31dh, Reg8, 0, 6, Dw2Inval, Dw2Inval 32bh, Reg8, 0, 7, Dw2Inval, Dw2Inval 33axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval 34cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval 35dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval 36bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval 37spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval 38bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval 39sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval 40dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval 41r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval 42r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval 43r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval 44r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval 45r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval 46r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval 47r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval 48r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval 49// 16 bit regs 50ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval 51cx, Reg16, 0, 1, Dw2Inval, Dw2Inval 52dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval 53bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval 54sp, Reg16, 0, 4, Dw2Inval, Dw2Inval 55bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval 56si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval 57di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval 58r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval 59r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval 60r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval 61r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval 62r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval 63r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval 64r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval 65r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval 66// 32 bit regs 67eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval 68ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval 69edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval 70ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval 71esp, Reg32, 0, 4, 4, Dw2Inval 72ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval 73esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval 74edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval 75r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval 76r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval 77r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval 78r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval 79r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval 80r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval 81r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval 82r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval 83rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 84rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 85rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 86rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 87rsp, Reg64, 0, 4, Dw2Inval, 7 88rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 89rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 90rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 91r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 92r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 93r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 94r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 95r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 96r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 97r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 98r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 99// Segment registers. 100es, SReg2, 0, 0, 40, 50 101cs, SReg2, 0, 1, 41, 51 102ss, SReg2, 0, 2, 42, 52 103ds, SReg2, 0, 3, 43, 53 104fs, SReg3, 0, 4, 44, 54 105gs, SReg3, 0, 5, 45, 55 106flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval 107// Control registers. 108cr0, Control, 0, 0, Dw2Inval, Dw2Inval 109cr1, Control, 0, 1, Dw2Inval, Dw2Inval 110cr2, Control, 0, 2, Dw2Inval, Dw2Inval 111cr3, Control, 0, 3, Dw2Inval, Dw2Inval 112cr4, Control, 0, 4, Dw2Inval, Dw2Inval 113cr5, Control, 0, 5, Dw2Inval, Dw2Inval 114cr6, Control, 0, 6, Dw2Inval, Dw2Inval 115cr7, Control, 0, 7, Dw2Inval, Dw2Inval 116cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval 117cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval 118cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval 119cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval 120cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval 121cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval 122cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval 123cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval 124// Debug registers. 125db0, Debug, 0, 0, Dw2Inval, Dw2Inval 126db1, Debug, 0, 1, Dw2Inval, Dw2Inval 127db2, Debug, 0, 2, Dw2Inval, Dw2Inval 128db3, Debug, 0, 3, Dw2Inval, Dw2Inval 129db4, Debug, 0, 4, Dw2Inval, Dw2Inval 130db5, Debug, 0, 5, Dw2Inval, Dw2Inval 131db6, Debug, 0, 6, Dw2Inval, Dw2Inval 132db7, Debug, 0, 7, Dw2Inval, Dw2Inval 133db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval 134db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval 135db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval 136db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval 137db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval 138db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval 139db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval 140db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval 141dr0, Debug, 0, 0, Dw2Inval, Dw2Inval 142dr1, Debug, 0, 1, Dw2Inval, Dw2Inval 143dr2, Debug, 0, 2, Dw2Inval, Dw2Inval 144dr3, Debug, 0, 3, Dw2Inval, Dw2Inval 145dr4, Debug, 0, 4, Dw2Inval, Dw2Inval 146dr5, Debug, 0, 5, Dw2Inval, Dw2Inval 147dr6, Debug, 0, 6, Dw2Inval, Dw2Inval 148dr7, Debug, 0, 7, Dw2Inval, Dw2Inval 149dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval 150dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval 151dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval 152dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval 153dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval 154dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval 155dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval 156dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval 157// Test registers. 158tr0, Test, 0, 0, Dw2Inval, Dw2Inval 159tr1, Test, 0, 1, Dw2Inval, Dw2Inval 160tr2, Test, 0, 2, Dw2Inval, Dw2Inval 161tr3, Test, 0, 3, Dw2Inval, Dw2Inval 162tr4, Test, 0, 4, Dw2Inval, Dw2Inval 163tr5, Test, 0, 5, Dw2Inval, Dw2Inval 164tr6, Test, 0, 6, Dw2Inval, Dw2Inval 165tr7, Test, 0, 7, Dw2Inval, Dw2Inval 166// MMX and simd registers. 167mm0, RegMMX, 0, 0, 29, 41 168mm1, RegMMX, 0, 1, 30, 42 169mm2, RegMMX, 0, 2, 31, 43 170mm3, RegMMX, 0, 3, 32, 44 171mm4, RegMMX, 0, 4, 33, 45 172mm5, RegMMX, 0, 5, 34, 46 173mm6, RegMMX, 0, 6, 35, 47 174mm7, RegMMX, 0, 7, 36, 48 175xmm0, RegXMM, 0, 0, 21, 17 176xmm1, RegXMM, 0, 1, 22, 18 177xmm2, RegXMM, 0, 2, 23, 19 178xmm3, RegXMM, 0, 3, 24, 20 179xmm4, RegXMM, 0, 4, 25, 21 180xmm5, RegXMM, 0, 5, 26, 22 181xmm6, RegXMM, 0, 6, 27, 23 182xmm7, RegXMM, 0, 7, 28, 24 183xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 184xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 185xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 186xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 187xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 188xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 189xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 190xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 191// AVX registers. 192ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval 193ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval 194ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval 195ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval 196ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval 197ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval 198ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval 199ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval 200ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval 201ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval 202ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval 203ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval 204ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval 205ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval 206ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval 207ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval 208// No type will make these registers rejected for all purposes except 209// for addressing. This saves creating one extra type for RIP/EIP. 210rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 211eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval 212// No type will make these registers rejected for all purposes except 213// for addressing. 214eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval 215riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval 216// fp regs. 217st(0), FloatReg|FloatAcc, 0, 0, 11, 33 218st(1), FloatReg, 0, 1, 12, 34 219st(2), FloatReg, 0, 2, 13, 35 220st(3), FloatReg, 0, 3, 14, 36 221st(4), FloatReg, 0, 4, 15, 37 222st(5), FloatReg, 0, 5, 16, 38 223st(6), FloatReg, 0, 6, 17, 39 224st(7), FloatReg, 0, 7, 18, 40 225// Pseudo-register names only used in .cfi_* directives 226eflags, 0, 0, 0, 9, 49 227rflags, 0, 0, 0, Dw2Inval, 49 228fs.base, 0, 0, 0, Dw2Inval, 58 229gs.base, 0, 0, 0, Dw2Inval, 59 230tr, 0, 0, 0, 48, 62 231ldtr, 0, 0, 0, 49, 63 232// st0...7 for backward compatibility 233st0, 0, 0, 0, 11, 33 234st1, 0, 0, 1, 12, 34 235st2, 0, 0, 2, 13, 35 236st3, 0, 0, 3, 14, 36 237st4, 0, 0, 4, 15, 37 238st5, 0, 0, 5, 16, 38 239st6, 0, 0, 6, 17, 39 240st7, 0, 0, 7, 18, 40 241fcw, 0, 0, 0, 37, 65 242fsw, 0, 0, 0, 38, 66 243mxcsr, 0, 0, 0, 39, 64 244