12016-09-16 Peter Bergner <bergner@vnet.ibm.com> 2 3 Apply from master. 4 2016-09-14 Peter Bergner <bergner@vnet.ibm.com> 5 6 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. 7 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, 8 xor3>: Delete mnemonics. 9 <cp_abort>: Rename mnemonic from ... 10 <cpabort>: ...to this. 11 <setb>: Change to a X form instruction. 12 <sync>: Change to 1 operand form. 13 <copy>: Delete mnemonic. 14 <copy_first>: Rename mnemonic from ... 15 <copy>: ...to this. 16 <paste, paste.>: Delete mnemonics. 17 <paste_last>: Rename mnemonic from ... 18 <paste.>: ...to this. 19 202016-07-27 Maciej W. Rozycki <macro@imgtec.com> 21 22 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", 23 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to 24 "j". 25 262016-07-27 Graham Markall <graham.markall@embecosm.com> 27 28 * arc-nps400-tbl.h: Change block comments to GNU format. 29 * arc-dis.c: Add new globals addrtypenames, 30 addrtypenames_max, and addtypeunknown. 31 (get_addrtype): New function. 32 (print_insn_arc): Print colons and address types when 33 required. 34 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to 35 define insert and extract functions for all address types. 36 (arc_operands): Add operands for colon and all address 37 types. 38 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. 39 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, 40 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. 41 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. 42 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, 43 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. 44 452016-07-21 H.J. Lu <hongjiu.lu@intel.com> 46 47 * configure: Regenerated. 48 492016-07-20 Claudiu Zissulescu <claziss@synopsys.com> 50 51 * arc-dis.c (skipclass): New structure. 52 (decodelist): New variable. 53 (is_compatible_p): New function. 54 (new_element): Likewise. 55 (skip_class_p): Likewise. 56 (find_format_from_table): Use skip_class_p function. 57 (find_format): Decode first the extension instructions. 58 (print_insn_arc): Select either ARCEM or ARCHS based on elf 59 e_flags. 60 (parse_option): New function. 61 (parse_disassembler_options): Likewise. 62 (print_arc_disassembler_options): Likewise. 63 (print_insn_arc): Use parse_disassembler_options function. Proper 64 select ARCv2 cpu variant. 65 * disassemble.c (disassembler_usage): Add ARC disassembler 66 options. 67 682016-07-13 Maciej W. Rozycki <macro@imgtec.com> 69 70 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS 71 annotation from the "nal" entry and reorder it beyond "bltzal". 72 732016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> 74 75 * sparc-opc.c (ldtxa): New macro. 76 (sparc_opcodes): Use the macro defined above to add entries for 77 the LDTXA instructions. 78 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA 79 instruction. 80 812016-07-07 James Bowman <james.bowman@ftdichip.com> 82 83 * ft32-opc.c (ft32_opc_info): Correct mask for "callc" 84 and "jmpc". 85 862016-07-01 Jan Beulich <jbeulich@suse.com> 87 88 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove. 89 (movzb): Adjust to cover all permitted suffixes. 90 (movzw): New. 91 * i386-tbl.h: Re-generate. 92 932016-07-01 Jan Beulich <jbeulich@suse.com> 94 95 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant. 96 (lgdt): Remove Tbyte from non-64-bit variant. 97 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64, 98 xsaves64, xsavec64): Remove Disp16. 99 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd): 100 Remove Disp32S from non-64-bit variants. Remove Disp16 from 101 64-bit variants. 102 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd, 103 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi, 104 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from 105 64-bit variants. 106 * i386-tbl.h: Re-generate. 107 1082016-07-01 Jan Beulich <jbeulich@suse.com> 109 110 * i386-opc.tbl (xlat): Remove RepPrefixOk. 111 * i386-tbl.h: Re-generate. 112 1132016-06-30 Yao Qi <yao.qi@linaro.org> 114 115 * arm-dis.c (print_insn): Fix typo in comment. 116 1172016-06-28 Richard Sandiford <richard.sandiford@arm.com> 118 119 * aarch64-opc.c (operand_general_constraint_met_p): Check the 120 range of ldst_elemlist operands. 121 (print_register_list): Use PRIi64 to print the index. 122 (aarch64_print_operand): Likewise. 123 1242016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 125 126 * mcore-opc.h: Remove sentinal. 127 * mcore-dis.c (print_insn_mcore): Adjust. 128 1292016-06-23 Graham Markall <graham.markall@embecosm.com> 130 131 * arc-opc.c: Correct description of availability of NPS400 132 features. 133 1342016-06-22 Peter Bergner <bergner@vnet.ibm.com> 135 136 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. 137 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, 138 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, 139 xor3>: New mnemonics. 140 <setb>: Change to a VX form instruction. 141 (insert_sh6): Add support for rldixor. 142 (extract_sh6): Likewise. 143 1442016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 145 146 * arc-ext.h: Wrap in extern C. 147 1482016-06-21 Graham Markall <graham.markall@embecosm.com> 149 150 * arc-dis.c (arc_insn_length): Add comment on instruction length. 151 Use same method for determining instruction length on ARC700 and 152 NPS-400. 153 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. 154 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions 155 with the NPS400 subclass. 156 * arc-opc.c: Likewise. 157 1582016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 159 160 * sparc-opc.c (rdasr): New macro. 161 (wrasr): Likewise. 162 (rdpr): Likewise. 163 (wrpr): Likewise. 164 (rdhpr): Likewise. 165 (wrhpr): Likewise. 166 (sparc_opcodes): Use the macros above to fix and expand the 167 definition of read/write instructions from/to 168 asr/privileged/hyperprivileged instructions. 169 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and 170 %hva_mask_nz. Prefer softint_set and softint_clear over 171 set_softint and clear_softint. 172 (print_insn_sparc): Support %ver in Rd. 173 1742016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 175 176 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode 177 architecture according to the hardware capabilities they require. 178 1792016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 180 181 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. 182 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and 183 bfd_mach_sparc_v9{c,d,e,v,m}. 184 * sparc-opc.c (MASK_V9C): Define. 185 (MASK_V9D): Likewise. 186 (MASK_V9E): Likewise. 187 (MASK_V9V): Likewise. 188 (MASK_V9M): Likewise. 189 (v6): Add MASK_V9{C,D,E,V,M}. 190 (v6notlet): Likewise. 191 (v7): Likewise. 192 (v8): Likewise. 193 (v9): Likewise. 194 (v9andleon): Likewise. 195 (v9a): Likewise. 196 (v9b): Likewise. 197 (v9c): Define. 198 (v9d): Likewise. 199 (v9e): Likewise. 200 (v9v): Likewise. 201 (v9m): Likewise. 202 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}. 203 2042016-06-15 Nick Clifton <nickc@redhat.com> 205 206 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer 207 constants to match expected behaviour. 208 (nds32_parse_opcode): Likewise. Also for whitespace. 209 2102016-06-15 Andrew Burgess <andrew.burgess@embecosm.com> 211 212 * arc-opc.c (extract_rhv1): Extract value from insn. 213 2142016-06-14 Graham Markall <graham.markall@embecosm.com> 215 216 * arc-nps400-tbl.h: Add ldbit instruction. 217 * arc-opc.c: Add flag classes required for ldbit. 218 2192016-06-14 Graham Markall <graham.markall@embecosm.com> 220 221 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf 222 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 223 support the above instructions. 224 2252016-06-14 Graham Markall <graham.markall@embecosm.com> 226 227 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, 228 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, 229 csma, cbba, zncv, and hofs. 230 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 231 support the above instructions. 232 2332016-06-06 Graham Markall <graham.markall@embecosm.com> 234 235 * arc-nps400-tbl.h: Add andab and orab instructions. 236 2372016-06-06 Graham Markall <graham.markall@embecosm.com> 238 239 * arc-nps400-tbl.h: Add addl-like instructions. 240 2412016-06-06 Graham Markall <graham.markall@embecosm.com> 242 243 * arc-nps400-tbl.h: Add mxb and imxb instructions. 244 2452016-06-06 Graham Markall <graham.markall@embecosm.com> 246 247 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey 248 instructions. 249 2502016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 251 252 * s390-dis.c (option_use_insn_len_bits_p): New file scope 253 variable. 254 (init_disasm): Handle new command line option "insnlength". 255 (print_s390_disassembler_options): Mention new option in help 256 output. 257 (print_insn_s390): Use the encoded insn length when dumping 258 unknown instructions. 259 2602016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com> 261 262 * avr-dis.c (avr_operand): Add default data address space origin (0x800000) 263 to the address and set as symbol address for LDS/ STS immediate operands. 264 2652016-06-07 Alan Modra <amodra@gmail.com> 266 267 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default 268 cpu for "vle" to e500. 269 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. 270 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. 271 (PPCNONE): Delete, substitute throughout. 272 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" 273 except for major opcode 4 and 31. 274 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. 275 2762016-06-07 Matthew Wahab <matthew.wahab@arm.com> 277 278 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with 279 ARM_EXT_RAS in relevant entries. 280 2812016-06-03 Peter Bergner <bergner@vnet.ibm.com> 282 283 PR binutils/20196 284 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable 285 opcodes for E6500. 286 2872016-06-03 H.J. Lu <hongjiu.lu@intel.com> 288 289 PR binutis/18386 290 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. 291 (indir_v_mode): New. 292 Add comments for '&'. 293 (reg_table): Replace "{T|}" with "{&|}" on call and jmp. 294 (putop): Handle '&'. 295 (intel_operand_size): Handle indir_v_mode. 296 (OP_E_register): Likewise. 297 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 298 64-bit indirect call/jmp for AMD64. 299 * i386-tbl.h: Regenerated 300 3012016-06-02 Andrew Burgess <andrew.burgess@embecosm.com> 302 303 * arc-dis.c (struct arc_operand_iterator): New structure. 304 (find_format_from_table): All the old content from find_format, 305 with some minor adjustments, and parameter renaming. 306 (find_format_long_instructions): New function. 307 (find_format): Rewritten. 308 (arc_insn_length): Add LSB parameter. 309 (extract_operand_value): New function. 310 (operand_iterator_next): New function. 311 (print_insn_arc): Use new functions to find opcode, and iterator 312 over operands. 313 * arc-opc.c (insert_nps_3bit_dst_short): New function. 314 (extract_nps_3bit_dst_short): New function. 315 (insert_nps_3bit_src2_short): New function. 316 (extract_nps_3bit_src2_short): New function. 317 (insert_nps_bitop1_size): New function. 318 (extract_nps_bitop1_size): New function. 319 (insert_nps_bitop2_size): New function. 320 (extract_nps_bitop2_size): New function. 321 (insert_nps_bitop_mod4_msb): New function. 322 (extract_nps_bitop_mod4_msb): New function. 323 (insert_nps_bitop_mod4_lsb): New function. 324 (extract_nps_bitop_mod4_lsb): New function. 325 (insert_nps_bitop_dst_pos3_pos4): New function. 326 (extract_nps_bitop_dst_pos3_pos4): New function. 327 (insert_nps_bitop_ins_ext): New function. 328 (extract_nps_bitop_ins_ext): New function. 329 (arc_operands): Add new operands. 330 (arc_long_opcodes): New global array. 331 (arc_num_long_opcodes): New global. 332 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. 333 3342016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 335 336 * nds32-asm.h: Add extern "C". 337 * sh-opc.h: Likewise. 338 3392016-06-01 Graham Markall <graham.markall@embecosm.com> 340 341 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and 342 0,b,limm to the rflt instruction. 343 3442016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 345 346 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned 347 constant. 348 3492016-05-29 H.J. Lu <hongjiu.lu@intel.com> 350 351 PR gas/20145 352 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, 353 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, 354 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, 355 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, 356 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. 357 * i386-init.h: Regenerated. 358 3592016-05-27 H.J. Lu <hongjiu.lu@intel.com> 360 361 PR gas/20145 362 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove 363 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from 364 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. 365 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and 366 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from 367 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, 368 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. 369 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, 370 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, 371 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, 372 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX 373 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable 374 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and 375 CpuRegMask for AVX512. 376 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM 377 and CpuRegMask. 378 (set_bitfield_from_cpu_flag_init): New function. 379 (set_bitfield): Remove const on f. Call 380 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. 381 * i386-opc.h (CpuRegMMX): New. 382 (CpuRegXMM): Likewise. 383 (CpuRegYMM): Likewise. 384 (CpuRegZMM): Likewise. 385 (CpuRegMask): Likewise. 386 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm 387 and cpuregmask. 388 * i386-init.h: Regenerated. 389 * i386-tbl.h: Likewise. 390 3912016-05-27 H.J. Lu <hongjiu.lu@intel.com> 392 393 PR gas/20154 394 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. 395 (opcode_modifiers): Add AMD64 and Intel64. 396 (main): Properly verify CpuMax. 397 * i386-opc.h (CpuAMD64): Removed. 398 (CpuIntel64): Likewise. 399 (CpuMax): Set to CpuNo64. 400 (i386_cpu_flags): Remove cpuamd64 and cpuintel64. 401 (AMD64): New. 402 (Intel64): Likewise. 403 (i386_opcode_modifier): Add amd64 and intel64. 404 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 405 on call and jmp. 406 * i386-init.h: Regenerated. 407 * i386-tbl.h: Likewise. 408 4092016-05-27 H.J. Lu <hongjiu.lu@intel.com> 410 411 PR gas/20154 412 * i386-gen.c (main): Fail if CpuMax is incorrect. 413 * i386-opc.h (CpuMax): Set to CpuIntel64. 414 * i386-tbl.h: Regenerated. 415 4162016-05-27 Nick Clifton <nickc@redhat.com> 417 418 PR target/20150 419 * msp430-dis.c (msp430dis_read_two_bytes): New function. 420 (msp430dis_opcode_unsigned): New function. 421 (msp430dis_opcode_signed): New function. 422 (msp430_singleoperand): Use the new opcode reading functions. 423 Only disassenmble bytes if they were successfully read. 424 (msp430_doubleoperand): Likewise. 425 (msp430_branchinstr): Likewise. 426 (msp430x_callx_instr): Likewise. 427 (print_insn_msp430): Check that it is safe to read bytes before 428 attempting disassembly. Use the new opcode reading functions. 429 4302016-05-26 Peter Bergner <bergner@vnet.ibm.com> 431 432 * ppc-opc.c (CY): New define. Document it. 433 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. 434 4352016-05-25 H.J. Lu <hongjiu.lu@intel.com> 436 437 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, 438 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS 439 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, 440 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to 441 CPU_ANY_AVX_FLAGS. 442 * i386-init.h: Regenerated. 443 4442016-05-25 H.J. Lu <hongjiu.lu@intel.com> 445 446 PR gas/20141 447 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, 448 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. 449 * i386-init.h: Regenerated. 450 4512016-05-25 H.J. Lu <hongjiu.lu@intel.com> 452 453 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to 454 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. 455 * i386-init.h: Regenerated. 456 4572016-05-23 Claudiu Zissulescu <claziss@synopsys.com> 458 459 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type 460 information. 461 (print_insn_arc): Set insn_type information. 462 * arc-opc.c (C_CC): Add F_CLASS_COND. 463 * arc-tbl.h (bbit0, bbit1): Update subclass to COND. 464 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. 465 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. 466 (breq, breq_s, brge, brhs, brlo, brlt): Likewise. 467 (brne, brne_s, jeq_s, jne_s): Likewise. 468 4692016-05-23 Claudiu Zissulescu <claziss@synopsys.com> 470 471 * arc-tbl.h (neg): New instruction variant. 472 4732016-05-23 Cupertino Miranda <cmiranda@synopsys.com> 474 475 * arc-dis.c (find_format, find_format, get_auxreg) 476 (print_insn_arc): Changed. 477 * arc-ext.h (INSERT_XOP): Likewise. 478 4792016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 480 481 * tic54x-dis.c (sprint_mmr): Adjust. 482 * tic54x-opc.c: Likewise. 483 4842016-05-19 Alan Modra <amodra@gmail.com> 485 486 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. 487 4882016-05-19 Alan Modra <amodra@gmail.com> 489 490 * ppc-opc.c: Formatting. 491 (NSISIGNOPT): Define. 492 (powerpc_opcodes <subis>): Use NSISIGNOPT. 493 4942016-05-18 Maciej W. Rozycki <macro@imgtec.com> 495 496 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, 497 replacing references to `micromips_ase' throughout. 498 (_print_insn_mips): Don't use file-level microMIPS annotation to 499 determine the disassembly mode with the symbol table. 500 5012016-05-13 Peter Bergner <bergner@vnet.ibm.com> 502 503 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. 504 5052016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> 506 507 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and 508 mips64r6. 509 * mips-opc.c (D34): New macro. 510 (mips_builtin_opcodes): Define bposge32c for DSPr3. 511 5122016-05-10 Alexander Fomin <alexander.fomin@intel.com> 513 514 * i386-dis.c (prefix_table): Add RDPID instruction. 515 * i386-gen.c (cpu_flag_init): Add RDPID flag. 516 (cpu_flags): Add RDPID bitfield. 517 * i386-opc.h (enum): Add RDPID element. 518 (i386_cpu_flags): Add RDPID field. 519 * i386-opc.tbl: Add RDPID instruction. 520 * i386-init.h: Regenerate. 521 * i386-tbl.h: Regenerate. 522 5232016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> 524 525 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get 526 branch type of a symbol. 527 (print_insn): Likewise. 528 5292016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> 530 531 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M 532 Mainline Security Extensions instructions. 533 (thumb_opcodes): Add entries for narrow ARMv8-M Security 534 Extensions instructions. 535 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions 536 instructions. 537 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions 538 special registers. 539 5402016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> 541 542 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. 543 5442016-05-03 Claudiu Zissulescu <claziss@synopsys.com> 545 546 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. 547 (arcExtMap_genOpcode): Likewise. 548 * arc-opc.c (arg_32bit_rc): Define new variable. 549 (arg_32bit_u6): Likewise. 550 (arg_32bit_limm): Likewise. 551 5522016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com> 553 554 * aarch64-gen.c (VERIFIER): Define. 555 * aarch64-opc.c (VERIFIER): Define. 556 (verify_ldpsw): Use static linkage. 557 * aarch64-opc.h (verify_ldpsw): Remove. 558 * aarch64-tbl.h: Use VERIFIER for verifiers. 559 5602016-04-28 Nick Clifton <nickc@redhat.com> 561 562 PR target/19722 563 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. 564 * aarch64-opc.c (verify_ldpsw): New function. 565 * aarch64-opc.h (verify_ldpsw): New prototype. 566 * aarch64-tbl.h: Add initialiser for verifier field. 567 (LDPSW): Set verifier to verify_ldpsw. 568 5692016-04-23 H.J. Lu <hongjiu.lu@intel.com> 570 571 PR binutils/19983 572 PR binutils/19984 573 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is 574 smaller than address size. 575 5762016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 577 578 * alpha-dis.c: Regenerate. 579 * crx-dis.c: Likewise. 580 * disassemble.c: Likewise. 581 * epiphany-opc.c: Likewise. 582 * fr30-opc.c: Likewise. 583 * frv-opc.c: Likewise. 584 * ip2k-opc.c: Likewise. 585 * iq2000-opc.c: Likewise. 586 * lm32-opc.c: Likewise. 587 * lm32-opinst.c: Likewise. 588 * m32c-opc.c: Likewise. 589 * m32r-opc.c: Likewise. 590 * m32r-opinst.c: Likewise. 591 * mep-opc.c: Likewise. 592 * mt-opc.c: Likewise. 593 * or1k-opc.c: Likewise. 594 * or1k-opinst.c: Likewise. 595 * tic80-opc.c: Likewise. 596 * xc16x-opc.c: Likewise. 597 * xstormy16-opc.c: Likewise. 598 5992016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> 600 601 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, 602 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, 603 calcsd, and calcxd instructions. 604 * arc-opc.c (insert_nps_bitop_size): Delete. 605 (extract_nps_bitop_size): Delete. 606 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. 607 (extract_nps_qcmp_m3): Define. 608 (extract_nps_qcmp_m2): Define. 609 (extract_nps_qcmp_m1): Define. 610 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. 611 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL 612 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, 613 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, 614 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and 615 NPS_QCMP_M3. 616 6172016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> 618 619 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions. 620 6212016-04-15 H.J. Lu <hongjiu.lu@intel.com> 622 623 * Makefile.in: Regenerated with automake 1.11.6. 624 * aclocal.m4: Likewise. 625 6262016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> 627 628 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst 629 instructions. 630 * arc-opc.c (insert_nps_cmem_uimm16): New function. 631 (extract_nps_cmem_uimm16): New function. 632 (arc_operands): Add NPS_XLDST_UIMM16 operand. 633 6342016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> 635 636 * arc-dis.c (arc_insn_length): New function. 637 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned. 638 (find_format): Change insnLen parameter to unsigned. 639 6402016-04-13 Nick Clifton <nickc@redhat.com> 641 642 PR target/19937 643 * v850-opc.c (v850_opcodes): Correct masks for long versions of 644 the LD.B and LD.BU instructions. 645 6462016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 647 648 * arc-dis.c (find_format): Check for extension flags. 649 (print_flags): New function. 650 (print_insn_arc): Update for .extCondCode, .extCoreRegister and 651 .extAuxRegister. 652 * arc-ext.c (arcExtMap_coreRegName): Use 653 LAST_EXTENSION_CORE_REGISTER. 654 (arcExtMap_coreReadWrite): Likewise. 655 (dump_ARC_extmap): Update printing. 656 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. 657 (arc_aux_regs): Add cpu field. 658 * arc-regs.h: Add cpu field, lower case name aux registers. 659 6602016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 661 662 * arc-tbl.h: Add rtsc, sleep with no arguments. 663 6642016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 665 666 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): 667 Initialize. 668 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) 669 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) 670 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) 671 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) 672 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) 673 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) 674 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) 675 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) 676 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. 677 (arc_opcode arc_opcodes): Null terminate the array. 678 (arc_num_opcodes): Remove. 679 * arc-ext.h (INSERT_XOP): Define. 680 (extInstruction_t): Likewise. 681 (arcExtMap_instName): Delete. 682 (arcExtMap_insn): New function. 683 (arcExtMap_genOpcode): Likewise. 684 * arc-ext.c (ExtInstruction): Remove. 685 (create_map): Zero initialize instruction fields. 686 (arcExtMap_instName): Remove. 687 (arcExtMap_insn): New function. 688 (dump_ARC_extmap): More info while debuging. 689 (arcExtMap_genOpcode): New function. 690 * arc-dis.c (find_format): New function. 691 (print_insn_arc): Use find_format. 692 (arc_get_disassembler): Enable dump_ARC_extmap only when 693 debugging. 694 6952016-04-11 Maciej W. Rozycki <macro@imgtec.com> 696 697 * mips-dis.c (print_mips16_insn_arg): Mask unused extended 698 instruction bits out. 699 7002016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> 701 702 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. 703 * arc-opc.c (arc_flag_operands): Add new flags. 704 (arc_flag_classes): Add new classes. 705 7062016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> 707 708 * arc-opc.c (arc_opcodes): Extend comment to discus table layout. 709 7102016-04-05 Andrew Burgess <andrew.burgess@embecosm.com> 711 712 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, 713 encode1, rflt, crc16, and crc32 instructions. 714 * arc-opc.c (arc_flag_operands): Add F_NPS_R. 715 (arc_flag_classes): Add C_NPS_R. 716 (insert_nps_bitop_size_2b): New function. 717 (extract_nps_bitop_size_2b): Likewise. 718 (insert_nps_bitop_uimm8): Likewise. 719 (extract_nps_bitop_uimm8): Likewise. 720 (arc_operands): Add new operand entries. 721 7222016-04-05 Claudiu Zissulescu <claziss@synopsys.com> 723 724 * arc-regs.h: Add a new subclass field. Add double assist 725 accumulator register values. 726 * arc-tbl.h: Use DPA subclass to mark the double assist 727 instructions. Use DPX/SPX subclas to mark the FPX instructions. 728 * arc-opc.c (RSP): Define instead of SP. 729 (arc_aux_regs): Add the subclass field. 730 7312016-04-05 Jiong Wang <jiong.wang@arm.com> 732 733 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar). 734 7352016-03-31 Andrew Burgess <andrew.burgess@embecosm.com> 736 737 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and 738 NPS_R_SRC1. 739 7402016-03-30 Andrew Burgess <andrew.burgess@embecosm.com> 741 742 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace 743 issues. No functional changes. 744 7452016-03-30 Claudiu Zissulescu <claziss@synopsys.com> 746 747 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) 748 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1) 749 (RTT): Remove duplicate. 750 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*) 751 (PCT_CONFIG*): Remove. 752 (D1L, D1H, D2H, D2L): Define. 753 7542016-03-29 Claudiu Zissulescu <claziss@synopsys.com> 755 756 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo. 757 7582016-03-29 Claudiu Zissulescu <claziss@synopsys.com> 759 760 * arc-tbl.h (invld07): Remove. 761 * arc-ext-tbl.h: New file. 762 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. 763 * arc-opc.c (arc_opcodes): Add ext-tbl include. 764 7652016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com> 766 767 Fix -Wstack-usage warnings. 768 * aarch64-dis.c (print_operands): Substitute size. 769 * aarch64-opc.c (print_register_offset_address): Substitute tblen. 770 7712016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com> 772 773 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order 774 to get a proper diagnostic when an invalid ASR register is used. 775 7762016-03-22 Nick Clifton <nickc@redhat.com> 777 778 * configure: Regenerate. 779 7802016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 781 782 * arc-nps400-tbl.h: New file. 783 * arc-opc.c: Add top level comment. 784 (insert_nps_3bit_dst): New function. 785 (extract_nps_3bit_dst): New function. 786 (insert_nps_3bit_src2): New function. 787 (extract_nps_3bit_src2): New function. 788 (insert_nps_bitop_size): New function. 789 (extract_nps_bitop_size): New function. 790 (arc_flag_operands): Add nps400 entries. 791 (arc_flag_classes): Add nps400 entries. 792 (arc_operands): Add nps400 entries. 793 (arc_opcodes): Add nps400 include. 794 7952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 796 797 * arc-opc.c (arc_flag_classes): Convert all flag classes to use 798 the new class enum values. 799 8002016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 801 802 * arc-dis.c (print_insn_arc): Handle nps400. 803 8042016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 805 806 * arc-opc.c (BASE): Delete. 807 8082016-03-18 Nick Clifton <nickc@redhat.com> 809 810 PR target/19721 811 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand 812 of MOV insn that aliases an ORR insn. 813 8142016-03-16 Jiong Wang <jiong.wang@arm.com> 815 816 * arm-dis.c (neon_opcodes): Support new FP16 instructions. 817 8182016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 819 820 * mcore-opc.h: Add const qualifiers. 821 * microblaze-opc.h (struct op_code_struct): Likewise. 822 * sh-opc.h: Likewise. 823 * tic4x-dis.c (tic4x_print_indirect): Likewise. 824 (tic4x_print_op): Likewise. 825 8262016-03-02 Alan Modra <amodra@gmail.com> 827 828 * or1k-desc.h: Regenerate. 829 * fr30-ibld.c: Regenerate. 830 * rl78-decode.c: Regenerate. 831 8322016-03-01 Nick Clifton <nickc@redhat.com> 833 834 PR target/19747 835 * rl78-dis.c (print_insn_rl78_common): Fix typo. 836 8372016-02-24 Renlin Li <renlin.li@arm.com> 838 839 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. 840 (print_insn_coprocessor): Support fp16 instructions. 841 8422016-02-24 Renlin Li <renlin.li@arm.com> 843 844 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm, 845 vminnm, vrint(mpna). 846 8472016-02-24 Renlin Li <renlin.li@arm.com> 848 849 * arm-dis.c (print_insn_coprocessor): Check co-processor number for 850 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. 851 8522016-02-15 H.J. Lu <hongjiu.lu@intel.com> 853 854 * i386-dis.c (print_insn): Parenthesize expression to prevent 855 truncated addresses. 856 (OP_J): Likewise. 857 8582016-02-10 Claudiu Zissulescu <claziss@synopsys.com> 859 Janek van Oirschot <jvanoirs@synopsys.com> 860 861 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New 862 variable. 863 8642016-02-04 Nick Clifton <nickc@redhat.com> 865 866 PR target/19561 867 * msp430-dis.c (print_insn_msp430): Add a special case for 868 decoding an RRC instruction with the ZC bit set in the extension 869 word. 870 8712016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> 872 873 * cgen-ibld.in (insert_normal): Rework calculation of shift. 874 * epiphany-ibld.c: Regenerate. 875 * fr30-ibld.c: Regenerate. 876 * frv-ibld.c: Regenerate. 877 * ip2k-ibld.c: Regenerate. 878 * iq2000-ibld.c: Regenerate. 879 * lm32-ibld.c: Regenerate. 880 * m32c-ibld.c: Regenerate. 881 * m32r-ibld.c: Regenerate. 882 * mep-ibld.c: Regenerate. 883 * mt-ibld.c: Regenerate. 884 * or1k-ibld.c: Regenerate. 885 * xc16x-ibld.c: Regenerate. 886 * xstormy16-ibld.c: Regenerate. 887 8882016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> 889 890 * epiphany-dis.c: Regenerated from latest cpu files. 891 8922016-02-01 Michael McConville <mmcco@mykolab.com> 893 894 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask 895 test bit. 896 8972016-01-25 Renlin Li <renlin.li@arm.com> 898 899 * arm-dis.c (mapping_symbol_for_insn): New function. 900 (find_ifthen_state): Call mapping_symbol_for_insn(). 901 9022016-01-20 Matthew Wahab <matthew.wahab@arm.com> 903 904 * aarch64-opc.c (operand_general_constraint_met_p): Check validity 905 of MSR UAO immediate operand. 906 9072016-01-18 Maciej W. Rozycki <macro@imgtec.com> 908 909 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS 910 instruction support. 911 9122016-01-17 Alan Modra <amodra@gmail.com> 913 914 * configure: Regenerate. 915 9162016-01-14 Nick Clifton <nickc@redhat.com> 917 918 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw 919 instructions that can support stack pointer operations. 920 * rl78-decode.c: Regenerate. 921 * rl78-dis.c: Fix display of stack pointer in MOVW based 922 instructions. 923 9242016-01-14 Matthew Wahab <matthew.wahab@arm.com> 925 926 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals 927 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, 928 erxtatus_el1 and erxaddr_el1. 929 9302016-01-12 Matthew Wahab <matthew.wahab@arm.com> 931 932 * arm-dis.c (arm_opcodes): Add "esb". 933 (thumb_opcodes): Likewise. 934 9352016-01-11 Peter Bergner <bergner@vnet.ibm.com> 936 937 * ppc-opc.c <xscmpnedp>: Delete. 938 <xvcmpnedp>: Likewise. 939 <xvcmpnedp.>: Likewise. 940 <xvcmpnesp>: Likewise. 941 <xvcmpnesp.>: Likewise. 942 9432016-01-08 Andreas Schwab <schwab@linux-m68k.org> 944 945 PR gas/13050 946 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in 947 addition to ISA_A. 948 9492016-01-01 Alan Modra <amodra@gmail.com> 950 951 Update year range in copyright notice of all files. 952 953For older changes see ChangeLog-2015 954 955Copyright (C) 2016 Free Software Foundation, Inc. 956 957Copying and distribution of this file, with or without modification, 958are permitted in any medium without royalty provided the copyright 959notice and this notice are preserved. 960 961Local Variables: 962mode: change-log 963left-margin: 8 964fill-column: 74 965version-control: never 966End: 967