1 /* Nios II opcode list for GAS, the GNU assembler. 2 Copyright (C) 2012, 2013 Free Software Foundation, Inc. 3 Contributed by Nigel Gray (ngray@altera.com). 4 Contributed by Mentor Graphics, Inc. 5 6 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. 7 8 GAS/GDB is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS/GDB is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS or GDB; see the file COPYING3. If not, write to 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23 #ifndef _NIOS2_H_ 24 #define _NIOS2_H_ 25 26 #include "bfd.h" 27 28 /**************************************************************************** 29 * This file contains structures, bit masks and shift counts used 30 * by the GNU toolchain to define the Nios II instruction set and 31 * access various opcode fields. 32 ****************************************************************************/ 33 34 /* Identify different overflow situations for error messages. */ 35 enum overflow_type 36 { 37 call_target_overflow = 0, 38 branch_target_overflow, 39 address_offset_overflow, 40 signed_immed16_overflow, 41 unsigned_immed16_overflow, 42 unsigned_immed5_overflow, 43 custom_opcode_overflow, 44 no_overflow 45 }; 46 47 /* This structure holds information for a particular instruction. 48 49 The args field is a string describing the operands. The following 50 letters can appear in the args: 51 c - a 5-bit control register index 52 d - a 5-bit destination register index 53 s - a 5-bit left source register index 54 t - a 5-bit right source register index 55 i - a 16-bit signed immediate 56 u - a 16-bit unsigned immediate 57 o - a 16-bit signed program counter relative offset 58 j - a 5-bit unsigned immediate 59 b - a 5-bit break instruction constant 60 l - a 8-bit custom instruction constant 61 m - a 26-bit unsigned immediate 62 Literal ',', '(', and ')' characters may also appear in the args as 63 delimiters. 64 65 The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection 66 of bits describing the instruction, notably any relevant hazard 67 information. 68 69 When assembling, the match field contains the opcode template, which 70 is modified by the arguments to produce the actual opcode 71 that is emitted. If pinfo is INSN_MACRO, then this is 0. 72 73 If pinfo is INSN_MACRO, the mask field stores the macro identifier. 74 Otherwise this is a bit mask for the relevant portions of the opcode 75 when disassembling. If the actual opcode anded with the match field 76 equals the opcode field, then we have found the correct instruction. */ 77 78 struct nios2_opcode 79 { 80 const char *name; /* The name of the instruction. */ 81 const char *args; /* A string describing the arguments for this 82 instruction. */ 83 const char *args_test; /* Like args, but with an extra argument for 84 the expected opcode. */ 85 unsigned long num_args; /* The number of arguments the instruction 86 takes. */ 87 unsigned long match; /* The basic opcode for the instruction. */ 88 unsigned long mask; /* Mask for the opcode field of the 89 instruction. */ 90 unsigned long pinfo; /* Is this a real instruction or instruction 91 macro? */ 92 enum overflow_type overflow_msg; /* Used to generate informative 93 message when fixup overflows. */ 94 }; 95 96 /* This value is used in the nios2_opcode.pinfo field to indicate that the 97 instruction is a macro or pseudo-op. This requires special treatment by 98 the assembler, and is used by the disassembler to determine whether to 99 check for a nop. */ 100 #define NIOS2_INSN_MACRO 0x80000000 101 #define NIOS2_INSN_MACRO_MOV 0x80000001 102 #define NIOS2_INSN_MACRO_MOVI 0x80000002 103 #define NIOS2_INSN_MACRO_MOVIA 0x80000004 104 105 #define NIOS2_INSN_RELAXABLE 0x40000000 106 #define NIOS2_INSN_UBRANCH 0x00000010 107 #define NIOS2_INSN_CBRANCH 0x00000020 108 #define NIOS2_INSN_CALL 0x00000040 109 110 #define NIOS2_INSN_ADDI 0x00000080 111 #define NIOS2_INSN_ANDI 0x00000100 112 #define NIOS2_INSN_ORI 0x00000200 113 #define NIOS2_INSN_XORI 0x00000400 114 115 116 /* Associates a register name ($6) with a 5-bit index (eg 6). */ 117 struct nios2_reg 118 { 119 const char *name; 120 const int index; 121 }; 122 123 124 /* These are bit masks and shift counts for accessing the various 125 fields of a Nios II instruction. */ 126 127 /* Macros for getting and setting an instruction field. */ 128 #define GET_INSN_FIELD(X, i) \ 129 (((i) & OP_MASK_##X) >> OP_SH_##X) 130 #define SET_INSN_FIELD(X, i, j) \ 131 ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X))) 132 133 /* Instruction field definitions. */ 134 #define IW_A_LSB 27 135 #define IW_A_MSB 31 136 #define IW_A_SZ 5 137 #define IW_A_MASK 0x1f 138 139 #define IW_B_LSB 22 140 #define IW_B_MSB 26 141 #define IW_B_SZ 5 142 #define IW_B_MASK 0x1f 143 144 #define IW_C_LSB 17 145 #define IW_C_MSB 21 146 #define IW_C_SZ 5 147 #define IW_C_MASK 0x1f 148 149 #define IW_IMM16_LSB 6 150 #define IW_IMM16_MSB 21 151 #define IW_IMM16_SZ 16 152 #define IW_IMM16_MASK 0xffff 153 154 #define IW_IMM26_LSB 6 155 #define IW_IMM26_MSB 31 156 #define IW_IMM26_SZ 26 157 #define IW_IMM26_MASK 0x3ffffff 158 159 #define IW_OP_LSB 0 160 #define IW_OP_MSB 5 161 #define IW_OP_SZ 6 162 #define IW_OP_MASK 0x3f 163 164 #define IW_OPX_LSB 11 165 #define IW_OPX_MSB 16 166 #define IW_OPX_SZ 6 167 #define IW_OPX_MASK 0x3f 168 169 #define IW_SHIFT_IMM5_LSB 6 170 #define IW_SHIFT_IMM5_MSB 10 171 #define IW_SHIFT_IMM5_SZ 5 172 #define IW_SHIFT_IMM5_MASK 0x1f 173 174 #define IW_CONTROL_REGNUM_LSB 6 175 #define IW_CONTROL_REGNUM_MSB 9 176 #define IW_CONTROL_REGNUM_SZ 4 177 #define IW_CONTROL_REGNUM_MASK 0xf 178 179 /* Operator mask and shift. */ 180 #define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB) 181 #define OP_SH_OP IW_OP_LSB 182 183 /* Masks and shifts for I-type instructions. */ 184 #define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB) 185 #define OP_SH_IOP IW_OP_LSB 186 187 #define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB) 188 #define OP_SH_IMM16 IW_IMM16_LSB 189 190 #define OP_MASK_IRD (IW_B_MASK << IW_B_LSB) 191 #define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */ 192 193 #define OP_MASK_IRT (IW_B_MASK << IW_B_LSB) 194 #define OP_SH_IRT IW_B_LSB 195 196 #define OP_MASK_IRS (IW_A_MASK << IW_A_LSB) 197 #define OP_SH_IRS IW_A_LSB 198 199 /* Masks and shifts for R-type instructions. */ 200 #define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB) 201 #define OP_SH_ROP IW_OP_LSB 202 203 #define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB) 204 #define OP_SH_ROPX IW_OPX_LSB 205 206 #define OP_MASK_RRD (IW_C_MASK << IW_C_LSB) 207 #define OP_SH_RRD IW_C_LSB 208 209 #define OP_MASK_RRT (IW_B_MASK << IW_B_LSB) 210 #define OP_SH_RRT IW_B_LSB 211 212 #define OP_MASK_RRS (IW_A_MASK << IW_A_LSB) 213 #define OP_SH_RRS IW_A_LSB 214 215 /* Masks and shifts for J-type instructions. */ 216 #define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB) 217 #define OP_SH_JOP IW_OP_LSB 218 219 #define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB) 220 #define OP_SH_IMM26 IW_IMM26_LSB 221 222 /* Masks and shifts for CTL instructions. */ 223 #define OP_MASK_RCTL 0x000007c0 224 #define OP_SH_RCTL 6 225 226 /* Break instruction imm5 field. */ 227 #define OP_MASK_TRAP_IMM5 0x000007c0 228 #define OP_SH_TRAP_IMM5 6 229 230 /* Instruction imm5 field. */ 231 #define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB) 232 #define OP_SH_IMM5 IW_SHIFT_IMM5_LSB 233 234 /* Cache operation fields (type j,i(s)). */ 235 #define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB) 236 #define OP_SH_CACHE_OPX IW_B_LSB 237 #define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB) 238 #define OP_SH_CACHE_RRS IW_A_LSB 239 240 /* Custom instruction masks. */ 241 #define OP_MASK_CUSTOM_A 0x00010000 242 #define OP_SH_CUSTOM_A 16 243 244 #define OP_MASK_CUSTOM_B 0x00008000 245 #define OP_SH_CUSTOM_B 15 246 247 #define OP_MASK_CUSTOM_C 0x00004000 248 #define OP_SH_CUSTOM_C 14 249 250 #define OP_MASK_CUSTOM_N 0x00003fc0 251 #define OP_SH_CUSTOM_N 6 252 #define OP_MAX_CUSTOM_N 255 253 254 /* OP instruction values. */ 255 #define OP_ADDI 4 256 #define OP_ANDHI 44 257 #define OP_ANDI 12 258 #define OP_BEQ 38 259 #define OP_BGE 14 260 #define OP_BGEU 46 261 #define OP_BLT 22 262 #define OP_BLTU 54 263 #define OP_BNE 30 264 #define OP_BR 6 265 #define OP_CALL 0 266 #define OP_CMPEQI 32 267 #define OP_CMPGEI 8 268 #define OP_CMPGEUI 40 269 #define OP_CMPLTI 16 270 #define OP_CMPLTUI 48 271 #define OP_CMPNEI 24 272 #define OP_CUSTOM 50 273 #define OP_FLUSHD 59 274 #define OP_FLUSHDA 27 275 #define OP_INITD 51 276 #define OP_INITDA 19 277 #define OP_JMPI 1 278 #define OP_LDB 7 279 #define OP_LDBIO 39 280 #define OP_LDBU 3 281 #define OP_LDBUIO 35 282 #define OP_LDH 15 283 #define OP_LDHIO 47 284 #define OP_LDHU 11 285 #define OP_LDHUIO 43 286 #define OP_LDL 31 287 #define OP_LDW 23 288 #define OP_LDWIO 55 289 #define OP_MULI 36 290 #define OP_OPX 58 291 #define OP_ORHI 52 292 #define OP_ORI 20 293 #define OP_RDPRS 56 294 #define OP_STB 5 295 #define OP_STBIO 37 296 #define OP_STC 29 297 #define OP_STH 13 298 #define OP_STHIO 45 299 #define OP_STW 21 300 #define OP_STWIO 53 301 #define OP_XORHI 60 302 #define OP_XORI 28 303 304 /* OPX instruction values. */ 305 #define OPX_ADD 49 306 #define OPX_AND 14 307 #define OPX_BREAK 52 308 #define OPX_BRET 9 309 #define OPX_CALLR 29 310 #define OPX_CMPEQ 32 311 #define OPX_CMPGE 8 312 #define OPX_CMPGEU 40 313 #define OPX_CMPLT 16 314 #define OPX_CMPLTU 48 315 #define OPX_CMPNE 24 316 #define OPX_CRST 62 317 #define OPX_DIV 37 318 #define OPX_DIVU 36 319 #define OPX_ERET 1 320 #define OPX_FLUSHI 12 321 #define OPX_FLUSHP 4 322 #define OPX_HBREAK 53 323 #define OPX_INITI 41 324 #define OPX_INTR 61 325 #define OPX_JMP 13 326 #define OPX_MUL 39 327 #define OPX_MULXSS 31 328 #define OPX_MULXSU 23 329 #define OPX_MULXUU 7 330 #define OPX_NEXTPC 28 331 #define OPX_NOR 6 332 #define OPX_OR 22 333 #define OPX_RDCTL 38 334 #define OPX_RET 5 335 #define OPX_ROL 3 336 #define OPX_ROLI 2 337 #define OPX_ROR 11 338 #define OPX_SLL 19 339 #define OPX_SLLI 18 340 #define OPX_SRA 59 341 #define OPX_SRAI 58 342 #define OPX_SRL 27 343 #define OPX_SRLI 26 344 #define OPX_SUB 57 345 #define OPX_SYNC 54 346 #define OPX_TRAP 45 347 #define OPX_WRCTL 46 348 #define OPX_WRPRS 20 349 #define OPX_XOR 30 350 351 /* The following macros define the opcode matches for each 352 instruction code & OP_MASK_INST == OP_MATCH_INST. */ 353 354 /* OP instruction matches. */ 355 #define OP_MATCH_ADDI OP_ADDI 356 #define OP_MATCH_ANDHI OP_ANDHI 357 #define OP_MATCH_ANDI OP_ANDI 358 #define OP_MATCH_BEQ OP_BEQ 359 #define OP_MATCH_BGE OP_BGE 360 #define OP_MATCH_BGEU OP_BGEU 361 #define OP_MATCH_BLT OP_BLT 362 #define OP_MATCH_BLTU OP_BLTU 363 #define OP_MATCH_BNE OP_BNE 364 #define OP_MATCH_BR OP_BR 365 #define OP_MATCH_FLUSHD OP_FLUSHD 366 #define OP_MATCH_FLUSHDA OP_FLUSHDA 367 #define OP_MATCH_INITD OP_INITD 368 #define OP_MATCH_INITDA OP_INITDA 369 #define OP_MATCH_CALL OP_CALL 370 #define OP_MATCH_CMPEQI OP_CMPEQI 371 #define OP_MATCH_CMPGEI OP_CMPGEI 372 #define OP_MATCH_CMPGEUI OP_CMPGEUI 373 #define OP_MATCH_CMPLTI OP_CMPLTI 374 #define OP_MATCH_CMPLTUI OP_CMPLTUI 375 #define OP_MATCH_CMPNEI OP_CMPNEI 376 #define OP_MATCH_JMPI OP_JMPI 377 #define OP_MATCH_LDB OP_LDB 378 #define OP_MATCH_LDBIO OP_LDBIO 379 #define OP_MATCH_LDBU OP_LDBU 380 #define OP_MATCH_LDBUIO OP_LDBUIO 381 #define OP_MATCH_LDH OP_LDH 382 #define OP_MATCH_LDHIO OP_LDHIO 383 #define OP_MATCH_LDHU OP_LDHU 384 #define OP_MATCH_LDHUIO OP_LDHUIO 385 #define OP_MATCH_LDL OP_LDL 386 #define OP_MATCH_LDW OP_LDW 387 #define OP_MATCH_LDWIO OP_LDWIO 388 #define OP_MATCH_MULI OP_MULI 389 #define OP_MATCH_OPX OP_OPX 390 #define OP_MATCH_ORHI OP_ORHI 391 #define OP_MATCH_ORI OP_ORI 392 #define OP_MATCH_RDPRS OP_RDPRS 393 #define OP_MATCH_STB OP_STB 394 #define OP_MATCH_STBIO OP_STBIO 395 #define OP_MATCH_STC OP_STC 396 #define OP_MATCH_STH OP_STH 397 #define OP_MATCH_STHIO OP_STHIO 398 #define OP_MATCH_STW OP_STW 399 #define OP_MATCH_STWIO OP_STWIO 400 #define OP_MATCH_CUSTOM OP_CUSTOM 401 #define OP_MATCH_XORHI OP_XORHI 402 #define OP_MATCH_XORI OP_XORI 403 #define OP_MATCH_OPX OP_OPX 404 405 /* OPX instruction values. */ 406 #define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX) 407 408 #define OP_MATCH_ADD OPX_MATCH (OPX_ADD) 409 #define OP_MATCH_AND OPX_MATCH (OPX_AND) 410 #define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK)) 411 #define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET)) 412 #define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR)) 413 #define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ) 414 #define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE) 415 #define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU) 416 #define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT) 417 #define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU) 418 #define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE) 419 #define OP_MATCH_DIV OPX_MATCH (OPX_DIV) 420 #define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU) 421 #define OP_MATCH_JMP OPX_MATCH (OPX_JMP) 422 #define OP_MATCH_MUL OPX_MATCH (OPX_MUL) 423 #define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS) 424 #define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU) 425 #define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU) 426 #define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC) 427 #define OP_MATCH_NOR OPX_MATCH (OPX_NOR) 428 #define OP_MATCH_OR OPX_MATCH (OPX_OR) 429 #define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL) 430 #define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET)) 431 #define OP_MATCH_ROL OPX_MATCH (OPX_ROL) 432 #define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI) 433 #define OP_MATCH_ROR OPX_MATCH (OPX_ROR) 434 #define OP_MATCH_SLL OPX_MATCH (OPX_SLL) 435 #define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI) 436 #define OP_MATCH_SRA OPX_MATCH (OPX_SRA) 437 #define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI) 438 #define OP_MATCH_SRL OPX_MATCH (OPX_SRL) 439 #define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI) 440 #define OP_MATCH_SUB OPX_MATCH (OPX_SUB) 441 #define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC) 442 #define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP)) 443 #define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET)) 444 #define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL) 445 #define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS) 446 #define OP_MATCH_XOR OPX_MATCH (OPX_XOR) 447 #define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI) 448 #define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP) 449 #define OP_MATCH_INITI OPX_MATCH (OPX_INITI) 450 451 /* Some unusual op masks. */ 452 #define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ 453 | OP_MASK_ROPX | OP_MASK_OP) \ 454 & 0xfffff03f) 455 #define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 456 | OP_MASK_OP)) 457 #define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 458 | OP_MASK_OP)) 459 #define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 460 | OP_MASK_OP)) 461 #define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ 462 | OP_MASK_ROPX | OP_MASK_OP) \ 463 & 0xfffff83f) 464 #define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 465 | OP_MASK_OP)) /*& 0xfffff83f */ 466 #define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ 467 | OP_MASK_OP)) 468 #define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 469 | OP_MASK_OP)) 470 #define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ 471 | OP_MASK_OP)) 472 473 #define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) 474 #define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) 475 #define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) 476 #define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) 477 #define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ 478 | OP_MASK_OP)) /*& 0xfffff83f */ 479 480 #ifndef OP_MASK 481 #define OP_MASK 0xffffffff 482 #endif 483 484 /* These convenience macros to extract instruction fields are used by GDB. */ 485 #define GET_IW_A(Iw) \ 486 (((Iw) >> IW_A_LSB) & IW_A_MASK) 487 #define GET_IW_B(Iw) \ 488 (((Iw) >> IW_B_LSB) & IW_B_MASK) 489 #define GET_IW_C(Iw) \ 490 (((Iw) >> IW_C_LSB) & IW_C_MASK) 491 #define GET_IW_CONTROL_REGNUM(Iw) \ 492 (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK) 493 #define GET_IW_IMM16(Iw) \ 494 (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK) 495 #define GET_IW_IMM26(Iw) \ 496 (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK) 497 #define GET_IW_OP(Iw) \ 498 (((Iw) >> IW_OP_LSB) & IW_OP_MASK) 499 #define GET_IW_OPX(Iw) \ 500 (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK) 501 502 /* These are the data structures we use to hold the instruction information. */ 503 extern const struct nios2_opcode nios2_builtin_opcodes[]; 504 extern const int bfd_nios2_num_builtin_opcodes; 505 extern struct nios2_opcode *nios2_opcodes; 506 extern int bfd_nios2_num_opcodes; 507 508 /* These are the data structures used to hold the register information. */ 509 extern const struct nios2_reg nios2_builtin_regs[]; 510 extern struct nios2_reg *nios2_regs; 511 extern const int nios2_num_builtin_regs; 512 extern int nios2_num_regs; 513 514 /* Machine-independent macro for number of opcodes. */ 515 #define NUMOPCODES bfd_nios2_num_opcodes 516 #define NUMREGISTERS nios2_num_regs; 517 518 /* This is made extern so that the assembler can use it to find out 519 what instruction caused an error. */ 520 extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long); 521 522 #endif /* _NIOS2_H */ 523