1 /* Opcode table for the ARC. 2 Copyright (C) 1994-2017 Free Software Foundation, Inc. 3 4 Contributed by Claudiu Zissulescu (claziss@synopsys.com) 5 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 7 the GNU Binutils. 8 9 GAS/GDB is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS/GDB is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS or GDB; see the file COPYING3. If not, write to 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #ifndef OPCODE_ARC_H 25 #define OPCODE_ARC_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #ifndef MAX_INSN_ARGS 32 #define MAX_INSN_ARGS 16 33 #endif 34 35 #ifndef MAX_INSN_FLGS 36 #define MAX_INSN_FLGS 3 37 #endif 38 39 /* Instruction Class. */ 40 typedef enum 41 { 42 ACL, 43 ARITH, 44 AUXREG, 45 BBIT0, 46 BBIT1, 47 BI, 48 BIH, 49 BITOP, 50 BITSTREAM, 51 BMU, 52 BRANCH, 53 BRCC, 54 CONTROL, 55 DIVREM, 56 DMA, 57 DPI, 58 DSP, 59 EI, 60 ENTER, 61 FLOAT, 62 INVALID, 63 JLI, 64 JUMP, 65 KERNEL, 66 LEAVE, 67 LOAD, 68 LOGICAL, 69 LOOP, 70 MEMORY, 71 MISC, 72 MOVE, 73 MPY, 74 NET, 75 PROTOCOL_DECODE, 76 PMU, 77 POP, 78 PUSH, 79 STORE, 80 SUB, 81 ULTRAIP, 82 XY 83 } insn_class_t; 84 85 /* Instruction Subclass. */ 86 typedef enum 87 { 88 NONE, 89 CVT, 90 BTSCN, 91 CD1, 92 CD2, 93 COND, 94 DIV, 95 DP, 96 DPA, 97 DPX, 98 MPY1E, 99 MPY6E, 100 MPY7E, 101 MPY8E, 102 MPY9E, 103 NPS400, 104 QUARKSE, 105 SHFT1, 106 SHFT2, 107 SWAP, 108 SP, 109 SPX 110 } insn_subclass_t; 111 112 /* Flags class. */ 113 typedef enum 114 { 115 F_CLASS_NONE = 0, 116 117 /* At most one flag from the set of flags can appear in the 118 instruction. */ 119 F_CLASS_OPTIONAL = (1 << 0), 120 121 /* Exactly one from from the set of flags must appear in the 122 instruction. */ 123 F_CLASS_REQUIRED = (1 << 1), 124 125 /* The conditional code can be extended over the standard variants 126 via .extCondCode pseudo-op. */ 127 F_CLASS_EXTEND = (1 << 2), 128 129 /* Condition code flag. */ 130 F_CLASS_COND = (1 << 3), 131 132 /* Write back mode. */ 133 F_CLASS_WB = (1 << 4), 134 135 /* Data size. */ 136 F_CLASS_ZZ = (1 << 5), 137 138 /* Implicit flag. */ 139 F_CLASS_IMPLICIT = (1 << 6) 140 } flag_class_t; 141 142 /* The opcode table is an array of struct arc_opcode. */ 143 struct arc_opcode 144 { 145 /* The opcode name. */ 146 const char * name; 147 148 /* The opcode itself. Those bits which will be filled in with 149 operands are zeroes. */ 150 unsigned long long opcode; 151 152 /* The opcode mask. This is used by the disassembler. This is a 153 mask containing ones indicating those bits which must match the 154 opcode field, and zeroes indicating those bits which need not 155 match (and are presumably filled in by operands). */ 156 unsigned long long mask; 157 158 /* One bit flags for the opcode. These are primarily used to 159 indicate specific processors and environments support the 160 instructions. The defined values are listed below. */ 161 unsigned cpu; 162 163 /* The instruction class. This is used by gdb. */ 164 insn_class_t insn_class; 165 166 /* The instruction subclass. */ 167 insn_subclass_t subclass; 168 169 /* An array of operand codes. Each code is an index into the 170 operand table. They appear in the order which the operands must 171 appear in assembly code, and are terminated by a zero. */ 172 unsigned char operands[MAX_INSN_ARGS + 1]; 173 174 /* An array of flag codes. Each code is an index into the flag 175 table. They appear in the order which the flags must appear in 176 assembly code, and are terminated by a zero. */ 177 unsigned char flags[MAX_INSN_FLGS + 1]; 178 }; 179 180 /* The table itself is sorted by major opcode number, and is otherwise 181 in the order in which the disassembler should consider 182 instructions. */ 183 extern const struct arc_opcode arc_opcodes[]; 184 185 /* Return length of an instruction represented by OPCODE, in bytes. */ 186 extern int arc_opcode_len (const struct arc_opcode *opcode); 187 188 /* CPU Availability. */ 189 #define ARC_OPCODE_NONE 0x0000 190 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ 191 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ 192 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ 193 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ 194 195 /* CPU combi. */ 196 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ 197 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) 198 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) 199 #define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) 200 201 /* CPU extensions. */ 202 #define ARC_EA 0x0001 203 #define ARC_CD 0x0001 /* Mutual exclusive with EA. */ 204 #define ARC_LLOCK 0x0002 205 #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ 206 #define ARC_MPY 0x0004 207 #define ARC_MULT 0x0004 208 #define ARC_NPS400 0x0008 209 210 /* Floating point support. */ 211 #define ARC_DPFP 0x0010 212 #define ARC_SPFP 0x0020 213 #define ARC_FPU 0x0030 214 #define ARC_FPUDA 0x0040 215 216 /* NORM & SWAP. */ 217 #define ARC_SWAP 0x0100 218 #define ARC_NORM 0x0200 219 #define ARC_BSCAN 0x0200 220 221 /* A7 specific. */ 222 #define ARC_UIX 0x1000 223 #define ARC_TSTAMP 0x1000 224 225 /* A6 specific. */ 226 #define ARC_VBFDW 0x1000 227 #define ARC_BARREL 0x1000 228 #define ARC_DSPA 0x1000 229 230 /* EM specific. */ 231 #define ARC_SHIFT 0x1000 232 233 /* V2 specific. */ 234 #define ARC_INTR 0x1000 235 #define ARC_DIV 0x1000 236 237 /* V1 specific. */ 238 #define ARC_XMAC 0x1000 239 #define ARC_CRC 0x1000 240 241 /* The operands table is an array of struct arc_operand. */ 242 struct arc_operand 243 { 244 /* The number of bits in the operand. */ 245 unsigned int bits; 246 247 /* How far the operand is left shifted in the instruction. */ 248 unsigned int shift; 249 250 /* The default relocation type for this operand. */ 251 signed int default_reloc; 252 253 /* One bit syntax flags. */ 254 unsigned int flags; 255 256 /* Insertion function. This is used by the assembler. To insert an 257 operand value into an instruction, check this field. 258 259 If it is NULL, execute 260 i |= (op & ((1 << o->bits) - 1)) << o->shift; 261 (i is the instruction which we are filling in, o is a pointer to 262 this structure, and op is the opcode value; this assumes twos 263 complement arithmetic). 264 265 If this field is not NULL, then simply call it with the 266 instruction and the operand value. It will return the new value 267 of the instruction. If the ERRMSG argument is not NULL, then if 268 the operand value is illegal, *ERRMSG will be set to a warning 269 string (the operand will be inserted in any case). If the 270 operand value is legal, *ERRMSG will be unchanged (most operands 271 can accept any value). */ 272 unsigned long long (*insert) (unsigned long long instruction, 273 long long int op, 274 const char **errmsg); 275 276 /* Extraction function. This is used by the disassembler. To 277 extract this operand type from an instruction, check this field. 278 279 If it is NULL, compute 280 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 281 if ((o->flags & ARC_OPERAND_SIGNED) != 0 282 && (op & (1 << (o->bits - 1))) != 0) 283 op -= 1 << o->bits; 284 (i is the instruction, o is a pointer to this structure, and op 285 is the result; this assumes twos complement arithmetic). 286 287 If this field is not NULL, then simply call it with the 288 instruction value. It will return the value of the operand. If 289 the INVALID argument is not NULL, *INVALID will be set to 290 TRUE if this operand type can not actually be extracted from 291 this operand (i.e., the instruction does not match). If the 292 operand is valid, *INVALID will not be changed. */ 293 long long int (*extract) (unsigned long long instruction, 294 bfd_boolean *invalid); 295 }; 296 297 /* Elements in the table are retrieved by indexing with values from 298 the operands field of the arc_opcodes table. */ 299 extern const struct arc_operand arc_operands[]; 300 extern const unsigned arc_num_operands; 301 extern const unsigned arc_Toperand; 302 extern const unsigned arc_NToperand; 303 304 /* Values defined for the flags field of a struct arc_operand. */ 305 306 /* This operand does not actually exist in the assembler input. This 307 is used to support extended mnemonics, for which two operands fields 308 are identical. The assembler should call the insert function with 309 any op value. The disassembler should call the extract function, 310 ignore the return value, and check the value placed in the invalid 311 argument. */ 312 #define ARC_OPERAND_FAKE 0x0001 313 314 /* This operand names an integer register. */ 315 #define ARC_OPERAND_IR 0x0002 316 317 /* This operand takes signed values. */ 318 #define ARC_OPERAND_SIGNED 0x0004 319 320 /* This operand takes unsigned values. This exists primarily so that 321 a flags value of 0 can be treated as end-of-arguments. */ 322 #define ARC_OPERAND_UNSIGNED 0x0008 323 324 /* This operand takes long immediate values. */ 325 #define ARC_OPERAND_LIMM 0x0010 326 327 /* This operand is identical like the previous one. */ 328 #define ARC_OPERAND_DUPLICATE 0x0020 329 330 /* This operand is PC relative. Used for internal relocs. */ 331 #define ARC_OPERAND_PCREL 0x0040 332 333 /* This operand is truncated. The truncation is done accordingly to 334 operand alignment attribute. */ 335 #define ARC_OPERAND_TRUNCATE 0x0080 336 337 /* This operand is 16bit aligned. */ 338 #define ARC_OPERAND_ALIGNED16 0x0100 339 340 /* This operand is 32bit aligned. */ 341 #define ARC_OPERAND_ALIGNED32 0x0200 342 343 /* This operand can be ignored by matching process if it is not 344 present. */ 345 #define ARC_OPERAND_IGNORE 0x0400 346 347 /* Don't check the range when matching. */ 348 #define ARC_OPERAND_NCHK 0x0800 349 350 /* Mark the braket possition. */ 351 #define ARC_OPERAND_BRAKET 0x1000 352 353 /* Address type operand for NPS400. */ 354 #define ARC_OPERAND_ADDRTYPE 0x2000 355 356 /* Mark the colon position. */ 357 #define ARC_OPERAND_COLON 0x4000 358 359 /* Mask for selecting the type for typecheck purposes. */ 360 #define ARC_OPERAND_TYPECHECK_MASK \ 361 (ARC_OPERAND_IR \ 362 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ 363 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \ 364 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON) 365 366 /* Macro to determine if an operand is a fake operand. */ 367 #define ARC_OPERAND_IS_FAKE(op) \ 368 ((operand->flags & ARC_OPERAND_FAKE) \ 369 && !((operand->flags & ARC_OPERAND_BRAKET) \ 370 || (operand->flags & ARC_OPERAND_COLON))) 371 372 /* The flags structure. */ 373 struct arc_flag_operand 374 { 375 /* The flag name. */ 376 const char * name; 377 378 /* The flag code. */ 379 unsigned code; 380 381 /* The number of bits in the operand. */ 382 unsigned int bits; 383 384 /* How far the operand is left shifted in the instruction. */ 385 unsigned int shift; 386 387 /* Available for disassembler. */ 388 unsigned char favail; 389 }; 390 391 /* The flag operands table. */ 392 extern const struct arc_flag_operand arc_flag_operands[]; 393 extern const unsigned arc_num_flag_operands; 394 395 /* The flag's class structure. */ 396 struct arc_flag_class 397 { 398 /* Flag class. */ 399 flag_class_t flag_class; 400 401 /* List of valid flags (codes). */ 402 unsigned flags[256]; 403 }; 404 405 extern const struct arc_flag_class arc_flag_classes[]; 406 407 /* Structure for special cases. */ 408 struct arc_flag_special 409 { 410 /* Name of special case instruction. */ 411 const char *name; 412 413 /* List of flags applicable for special case instruction. */ 414 unsigned flags[32]; 415 }; 416 417 extern const struct arc_flag_special arc_flag_special_cases[]; 418 extern const unsigned arc_num_flag_special; 419 420 /* Relocation equivalence structure. */ 421 struct arc_reloc_equiv_tab 422 { 423 const char * name; /* String to lookup. */ 424 const char * mnemonic; /* Extra matching condition. */ 425 unsigned flags[32]; /* Extra matching condition. */ 426 signed int oldreloc; /* Old relocation. */ 427 signed int newreloc; /* New relocation. */ 428 }; 429 430 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; 431 extern const unsigned arc_num_equiv_tab; 432 433 /* Structure for operand operations for pseudo/alias instructions. */ 434 struct arc_operand_operation 435 { 436 /* The index for operand from operand array. */ 437 unsigned operand_idx; 438 439 /* Defines if it needs the operand inserted by the assembler or 440 whether this operand comes from the pseudo instruction's 441 operands. */ 442 unsigned char needs_insert; 443 444 /* Count we have to add to the operand. Use negative number to 445 subtract from the operand. Also use this number to add to 0 if 446 the operand needs to be inserted (i.e. needs_insert == 1). */ 447 int count; 448 449 /* Index of the operand to swap with. To be done AFTER applying 450 inc_count. */ 451 unsigned swap_operand_idx; 452 }; 453 454 /* Structure for pseudo/alias instructions. */ 455 struct arc_pseudo_insn 456 { 457 /* Mnemonic for pseudo/alias insn. */ 458 const char * mnemonic_p; 459 460 /* Mnemonic for real instruction. */ 461 const char * mnemonic_r; 462 463 /* Flag that will have to be added (if any). */ 464 const char * flag_r; 465 466 /* Amount of operands. */ 467 unsigned operand_cnt; 468 469 /* Array of operand operations. */ 470 struct arc_operand_operation operand[6]; 471 }; 472 473 extern const struct arc_pseudo_insn arc_pseudo_insns[]; 474 extern const unsigned arc_num_pseudo_insn; 475 476 /* Structure for AUXILIARY registers. */ 477 struct arc_aux_reg 478 { 479 /* Register address. */ 480 int address; 481 482 /* One bit flags for the opcode. These are primarily used to 483 indicate specific processors and environments support the 484 instructions. */ 485 unsigned cpu; 486 487 /* AUX register subclass. */ 488 insn_subclass_t subclass; 489 490 /* Register name. */ 491 const char * name; 492 493 /* Size of the string. */ 494 size_t length; 495 }; 496 497 extern const struct arc_aux_reg arc_aux_regs[]; 498 extern const unsigned arc_num_aux_regs; 499 500 extern const struct arc_opcode arc_relax_opcodes[]; 501 extern const unsigned arc_num_relax_opcodes; 502 503 /* Macro used for generating one class of NPS instructions. */ 504 #define NPS_CMEM_HIGH_VALUE 0x57f0 505 506 /* Macros to help generating regular pattern instructions. */ 507 #define FIELDA(word) (word & 0x3F) 508 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12)) 509 #define FIELDC(word) ((word & 0x3F) << 6) 510 #define FIELDF (0x01 << 15) 511 #define FIELDQ (0x1F) 512 513 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) 514 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) 515 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) 516 517 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP)) 518 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62)) 519 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62)) 520 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 521 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62)) 522 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62)) 523 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62)) 524 #define INSN3OP_0LL(MOP,SOP) \ 525 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62)) 526 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22)) 527 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 528 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22)) 529 #define INSN3OP_0LU(MOP,SOP) \ 530 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62)) 531 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22)) 532 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62)) 533 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22)) 534 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62)) 535 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62)) 536 #define INSN3OP_C0LL(MOP,SOP) \ 537 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62)) 538 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5)) 539 #define INSN3OP_C0LU(MOP,SOP) \ 540 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62)) 541 542 #define MASK_32BIT(VAL) (0xffffffff & (VAL)) 543 544 #define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 545 #define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 546 #define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63)))) 547 #define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63)))) 548 #define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) 549 #define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63)))) 550 #define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63)))) 551 #define MINSN3OP_0LL (MASK_32BIT (~(FIELDF))) 552 #define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 553 #define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 554 #define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) 555 #define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63)))) 556 #define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 557 #define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 558 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) 559 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63)))) 560 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) 561 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ))) 562 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) 563 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) 564 565 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP)) 566 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62)) 567 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)) 568 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 569 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22)) 570 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 571 572 #define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) 573 #define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63))))) 574 #define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63))))) 575 #define MINSN2OP_0L (MASK_32BIT ((~(FIELDF)))) 576 #define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) 577 #define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63))))) 578 579 /* Various constants used when defining an extension instruction. */ 580 #define ARC_SYNTAX_3OP (1 << 0) 581 #define ARC_SYNTAX_2OP (1 << 1) 582 #define ARC_SYNTAX_1OP (1 << 2) 583 #define ARC_SYNTAX_NOP (1 << 3) 584 #define ARC_SYNTAX_MASK (0x0F) 585 586 #define ARC_OP1_MUST_BE_IMM (1 << 0) 587 #define ARC_OP1_IMM_IMPLIED (1 << 1) 588 589 #define ARC_SUFFIX_NONE (1 << 0) 590 #define ARC_SUFFIX_COND (1 << 1) 591 #define ARC_SUFFIX_FLAG (1 << 2) 592 593 #define ARC_REGISTER_READONLY (1 << 0) 594 #define ARC_REGISTER_WRITEONLY (1 << 1) 595 #define ARC_REGISTER_NOSHORT_CUT (1 << 2) 596 597 /* Constants needed to initialize extension instructions. */ 598 extern const unsigned char flags_none[MAX_INSN_FLGS + 1]; 599 extern const unsigned char flags_f[MAX_INSN_FLGS + 1]; 600 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1]; 601 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1]; 602 603 extern const unsigned char arg_none[MAX_INSN_ARGS + 1]; 604 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1]; 605 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1]; 606 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1]; 607 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1]; 608 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1]; 609 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1]; 610 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1]; 611 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1]; 612 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1]; 613 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1]; 614 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1]; 615 616 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1]; 617 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1]; 618 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1]; 619 620 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1]; 621 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1]; 622 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1]; 623 624 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1]; 625 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1]; 626 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1]; 627 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1]; 628 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1]; 629 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1]; 630 631 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1]; 632 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1]; 633 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1]; 634 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1]; 635 636 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1]; 637 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1]; 638 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1]; 639 640 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP 641 Instruction Set Reference Manual v2.4 for a description of address types. */ 642 643 typedef enum 644 { 645 /* Addresses in memory. */ 646 647 /* Buffer descriptor. */ 648 ARC_NPS400_ADDRTYPE_BD, 649 650 /* Job identifier. */ 651 ARC_NPS400_ADDRTYPE_JID, 652 653 /* Linked Buffer Descriptor. */ 654 ARC_NPS400_ADDRTYPE_LBD, 655 656 /* Multicast Buffer Descriptor. */ 657 ARC_NPS400_ADDRTYPE_MBD, 658 659 /* Summarized Address. */ 660 ARC_NPS400_ADDRTYPE_SD, 661 662 /* SMEM Security Context Local Memory. */ 663 ARC_NPS400_ADDRTYPE_SM, 664 665 /* Extended Address. */ 666 ARC_NPS400_ADDRTYPE_XA, 667 668 /* Extended Summarized Address. */ 669 ARC_NPS400_ADDRTYPE_XD, 670 671 /* CMEM offset addresses. */ 672 673 /* On-demand Counter Descriptor. */ 674 ARC_NPS400_ADDRTYPE_CD, 675 676 /* CMEM Buffer Descriptor. */ 677 ARC_NPS400_ADDRTYPE_CBD, 678 679 /* CMEM Job Identifier. */ 680 ARC_NPS400_ADDRTYPE_CJID, 681 682 /* CMEM Linked Buffer Descriptor. */ 683 ARC_NPS400_ADDRTYPE_CLBD, 684 685 /* CMEM Offset. */ 686 ARC_NPS400_ADDRTYPE_CM, 687 688 /* CMEM Summarized Address. */ 689 ARC_NPS400_ADDRTYPE_CSD, 690 691 /* CMEM Extended Address. */ 692 ARC_NPS400_ADDRTYPE_CXA, 693 694 /* CMEM Extended Summarized Address. */ 695 ARC_NPS400_ADDRTYPE_CXD 696 697 } arc_nps_address_type; 698 699 #define ARC_NUM_ADDRTYPES 16 700 701 #ifdef __cplusplus 702 } 703 #endif 704 705 #endif /* OPCODE_ARC_H */ 706