1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2017 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* The offset for pc-relative addressing is currently defined to be 0. */ 35 #define AARCH64_PCREL_OFFSET 0 36 37 typedef uint32_t aarch64_insn; 38 39 /* The following bitmasks control CPU features. */ 40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ 42 #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ 43 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 44 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 45 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 46 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 47 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ 48 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ 49 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ 50 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ 51 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ 52 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ 53 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ 54 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ 55 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ 56 #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ 57 #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ 58 59 /* Architectures are the sum of the base and extensions. */ 60 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 61 AARCH64_FEATURE_FP \ 62 | AARCH64_FEATURE_SIMD) 63 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ 64 AARCH64_FEATURE_CRC \ 65 | AARCH64_FEATURE_V8_1 \ 66 | AARCH64_FEATURE_LSE \ 67 | AARCH64_FEATURE_PAN \ 68 | AARCH64_FEATURE_LOR \ 69 | AARCH64_FEATURE_RDMA) 70 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ 71 AARCH64_FEATURE_V8_2 \ 72 | AARCH64_FEATURE_F16 \ 73 | AARCH64_FEATURE_RAS) 74 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ 75 AARCH64_FEATURE_V8_3 \ 76 | AARCH64_FEATURE_RCPC \ 77 | AARCH64_FEATURE_COMPNUM) 78 79 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 80 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 81 82 /* CPU-specific features. */ 83 typedef unsigned long aarch64_feature_set; 84 85 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 86 ((~(CPU) & (FEAT)) == 0) 87 88 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 89 (((CPU) & (FEAT)) != 0) 90 91 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 92 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 93 94 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 95 do \ 96 { \ 97 (TARG) = (F1) | (F2); \ 98 } \ 99 while (0) 100 101 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 102 do \ 103 { \ 104 (TARG) = (F1) &~ (F2); \ 105 } \ 106 while (0) 107 108 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 109 110 enum aarch64_operand_class 111 { 112 AARCH64_OPND_CLASS_NIL, 113 AARCH64_OPND_CLASS_INT_REG, 114 AARCH64_OPND_CLASS_MODIFIED_REG, 115 AARCH64_OPND_CLASS_FP_REG, 116 AARCH64_OPND_CLASS_SIMD_REG, 117 AARCH64_OPND_CLASS_SIMD_ELEMENT, 118 AARCH64_OPND_CLASS_SISD_REG, 119 AARCH64_OPND_CLASS_SIMD_REGLIST, 120 AARCH64_OPND_CLASS_SVE_REG, 121 AARCH64_OPND_CLASS_PRED_REG, 122 AARCH64_OPND_CLASS_ADDRESS, 123 AARCH64_OPND_CLASS_IMMEDIATE, 124 AARCH64_OPND_CLASS_SYSTEM, 125 AARCH64_OPND_CLASS_COND, 126 }; 127 128 /* Operand code that helps both parsing and coding. 129 Keep AARCH64_OPERANDS synced. */ 130 131 enum aarch64_opnd 132 { 133 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 134 135 AARCH64_OPND_Rd, /* Integer register as destination. */ 136 AARCH64_OPND_Rn, /* Integer register as source. */ 137 AARCH64_OPND_Rm, /* Integer register as source. */ 138 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 139 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 140 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 141 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 142 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 143 144 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 145 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 146 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ 147 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 148 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 149 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 150 151 AARCH64_OPND_Fd, /* Floating-point Fd. */ 152 AARCH64_OPND_Fn, /* Floating-point Fn. */ 153 AARCH64_OPND_Fm, /* Floating-point Fm. */ 154 AARCH64_OPND_Fa, /* Floating-point Fa. */ 155 AARCH64_OPND_Ft, /* Floating-point Ft. */ 156 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 157 158 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 159 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 160 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 161 162 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 163 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 164 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 165 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 166 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 167 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 168 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 169 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 170 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 171 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 172 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 173 structure to all lanes. */ 174 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 175 176 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ 177 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ 178 179 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 180 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 181 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 182 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 183 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 184 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 185 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 186 (no encoding). */ 187 AARCH64_OPND_IMM0, /* Immediate for #0. */ 188 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 189 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 190 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 191 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 192 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 193 AARCH64_OPND_IMM, /* Immediate. */ 194 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 195 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 196 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 197 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 198 AARCH64_OPND_BIT_NUM, /* Immediate. */ 199 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 200 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 201 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ 202 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 203 each condition flag. */ 204 205 AARCH64_OPND_LIMM, /* Logical Immediate. */ 206 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 207 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 208 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 209 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 210 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ 211 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ 212 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ 213 214 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 215 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 216 217 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 218 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 219 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 220 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 221 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 222 223 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 224 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 225 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 226 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 227 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 228 negative or unaligned and there is 229 no writeback allowed. This operand code 230 is only used to support the programmer- 231 friendly feature of using LDR/STR as the 232 the mnemonic name for LDUR/STUR instructions 233 wherever there is no ambiguity. */ 234 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ 235 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 236 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 237 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 238 239 AARCH64_OPND_SYSREG, /* System register operand. */ 240 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 241 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 242 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 243 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 244 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 245 AARCH64_OPND_BARRIER, /* Barrier operand. */ 246 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 247 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 248 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 249 250 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ 251 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ 252 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ 253 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ 254 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ 255 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ 256 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ 257 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ 258 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ 259 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ 260 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ 261 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ 262 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ 263 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ 264 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ 265 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ 266 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ 267 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ 268 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ 269 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ 270 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ 271 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ 272 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ 273 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 274 Bit 14 controls S/U choice. */ 275 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 276 Bit 22 controls S/U choice. */ 277 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 278 Bit 14 controls S/U choice. */ 279 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 280 Bit 22 controls S/U choice. */ 281 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 282 Bit 14 controls S/U choice. */ 283 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 284 Bit 22 controls S/U choice. */ 285 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 286 Bit 14 controls S/U choice. */ 287 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 288 Bit 22 controls S/U choice. */ 289 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ 290 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ 291 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ 292 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ 293 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ 294 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ 295 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ 296 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ 297 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ 298 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ 299 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ 300 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ 301 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ 302 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ 303 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ 304 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ 305 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ 306 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ 307 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ 308 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ 309 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ 310 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ 311 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ 312 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ 313 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ 314 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ 315 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ 316 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ 317 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ 318 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ 319 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ 320 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ 321 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ 322 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ 323 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ 324 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ 325 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ 326 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ 327 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ 328 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ 329 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ 330 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ 331 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ 332 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ 333 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ 334 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ 335 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ 336 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ 337 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ 338 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ 339 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ 340 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ 341 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ 342 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ 343 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ 344 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ 345 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ 346 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ 347 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ 348 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ 349 }; 350 351 /* Qualifier constrains an operand. It either specifies a variant of an 352 operand type or limits values available to an operand type. 353 354 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 355 356 enum aarch64_opnd_qualifier 357 { 358 /* Indicating no further qualification on an operand. */ 359 AARCH64_OPND_QLF_NIL, 360 361 /* Qualifying an operand which is a general purpose (integer) register; 362 indicating the operand data size or a specific register. */ 363 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 364 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 365 AARCH64_OPND_QLF_WSP, /* WSP. */ 366 AARCH64_OPND_QLF_SP, /* SP. */ 367 368 /* Qualifying an operand which is a floating-point register, a SIMD 369 vector element or a SIMD vector element list; indicating operand data 370 size or the size of each SIMD vector element in the case of a SIMD 371 vector element list. 372 These qualifiers are also used to qualify an address operand to 373 indicate the size of data element a load/store instruction is 374 accessing. 375 They are also used for the immediate shift operand in e.g. SSHR. Such 376 a use is only for the ease of operand encoding/decoding and qualifier 377 sequence matching; such a use should not be applied widely; use the value 378 constraint qualifiers for immediate operands wherever possible. */ 379 AARCH64_OPND_QLF_S_B, 380 AARCH64_OPND_QLF_S_H, 381 AARCH64_OPND_QLF_S_S, 382 AARCH64_OPND_QLF_S_D, 383 AARCH64_OPND_QLF_S_Q, 384 385 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 386 register list; indicating register shape. 387 They are also used for the immediate shift operand in e.g. SSHR. Such 388 a use is only for the ease of operand encoding/decoding and qualifier 389 sequence matching; such a use should not be applied widely; use the value 390 constraint qualifiers for immediate operands wherever possible. */ 391 AARCH64_OPND_QLF_V_8B, 392 AARCH64_OPND_QLF_V_16B, 393 AARCH64_OPND_QLF_V_2H, 394 AARCH64_OPND_QLF_V_4H, 395 AARCH64_OPND_QLF_V_8H, 396 AARCH64_OPND_QLF_V_2S, 397 AARCH64_OPND_QLF_V_4S, 398 AARCH64_OPND_QLF_V_1D, 399 AARCH64_OPND_QLF_V_2D, 400 AARCH64_OPND_QLF_V_1Q, 401 402 AARCH64_OPND_QLF_P_Z, 403 AARCH64_OPND_QLF_P_M, 404 405 /* Constraint on value. */ 406 AARCH64_OPND_QLF_CR, /* CRn, CRm. */ 407 AARCH64_OPND_QLF_imm_0_7, 408 AARCH64_OPND_QLF_imm_0_15, 409 AARCH64_OPND_QLF_imm_0_31, 410 AARCH64_OPND_QLF_imm_0_63, 411 AARCH64_OPND_QLF_imm_1_32, 412 AARCH64_OPND_QLF_imm_1_64, 413 414 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 415 or shift-ones. */ 416 AARCH64_OPND_QLF_LSL, 417 AARCH64_OPND_QLF_MSL, 418 419 /* Special qualifier helping retrieve qualifier information during the 420 decoding time (currently not in use). */ 421 AARCH64_OPND_QLF_RETRIEVE, 422 }; 423 424 /* Instruction class. */ 425 426 enum aarch64_insn_class 427 { 428 addsub_carry, 429 addsub_ext, 430 addsub_imm, 431 addsub_shift, 432 asimdall, 433 asimddiff, 434 asimdelem, 435 asimdext, 436 asimdimm, 437 asimdins, 438 asimdmisc, 439 asimdperm, 440 asimdsame, 441 asimdshf, 442 asimdtbl, 443 asisddiff, 444 asisdelem, 445 asisdlse, 446 asisdlsep, 447 asisdlso, 448 asisdlsop, 449 asisdmisc, 450 asisdone, 451 asisdpair, 452 asisdsame, 453 asisdshf, 454 bitfield, 455 branch_imm, 456 branch_reg, 457 compbranch, 458 condbranch, 459 condcmp_imm, 460 condcmp_reg, 461 condsel, 462 cryptoaes, 463 cryptosha2, 464 cryptosha3, 465 dp_1src, 466 dp_2src, 467 dp_3src, 468 exception, 469 extract, 470 float2fix, 471 float2int, 472 floatccmp, 473 floatcmp, 474 floatdp1, 475 floatdp2, 476 floatdp3, 477 floatimm, 478 floatsel, 479 ldst_immpost, 480 ldst_immpre, 481 ldst_imm9, /* immpost or immpre */ 482 ldst_imm10, /* LDRAA/LDRAB */ 483 ldst_pos, 484 ldst_regoff, 485 ldst_unpriv, 486 ldst_unscaled, 487 ldstexcl, 488 ldstnapair_offs, 489 ldstpair_off, 490 ldstpair_indexed, 491 loadlit, 492 log_imm, 493 log_shift, 494 lse_atomic, 495 movewide, 496 pcreladdr, 497 ic_system, 498 sve_cpy, 499 sve_index, 500 sve_limm, 501 sve_misc, 502 sve_movprfx, 503 sve_pred_zm, 504 sve_shift_pred, 505 sve_shift_unpred, 506 sve_size_bhs, 507 sve_size_bhsd, 508 sve_size_hsd, 509 sve_size_sd, 510 testbranch, 511 }; 512 513 /* Opcode enumerators. */ 514 515 enum aarch64_op 516 { 517 OP_NIL, 518 OP_STRB_POS, 519 OP_LDRB_POS, 520 OP_LDRSB_POS, 521 OP_STRH_POS, 522 OP_LDRH_POS, 523 OP_LDRSH_POS, 524 OP_STR_POS, 525 OP_LDR_POS, 526 OP_STRF_POS, 527 OP_LDRF_POS, 528 OP_LDRSW_POS, 529 OP_PRFM_POS, 530 531 OP_STURB, 532 OP_LDURB, 533 OP_LDURSB, 534 OP_STURH, 535 OP_LDURH, 536 OP_LDURSH, 537 OP_STUR, 538 OP_LDUR, 539 OP_STURV, 540 OP_LDURV, 541 OP_LDURSW, 542 OP_PRFUM, 543 544 OP_LDR_LIT, 545 OP_LDRV_LIT, 546 OP_LDRSW_LIT, 547 OP_PRFM_LIT, 548 549 OP_ADD, 550 OP_B, 551 OP_BL, 552 553 OP_MOVN, 554 OP_MOVZ, 555 OP_MOVK, 556 557 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 558 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 559 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 560 561 OP_MOV_V, /* MOV alias for moving vector register. */ 562 563 OP_ASR_IMM, 564 OP_LSR_IMM, 565 OP_LSL_IMM, 566 567 OP_BIC, 568 569 OP_UBFX, 570 OP_BFXIL, 571 OP_SBFX, 572 OP_SBFIZ, 573 OP_BFI, 574 OP_BFC, /* ARMv8.2. */ 575 OP_UBFIZ, 576 OP_UXTB, 577 OP_UXTH, 578 OP_UXTW, 579 580 OP_CINC, 581 OP_CINV, 582 OP_CNEG, 583 OP_CSET, 584 OP_CSETM, 585 586 OP_FCVT, 587 OP_FCVTN, 588 OP_FCVTN2, 589 OP_FCVTL, 590 OP_FCVTL2, 591 OP_FCVTXN_S, /* Scalar version. */ 592 593 OP_ROR_IMM, 594 595 OP_SXTL, 596 OP_SXTL2, 597 OP_UXTL, 598 OP_UXTL2, 599 600 OP_MOV_P_P, 601 OP_MOV_Z_P_Z, 602 OP_MOV_Z_V, 603 OP_MOV_Z_Z, 604 OP_MOV_Z_Zi, 605 OP_MOVM_P_P_P, 606 OP_MOVS_P_P, 607 OP_MOVZS_P_P_P, 608 OP_MOVZ_P_P_P, 609 OP_NOTS_P_P_P_Z, 610 OP_NOT_P_P_P_Z, 611 612 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ 613 614 OP_TOTAL_NUM, /* Pseudo. */ 615 }; 616 617 /* Maximum number of operands an instruction can have. */ 618 #define AARCH64_MAX_OPND_NUM 6 619 /* Maximum number of qualifier sequences an instruction can have. */ 620 #define AARCH64_MAX_QLF_SEQ_NUM 10 621 /* Operand qualifier typedef; optimized for the size. */ 622 typedef unsigned char aarch64_opnd_qualifier_t; 623 /* Operand qualifier sequence typedef. */ 624 typedef aarch64_opnd_qualifier_t \ 625 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 626 627 /* FIXME: improve the efficiency. */ 628 static inline bfd_boolean 629 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 630 { 631 int i; 632 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 633 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 634 return FALSE; 635 return TRUE; 636 } 637 638 /* This structure holds information for a particular opcode. */ 639 640 struct aarch64_opcode 641 { 642 /* The name of the mnemonic. */ 643 const char *name; 644 645 /* The opcode itself. Those bits which will be filled in with 646 operands are zeroes. */ 647 aarch64_insn opcode; 648 649 /* The opcode mask. This is used by the disassembler. This is a 650 mask containing ones indicating those bits which must match the 651 opcode field, and zeroes indicating those bits which need not 652 match (and are presumably filled in by operands). */ 653 aarch64_insn mask; 654 655 /* Instruction class. */ 656 enum aarch64_insn_class iclass; 657 658 /* Enumerator identifier. */ 659 enum aarch64_op op; 660 661 /* Which architecture variant provides this instruction. */ 662 const aarch64_feature_set *avariant; 663 664 /* An array of operand codes. Each code is an index into the 665 operand table. They appear in the order which the operands must 666 appear in assembly code, and are terminated by a zero. */ 667 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 668 669 /* A list of operand qualifier code sequence. Each operand qualifier 670 code qualifies the corresponding operand code. Each operand 671 qualifier sequence specifies a valid opcode variant and related 672 constraint on operands. */ 673 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 674 675 /* Flags providing information about this instruction */ 676 uint32_t flags; 677 678 /* If nonzero, this operand and operand 0 are both registers and 679 are required to have the same register number. */ 680 unsigned char tied_operand; 681 682 /* If non-NULL, a function to verify that a given instruction is valid. */ 683 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); 684 }; 685 686 typedef struct aarch64_opcode aarch64_opcode; 687 688 /* Table describing all the AArch64 opcodes. */ 689 extern aarch64_opcode aarch64_opcode_table[]; 690 691 /* Opcode flags. */ 692 #define F_ALIAS (1 << 0) 693 #define F_HAS_ALIAS (1 << 1) 694 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 695 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 696 #define F_P1 (1 << 2) 697 #define F_P2 (2 << 2) 698 #define F_P3 (3 << 2) 699 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 700 #define F_COND (1 << 4) 701 /* Instruction has the field of 'sf'. */ 702 #define F_SF (1 << 5) 703 /* Instruction has the field of 'size:Q'. */ 704 #define F_SIZEQ (1 << 6) 705 /* Floating-point instruction has the field of 'type'. */ 706 #define F_FPTYPE (1 << 7) 707 /* AdvSIMD scalar instruction has the field of 'size'. */ 708 #define F_SSIZE (1 << 8) 709 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 710 #define F_T (1 << 9) 711 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 712 #define F_GPRSIZE_IN_Q (1 << 10) 713 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 714 #define F_LDS_SIZE (1 << 11) 715 /* Optional operand; assume maximum of 1 operand can be optional. */ 716 #define F_OPD0_OPT (1 << 12) 717 #define F_OPD1_OPT (2 << 12) 718 #define F_OPD2_OPT (3 << 12) 719 #define F_OPD3_OPT (4 << 12) 720 #define F_OPD4_OPT (5 << 12) 721 /* Default value for the optional operand when omitted from the assembly. */ 722 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 723 /* Instruction that is an alias of another instruction needs to be 724 encoded/decoded by converting it to/from the real form, followed by 725 the encoding/decoding according to the rules of the real opcode. 726 This compares to the direct coding using the alias's information. 727 N.B. this flag requires F_ALIAS to be used together. */ 728 #define F_CONV (1 << 20) 729 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 730 friendly pseudo instruction available only in the assembly code (thus will 731 not show up in the disassembly). */ 732 #define F_PSEUDO (1 << 21) 733 /* Instruction has miscellaneous encoding/decoding rules. */ 734 #define F_MISC (1 << 22) 735 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 736 #define F_N (1 << 23) 737 /* Opcode dependent field. */ 738 #define F_OD(X) (((X) & 0x7) << 24) 739 /* Instruction has the field of 'sz'. */ 740 #define F_LSE_SZ (1 << 27) 741 /* Require an exact qualifier match, even for NIL qualifiers. */ 742 #define F_STRICT (1ULL << 28) 743 /* Next bit is 29. */ 744 745 static inline bfd_boolean 746 alias_opcode_p (const aarch64_opcode *opcode) 747 { 748 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 749 } 750 751 static inline bfd_boolean 752 opcode_has_alias (const aarch64_opcode *opcode) 753 { 754 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 755 } 756 757 /* Priority for disassembling preference. */ 758 static inline int 759 opcode_priority (const aarch64_opcode *opcode) 760 { 761 return (opcode->flags >> 2) & 0x3; 762 } 763 764 static inline bfd_boolean 765 pseudo_opcode_p (const aarch64_opcode *opcode) 766 { 767 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 768 } 769 770 static inline bfd_boolean 771 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 772 { 773 return (((opcode->flags >> 12) & 0x7) == idx + 1) 774 ? TRUE : FALSE; 775 } 776 777 static inline aarch64_insn 778 get_optional_operand_default_value (const aarch64_opcode *opcode) 779 { 780 return (opcode->flags >> 15) & 0x1f; 781 } 782 783 static inline unsigned int 784 get_opcode_dependent_value (const aarch64_opcode *opcode) 785 { 786 return (opcode->flags >> 24) & 0x7; 787 } 788 789 static inline bfd_boolean 790 opcode_has_special_coder (const aarch64_opcode *opcode) 791 { 792 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 793 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 794 : FALSE; 795 } 796 797 struct aarch64_name_value_pair 798 { 799 const char * name; 800 aarch64_insn value; 801 }; 802 803 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 804 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 805 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 806 extern const struct aarch64_name_value_pair aarch64_hint_options []; 807 808 typedef struct 809 { 810 const char * name; 811 aarch64_insn value; 812 uint32_t flags; 813 } aarch64_sys_reg; 814 815 extern const aarch64_sys_reg aarch64_sys_regs []; 816 extern const aarch64_sys_reg aarch64_pstatefields []; 817 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 818 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, 819 const aarch64_sys_reg *); 820 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, 821 const aarch64_sys_reg *); 822 823 typedef struct 824 { 825 const char *name; 826 uint32_t value; 827 uint32_t flags ; 828 } aarch64_sys_ins_reg; 829 830 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 831 extern bfd_boolean 832 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 833 const aarch64_sys_ins_reg *); 834 835 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 836 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 837 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 838 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 839 840 /* Shift/extending operator kinds. 841 N.B. order is important; keep aarch64_operand_modifiers synced. */ 842 enum aarch64_modifier_kind 843 { 844 AARCH64_MOD_NONE, 845 AARCH64_MOD_MSL, 846 AARCH64_MOD_ROR, 847 AARCH64_MOD_ASR, 848 AARCH64_MOD_LSR, 849 AARCH64_MOD_LSL, 850 AARCH64_MOD_UXTB, 851 AARCH64_MOD_UXTH, 852 AARCH64_MOD_UXTW, 853 AARCH64_MOD_UXTX, 854 AARCH64_MOD_SXTB, 855 AARCH64_MOD_SXTH, 856 AARCH64_MOD_SXTW, 857 AARCH64_MOD_SXTX, 858 AARCH64_MOD_MUL, 859 AARCH64_MOD_MUL_VL, 860 }; 861 862 bfd_boolean 863 aarch64_extend_operator_p (enum aarch64_modifier_kind); 864 865 enum aarch64_modifier_kind 866 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 867 /* Condition. */ 868 869 typedef struct 870 { 871 /* A list of names with the first one as the disassembly preference; 872 terminated by NULL if fewer than 3. */ 873 const char *names[4]; 874 aarch64_insn value; 875 } aarch64_cond; 876 877 extern const aarch64_cond aarch64_conds[16]; 878 879 const aarch64_cond* get_cond_from_value (aarch64_insn value); 880 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 881 882 /* Structure representing an operand. */ 883 884 struct aarch64_opnd_info 885 { 886 enum aarch64_opnd type; 887 aarch64_opnd_qualifier_t qualifier; 888 int idx; 889 890 union 891 { 892 struct 893 { 894 unsigned regno; 895 } reg; 896 struct 897 { 898 unsigned int regno; 899 int64_t index; 900 } reglane; 901 /* e.g. LVn. */ 902 struct 903 { 904 unsigned first_regno : 5; 905 unsigned num_regs : 3; 906 /* 1 if it is a list of reg element. */ 907 unsigned has_index : 1; 908 /* Lane index; valid only when has_index is 1. */ 909 int64_t index; 910 } reglist; 911 /* e.g. immediate or pc relative address offset. */ 912 struct 913 { 914 int64_t value; 915 unsigned is_fp : 1; 916 } imm; 917 /* e.g. address in STR (register offset). */ 918 struct 919 { 920 unsigned base_regno; 921 struct 922 { 923 union 924 { 925 int imm; 926 unsigned regno; 927 }; 928 unsigned is_reg; 929 } offset; 930 unsigned pcrel : 1; /* PC-relative. */ 931 unsigned writeback : 1; 932 unsigned preind : 1; /* Pre-indexed. */ 933 unsigned postind : 1; /* Post-indexed. */ 934 } addr; 935 const aarch64_cond *cond; 936 /* The encoding of the system register. */ 937 aarch64_insn sysreg; 938 /* The encoding of the PSTATE field. */ 939 aarch64_insn pstatefield; 940 const aarch64_sys_ins_reg *sysins_op; 941 const struct aarch64_name_value_pair *barrier; 942 const struct aarch64_name_value_pair *hint_option; 943 const struct aarch64_name_value_pair *prfop; 944 }; 945 946 /* Operand shifter; in use when the operand is a register offset address, 947 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 948 struct 949 { 950 enum aarch64_modifier_kind kind; 951 unsigned operator_present: 1; /* Only valid during encoding. */ 952 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 953 unsigned amount_present: 1; 954 int64_t amount; 955 } shifter; 956 957 unsigned skip:1; /* Operand is not completed if there is a fixup needed 958 to be done on it. In some (but not all) of these 959 cases, we need to tell libopcodes to skip the 960 constraint checking and the encoding for this 961 operand, so that the libopcodes can pick up the 962 right opcode before the operand is fixed-up. This 963 flag should only be used during the 964 assembling/encoding. */ 965 unsigned present:1; /* Whether this operand is present in the assembly 966 line; not used during the disassembly. */ 967 }; 968 969 typedef struct aarch64_opnd_info aarch64_opnd_info; 970 971 /* Structure representing an instruction. 972 973 It is used during both the assembling and disassembling. The assembler 974 fills an aarch64_inst after a successful parsing and then passes it to the 975 encoding routine to do the encoding. During the disassembling, the 976 disassembler calls the decoding routine to decode a binary instruction; on a 977 successful return, such a structure will be filled with information of the 978 instruction; then the disassembler uses the information to print out the 979 instruction. */ 980 981 struct aarch64_inst 982 { 983 /* The value of the binary instruction. */ 984 aarch64_insn value; 985 986 /* Corresponding opcode entry. */ 987 const aarch64_opcode *opcode; 988 989 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 990 const aarch64_cond *cond; 991 992 /* Operands information. */ 993 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 994 }; 995 996 typedef struct aarch64_inst aarch64_inst; 997 998 /* Diagnosis related declaration and interface. */ 999 1000 /* Operand error kind enumerators. 1001 1002 AARCH64_OPDE_RECOVERABLE 1003 Less severe error found during the parsing, very possibly because that 1004 GAS has picked up a wrong instruction template for the parsing. 1005 1006 AARCH64_OPDE_SYNTAX_ERROR 1007 General syntax error; it can be either a user error, or simply because 1008 that GAS is trying a wrong instruction template. 1009 1010 AARCH64_OPDE_FATAL_SYNTAX_ERROR 1011 Definitely a user syntax error. 1012 1013 AARCH64_OPDE_INVALID_VARIANT 1014 No syntax error, but the operands are not a valid combination, e.g. 1015 FMOV D0,S0 1016 1017 AARCH64_OPDE_UNTIED_OPERAND 1018 The asm failed to use the same register for a destination operand 1019 and a tied source operand. 1020 1021 AARCH64_OPDE_OUT_OF_RANGE 1022 Error about some immediate value out of a valid range. 1023 1024 AARCH64_OPDE_UNALIGNED 1025 Error about some immediate value not properly aligned (i.e. not being a 1026 multiple times of a certain value). 1027 1028 AARCH64_OPDE_REG_LIST 1029 Error about the register list operand having unexpected number of 1030 registers. 1031 1032 AARCH64_OPDE_OTHER_ERROR 1033 Error of the highest severity and used for any severe issue that does not 1034 fall into any of the above categories. 1035 1036 The enumerators are only interesting to GAS. They are declared here (in 1037 libopcodes) because that some errors are detected (and then notified to GAS) 1038 by libopcodes (rather than by GAS solely). 1039 1040 The first three errors are only deteced by GAS while the 1041 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 1042 only libopcodes has the information about the valid variants of each 1043 instruction. 1044 1045 The enumerators have an increasing severity. This is helpful when there are 1046 multiple instruction templates available for a given mnemonic name (e.g. 1047 FMOV); this mechanism will help choose the most suitable template from which 1048 the generated diagnostics can most closely describe the issues, if any. */ 1049 1050 enum aarch64_operand_error_kind 1051 { 1052 AARCH64_OPDE_NIL, 1053 AARCH64_OPDE_RECOVERABLE, 1054 AARCH64_OPDE_SYNTAX_ERROR, 1055 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 1056 AARCH64_OPDE_INVALID_VARIANT, 1057 AARCH64_OPDE_UNTIED_OPERAND, 1058 AARCH64_OPDE_OUT_OF_RANGE, 1059 AARCH64_OPDE_UNALIGNED, 1060 AARCH64_OPDE_REG_LIST, 1061 AARCH64_OPDE_OTHER_ERROR 1062 }; 1063 1064 /* N.B. GAS assumes that this structure work well with shallow copy. */ 1065 struct aarch64_operand_error 1066 { 1067 enum aarch64_operand_error_kind kind; 1068 int index; 1069 const char *error; 1070 int data[3]; /* Some data for extra information. */ 1071 }; 1072 1073 typedef struct aarch64_operand_error aarch64_operand_error; 1074 1075 /* Encoding entrypoint. */ 1076 1077 extern int 1078 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 1079 aarch64_insn *, aarch64_opnd_qualifier_t *, 1080 aarch64_operand_error *); 1081 1082 extern const aarch64_opcode * 1083 aarch64_replace_opcode (struct aarch64_inst *, 1084 const aarch64_opcode *); 1085 1086 /* Given the opcode enumerator OP, return the pointer to the corresponding 1087 opcode entry. */ 1088 1089 extern const aarch64_opcode * 1090 aarch64_get_opcode (enum aarch64_op); 1091 1092 /* Generate the string representation of an operand. */ 1093 extern void 1094 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 1095 const aarch64_opnd_info *, int, int *, bfd_vma *); 1096 1097 /* Miscellaneous interface. */ 1098 1099 extern int 1100 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 1101 1102 extern aarch64_opnd_qualifier_t 1103 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 1104 const aarch64_opnd_qualifier_t, int); 1105 1106 extern int 1107 aarch64_num_of_operands (const aarch64_opcode *); 1108 1109 extern int 1110 aarch64_stack_pointer_p (const aarch64_opnd_info *); 1111 1112 extern int 1113 aarch64_zero_register_p (const aarch64_opnd_info *); 1114 1115 extern int 1116 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); 1117 1118 /* Given an operand qualifier, return the expected data element size 1119 of a qualified operand. */ 1120 extern unsigned char 1121 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 1122 1123 extern enum aarch64_operand_class 1124 aarch64_get_operand_class (enum aarch64_opnd); 1125 1126 extern const char * 1127 aarch64_get_operand_name (enum aarch64_opnd); 1128 1129 extern const char * 1130 aarch64_get_operand_desc (enum aarch64_opnd); 1131 1132 extern bfd_boolean 1133 aarch64_sve_dupm_mov_immediate_p (uint64_t, int); 1134 1135 #ifdef DEBUG_AARCH64 1136 extern int debug_dump; 1137 1138 extern void 1139 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 1140 1141 #define DEBUG_TRACE(M, ...) \ 1142 { \ 1143 if (debug_dump) \ 1144 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1145 } 1146 1147 #define DEBUG_TRACE_IF(C, M, ...) \ 1148 { \ 1149 if (debug_dump && (C)) \ 1150 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1151 } 1152 #else /* !DEBUG_AARCH64 */ 1153 #define DEBUG_TRACE(M, ...) ; 1154 #define DEBUG_TRACE_IF(C, M, ...) ; 1155 #endif /* DEBUG_AARCH64 */ 1156 1157 extern const char *const aarch64_sve_pattern_array[32]; 1158 extern const char *const aarch64_sve_prfop_array[16]; 1159 1160 #ifdef __cplusplus 1161 } 1162 #endif 1163 1164 #endif /* OPCODE_AARCH64_H */ 1165