1 /* AArch64 assembler/disassembler support. 2 3 Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 /* The offset for pc-relative addressing is currently defined to be 0. */ 31 #define AARCH64_PCREL_OFFSET 0 32 33 typedef uint32_t aarch64_insn; 34 35 /* The following bitmasks control CPU features. */ 36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 40 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 41 42 /* Architectures are the sum of the base and extensions. */ 43 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 44 AARCH64_FEATURE_FP \ 45 | AARCH64_FEATURE_SIMD) 46 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 47 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 48 49 /* CPU-specific features. */ 50 typedef unsigned long aarch64_feature_set; 51 52 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 53 (((CPU) & (FEAT)) != 0) 54 55 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 56 do \ 57 { \ 58 (TARG) = (F1) | (F2); \ 59 } \ 60 while (0) 61 62 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 63 do \ 64 { \ 65 (TARG) = (F1) &~ (F2); \ 66 } \ 67 while (0) 68 69 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 70 71 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ 72 (((OPC) & (FEAT)) != 0) 73 74 enum aarch64_operand_class 75 { 76 AARCH64_OPND_CLASS_NIL, 77 AARCH64_OPND_CLASS_INT_REG, 78 AARCH64_OPND_CLASS_MODIFIED_REG, 79 AARCH64_OPND_CLASS_FP_REG, 80 AARCH64_OPND_CLASS_SIMD_REG, 81 AARCH64_OPND_CLASS_SIMD_ELEMENT, 82 AARCH64_OPND_CLASS_SISD_REG, 83 AARCH64_OPND_CLASS_SIMD_REGLIST, 84 AARCH64_OPND_CLASS_CP_REG, 85 AARCH64_OPND_CLASS_ADDRESS, 86 AARCH64_OPND_CLASS_IMMEDIATE, 87 AARCH64_OPND_CLASS_SYSTEM, 88 AARCH64_OPND_CLASS_COND, 89 }; 90 91 /* Operand code that helps both parsing and coding. 92 Keep AARCH64_OPERANDS synced. */ 93 94 enum aarch64_opnd 95 { 96 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 97 98 AARCH64_OPND_Rd, /* Integer register as destination. */ 99 AARCH64_OPND_Rn, /* Integer register as source. */ 100 AARCH64_OPND_Rm, /* Integer register as source. */ 101 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 102 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 103 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 104 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 105 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 106 107 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 108 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 109 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 110 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 111 112 AARCH64_OPND_Fd, /* Floating-point Fd. */ 113 AARCH64_OPND_Fn, /* Floating-point Fn. */ 114 AARCH64_OPND_Fm, /* Floating-point Fm. */ 115 AARCH64_OPND_Fa, /* Floating-point Fa. */ 116 AARCH64_OPND_Ft, /* Floating-point Ft. */ 117 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 118 119 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 120 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 121 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 122 123 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 124 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 125 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 126 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 127 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 128 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 129 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 130 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 131 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 132 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 133 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 134 structure to all lanes. */ 135 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 136 137 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 138 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 139 140 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 141 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 142 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 143 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 144 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 145 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 146 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 147 (no encoding). */ 148 AARCH64_OPND_IMM0, /* Immediate for #0. */ 149 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 150 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 151 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 152 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 153 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 154 AARCH64_OPND_IMM, /* Immediate. */ 155 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 156 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 157 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 158 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 159 AARCH64_OPND_BIT_NUM, /* Immediate. */ 160 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 161 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 162 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 163 each condition flag. */ 164 165 AARCH64_OPND_LIMM, /* Logical Immediate. */ 166 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 167 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 168 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 169 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 170 171 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 172 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 173 174 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 175 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 176 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 177 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 178 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 179 180 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 181 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 182 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 183 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 184 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 185 negative or unaligned and there is 186 no writeback allowed. This operand code 187 is only used to support the programmer- 188 friendly feature of using LDR/STR as the 189 the mnemonic name for LDUR/STUR instructions 190 wherever there is no ambiguity. */ 191 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 192 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 193 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 194 195 AARCH64_OPND_SYSREG, /* System register operand. */ 196 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 197 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 198 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 199 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 200 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 201 AARCH64_OPND_BARRIER, /* Barrier operand. */ 202 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 203 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 204 }; 205 206 /* Qualifier constrains an operand. It either specifies a variant of an 207 operand type or limits values available to an operand type. 208 209 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 210 211 enum aarch64_opnd_qualifier 212 { 213 /* Indicating no further qualification on an operand. */ 214 AARCH64_OPND_QLF_NIL, 215 216 /* Qualifying an operand which is a general purpose (integer) register; 217 indicating the operand data size or a specific register. */ 218 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 219 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 220 AARCH64_OPND_QLF_WSP, /* WSP. */ 221 AARCH64_OPND_QLF_SP, /* SP. */ 222 223 /* Qualifying an operand which is a floating-point register, a SIMD 224 vector element or a SIMD vector element list; indicating operand data 225 size or the size of each SIMD vector element in the case of a SIMD 226 vector element list. 227 These qualifiers are also used to qualify an address operand to 228 indicate the size of data element a load/store instruction is 229 accessing. 230 They are also used for the immediate shift operand in e.g. SSHR. Such 231 a use is only for the ease of operand encoding/decoding and qualifier 232 sequence matching; such a use should not be applied widely; use the value 233 constraint qualifiers for immediate operands wherever possible. */ 234 AARCH64_OPND_QLF_S_B, 235 AARCH64_OPND_QLF_S_H, 236 AARCH64_OPND_QLF_S_S, 237 AARCH64_OPND_QLF_S_D, 238 AARCH64_OPND_QLF_S_Q, 239 240 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 241 register list; indicating register shape. 242 They are also used for the immediate shift operand in e.g. SSHR. Such 243 a use is only for the ease of operand encoding/decoding and qualifier 244 sequence matching; such a use should not be applied widely; use the value 245 constraint qualifiers for immediate operands wherever possible. */ 246 AARCH64_OPND_QLF_V_8B, 247 AARCH64_OPND_QLF_V_16B, 248 AARCH64_OPND_QLF_V_4H, 249 AARCH64_OPND_QLF_V_8H, 250 AARCH64_OPND_QLF_V_2S, 251 AARCH64_OPND_QLF_V_4S, 252 AARCH64_OPND_QLF_V_1D, 253 AARCH64_OPND_QLF_V_2D, 254 AARCH64_OPND_QLF_V_1Q, 255 256 /* Constraint on value. */ 257 AARCH64_OPND_QLF_imm_0_7, 258 AARCH64_OPND_QLF_imm_0_15, 259 AARCH64_OPND_QLF_imm_0_31, 260 AARCH64_OPND_QLF_imm_0_63, 261 AARCH64_OPND_QLF_imm_1_32, 262 AARCH64_OPND_QLF_imm_1_64, 263 264 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 265 or shift-ones. */ 266 AARCH64_OPND_QLF_LSL, 267 AARCH64_OPND_QLF_MSL, 268 269 /* Special qualifier helping retrieve qualifier information during the 270 decoding time (currently not in use). */ 271 AARCH64_OPND_QLF_RETRIEVE, 272 }; 273 274 /* Instruction class. */ 275 276 enum aarch64_insn_class 277 { 278 addsub_carry, 279 addsub_ext, 280 addsub_imm, 281 addsub_shift, 282 asimdall, 283 asimddiff, 284 asimdelem, 285 asimdext, 286 asimdimm, 287 asimdins, 288 asimdmisc, 289 asimdperm, 290 asimdsame, 291 asimdshf, 292 asimdtbl, 293 asisddiff, 294 asisdelem, 295 asisdlse, 296 asisdlsep, 297 asisdlso, 298 asisdlsop, 299 asisdmisc, 300 asisdone, 301 asisdpair, 302 asisdsame, 303 asisdshf, 304 bitfield, 305 branch_imm, 306 branch_reg, 307 compbranch, 308 condbranch, 309 condcmp_imm, 310 condcmp_reg, 311 condsel, 312 cryptoaes, 313 cryptosha2, 314 cryptosha3, 315 dp_1src, 316 dp_2src, 317 dp_3src, 318 exception, 319 extract, 320 float2fix, 321 float2int, 322 floatccmp, 323 floatcmp, 324 floatdp1, 325 floatdp2, 326 floatdp3, 327 floatimm, 328 floatsel, 329 ldst_immpost, 330 ldst_immpre, 331 ldst_imm9, /* immpost or immpre */ 332 ldst_pos, 333 ldst_regoff, 334 ldst_unpriv, 335 ldst_unscaled, 336 ldstexcl, 337 ldstnapair_offs, 338 ldstpair_off, 339 ldstpair_indexed, 340 loadlit, 341 log_imm, 342 log_shift, 343 movewide, 344 pcreladdr, 345 ic_system, 346 testbranch, 347 }; 348 349 /* Opcode enumerators. */ 350 351 enum aarch64_op 352 { 353 OP_NIL, 354 OP_STRB_POS, 355 OP_LDRB_POS, 356 OP_LDRSB_POS, 357 OP_STRH_POS, 358 OP_LDRH_POS, 359 OP_LDRSH_POS, 360 OP_STR_POS, 361 OP_LDR_POS, 362 OP_STRF_POS, 363 OP_LDRF_POS, 364 OP_LDRSW_POS, 365 OP_PRFM_POS, 366 367 OP_STURB, 368 OP_LDURB, 369 OP_LDURSB, 370 OP_STURH, 371 OP_LDURH, 372 OP_LDURSH, 373 OP_STUR, 374 OP_LDUR, 375 OP_STURV, 376 OP_LDURV, 377 OP_LDURSW, 378 OP_PRFUM, 379 380 OP_LDR_LIT, 381 OP_LDRV_LIT, 382 OP_LDRSW_LIT, 383 OP_PRFM_LIT, 384 385 OP_ADD, 386 OP_B, 387 OP_BL, 388 389 OP_MOVN, 390 OP_MOVZ, 391 OP_MOVK, 392 393 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 394 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 395 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 396 397 OP_MOV_V, /* MOV alias for moving vector register. */ 398 399 OP_ASR_IMM, 400 OP_LSR_IMM, 401 OP_LSL_IMM, 402 403 OP_BIC, 404 405 OP_UBFX, 406 OP_BFXIL, 407 OP_SBFX, 408 OP_SBFIZ, 409 OP_BFI, 410 OP_UBFIZ, 411 OP_UXTB, 412 OP_UXTH, 413 OP_UXTW, 414 415 OP_CINC, 416 OP_CINV, 417 OP_CNEG, 418 OP_CSET, 419 OP_CSETM, 420 421 OP_FCVT, 422 OP_FCVTN, 423 OP_FCVTN2, 424 OP_FCVTL, 425 OP_FCVTL2, 426 OP_FCVTXN_S, /* Scalar version. */ 427 428 OP_ROR_IMM, 429 430 OP_SXTL, 431 OP_SXTL2, 432 OP_UXTL, 433 OP_UXTL2, 434 435 OP_TOTAL_NUM, /* Pseudo. */ 436 }; 437 438 /* Maximum number of operands an instruction can have. */ 439 #define AARCH64_MAX_OPND_NUM 6 440 /* Maximum number of qualifier sequences an instruction can have. */ 441 #define AARCH64_MAX_QLF_SEQ_NUM 10 442 /* Operand qualifier typedef; optimized for the size. */ 443 typedef unsigned char aarch64_opnd_qualifier_t; 444 /* Operand qualifier sequence typedef. */ 445 typedef aarch64_opnd_qualifier_t \ 446 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 447 448 /* FIXME: improve the efficiency. */ 449 static inline bfd_boolean 450 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 451 { 452 int i; 453 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 454 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 455 return FALSE; 456 return TRUE; 457 } 458 459 /* This structure holds information for a particular opcode. */ 460 461 struct aarch64_opcode 462 { 463 /* The name of the mnemonic. */ 464 const char *name; 465 466 /* The opcode itself. Those bits which will be filled in with 467 operands are zeroes. */ 468 aarch64_insn opcode; 469 470 /* The opcode mask. This is used by the disassembler. This is a 471 mask containing ones indicating those bits which must match the 472 opcode field, and zeroes indicating those bits which need not 473 match (and are presumably filled in by operands). */ 474 aarch64_insn mask; 475 476 /* Instruction class. */ 477 enum aarch64_insn_class iclass; 478 479 /* Enumerator identifier. */ 480 enum aarch64_op op; 481 482 /* Which architecture variant provides this instruction. */ 483 const aarch64_feature_set *avariant; 484 485 /* An array of operand codes. Each code is an index into the 486 operand table. They appear in the order which the operands must 487 appear in assembly code, and are terminated by a zero. */ 488 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 489 490 /* A list of operand qualifier code sequence. Each operand qualifier 491 code qualifies the corresponding operand code. Each operand 492 qualifier sequence specifies a valid opcode variant and related 493 constraint on operands. */ 494 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 495 496 /* Flags providing information about this instruction */ 497 uint32_t flags; 498 }; 499 500 typedef struct aarch64_opcode aarch64_opcode; 501 502 /* Table describing all the AArch64 opcodes. */ 503 extern aarch64_opcode aarch64_opcode_table[]; 504 505 /* Opcode flags. */ 506 #define F_ALIAS (1 << 0) 507 #define F_HAS_ALIAS (1 << 1) 508 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 509 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 510 #define F_P1 (1 << 2) 511 #define F_P2 (2 << 2) 512 #define F_P3 (3 << 2) 513 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 514 #define F_COND (1 << 4) 515 /* Instruction has the field of 'sf'. */ 516 #define F_SF (1 << 5) 517 /* Instruction has the field of 'size:Q'. */ 518 #define F_SIZEQ (1 << 6) 519 /* Floating-point instruction has the field of 'type'. */ 520 #define F_FPTYPE (1 << 7) 521 /* AdvSIMD scalar instruction has the field of 'size'. */ 522 #define F_SSIZE (1 << 8) 523 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 524 #define F_T (1 << 9) 525 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 526 #define F_GPRSIZE_IN_Q (1 << 10) 527 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 528 #define F_LDS_SIZE (1 << 11) 529 /* Optional operand; assume maximum of 1 operand can be optional. */ 530 #define F_OPD0_OPT (1 << 12) 531 #define F_OPD1_OPT (2 << 12) 532 #define F_OPD2_OPT (3 << 12) 533 #define F_OPD3_OPT (4 << 12) 534 #define F_OPD4_OPT (5 << 12) 535 /* Default value for the optional operand when omitted from the assembly. */ 536 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 537 /* Instruction that is an alias of another instruction needs to be 538 encoded/decoded by converting it to/from the real form, followed by 539 the encoding/decoding according to the rules of the real opcode. 540 This compares to the direct coding using the alias's information. 541 N.B. this flag requires F_ALIAS to be used together. */ 542 #define F_CONV (1 << 20) 543 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 544 friendly pseudo instruction available only in the assembly code (thus will 545 not show up in the disassembly). */ 546 #define F_PSEUDO (1 << 21) 547 /* Instruction has miscellaneous encoding/decoding rules. */ 548 #define F_MISC (1 << 22) 549 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 550 #define F_N (1 << 23) 551 /* Opcode dependent field. */ 552 #define F_OD(X) (((X) & 0x7) << 24) 553 /* Next bit is 27. */ 554 555 static inline bfd_boolean 556 alias_opcode_p (const aarch64_opcode *opcode) 557 { 558 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 559 } 560 561 static inline bfd_boolean 562 opcode_has_alias (const aarch64_opcode *opcode) 563 { 564 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 565 } 566 567 /* Priority for disassembling preference. */ 568 static inline int 569 opcode_priority (const aarch64_opcode *opcode) 570 { 571 return (opcode->flags >> 2) & 0x3; 572 } 573 574 static inline bfd_boolean 575 pseudo_opcode_p (const aarch64_opcode *opcode) 576 { 577 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 578 } 579 580 static inline bfd_boolean 581 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 582 { 583 return (((opcode->flags >> 12) & 0x7) == idx + 1) 584 ? TRUE : FALSE; 585 } 586 587 static inline aarch64_insn 588 get_optional_operand_default_value (const aarch64_opcode *opcode) 589 { 590 return (opcode->flags >> 15) & 0x1f; 591 } 592 593 static inline unsigned int 594 get_opcode_dependent_value (const aarch64_opcode *opcode) 595 { 596 return (opcode->flags >> 24) & 0x7; 597 } 598 599 static inline bfd_boolean 600 opcode_has_special_coder (const aarch64_opcode *opcode) 601 { 602 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 603 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 604 : FALSE; 605 } 606 607 struct aarch64_name_value_pair 608 { 609 const char * name; 610 aarch64_insn value; 611 }; 612 613 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 614 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 615 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 616 617 typedef struct 618 { 619 const char * name; 620 aarch64_insn value; 621 uint32_t flags; 622 } aarch64_sys_reg; 623 624 extern const aarch64_sys_reg aarch64_sys_regs []; 625 extern const aarch64_sys_reg aarch64_pstatefields []; 626 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 627 628 typedef struct 629 { 630 const char *template; 631 uint32_t value; 632 int has_xt; 633 } aarch64_sys_ins_reg; 634 635 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 636 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 637 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 638 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 639 640 /* Shift/extending operator kinds. 641 N.B. order is important; keep aarch64_operand_modifiers synced. */ 642 enum aarch64_modifier_kind 643 { 644 AARCH64_MOD_NONE, 645 AARCH64_MOD_MSL, 646 AARCH64_MOD_ROR, 647 AARCH64_MOD_ASR, 648 AARCH64_MOD_LSR, 649 AARCH64_MOD_LSL, 650 AARCH64_MOD_UXTB, 651 AARCH64_MOD_UXTH, 652 AARCH64_MOD_UXTW, 653 AARCH64_MOD_UXTX, 654 AARCH64_MOD_SXTB, 655 AARCH64_MOD_SXTH, 656 AARCH64_MOD_SXTW, 657 AARCH64_MOD_SXTX, 658 }; 659 660 bfd_boolean 661 aarch64_extend_operator_p (enum aarch64_modifier_kind); 662 663 enum aarch64_modifier_kind 664 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 665 /* Condition. */ 666 667 typedef struct 668 { 669 /* A list of names with the first one as the disassembly preference; 670 terminated by NULL if fewer than 3. */ 671 const char *names[3]; 672 aarch64_insn value; 673 } aarch64_cond; 674 675 extern const aarch64_cond aarch64_conds[16]; 676 677 const aarch64_cond* get_cond_from_value (aarch64_insn value); 678 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 679 680 /* Structure representing an operand. */ 681 682 struct aarch64_opnd_info 683 { 684 enum aarch64_opnd type; 685 aarch64_opnd_qualifier_t qualifier; 686 int idx; 687 688 union 689 { 690 struct 691 { 692 unsigned regno; 693 } reg; 694 struct 695 { 696 unsigned regno : 5; 697 unsigned index : 4; 698 } reglane; 699 /* e.g. LVn. */ 700 struct 701 { 702 unsigned first_regno : 5; 703 unsigned num_regs : 3; 704 /* 1 if it is a list of reg element. */ 705 unsigned has_index : 1; 706 /* Lane index; valid only when has_index is 1. */ 707 unsigned index : 4; 708 } reglist; 709 /* e.g. immediate or pc relative address offset. */ 710 struct 711 { 712 int64_t value; 713 unsigned is_fp : 1; 714 } imm; 715 /* e.g. address in STR (register offset). */ 716 struct 717 { 718 unsigned base_regno; 719 struct 720 { 721 union 722 { 723 int imm; 724 unsigned regno; 725 }; 726 unsigned is_reg; 727 } offset; 728 unsigned pcrel : 1; /* PC-relative. */ 729 unsigned writeback : 1; 730 unsigned preind : 1; /* Pre-indexed. */ 731 unsigned postind : 1; /* Post-indexed. */ 732 } addr; 733 const aarch64_cond *cond; 734 /* The encoding of the system register. */ 735 aarch64_insn sysreg; 736 /* The encoding of the PSTATE field. */ 737 aarch64_insn pstatefield; 738 const aarch64_sys_ins_reg *sysins_op; 739 const struct aarch64_name_value_pair *barrier; 740 const struct aarch64_name_value_pair *prfop; 741 }; 742 743 /* Operand shifter; in use when the operand is a register offset address, 744 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 745 struct 746 { 747 enum aarch64_modifier_kind kind; 748 int amount; 749 unsigned operator_present: 1; /* Only valid during encoding. */ 750 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 751 unsigned amount_present: 1; 752 } shifter; 753 754 unsigned skip:1; /* Operand is not completed if there is a fixup needed 755 to be done on it. In some (but not all) of these 756 cases, we need to tell libopcodes to skip the 757 constraint checking and the encoding for this 758 operand, so that the libopcodes can pick up the 759 right opcode before the operand is fixed-up. This 760 flag should only be used during the 761 assembling/encoding. */ 762 unsigned present:1; /* Whether this operand is present in the assembly 763 line; not used during the disassembly. */ 764 }; 765 766 typedef struct aarch64_opnd_info aarch64_opnd_info; 767 768 /* Structure representing an instruction. 769 770 It is used during both the assembling and disassembling. The assembler 771 fills an aarch64_inst after a successful parsing and then passes it to the 772 encoding routine to do the encoding. During the disassembling, the 773 disassembler calls the decoding routine to decode a binary instruction; on a 774 successful return, such a structure will be filled with information of the 775 instruction; then the disassembler uses the information to print out the 776 instruction. */ 777 778 struct aarch64_inst 779 { 780 /* The value of the binary instruction. */ 781 aarch64_insn value; 782 783 /* Corresponding opcode entry. */ 784 const aarch64_opcode *opcode; 785 786 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 787 const aarch64_cond *cond; 788 789 /* Operands information. */ 790 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 791 }; 792 793 typedef struct aarch64_inst aarch64_inst; 794 795 /* Diagnosis related declaration and interface. */ 796 797 /* Operand error kind enumerators. 798 799 AARCH64_OPDE_RECOVERABLE 800 Less severe error found during the parsing, very possibly because that 801 GAS has picked up a wrong instruction template for the parsing. 802 803 AARCH64_OPDE_SYNTAX_ERROR 804 General syntax error; it can be either a user error, or simply because 805 that GAS is trying a wrong instruction template. 806 807 AARCH64_OPDE_FATAL_SYNTAX_ERROR 808 Definitely a user syntax error. 809 810 AARCH64_OPDE_INVALID_VARIANT 811 No syntax error, but the operands are not a valid combination, e.g. 812 FMOV D0,S0 813 814 AARCH64_OPDE_OUT_OF_RANGE 815 Error about some immediate value out of a valid range. 816 817 AARCH64_OPDE_UNALIGNED 818 Error about some immediate value not properly aligned (i.e. not being a 819 multiple times of a certain value). 820 821 AARCH64_OPDE_REG_LIST 822 Error about the register list operand having unexpected number of 823 registers. 824 825 AARCH64_OPDE_OTHER_ERROR 826 Error of the highest severity and used for any severe issue that does not 827 fall into any of the above categories. 828 829 The enumerators are only interesting to GAS. They are declared here (in 830 libopcodes) because that some errors are detected (and then notified to GAS) 831 by libopcodes (rather than by GAS solely). 832 833 The first three errors are only deteced by GAS while the 834 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 835 only libopcodes has the information about the valid variants of each 836 instruction. 837 838 The enumerators have an increasing severity. This is helpful when there are 839 multiple instruction templates available for a given mnemonic name (e.g. 840 FMOV); this mechanism will help choose the most suitable template from which 841 the generated diagnostics can most closely describe the issues, if any. */ 842 843 enum aarch64_operand_error_kind 844 { 845 AARCH64_OPDE_NIL, 846 AARCH64_OPDE_RECOVERABLE, 847 AARCH64_OPDE_SYNTAX_ERROR, 848 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 849 AARCH64_OPDE_INVALID_VARIANT, 850 AARCH64_OPDE_OUT_OF_RANGE, 851 AARCH64_OPDE_UNALIGNED, 852 AARCH64_OPDE_REG_LIST, 853 AARCH64_OPDE_OTHER_ERROR 854 }; 855 856 /* N.B. GAS assumes that this structure work well with shallow copy. */ 857 struct aarch64_operand_error 858 { 859 enum aarch64_operand_error_kind kind; 860 int index; 861 const char *error; 862 int data[3]; /* Some data for extra information. */ 863 }; 864 865 typedef struct aarch64_operand_error aarch64_operand_error; 866 867 /* Encoding entrypoint. */ 868 869 extern int 870 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 871 aarch64_insn *, aarch64_opnd_qualifier_t *, 872 aarch64_operand_error *); 873 874 extern const aarch64_opcode * 875 aarch64_replace_opcode (struct aarch64_inst *, 876 const aarch64_opcode *); 877 878 /* Given the opcode enumerator OP, return the pointer to the corresponding 879 opcode entry. */ 880 881 extern const aarch64_opcode * 882 aarch64_get_opcode (enum aarch64_op); 883 884 /* Generate the string representation of an operand. */ 885 extern void 886 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 887 const aarch64_opnd_info *, int, int *, bfd_vma *); 888 889 /* Miscellaneous interface. */ 890 891 extern int 892 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 893 894 extern aarch64_opnd_qualifier_t 895 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 896 const aarch64_opnd_qualifier_t, int); 897 898 extern int 899 aarch64_num_of_operands (const aarch64_opcode *); 900 901 extern int 902 aarch64_stack_pointer_p (const aarch64_opnd_info *); 903 904 extern 905 int aarch64_zero_register_p (const aarch64_opnd_info *); 906 907 /* Given an operand qualifier, return the expected data element size 908 of a qualified operand. */ 909 extern unsigned char 910 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 911 912 extern enum aarch64_operand_class 913 aarch64_get_operand_class (enum aarch64_opnd); 914 915 extern const char * 916 aarch64_get_operand_name (enum aarch64_opnd); 917 918 extern const char * 919 aarch64_get_operand_desc (enum aarch64_opnd); 920 921 #ifdef DEBUG_AARCH64 922 extern int debug_dump; 923 924 extern void 925 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 926 927 #define DEBUG_TRACE(M, ...) \ 928 { \ 929 if (debug_dump) \ 930 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 931 } 932 933 #define DEBUG_TRACE_IF(C, M, ...) \ 934 { \ 935 if (debug_dump && (C)) \ 936 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 937 } 938 #else /* !DEBUG_AARCH64 */ 939 #define DEBUG_TRACE(M, ...) ; 940 #define DEBUG_TRACE_IF(C, M, ...) ; 941 #endif /* DEBUG_AARCH64 */ 942 943 #endif /* OPCODE_AARCH64_H */ 944