1 /* Target dependent code for GDB on TI C6x systems. 2 3 Copyright (C) 2010-2016 Free Software Foundation, Inc. 4 Contributed by Andrew Jenner <andrew@codesourcery.com> 5 Contributed by Yao Qi <yao@codesourcery.com> 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "frame.h" 24 #include "frame-unwind.h" 25 #include "frame-base.h" 26 #include "trad-frame.h" 27 #include "dwarf2-frame.h" 28 #include "symtab.h" 29 #include "inferior.h" 30 #include "gdbtypes.h" 31 #include "gdbcore.h" 32 #include "gdbcmd.h" 33 #include "target.h" 34 #include "dis-asm.h" 35 #include "regcache.h" 36 #include "value.h" 37 #include "symfile.h" 38 #include "arch-utils.h" 39 #include "floatformat.h" 40 #include "glibc-tdep.h" 41 #include "infcall.h" 42 #include "regset.h" 43 #include "tramp-frame.h" 44 #include "linux-tdep.h" 45 #include "solib.h" 46 #include "objfiles.h" 47 #include "osabi.h" 48 #include "tic6x-tdep.h" 49 #include "language.h" 50 #include "target-descriptions.h" 51 52 #include "features/tic6x-c64xp.c" 53 #include "features/tic6x-c64x.c" 54 #include "features/tic6x-c62x.c" 55 56 #define TIC6X_OPCODE_SIZE 4 57 #define TIC6X_FETCH_PACKET_SIZE 32 58 59 #define INST_S_BIT(INST) ((INST >> 1) & 1) 60 #define INST_X_BIT(INST) ((INST >> 12) & 1) 61 62 const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 }; 63 const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 }; 64 65 struct tic6x_unwind_cache 66 { 67 /* The frame's base, optionally used by the high-level debug info. */ 68 CORE_ADDR base; 69 70 /* The previous frame's inner most stack address. Used as this 71 frame ID's stack_addr. */ 72 CORE_ADDR cfa; 73 74 /* The address of the first instruction in this function */ 75 CORE_ADDR pc; 76 77 /* Which register holds the return address for the frame. */ 78 int return_regnum; 79 80 /* The offset of register saved on stack. If register is not saved, the 81 corresponding element is -1. */ 82 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS]; 83 }; 84 85 86 /* Name of TI C6x core registers. */ 87 static const char *const tic6x_register_names[] = 88 { 89 "A0", "A1", "A2", "A3", /* 0 1 2 3 */ 90 "A4", "A5", "A6", "A7", /* 4 5 6 7 */ 91 "A8", "A9", "A10", "A11", /* 8 9 10 11 */ 92 "A12", "A13", "A14", "A15", /* 12 13 14 15 */ 93 "B0", "B1", "B2", "B3", /* 16 17 18 19 */ 94 "B4", "B5", "B6", "B7", /* 20 21 22 23 */ 95 "B8", "B9", "B10", "B11", /* 24 25 26 27 */ 96 "B12", "B13", "B14", "B15", /* 28 29 30 31 */ 97 "CSR", "PC", /* 32 33 */ 98 }; 99 100 /* This array maps the arguments to the register number which passes argument 101 in function call according to C6000 ELF ABI. */ 102 static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 }; 103 104 /* This is the implementation of gdbarch method register_name. */ 105 106 static const char * 107 tic6x_register_name (struct gdbarch *gdbarch, int regno) 108 { 109 if (regno < 0) 110 return NULL; 111 112 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 113 return tdesc_register_name (gdbarch, regno); 114 else if (regno >= ARRAY_SIZE (tic6x_register_names)) 115 return ""; 116 else 117 return tic6x_register_names[regno]; 118 } 119 120 /* This is the implementation of gdbarch method register_type. */ 121 122 static struct type * 123 tic6x_register_type (struct gdbarch *gdbarch, int regno) 124 { 125 126 if (regno == TIC6X_PC_REGNUM) 127 return builtin_type (gdbarch)->builtin_func_ptr; 128 else 129 return builtin_type (gdbarch)->builtin_uint32; 130 } 131 132 static void 133 tic6x_setup_default (struct tic6x_unwind_cache *cache) 134 { 135 int i; 136 137 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) 138 cache->reg_saved[i] = -1; 139 } 140 141 static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR); 142 static int tic6x_register_number (int reg, int side, int crosspath); 143 144 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly. 145 Bail out early if CURRENT_PC is reached. Returns the address of the first 146 instruction after the prologue. */ 147 148 static CORE_ADDR 149 tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, 150 const CORE_ADDR current_pc, 151 struct tic6x_unwind_cache *cache, 152 struct frame_info *this_frame) 153 { 154 unsigned long inst; 155 unsigned int src_reg, base_reg, dst_reg; 156 int i; 157 CORE_ADDR pc = start_pc; 158 CORE_ADDR return_pc = start_pc; 159 int frame_base_offset_to_sp = 0; 160 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */ 161 int non_stw_insn_counter = 0; 162 163 if (start_pc >= current_pc) 164 return_pc = current_pc; 165 166 cache->base = 0; 167 168 /* The landmarks in prologue is one or two SUB instructions to SP. 169 Instructions on setting up dsbt are in the last part of prologue, if 170 needed. In maxim, prologue can be divided to three parts by two 171 `sub sp, xx, sp' insns. */ 172 173 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the 174 2nd one is optional. */ 175 while (pc < current_pc) 176 { 177 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); 178 179 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0 180 || (inst & 0x0ffc) == 0x9c0) 181 { 182 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */ 183 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, 184 INST_S_BIT (inst), 0); 185 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f, 186 INST_S_BIT (inst), 0); 187 188 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM) 189 { 190 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to 191 offset. The constant offset is decoded in bit 13-17 in all 192 these three kinds of instructions. */ 193 unsigned int ucst5 = (inst >> 13) & 0x1f; 194 195 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */ 196 frame_base_offset_to_sp += ucst5 << 2; 197 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */ 198 frame_base_offset_to_sp += ucst5 << 1; 199 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */ 200 frame_base_offset_to_sp += ucst5; 201 else 202 gdb_assert_not_reached ("unexpected instruction"); 203 204 return_pc = pc + 4; 205 } 206 } 207 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */ 208 { 209 /* The y bit determines which file base is read from. */ 210 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, 211 (inst >> 7) & 1, 0); 212 213 if (base_reg == TIC6X_SP_REGNUM) 214 { 215 src_reg = tic6x_register_number ((inst >> 23) & 0x1f, 216 INST_S_BIT (inst), 0); 217 218 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2; 219 220 return_pc = pc + 4; 221 } 222 non_stw_insn_counter = 0; 223 } 224 else 225 { 226 non_stw_insn_counter++; 227 /* Following instruction sequence may be emitted in prologue: 228 229 <+0>: subah .D2 b15,28,b15 230 <+4>: or .L2X 0,a4,b0 231 <+8>: || stw .D2T2 b14,*+b15(56) 232 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220> 233 <+16>:|| stw .D2T1 a10,*+b15(48) 234 <+20>:stw .D2T2 b3,*+b15(52) 235 <+24>:stw .D2T1 a4,*+b15(40) 236 237 we should look forward for next instruction instead of breaking loop 238 here. So far, we allow almost two sequential non-stw instructions 239 in prologue. */ 240 if (non_stw_insn_counter >= 2) 241 break; 242 } 243 244 245 pc += 4; 246 } 247 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like, 248 ldw .D2T2 *+b14(0),b14 */ 249 inst = tic6x_fetch_instruction (gdbarch, pc); 250 /* The s bit determines which file dst will be loaded into, same effect as 251 other places. */ 252 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0); 253 /* The y bit (bit 7), instead of s bit, determines which file base be 254 used. */ 255 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0); 256 257 if ((inst & 0x164) == 0x64 /* ldw */ 258 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */ 259 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */ 260 { 261 return_pc = pc + 4; 262 } 263 264 if (this_frame) 265 { 266 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); 267 268 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1) 269 { 270 /* If the FP now holds an offset from the CFA then this is a frame 271 which uses the frame pointer. */ 272 273 cache->cfa = get_frame_register_unsigned (this_frame, 274 TIC6X_FP_REGNUM); 275 } 276 else 277 { 278 /* FP doesn't hold an offset from the CFA. If SP still holds an 279 offset from the CFA then we might be in a function which omits 280 the frame pointer. */ 281 282 cache->cfa = cache->base + frame_base_offset_to_sp; 283 } 284 } 285 286 /* Adjust all the saved registers such that they contain addresses 287 instead of offsets. */ 288 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) 289 if (cache->reg_saved[i] != -1) 290 cache->reg_saved[i] = cache->base + cache->reg_saved[i]; 291 292 return return_pc; 293 } 294 295 /* This is the implementation of gdbarch method skip_prologue. */ 296 297 static CORE_ADDR 298 tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 299 { 300 CORE_ADDR func_addr; 301 struct tic6x_unwind_cache cache; 302 303 /* See if we can determine the end of the prologue via the symbol table. 304 If so, then return either PC, or the PC after the prologue, whichever is 305 greater. */ 306 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 307 { 308 CORE_ADDR post_prologue_pc 309 = skip_prologue_using_sal (gdbarch, func_addr); 310 if (post_prologue_pc != 0) 311 return max (start_pc, post_prologue_pc); 312 } 313 314 /* Can't determine prologue from the symbol table, need to examine 315 instructions. */ 316 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 317 NULL); 318 } 319 320 /* This is the implementation of gdbarch method breakpiont_from_pc. */ 321 322 static const gdb_byte * 323 tic6x_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, 324 int *bp_size) 325 { 326 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 327 328 *bp_size = 4; 329 330 if (tdep == NULL || tdep->breakpoint == NULL) 331 { 332 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch)) 333 return tic6x_bkpt_illegal_opcode_be; 334 else 335 return tic6x_bkpt_illegal_opcode_le; 336 } 337 else 338 return tdep->breakpoint; 339 } 340 341 /* This is the implementation of gdbarch method print_insn. */ 342 343 static int 344 tic6x_print_insn (bfd_vma memaddr, disassemble_info *info) 345 { 346 return print_insn_tic6x (memaddr, info); 347 } 348 349 static void 350 tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 351 struct dwarf2_frame_state_reg *reg, 352 struct frame_info *this_frame) 353 { 354 /* Mark the PC as the destination for the return address. */ 355 if (regnum == gdbarch_pc_regnum (gdbarch)) 356 reg->how = DWARF2_FRAME_REG_RA; 357 358 /* Mark the stack pointer as the call frame address. */ 359 else if (regnum == gdbarch_sp_regnum (gdbarch)) 360 reg->how = DWARF2_FRAME_REG_CFA; 361 362 /* The above was taken from the default init_reg in dwarf2-frame.c 363 while the below is c6x specific. */ 364 365 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as 366 callee-save. */ 367 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31)) 368 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 369 else 370 /* All other registers are caller-save. */ 371 reg->how = DWARF2_FRAME_REG_UNDEFINED; 372 } 373 374 /* This is the implementation of gdbarch method unwind_pc. */ 375 376 static CORE_ADDR 377 tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 378 { 379 gdb_byte buf[8]; 380 381 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf); 382 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 383 } 384 385 /* This is the implementation of gdbarch method unwind_sp. */ 386 387 static CORE_ADDR 388 tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) 389 { 390 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM); 391 } 392 393 394 /* Frame base handling. */ 395 396 static struct tic6x_unwind_cache* 397 tic6x_frame_unwind_cache (struct frame_info *this_frame, 398 void **this_prologue_cache) 399 { 400 struct gdbarch *gdbarch = get_frame_arch (this_frame); 401 CORE_ADDR current_pc; 402 struct tic6x_unwind_cache *cache; 403 404 if (*this_prologue_cache) 405 return (struct tic6x_unwind_cache *) *this_prologue_cache; 406 407 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); 408 (*this_prologue_cache) = cache; 409 410 cache->return_regnum = TIC6X_RA_REGNUM; 411 412 tic6x_setup_default (cache); 413 414 cache->pc = get_frame_func (this_frame); 415 current_pc = get_frame_pc (this_frame); 416 417 /* Prologue analysis does the rest... */ 418 if (cache->pc != 0) 419 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); 420 421 return cache; 422 } 423 424 static void 425 tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache, 426 struct frame_id *this_id) 427 { 428 struct tic6x_unwind_cache *cache = 429 tic6x_frame_unwind_cache (this_frame, this_cache); 430 431 /* This marks the outermost frame. */ 432 if (cache->base == 0) 433 return; 434 435 (*this_id) = frame_id_build (cache->cfa, cache->pc); 436 } 437 438 static struct value * 439 tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache, 440 int regnum) 441 { 442 struct tic6x_unwind_cache *cache = 443 tic6x_frame_unwind_cache (this_frame, this_cache); 444 445 gdb_assert (regnum >= 0); 446 447 /* The PC of the previous frame is stored in the RA register of 448 the current frame. Frob regnum so that we pull the value from 449 the correct place. */ 450 if (regnum == TIC6X_PC_REGNUM) 451 regnum = cache->return_regnum; 452 453 if (regnum == TIC6X_SP_REGNUM && cache->cfa) 454 return frame_unwind_got_constant (this_frame, regnum, cache->cfa); 455 456 /* If we've worked out where a register is stored then load it from 457 there. */ 458 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1) 459 return frame_unwind_got_memory (this_frame, regnum, 460 cache->reg_saved[regnum]); 461 462 return frame_unwind_got_register (this_frame, regnum, regnum); 463 } 464 465 static CORE_ADDR 466 tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache) 467 { 468 struct tic6x_unwind_cache *info 469 = tic6x_frame_unwind_cache (this_frame, this_cache); 470 return info->base; 471 } 472 473 static const struct frame_unwind tic6x_frame_unwind = 474 { 475 NORMAL_FRAME, 476 default_frame_unwind_stop_reason, 477 tic6x_frame_this_id, 478 tic6x_frame_prev_register, 479 NULL, 480 default_frame_sniffer 481 }; 482 483 static const struct frame_base tic6x_frame_base = 484 { 485 &tic6x_frame_unwind, 486 tic6x_frame_base_address, 487 tic6x_frame_base_address, 488 tic6x_frame_base_address 489 }; 490 491 492 static struct tic6x_unwind_cache * 493 tic6x_make_stub_cache (struct frame_info *this_frame) 494 { 495 struct tic6x_unwind_cache *cache; 496 497 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); 498 499 cache->return_regnum = TIC6X_RA_REGNUM; 500 501 tic6x_setup_default (cache); 502 503 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); 504 505 return cache; 506 } 507 508 static void 509 tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache, 510 struct frame_id *this_id) 511 { 512 struct tic6x_unwind_cache *cache; 513 514 if (*this_cache == NULL) 515 *this_cache = tic6x_make_stub_cache (this_frame); 516 cache = (struct tic6x_unwind_cache *) *this_cache; 517 518 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame)); 519 } 520 521 static int 522 tic6x_stub_unwind_sniffer (const struct frame_unwind *self, 523 struct frame_info *this_frame, 524 void **this_prologue_cache) 525 { 526 CORE_ADDR addr_in_block; 527 528 addr_in_block = get_frame_address_in_block (this_frame); 529 if (in_plt_section (addr_in_block)) 530 return 1; 531 532 return 0; 533 } 534 535 static const struct frame_unwind tic6x_stub_unwind = 536 { 537 NORMAL_FRAME, 538 default_frame_unwind_stop_reason, 539 tic6x_stub_this_id, 540 tic6x_frame_prev_register, 541 NULL, 542 tic6x_stub_unwind_sniffer 543 }; 544 545 /* Return the instruction on address PC. */ 546 547 static unsigned long 548 tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc) 549 { 550 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 551 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order); 552 } 553 554 /* Compute the condition of INST if it is a conditional instruction. Always 555 return 1 if INST is not a conditional instruction. */ 556 557 static int 558 tic6x_condition_true (struct frame_info *frame, unsigned long inst) 559 { 560 int register_number; 561 int register_value; 562 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 }; 563 564 register_number = register_numbers[(inst >> 29) & 7]; 565 if (register_number == -1) 566 return 1; 567 568 register_value = get_frame_register_signed (frame, register_number); 569 if ((inst & 0x10000000) != 0) 570 return register_value == 0; 571 return register_value != 0; 572 } 573 574 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in 575 instruction. */ 576 577 static int 578 tic6x_register_number (int reg, int side, int crosspath) 579 { 580 int r = (reg & 15) | ((crosspath ^ side) << 4); 581 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */ 582 r += 37; 583 return r; 584 } 585 586 static int 587 tic6x_extract_signed_field (int value, int low_bit, int bits) 588 { 589 int mask = (1 << bits) - 1; 590 int r = (value >> low_bit) & mask; 591 if ((r & (1 << (bits - 1))) != 0) 592 r -= mask + 1; 593 return r; 594 } 595 596 /* Determine where to set a single step breakpoint. */ 597 598 static CORE_ADDR 599 tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc) 600 { 601 struct gdbarch *gdbarch = get_frame_arch (frame); 602 unsigned long inst; 603 int register_number; 604 int last = 0; 605 606 do 607 { 608 inst = tic6x_fetch_instruction (gdbarch, pc); 609 610 last = !(inst & 1); 611 612 if (inst == TIC6X_INST_SWE) 613 { 614 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 615 616 if (tdep->syscall_next_pc != NULL) 617 return tdep->syscall_next_pc (frame); 618 } 619 620 if (tic6x_condition_true (frame, inst)) 621 { 622 if ((inst & 0x0000007c) == 0x00000010) 623 { 624 /* B with displacement */ 625 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); 626 pc += tic6x_extract_signed_field (inst, 7, 21) << 2; 627 break; 628 } 629 if ((inst & 0x0f83effc) == 0x00000360) 630 { 631 /* B with register */ 632 633 register_number = tic6x_register_number ((inst >> 18) & 0x1f, 634 INST_S_BIT (inst), 635 INST_X_BIT (inst)); 636 pc = get_frame_register_unsigned (frame, register_number); 637 break; 638 } 639 if ((inst & 0x00001ffc) == 0x00001020) 640 { 641 /* BDEC */ 642 register_number = tic6x_register_number ((inst >> 23) & 0x1f, 643 INST_S_BIT (inst), 0); 644 if (get_frame_register_signed (frame, register_number) >= 0) 645 { 646 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); 647 pc += tic6x_extract_signed_field (inst, 7, 10) << 2; 648 } 649 break; 650 } 651 if ((inst & 0x00001ffc) == 0x00000120) 652 { 653 /* BNOP with displacement */ 654 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); 655 pc += tic6x_extract_signed_field (inst, 16, 12) << 2; 656 break; 657 } 658 if ((inst & 0x0f830ffe) == 0x00800362) 659 { 660 /* BNOP with register */ 661 register_number = tic6x_register_number ((inst >> 18) & 0x1f, 662 1, INST_X_BIT (inst)); 663 pc = get_frame_register_unsigned (frame, register_number); 664 break; 665 } 666 if ((inst & 0x00001ffc) == 0x00000020) 667 { 668 /* BPOS */ 669 register_number = tic6x_register_number ((inst >> 23) & 0x1f, 670 INST_S_BIT (inst), 0); 671 if (get_frame_register_signed (frame, register_number) >= 0) 672 { 673 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); 674 pc += tic6x_extract_signed_field (inst, 13, 10) << 2; 675 } 676 break; 677 } 678 if ((inst & 0xf000007c) == 0x10000010) 679 { 680 /* CALLP */ 681 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); 682 pc += tic6x_extract_signed_field (inst, 7, 21) << 2; 683 break; 684 } 685 } 686 pc += TIC6X_OPCODE_SIZE; 687 } 688 while (!last); 689 return pc; 690 } 691 692 /* This is the implementation of gdbarch method software_single_step. */ 693 694 static int 695 tic6x_software_single_step (struct frame_info *frame) 696 { 697 struct gdbarch *gdbarch = get_frame_arch (frame); 698 struct address_space *aspace = get_frame_address_space (frame); 699 CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame)); 700 701 insert_single_step_breakpoint (gdbarch, aspace, next_pc); 702 703 return 1; 704 } 705 706 /* This is the implementation of gdbarch method frame_align. */ 707 708 static CORE_ADDR 709 tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 710 { 711 return align_down (addr, 8); 712 } 713 714 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its 715 value into VALBUF. */ 716 717 static void 718 tic6x_extract_return_value (struct type *valtype, struct regcache *regcache, 719 enum bfd_endian byte_order, gdb_byte *valbuf) 720 { 721 int len = TYPE_LENGTH (valtype); 722 723 /* pointer types are returned in register A4, 724 up to 32-bit types in A4 725 up to 64-bit types in A5:A4 */ 726 if (len <= 4) 727 { 728 /* In big-endian, 729 - one-byte structure or union occupies the LSB of single even register. 730 - for two-byte structure or union, the first byte occupies byte 1 of 731 register and the second byte occupies byte 0. 732 so, we read the contents in VAL from the LSBs of register. */ 733 if (len < 3 && byte_order == BFD_ENDIAN_BIG) 734 regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, 735 valbuf); 736 else 737 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); 738 } 739 else if (len <= 8) 740 { 741 /* For a 5-8 byte structure or union in big-endian, the first byte 742 occupies byte 3 (the MSB) of the upper (odd) register and the 743 remaining bytes fill the decreasingly significant bytes. 5-7 744 byte structures or unions have padding in the LSBs of the 745 lower (even) register. */ 746 if (byte_order == BFD_ENDIAN_BIG) 747 { 748 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4); 749 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf); 750 } 751 else 752 { 753 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); 754 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4); 755 } 756 } 757 } 758 759 /* Write into appropriate registers a function return value 760 of type TYPE, given in virtual format. */ 761 762 static void 763 tic6x_store_return_value (struct type *valtype, struct regcache *regcache, 764 enum bfd_endian byte_order, const gdb_byte *valbuf) 765 { 766 int len = TYPE_LENGTH (valtype); 767 768 /* return values of up to 8 bytes are returned in A5:A4 */ 769 770 if (len <= 4) 771 { 772 if (len < 3 && byte_order == BFD_ENDIAN_BIG) 773 regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, 774 valbuf); 775 else 776 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); 777 } 778 else if (len <= 8) 779 { 780 if (byte_order == BFD_ENDIAN_BIG) 781 { 782 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4); 783 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf); 784 } 785 else 786 { 787 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); 788 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4); 789 } 790 } 791 } 792 793 /* This is the implementation of gdbarch method return_value. */ 794 795 static enum return_value_convention 796 tic6x_return_value (struct gdbarch *gdbarch, struct value *function, 797 struct type *type, struct regcache *regcache, 798 gdb_byte *readbuf, const gdb_byte *writebuf) 799 { 800 /* In C++, when function returns an object, even its size is small 801 enough, it stii has to be passed via reference, pointed by register 802 A3. */ 803 if (current_language->la_language == language_cplus) 804 { 805 if (type != NULL) 806 { 807 type = check_typedef (type); 808 if (language_pass_by_reference (type)) 809 return RETURN_VALUE_STRUCT_CONVENTION; 810 } 811 } 812 813 if (TYPE_LENGTH (type) > 8) 814 return RETURN_VALUE_STRUCT_CONVENTION; 815 816 if (readbuf) 817 tic6x_extract_return_value (type, regcache, 818 gdbarch_byte_order (gdbarch), readbuf); 819 if (writebuf) 820 tic6x_store_return_value (type, regcache, 821 gdbarch_byte_order (gdbarch), writebuf); 822 823 return RETURN_VALUE_REGISTER_CONVENTION; 824 } 825 826 /* This is the implementation of gdbarch method dummy_id. */ 827 828 static struct frame_id 829 tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 830 { 831 return frame_id_build 832 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM), 833 get_frame_pc (this_frame)); 834 } 835 836 /* Get the alignment requirement of TYPE. */ 837 838 static int 839 tic6x_arg_type_alignment (struct type *type) 840 { 841 int len = TYPE_LENGTH (check_typedef (type)); 842 enum type_code typecode = TYPE_CODE (check_typedef (type)); 843 844 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) 845 { 846 /* The stack alignment of a structure (and union) passed by value is the 847 smallest power of two greater than or equal to its size. 848 This cannot exceed 8 bytes, which is the largest allowable size for 849 a structure passed by value. */ 850 851 if (len <= 2) 852 return len; 853 else if (len <= 4) 854 return 4; 855 else if (len <= 8) 856 return 8; 857 else 858 gdb_assert_not_reached ("unexpected length of data"); 859 } 860 else 861 { 862 if (len <= 4) 863 return 4; 864 else if (len == 8) 865 { 866 if (typecode == TYPE_CODE_COMPLEX) 867 return 4; 868 else 869 return 8; 870 } 871 else if (len == 16) 872 { 873 if (typecode == TYPE_CODE_COMPLEX) 874 return 8; 875 else 876 return 16; 877 } 878 else 879 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"), 880 len); 881 } 882 } 883 884 /* This is the implementation of gdbarch method push_dummy_call. */ 885 886 static CORE_ADDR 887 tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 888 struct regcache *regcache, CORE_ADDR bp_addr, 889 int nargs, struct value **args, CORE_ADDR sp, 890 int struct_return, CORE_ADDR struct_addr) 891 { 892 int argreg = 0; 893 int argnum; 894 int stack_offset = 4; 895 int references_offset = 4; 896 CORE_ADDR func_addr = find_function_addr (function, NULL); 897 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 898 struct type *func_type = value_type (function); 899 /* The first arg passed on stack. Mostly the first 10 args are passed by 900 registers. */ 901 int first_arg_on_stack = 10; 902 903 /* Set the return address register to point to the entry point of 904 the program, where a breakpoint lies in wait. */ 905 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr); 906 907 /* The caller must pass an argument in A3 containing a destination address 908 for the returned value. The callee returns the object by copying it to 909 the address in A3. */ 910 if (struct_return) 911 regcache_cooked_write_unsigned (regcache, 3, struct_addr); 912 913 /* Determine the type of this function. */ 914 func_type = check_typedef (func_type); 915 if (TYPE_CODE (func_type) == TYPE_CODE_PTR) 916 func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); 917 918 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC 919 || TYPE_CODE (func_type) == TYPE_CODE_METHOD); 920 921 /* For a variadic C function, the last explicitly declared argument and all 922 remaining arguments are passed on the stack. */ 923 if (TYPE_VARARGS (func_type)) 924 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1; 925 926 /* Now make space on the stack for the args. */ 927 for (argnum = 0; argnum < nargs; argnum++) 928 { 929 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4); 930 if (argnum >= 10 - argreg) 931 references_offset += len; 932 stack_offset += len; 933 } 934 sp -= stack_offset; 935 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1 936 Stack Alignment. */ 937 sp = align_down (sp, 8); 938 stack_offset = 4; 939 940 /* Now load as many as possible of the first arguments into 941 registers, and push the rest onto the stack. Loop through args 942 from first to last. */ 943 for (argnum = 0; argnum < nargs; argnum++) 944 { 945 const gdb_byte *val; 946 struct value *arg = args[argnum]; 947 struct type *arg_type = check_typedef (value_type (arg)); 948 int len = TYPE_LENGTH (arg_type); 949 enum type_code typecode = TYPE_CODE (arg_type); 950 951 val = value_contents (arg); 952 953 /* Copy the argument to general registers or the stack in 954 register-sized pieces. */ 955 if (argreg < first_arg_on_stack) 956 { 957 if (len <= 4) 958 { 959 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) 960 { 961 /* In big-endian, 962 - one-byte structure or union occupies the LSB of single 963 even register. 964 - for two-byte structure or union, the first byte 965 occupies byte 1 of register and the second byte occupies 966 byte 0. 967 so, we write the contents in VAL to the lsp of 968 register. */ 969 if (len < 3 && byte_order == BFD_ENDIAN_BIG) 970 regcache_cooked_write_part (regcache, arg_regs[argreg], 971 4 - len, len, val); 972 else 973 regcache_cooked_write (regcache, arg_regs[argreg], val); 974 } 975 else 976 { 977 /* The argument is being passed by value in a single 978 register. */ 979 CORE_ADDR regval = extract_unsigned_integer (val, len, 980 byte_order); 981 982 regcache_cooked_write_unsigned (regcache, arg_regs[argreg], 983 regval); 984 } 985 } 986 else 987 { 988 if (len <= 8) 989 { 990 if (typecode == TYPE_CODE_STRUCT 991 || typecode == TYPE_CODE_UNION) 992 { 993 /* For a 5-8 byte structure or union in big-endian, the 994 first byte occupies byte 3 (the MSB) of the upper (odd) 995 register and the remaining bytes fill the decreasingly 996 significant bytes. 5-7 byte structures or unions have 997 padding in the LSBs of the lower (even) register. */ 998 if (byte_order == BFD_ENDIAN_BIG) 999 { 1000 regcache_cooked_write (regcache, 1001 arg_regs[argreg] + 1, val); 1002 regcache_cooked_write_part (regcache, 1003 arg_regs[argreg], 0, 1004 len - 4, val + 4); 1005 } 1006 else 1007 { 1008 regcache_cooked_write (regcache, arg_regs[argreg], 1009 val); 1010 regcache_cooked_write_part (regcache, 1011 arg_regs[argreg] + 1, 0, 1012 len - 4, val + 4); 1013 } 1014 } 1015 else 1016 { 1017 /* The argument is being passed by value in a pair of 1018 registers. */ 1019 ULONGEST regval = extract_unsigned_integer (val, len, 1020 byte_order); 1021 1022 regcache_cooked_write_unsigned (regcache, 1023 arg_regs[argreg], 1024 regval); 1025 regcache_cooked_write_unsigned (regcache, 1026 arg_regs[argreg] + 1, 1027 regval >> 32); 1028 } 1029 } 1030 else 1031 { 1032 /* The argument is being passed by reference in a single 1033 register. */ 1034 CORE_ADDR addr; 1035 1036 /* It is not necessary to adjust REFERENCES_OFFSET to 1037 8-byte aligned in some cases, in which 4-byte alignment 1038 is sufficient. For simplicity, we adjust 1039 REFERENCES_OFFSET to 8-byte aligned. */ 1040 references_offset = align_up (references_offset, 8); 1041 1042 addr = sp + references_offset; 1043 write_memory (addr, val, len); 1044 references_offset += align_up (len, 4); 1045 regcache_cooked_write_unsigned (regcache, arg_regs[argreg], 1046 addr); 1047 } 1048 } 1049 argreg++; 1050 } 1051 else 1052 { 1053 /* The argument is being passed on the stack. */ 1054 CORE_ADDR addr; 1055 1056 /* There are six different cases of alignment, and these rules can 1057 be found in tic6x_arg_type_alignment: 1058 1059 1) 4-byte aligned if size is less than or equal to 4 byte, such 1060 as short, int, struct, union etc. 1061 2) 8-byte aligned if size is less than or equal to 8-byte, such 1062 as double, long long, 1063 3) 4-byte aligned if it is of type _Complex float, even its size 1064 is 8-byte. 1065 4) 8-byte aligned if it is of type _Complex double or _Complex 1066 long double, even its size is 16-byte. Because, the address of 1067 variable is passed as reference. 1068 5) struct and union larger than 8-byte are passed by reference, so 1069 it is 4-byte aligned. 1070 6) struct and union of size between 4 byte and 8 byte varies. 1071 alignment of struct variable is the alignment of its first field, 1072 while alignment of union variable is the max of all its fields' 1073 alignment. */ 1074 1075 if (len <= 4) 1076 ; /* Default is 4-byte aligned. Nothing to be done. */ 1077 else if (len <= 8) 1078 stack_offset = align_up (stack_offset, 1079 tic6x_arg_type_alignment (arg_type)); 1080 else if (len == 16) 1081 { 1082 /* _Complex double or _Complex long double */ 1083 if (typecode == TYPE_CODE_COMPLEX) 1084 { 1085 /* The argument is being passed by reference on stack. */ 1086 CORE_ADDR addr; 1087 references_offset = align_up (references_offset, 8); 1088 1089 addr = sp + references_offset; 1090 /* Store variable on stack. */ 1091 write_memory (addr, val, len); 1092 1093 references_offset += align_up (len, 4); 1094 1095 /* Pass the address of variable on stack as reference. */ 1096 store_unsigned_integer ((gdb_byte *) val, 4, byte_order, 1097 addr); 1098 len = 4; 1099 1100 } 1101 else 1102 internal_error (__FILE__, __LINE__, 1103 _("unexpected type %d of arg %d"), 1104 typecode, argnum); 1105 } 1106 else 1107 internal_error (__FILE__, __LINE__, 1108 _("unexpected length %d of arg %d"), len, argnum); 1109 1110 addr = sp + stack_offset; 1111 write_memory (addr, val, len); 1112 stack_offset += align_up (len, 4); 1113 } 1114 } 1115 1116 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp); 1117 1118 /* Return adjusted stack pointer. */ 1119 return sp; 1120 } 1121 1122 /* This is the implementation of gdbarch method stack_frame_destroyed_p. */ 1123 1124 static int 1125 tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1126 { 1127 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); 1128 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */ 1129 if ((inst & 0x0f83effc) == 0x360) 1130 { 1131 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, 1132 INST_S_BIT (inst), 1133 INST_X_BIT (inst)); 1134 if (src2 == TIC6X_RA_REGNUM) 1135 return 1; 1136 } 1137 1138 return 0; 1139 } 1140 1141 /* This is the implementation of gdbarch method get_longjmp_target. */ 1142 1143 static int 1144 tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 1145 { 1146 struct gdbarch *gdbarch = get_frame_arch (frame); 1147 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1148 CORE_ADDR jb_addr; 1149 gdb_byte buf[4]; 1150 1151 /* JMP_BUF is passed by reference in A4. */ 1152 jb_addr = get_frame_register_unsigned (frame, 4); 1153 1154 /* JMP_BUF contains 13 elements of type int, and return address is stored 1155 in the last slot. */ 1156 if (target_read_memory (jb_addr + 12 * 4, buf, 4)) 1157 return 0; 1158 1159 *pc = extract_unsigned_integer (buf, 4, byte_order); 1160 1161 return 1; 1162 } 1163 1164 /* This is the implementation of gdbarch method 1165 return_in_first_hidden_param_p. */ 1166 1167 static int 1168 tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch, 1169 struct type *type) 1170 { 1171 return 0; 1172 } 1173 1174 static struct gdbarch * 1175 tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1176 { 1177 struct gdbarch *gdbarch; 1178 struct gdbarch_tdep *tdep; 1179 struct tdesc_arch_data *tdesc_data = NULL; 1180 const struct target_desc *tdesc = info.target_desc; 1181 int has_gp = 0; 1182 1183 /* Check any target description for validity. */ 1184 if (tdesc_has_registers (tdesc)) 1185 { 1186 const struct tdesc_feature *feature; 1187 int valid_p, i; 1188 1189 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core"); 1190 1191 if (feature == NULL) 1192 return NULL; 1193 1194 tdesc_data = tdesc_data_alloc (); 1195 1196 valid_p = 1; 1197 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */ 1198 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 1199 tic6x_register_names[i]); 1200 1201 /* CSR */ 1202 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, 1203 tic6x_register_names[TIC6X_CSR_REGNUM]); 1204 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, 1205 tic6x_register_names[TIC6X_PC_REGNUM]); 1206 1207 if (!valid_p) 1208 { 1209 tdesc_data_cleanup (tdesc_data); 1210 return NULL; 1211 } 1212 1213 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp"); 1214 if (feature) 1215 { 1216 int j = 0; 1217 static const char *const gp[] = 1218 { 1219 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", 1220 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", 1221 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", 1222 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", 1223 }; 1224 1225 has_gp = 1; 1226 valid_p = 1; 1227 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */ 1228 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, 1229 gp[j]); 1230 1231 if (!valid_p) 1232 { 1233 tdesc_data_cleanup (tdesc_data); 1234 return NULL; 1235 } 1236 } 1237 1238 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp"); 1239 if (feature) 1240 { 1241 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR"); 1242 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC"); 1243 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC"); 1244 1245 if (!valid_p) 1246 { 1247 tdesc_data_cleanup (tdesc_data); 1248 return NULL; 1249 } 1250 } 1251 1252 } 1253 1254 /* Find a candidate among extant architectures. */ 1255 for (arches = gdbarch_list_lookup_by_info (arches, &info); 1256 arches != NULL; 1257 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 1258 { 1259 tdep = gdbarch_tdep (arches->gdbarch); 1260 1261 if (has_gp != tdep->has_gp) 1262 continue; 1263 1264 if (tdep && tdep->breakpoint) 1265 return arches->gdbarch; 1266 } 1267 1268 tdep = XCNEW (struct gdbarch_tdep); 1269 1270 tdep->has_gp = has_gp; 1271 gdbarch = gdbarch_alloc (&info, tdep); 1272 1273 /* Data type sizes. */ 1274 set_gdbarch_ptr_bit (gdbarch, 32); 1275 set_gdbarch_addr_bit (gdbarch, 32); 1276 set_gdbarch_short_bit (gdbarch, 16); 1277 set_gdbarch_int_bit (gdbarch, 32); 1278 set_gdbarch_long_bit (gdbarch, 32); 1279 set_gdbarch_long_long_bit (gdbarch, 64); 1280 set_gdbarch_float_bit (gdbarch, 32); 1281 set_gdbarch_double_bit (gdbarch, 64); 1282 1283 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 1284 set_gdbarch_double_format (gdbarch, floatformats_ieee_double); 1285 1286 /* The register set. */ 1287 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS); 1288 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM); 1289 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM); 1290 1291 set_gdbarch_register_name (gdbarch, tic6x_register_name); 1292 set_gdbarch_register_type (gdbarch, tic6x_register_type); 1293 1294 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1295 1296 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue); 1297 set_gdbarch_breakpoint_from_pc (gdbarch, tic6x_breakpoint_from_pc); 1298 1299 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc); 1300 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp); 1301 1302 /* Unwinding. */ 1303 dwarf2_append_unwinders (gdbarch); 1304 1305 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind); 1306 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind); 1307 frame_base_set_default (gdbarch, &tic6x_frame_base); 1308 1309 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg); 1310 1311 /* Single stepping. */ 1312 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step); 1313 1314 set_gdbarch_print_insn (gdbarch, tic6x_print_insn); 1315 1316 /* Call dummy code. */ 1317 set_gdbarch_frame_align (gdbarch, tic6x_frame_align); 1318 1319 set_gdbarch_return_value (gdbarch, tic6x_return_value); 1320 1321 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id); 1322 1323 /* Enable inferior call support. */ 1324 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call); 1325 1326 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target); 1327 1328 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p); 1329 1330 set_gdbarch_return_in_first_hidden_param_p (gdbarch, 1331 tic6x_return_in_first_hidden_param_p); 1332 1333 /* Hook in ABI-specific overrides, if they have been registered. */ 1334 gdbarch_init_osabi (info, gdbarch); 1335 1336 if (tdesc_data) 1337 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 1338 1339 return gdbarch; 1340 } 1341 1342 /* -Wmissing-prototypes */ 1343 extern initialize_file_ftype _initialize_tic6x_tdep; 1344 1345 void 1346 _initialize_tic6x_tdep (void) 1347 { 1348 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init); 1349 1350 initialize_tdesc_tic6x_c64xp (); 1351 initialize_tdesc_tic6x_c64x (); 1352 initialize_tdesc_tic6x_c62x (); 1353 } 1354