1# This testcase is part of GDB, the GNU debugger. 2 3# Copyright 2017-2024 Free Software Foundation, Inc. 4 5# This program is free software; you can redistribute it and/or modify 6# it under the terms of the GNU General Public License as published by 7# the Free Software Foundation; either version 3 of the License, or 8# (at your option) any later version. 9# 10# This program is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13# GNU General Public License for more details. 14# 15# You should have received a copy of the GNU General Public License 16# along with this program. If not, see <http://www.gnu.org/licenses/>. 17 18 19# These tests provides certain degree of testing for arc_insn functions, 20# however it is not a comprehensive testsuite that would go through all 21# possible ARC instructions - instead this particular test is focused on branch 22# instructions and whether branch targets are evaluated properly. Most of the 23# non-branch aspects of instruction decoder are used during prologue analysis, 24# so are indirictly tested there. 25 26# To maintain separation of test data and test logic, all of the information 27# about instructions, like if it has delay slot, condition code, branch target 28# address, is all specified in the test assembly file as a symbols, while this 29# test case reads those symbols to learn which values are right, then compares 30# values coming from decoder with those found in symbols. More information 31# about requirements to actual test cases can be found in corresponding 32# assembly file of this test case (arc-decode-insn.S). 33 34require {istarget "arc*-*-*"} 35 36standard_testfile .S 37 38if { [prepare_for_testing "failed to prepare" $testfile $srcfile] } { 39 return -1 40} 41 42if ![runto_main] { 43 return 0 44} 45 46# Helper function that reads properties of instruction from the ELF file via 47# its symbols and then confirms that decoder output aligns to the expected 48# values. 49proc test_branch_insn { test_name } { 50 51 # Make messages for failed cases more clear, by using hex in them. 52 set pc [get_hexadecimal_valueof &${test_name}_start -1] 53 54 # Calculate instruction length, based on ${test_name}_end symbol. 55 set end_pc [get_hexadecimal_valueof &${test_name}_end -1] 56 set length [expr $end_pc - $pc] 57 58 set target_address [get_hexadecimal_valueof &${test_name}_target -1] 59 60 # Figure out if there is a delay slot, using symbol 61 # ${test_name}_has_delay_slot. Note that it should be read via &, 62 # otherwise it would try to print value at the address specified in 63 # ${test_name}_has_delay_slot, while a symbol value itself is required. 64 if { 0 == [get_integer_valueof &${test_name}_has_delay_slot 0] } { 65 set has_delay_slot 0 66 } else { 67 set has_delay_slot 1 68 } 69 70 set cc [get_hexadecimal_valueof &${test_name}_cc 0] 71 72 # Can't use {} to create a list of items, because variables will not be 73 # evaluated inside the {}. 74 gdb_test_sequence "mt print arc arc-instruction $pc" "" [list \ 75 "length_with_limm = $length" \ 76 "cc = $cc" \ 77 "is_control_flow = 1" \ 78 "has_delay_slot = $has_delay_slot" \ 79 "branch_target = $target_address"] 80} 81 82set branch_test_list { } 83 84# Add items in the same groups as they can be enabled/disabled in assembly 85# file. 86lappend branch_test_list \ 87 j_c j_blink j_limm j_u6 j_s12 j_d_c j_d_blink j_d_u6 88lappend branch_test_list \ 89 jcc_c jcc_blink jcc_limm jcc_u6 jcc_d_c jcc_d_blink jcc_d_u6 \ 90 jcc_eq_s_blink jcc_ne_s_blink 91lappend branch_test_list \ 92 jl_c jl_limm jl_u6 jl_s12 jl_d_c jl_d_u6 jl_d_s12 jl_s_b jl_s_d_b 93lappend branch_test_list \ 94 jlcc_c jlcc_limm jlcc_u6 jlcc_d_c jlcc_d_u6 95lappend branch_test_list \ 96 b_s25 b_d_s25 b_s_s10 97lappend branch_test_list \ 98 bbit0_nt_b_c_s9 bbit0_d_nt_b_c_s9 bbit0_t_b_c_s9 bbit0_d_t_b_c_s9 \ 99 bbit0_nt_b_u6_s9 bbit0_d_nt_b_u6_s9 bbit0_t_b_u6_s9 bbit0_d_t_b_u6_s9 \ 100 bbit0_nt_b_limm_s9 bbit0_t_b_limm_s9 bbit0_nt_limm_c_s9 bbit0_t_limm_c_s9 \ 101 bbit0_nt_limm_u6_s9 bbit0_t_limm_u6_s9 \ 102 bbit1_nt_b_c_s9 bbit1_d_nt_b_c_s9 bbit1_t_b_c_s9 bbit1_d_t_b_c_s9 \ 103 bbit1_nt_b_u6_s9 bbit1_d_nt_b_u6_s9 bbit1_t_b_u6_s9 bbit1_d_t_b_u6_s9 \ 104 bbit1_nt_b_limm_s9 bbit1_t_b_limm_s9 bbit1_nt_limm_c_s9 bbit1_t_limm_c_s9 \ 105 bbit1_nt_limm_u6_s9 bbit1_t_limm_u6_s9 106lappend branch_test_list \ 107 bcc_s21 bcc_d_s21 \ 108 beq_s_s10 bne_s_s10 bgt_s_s7 bge_s_s7 blt_s_s7 ble_s_s7 bhi_s_s7 bhs_s_s7 \ 109 blo_s_s7 bls_s_s7 110lappend branch_test_list \ 111 bi_c bih_c 112lappend branch_test_list \ 113 bl_s25 bl_d_s25 bl_s_s13 \ 114 blcc_s21 blcc_d_s21 115lappend branch_test_list \ 116 breq_nt_b_c_s9 breq_d_nt_b_c_s9 breq_t_b_c_s9 breq_d_t_b_c_s9 \ 117 breq_nt_b_u6_s9 breq_d_nt_b_u6_s9 breq_t_b_u6_s9 breq_d_t_b_u6_s9 \ 118 breq_nt_b_limm_s9 breq_t_b_limm_s9 breq_nt_limm_c_s9 breq_t_limm_c_s9 \ 119 breq_nt_limm_u6_s9 breq_t_limm_u6_s9 120# lappend branch_test_list jli_s_u10 121lappend branch_test_list leave_s 122lappend branch_test_list lpcc_u7 123 124runto start_branch_tests 125foreach test $branch_test_list { 126 test_branch_insn $test 127} 128 129