1; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*- 2; Copyright 2000-2014 Free Software Foundation, Inc. 3; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 4; Modified by Julius Baxter, juliusbaxter@gmail.com 5; 6; This program is free software; you can redistribute it and/or modify 7; it under the terms of the GNU General Public License as published by 8; the Free Software Foundation; either version 3 of the License, or 9; (at your option) any later version. 10; 11; This program is distributed in the hope that it will be useful, 12; but WITHOUT ANY WARRANTY; without even the implied warranty of 13; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14; GNU General Public License for more details. 15; 16; You should have received a copy of the GNU General Public License 17; along with this program; if not, see <http://www.gnu.org/licenses/> 18 19; Hardware pieces. 20; These entries list the elements of the raw hardware. 21; They're also used to provide tables and other elements of the assembly 22; language. 23 24(define-hardware 25 (name h-pc) 26 (comment "program counter") 27 (attrs PC (MACH ORBIS-MACHS)) 28 (type pc UWI) 29 (get () (raw-reg h-pc)) 30 (set (newval) (sequence () 31 (set (reg h-sys-ppc) (raw-reg h-pc)) 32 (set (raw-reg h-pc) newval) 33 )) 34 ) 35 36(define-pmacro REG-INDICES 37 ((r0 0) 38 (r1 1) 39 (r2 2) 40 (r3 3) 41 (r4 4) 42 (r5 5) 43 (r6 6) 44 (r7 7) 45 (r8 8) 46 (r9 9) 47 (r10 10) 48 (r11 11) 49 (r12 12) 50 (r13 13) 51 (r14 14) 52 (r15 15) 53 (r16 16) 54 (r17 17) 55 (r18 18) 56 (r19 19) 57 (r20 20) 58 (r21 21) 59 (r22 22) 60 (r23 23) 61 (r24 24) 62 (r25 25) 63 (r26 26) 64 (r27 27) 65 (r28 28) 66 (r29 29) 67 (r30 30) 68 (r31 31) 69 (lr 9) 70 (sp 1) 71 (fp 2)) 72 ) 73 74(define-hardware 75 (name h-fsr) 76 (comment "floating point registers (single, virtual)") 77 (attrs VIRTUAL (MACH ORFPX32-MACHS)) 78 (type register SF (32)) 79 (indices keyword "" REG-INDICES) 80 (get (index) (subword SF (trunc SI (reg h-gpr index)) 0)) 81 (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0)))) 82 ) 83 84(define-hardware 85 (name h-fdr) (comment "floating point registers (double, virtual)") 86 (attrs VIRTUAL (MACH ORFPX64-MACHS)) 87 (type register DF (32)) 88 (indices keyword "" REG-INDICES) 89 (get (index) (subword DF (trunc DI (reg h-gpr index)) 0)) 90 (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0)))) 91 ) 92 93(define-hardware 94 (name h-spr) (comment "special purpose registers") 95 (attrs VIRTUAL (MACH ORBIS-MACHS)) 96 (type register UWI (#x20000)) 97 (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index)) 98 (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval)) 99) 100 101(define-pmacro spr-shift 11) 102(define-pmacro (spr-address spr-group spr-index) 103 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 104 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 105 106(define-hardware 107 (name h-gpr) (comment "general registers") 108 (attrs (MACH ORBIS-MACHS)) 109 (type register UWI (32)) 110 (indices keyword "" REG-INDICES) 111 (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0)))) 112 (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval)) 113 ) 114 115(define-normal-enum 116 except-number 117 "Exception numbers" 118 () 119 EXCEPT- 120 (("NONE" #x00) 121 ("RESET" #x01) 122 ("BUSERR" #x02) 123 ("DPF" #x03) 124 ("IPF" #x04) 125 ("TICK" #x05) 126 ("ALIGN" #x06) 127 ("ILLEGAL" #x07) 128 ("INT" #x08) 129 ("DTLBMISS" #x09) 130 ("ITLBMISS" #x0a) 131 ("RANGE" #x0b) 132 ("SYSCALL" #x0c) 133 ("FPE" #x0d) 134 ("TRAP" #x0e) 135 ) 136 ) 137 138(define-pmacro (raise-exception exnum) 139 (c-call VOID "@cpu@_exception" pc exnum)) 140 141(define-normal-enum 142 spr-groups 143 "special purpose register groups" 144 () 145 SPR-GROUP- 146 (("SYS" #x0) 147 ("DMMU" #x1) 148 ("IMMU" #x2) 149 ("DCACHE" #x3) 150 ("ICACHE" #x4) 151 ("MAC" #x5) 152 ("DEBUG" #x6) 153 ("PERF" #x7) 154 ("POWER" #x8) 155 ("PIC" #x9) 156 ("TICK" #xa) 157 ("FPU" #xb) 158 ) 159 ) 160 161(define-pmacro (spr-reg-info) 162 (.splice 163 (SYS VR #x000 "version register") 164 (SYS UPR #x001 "unit present register") 165 (SYS CPUCFGR #x002 "cpu configuration register") 166 (SYS DMMUCFGR #x003 "Data MMU configuration register") 167 (SYS IMMUCFGR #x004 "Insn MMU configuration register") 168 (SYS DCCFGR #x005 "Data cache configuration register") 169 (SYS ICCFGR #x006 "Insn cache configuration register") 170 (SYS DCFGR #x007 "Debug configuration register") 171 (SYS PCCFGR #x008 "Performance counters configuration register") 172 (SYS NPC #x010 "Next program counter") 173 (SYS SR #x011 "Supervision Register") 174 (SYS PPC #x012 "Previous program counter") 175 (SYS FPCSR #x014 "Floating point control status register") 176 (.unsplice 177 (.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n))) 178 (.iota #x10))) 179 (.unsplice 180 (.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n))) 181 (.iota #x10))) 182 (.unsplice 183 (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n))) 184 (.iota #x10))) 185 (.unsplice 186 (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n))) 187 (.iota #x200))) 188 189 (MAC MACLO #x001 "Multiply and accumulate result (low)") 190 (MAC MACHI #x002 "Multiply and accumulate result (high)") 191 (TICK TTMR #x000 "Tick timer mode register") 192 ) 193 ) 194 195(define-normal-enum 196 spr-reg-indices 197 "special purpose register indices" 198 () 199 SPR-INDEX- 200 (.map (.pmacro (args) 201 (.apply (.pmacro (group index n comment) 202 ((.sym group "-" index) n)) 203 args) 204 ) 205 (spr-reg-info) 206 ) 207 ) 208 209(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment) 210 (define-hardware 211 (name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index))) 212 (comment spr-comment) 213 (attrs VIRTUAL (MACH ORBIS-MACHS)) 214 (type register UWI) 215 (get () (reg UWI h-spr (spr-address spr-group spr-index))) 216 (set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval)) 217 ) 218 ) 219(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info)))) 220 221(define-pmacro (spr-field-info) 222 ((SYS VR REV 5 0 "revision field") 223 (SYS VR CFG 23 16 "configuration template field") 224 (SYS VR VER 31 24 "version field") 225 (SYS UPR UP 0 0 "UPR present bit") 226 (SYS UPR DCP 1 1 "data cache present bit") 227 (SYS UPR ICP 2 2 "insn cache present bit") 228 (SYS UPR DMP 3 3 "data MMU present bit") 229 (SYS UPR MP 4 4 "MAC unit present bit") 230 (SYS UPR IMP 5 5 "insn MMU present bit") 231 (SYS UPR DUP 6 6 "debug unit present bit") 232 (SYS UPR PCUP 7 7 "performance counters unit present bit") 233 (SYS UPR PICP 8 8 "programmable interrupt controller present bit") 234 (SYS UPR PMP 9 9 "power management present bit") 235 (SYS UPR TTP 10 10 "tick timer present bit") 236 (SYS UPR CUP 31 24 "custom units present field") 237 (SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field") 238 (SYS CPUCFGR CGF 4 4 "custom GPR file bit") 239 (SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit") 240 (SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit") 241 (SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit") 242 (SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit") 243 (SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit") 244 (SYS CPUCFGR ND 10 10 "no transfer delay bit") 245 (SYS SR SM 0 0 "supervisor mode bit") 246 (SYS SR TEE 1 1 "tick timer exception enabled bit") 247 (SYS SR IEE 2 2 "interrupt exception enabled bit") 248 (SYS SR DCE 3 3 "data cache enabled bit") 249 (SYS SR ICE 4 4 "insn cache enabled bit") 250 (SYS SR DME 5 5 "data MMU enabled bit") 251 (SYS SR IME 6 6 "insn MMU enabled bit") 252 (SYS SR LEE 7 7 "little endian enabled bit") 253 (SYS SR CE 8 8 "CID enable bit") 254 (SYS SR F 9 9 "flag bit") 255 (SYS SR CY 10 10 "carry bit") 256 (SYS SR OV 11 11 "overflow bit") 257 (SYS SR OVE 12 12 "overflow exception enabled bit") 258 (SYS SR DSX 13 13 "delay slot exception bit") 259 (SYS SR EPH 14 14 "exception prefix high bit") 260 (SYS SR FO 15 15 "fixed one bit") 261 (SYS SR SUMRA 16 16 "SPRs user mode read access bit") 262 (SYS SR CID 31 28 "context ID field") 263 (SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit") 264 (SYS FPCSR RM 2 1 "floating point rounding mode field") 265 (SYS FPCSR OVF 3 3 "floating point overflow flag bit") 266 (SYS FPCSR UNF 4 4 "floating point underflow bit") 267 (SYS FPCSR SNF 5 5 "floating point SNAN flag bit") 268 (SYS FPCSR QNF 6 6 "floating point QNAN flag bit") 269 (SYS FPCSR ZF 7 7 "floating point zero flag bit") 270 (SYS FPCSR IXF 8 8 "floating point inexact flag bit") 271 (SYS FPCSR IVF 9 9 "floating point invalid flag bit") 272 (SYS FPCSR INF 10 10 "floating point infinity flag bit") 273 (SYS FPCSR DZF 11 11 "floating point divide by zero flag bit") 274 ) 275 ) 276 277(define-normal-enum 278 spr-field-msbs 279 "SPR field msb positions" 280 () 281 SPR-FIELD-MSB- 282 (.map (.pmacro (args) 283 (.apply (.pmacro (group index field msb lsb comment) 284 ((.sym group "-" index "-" field) msb) 285 ) 286 args 287 ) 288 ) 289 (spr-field-info) 290 ) 291 ) 292 293(define-normal-enum 294 spr-field-lsbs 295 "SPR field lsb positions" 296 () 297 SPR-FIELD-SIZE- 298 (.map (.pmacro (args) 299 (.apply (.pmacro (group index field msb lsb comment) 300 ((.sym group "-" index "-" field) lsb) 301 ) 302 args 303 ) 304 ) 305 (spr-field-info) 306 ) 307 ) 308 309(define-normal-enum 310 spr-field-masks 311 "SPR field masks" 312 () 313 SPR-FIELD-MASK- 314 (.map (.pmacro (args) 315 (.apply (.pmacro (group index field msb lsb comment) 316 (.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb)) 317 ) 318 args 319 ) 320 ) 321 (spr-field-info) 322 ) 323 ) 324 325(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment) 326 (.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field))) 327 ) 328 (begin 329 (define-hardware 330 (name spr-field-name) 331 (comment spr-field-comment) 332 (attrs VIRTUAL (MACH ORBIS-MACHS)) 333 (type register UWI) 334 (get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb)) 335 (set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value)) 336 ) 337 ) 338 ) 339 ) 340(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info)))) 341 342(define-attr 343 (type boolean) 344 (for insn) 345 (name DELAYED-CTI) 346 (comment "delayed control transfer instruction") 347 (values #f #t) 348 (default #f) 349 ) 350 351(define-attr 352 (for insn) 353 (type boolean) 354 (name NOT-IN-DELAY-SLOT) 355 (comment "instruction cannot be in delay slot") 356 (values #f #t) 357 (default #f) 358 ) 359 360(define-attr 361 (for insn) 362 (type boolean) 363 (name FORCED-CTI) 364 (comment "instruction may forcefully transfer control (e.g., rfe)") 365 ) 366