1# sh testcase for pclr 2# mach: shdsp 3# as(shdsp): -defsym sim_cpu=1 -dsp 4 5 # FIXME: opcode table ambiguity in ignored bits 4-7. 6 7 .include "testutils.inc" 8 9 start 10pclr_cc: 11 set_grs_a5a5 12 lds r0, a0 13 pcopy a0, a1 14 lds r0, x0 15 lds r0, x1 16 lds r0, y0 17 lds r0, y1 18 pcopy x0, m0 19 pcopy y1, m1 20 21 assert_sreg 0xa5a5a5a5, x0 22 pclr x0 23 assert_sreg 0, x0 24 25 set_dcfalse 26 dct pclr x1 27 assert_sreg 0xa5a5a5a5, x1 28 set_dctrue 29 dct pclr x1 30 assert_sreg 0, x1 31 32 set_dctrue 33 dcf pclr y0 34 assert_sreg 0xa5a5a5a5, y0 35 set_dcfalse 36 dcf pclr y0 37 assert_sreg 0, y0 38 39 test_grs_a5a5 40 assert_sreg 0xa5a5a5a5, a0 41 assert_sreg 0xa5a5a5a5, y1 42 assert_sreg2 0xa5a5a5a5, a1 43 assert_sreg2 0xa5a5a5a5, m0 44 assert_sreg2 0xa5a5a5a5, m1 45 46pclr_pmuls: 47 set_grs_a5a5 48 lds r0, a0 49 pcopy a0, a1 50 lds r0, x0 51 lds r0, x1 52 lds r0, y0 53 lds r0, y1 54 pcopy x0, m0 55 pcopy y1, m1 56 57 pclr x0 pmuls y0, y1, a0 58 59 assert_sreg 0, x0 60 assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5 61 62 test_grs_a5a5 63 64 pass 65 exit 0 66