1# Hitachi H8 testcase 'shll' 2# mach(): h8300s h8sx 3# as(h8300): --defsym sim_cpu=0 4# as(h8300h): --defsym sim_cpu=1 5# as(h8300s): --defsym sim_cpu=2 6# as(h8sx): --defsym sim_cpu=3 7# ld(h8300h): -m h8300helf 8# ld(h8300s): -m h8300self 9# ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .data 16byte_dest: .byte 0xa5 17 .align 2 18word_dest: .word 0xa5a5 19 .align 4 20long_dest: .long 0xa5a5a5a5 21 22 .text 23 24shll_b_reg8_1: 25 set_grs_a5a5 ; Fill all general regs with a fixed pattern 26 set_ccr_zero 27 28 shll.b r0l ; shift left logical by one 29;;; .word 0x1008 30 31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 32 test_zero_clear 33 test_ovf_clear 34 test_neg_clear 35 test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010 36.if (sim_cpu) 37 test_h_gr32 0xa5a5a54a er0 38.endif 39 test_gr_a5a5 1 ; Make sure other general regs not disturbed 40 test_gr_a5a5 2 41 test_gr_a5a5 3 42 test_gr_a5a5 4 43 test_gr_a5a5 5 44 test_gr_a5a5 6 45 test_gr_a5a5 7 46 47shll_b_reg8_2: 48 set_grs_a5a5 ; Fill all general regs with a fixed pattern 49 set_ccr_zero 50 51 shll.b #2, r0l ; shift left logical by two 52;;; .word 0x1048 53 54 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 55 test_zero_clear 56 test_ovf_clear 57 test_neg_set 58 59 test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100 60.if (sim_cpu) 61 test_h_gr32 0xa5a5a594 er0 62.endif 63 test_gr_a5a5 1 ; Make sure other general regs not disturbed 64 test_gr_a5a5 2 65 test_gr_a5a5 3 66 test_gr_a5a5 4 67 test_gr_a5a5 5 68 test_gr_a5a5 6 69 test_gr_a5a5 7 70 71.if (sim_cpu == h8sx) 72shll_b_reg8_4: 73 set_grs_a5a5 ; Fill all general regs with a fixed pattern 74 set_ccr_zero 75 76 shll.b #4, r0l ; shift left logical by four 77;;; .word 0x10a8 78 79 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 80 test_zero_clear 81 test_ovf_clear 82 test_neg_clear 83 test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000 84 test_h_gr32 0xa5a5a550 er0 85 86 test_gr_a5a5 1 ; Make sure other general regs not disturbed 87 test_gr_a5a5 2 88 test_gr_a5a5 3 89 test_gr_a5a5 4 90 test_gr_a5a5 5 91 test_gr_a5a5 6 92 test_gr_a5a5 7 93 94shll_b_reg8_reg8: 95 set_grs_a5a5 ; Fill all general regs with a fixed pattern 96 set_ccr_zero 97 98 mov #5, r0h 99 shll.b r0h, r0l ; shift left logical by register value 100 101 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 102 test_zero_clear 103 test_ovf_clear 104 test_neg_set 105 test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000 106 test_h_gr32 0xa5a505a0 er0 107 108 test_gr_a5a5 1 ; Make sure other general regs not disturbed 109 test_gr_a5a5 2 110 test_gr_a5a5 3 111 test_gr_a5a5 4 112 test_gr_a5a5 5 113 test_gr_a5a5 6 114 test_gr_a5a5 7 115.endif 116 117.if (sim_cpu) ; Not available in h8300 mode 118shll_w_reg16_1: 119 set_grs_a5a5 ; Fill all general regs with a fixed pattern 120 set_ccr_zero 121 122 shll.w r0 ; shift left logical by one 123;;; .word 0x1010 124 125 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 126 test_zero_clear 127 test_ovf_clear 128 test_neg_clear 129 test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010 130 test_h_gr32 0xa5a54b4a er0 131 132 test_gr_a5a5 1 ; Make sure other general regs not disturbed 133 test_gr_a5a5 2 134 test_gr_a5a5 3 135 test_gr_a5a5 4 136 test_gr_a5a5 5 137 test_gr_a5a5 6 138 test_gr_a5a5 7 139 140shll_w_reg16_2: 141 set_grs_a5a5 ; Fill all general regs with a fixed pattern 142 set_ccr_zero 143 144 shll.w #2, r0 ; shift left logical by two 145;;; .word 0x1050 146 147 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 148 test_zero_clear 149 test_ovf_clear 150 test_neg_set 151 test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100 152 test_h_gr32 0xa5a59694 er0 153 154 test_gr_a5a5 1 ; Make sure other general regs not disturbed 155 test_gr_a5a5 2 156 test_gr_a5a5 3 157 test_gr_a5a5 4 158 test_gr_a5a5 5 159 test_gr_a5a5 6 160 test_gr_a5a5 7 161 162.if (sim_cpu == h8sx) 163shll_w_reg16_4: 164 set_grs_a5a5 ; Fill all general regs with a fixed pattern 165 set_ccr_zero 166 167 shll.w #4, r0 ; shift left logical by four 168;;; .word 0x1020 169 170 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 171 test_zero_clear 172 test_ovf_clear 173 test_neg_clear 174 test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000 175 test_h_gr32 0xa5a55a50 er0 176 177 test_gr_a5a5 1 ; Make sure other general regs not disturbed 178 test_gr_a5a5 2 179 test_gr_a5a5 3 180 test_gr_a5a5 4 181 test_gr_a5a5 5 182 test_gr_a5a5 6 183 test_gr_a5a5 7 184 185shll_w_reg16_8: 186 set_grs_a5a5 ; Fill all general regs with a fixed pattern 187 set_ccr_zero 188 189 shll.w #8, r0 ; shift left logical by eight 190;;; .word 0x1060 191 192 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 193 test_zero_clear 194 test_ovf_clear 195 test_neg_set 196 test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000 197 test_h_gr32 0xa5a5a500 er0 198 199 test_gr_a5a5 1 ; Make sure other general regs not disturbed 200 test_gr_a5a5 2 201 test_gr_a5a5 3 202 test_gr_a5a5 4 203 test_gr_a5a5 5 204 test_gr_a5a5 6 205 test_gr_a5a5 7 206 207shll_w_reg16_reg8: 208 set_grs_a5a5 ; Fill all general regs with a fixed pattern 209 set_ccr_zero 210 211 mov #5, r0h 212 shll.w r0h, r0 ; shift left logical by register value 213 214 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 215 test_zero_clear 216 test_ovf_clear 217 test_neg_set 218 test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000 219 test_h_gr32 0xa5a5b4a0 er0 220 221 test_gr_a5a5 1 ; Make sure other general regs not disturbed 222 test_gr_a5a5 2 223 test_gr_a5a5 3 224 test_gr_a5a5 4 225 test_gr_a5a5 5 226 test_gr_a5a5 6 227 test_gr_a5a5 7 228.endif 229 230shll_l_reg32_1: 231 set_grs_a5a5 ; Fill all general regs with a fixed pattern 232 set_ccr_zero 233 234 shll.l er0 ; shift left logical by one 235;;; .word 1030 236 237 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 238 test_zero_clear 239 test_ovf_clear 240 test_neg_clear 241 ; 1010 0101 1010 0101 1010 0101 1010 0101 242 ; -> 0100 1011 0100 1011 0100 1011 0100 1010 243 test_h_gr32 0x4b4b4b4a er0 244 245 test_gr_a5a5 1 ; Make sure other general regs not disturbed 246 test_gr_a5a5 2 247 test_gr_a5a5 3 248 test_gr_a5a5 4 249 test_gr_a5a5 5 250 test_gr_a5a5 6 251 test_gr_a5a5 7 252 253shll_l_reg32_2: 254 set_grs_a5a5 ; Fill all general regs with a fixed pattern 255 set_ccr_zero 256 257 shll.l #2, er0 ; shift left logical by two 258;;; .word 0x1070 259 260 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 261 test_zero_clear 262 test_ovf_clear 263 test_neg_set 264 ; 1010 0101 1010 0101 1010 0101 1010 0101 265 ; -> 1001 0110 1001 0110 1001 0110 1001 0100 266 test_h_gr32 0x96969694 er0 267 268 test_gr_a5a5 1 ; Make sure other general regs not disturbed 269 test_gr_a5a5 2 270 test_gr_a5a5 3 271 test_gr_a5a5 4 272 test_gr_a5a5 5 273 test_gr_a5a5 6 274 test_gr_a5a5 7 275 276.if (sim_cpu == h8sx) 277shll_l_reg32_4: 278 set_grs_a5a5 ; Fill all general regs with a fixed pattern 279 set_ccr_zero 280 281 shll.l #4, er0 ; shift left logical by four 282;;; .word 0x1038 283 284 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 285 test_zero_clear 286 test_ovf_clear 287 test_neg_clear 288 ; 1010 0101 1010 0101 1010 0101 1010 0101 289 ; -> 0101 1010 0101 1010 0101 1010 0101 0000 290 test_h_gr32 0x5a5a5a50 er0 291 292 test_gr_a5a5 1 ; Make sure other general regs not disturbed 293 test_gr_a5a5 2 294 test_gr_a5a5 3 295 test_gr_a5a5 4 296 test_gr_a5a5 5 297 test_gr_a5a5 6 298 test_gr_a5a5 7 299 300shll_l_reg32_8: 301 set_grs_a5a5 ; Fill all general regs with a fixed pattern 302 set_ccr_zero 303 304 shll.l #8, er0 ; shift left logical by eight 305;;; .word 0x1078 306 307 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 308 test_zero_clear 309 test_ovf_clear 310 test_neg_set 311 test_h_gr16 0xa500 r0 312 ; 1010 0101 1010 0101 1010 0101 1010 0101 313 ; -> 1010 0101 1010 0101 1010 0101 0000 0000 314 test_h_gr32 0xa5a5a500 er0 315 316 test_gr_a5a5 1 ; Make sure other general regs not disturbed 317 test_gr_a5a5 2 318 test_gr_a5a5 3 319 test_gr_a5a5 4 320 test_gr_a5a5 5 321 test_gr_a5a5 6 322 test_gr_a5a5 7 323 324shll_l_reg32_16: 325 set_grs_a5a5 ; Fill all general regs with a fixed pattern 326 set_ccr_zero 327 328 shll.l #16, er0 ; shift left logical by sixteen 329;;; .word 0x10f8 330 331 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 332 test_zero_clear 333 test_ovf_clear 334 test_neg_set 335 ; 1010 0101 1010 0101 1010 0101 1010 0101 336 ;; -> 1010 0101 1010 0101 0000 0000 0000 0000 337 test_h_gr32 0xa5a50000 er0 338 339 test_gr_a5a5 1 ; Make sure other general regs not disturbed 340 test_gr_a5a5 2 341 test_gr_a5a5 3 342 test_gr_a5a5 4 343 test_gr_a5a5 5 344 test_gr_a5a5 6 345 test_gr_a5a5 7 346 347shll_l_reg32_reg8: 348 set_grs_a5a5 ; Fill all general regs with a fixed pattern 349 set_ccr_zero 350 351 mov #5, r1l 352 shll.l r1l, er0 ; shift left logical by register value 353 354 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 355 test_zero_clear 356 test_ovf_clear 357 test_neg_set 358 ; 1010 0101 1010 0101 1010 0101 1010 0101 359 ; -> 1011 0100 1011 0100 1011 0100 1010 0000 360 test_h_gr32 0xb4b4b4a0 er0 361 362 test_h_gr32 0xa5a5a505 er1 363 test_gr_a5a5 2 ; Make sure other general regs not disturbed 364 test_gr_a5a5 3 365 test_gr_a5a5 4 366 test_gr_a5a5 5 367 test_gr_a5a5 6 368 test_gr_a5a5 7 369.endif 370.endif 371 372 pass 373 374 exit 0 375 376