1//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp 2// Spec Reference: dsp32shift vmax / vmax 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10imm32 r0, 0x11002001; 11imm32 r1, 0x12001001; 12imm32 r2, 0x11301302; 13imm32 r3, 0x43001003; 14imm32 r4, 0x11601604; 15imm32 r5, 0x71001705; 16imm32 r6, 0x81008006; 17imm32 r7, 0x1900b007; 18A0 = R3; 19R1 = VIT_MAX( R1 , R0 ) (ASL); 20R2 = VIT_MAX( R2 , R1 ) (ASL); 21R3 = VIT_MAX( R3 , R2 ) (ASL); 22R4 = VIT_MAX( R4 , R3 ) (ASL); 23R5 = VIT_MAX( R5 , R4 ) (ASL); 24R6 = VIT_MAX( R6 , R5 ) (ASL); 25R7 = VIT_MAX( R7 , R6 ) (ASL); 26R0 = VIT_MAX( R0 , R7 ) (ASL); 27CHECKREG r0, 0x20018100; 28CHECKREG r1, 0x12002001; 29CHECKREG r2, 0x13022001; 30CHECKREG r3, 0x43002001; 31CHECKREG r4, 0x16044300; 32CHECKREG r5, 0x71004300; 33CHECKREG r6, 0x81007100; 34CHECKREG r7, 0x19008100; 35 36imm32 r0, 0x11002001; 37imm32 r1, 0xd2001001; 38imm32 r2, 0x14301302; 39imm32 r3, 0x43001003; 40imm32 r4, 0x11f01604; 41imm32 r5, 0xb1001705; 42imm32 r6, 0xd1008006; 43imm32 r7, 0x39056707; 44R1 = VIT_MAX( R1 , R3 ) (ASL); 45R2 = VIT_MAX( R2 , R4 ) (ASL); 46R3 = VIT_MAX( R3 , R6 ) (ASL); 47R4 = VIT_MAX( R4 , R5 ) (ASL); 48R5 = VIT_MAX( R5 , R7 ) (ASL); 49R6 = VIT_MAX( R6 , R0 ) (ASL); 50R7 = VIT_MAX( R7 , R1 ) (ASL); 51R0 = VIT_MAX( R0 , R2 ) (ASL); 52CHECKREG r0, 0x20011604; 53CHECKREG r1, 0x10014300; 54CHECKREG r2, 0x14301604; 55CHECKREG r3, 0x4300D100; 56CHECKREG r4, 0x16041705; 57CHECKREG r5, 0x17056707; 58CHECKREG r6, 0xD1002001; 59CHECKREG r7, 0x67074300; 60 61imm32 r0, 0xa1011001; 62imm32 r1, 0x1b002001; 63imm32 r2, 0x81c01302; 64imm32 r3, 0x910d1403; 65imm32 r4, 0x2100e504; 66imm32 r5, 0x31007f65; 67imm32 r6, 0x41007006; 68imm32 r7, 0x15001801; 69R1 = VIT_MAX( R1 , R0 ) (ASR); 70R2 = VIT_MAX( R2 , R1 ) (ASR); 71R3 = VIT_MAX( R3 , R2 ) (ASR); 72R4 = VIT_MAX( R4 , R3 ) (ASR); 73R5 = VIT_MAX( R5 , R4 ) (ASR); 74R6 = VIT_MAX( R6 , R5 ) (ASR); 75R7 = VIT_MAX( R7 , R6 ) (ASR); 76R0 = VIT_MAX( R0 , R7 ) (ASR); 77CHECKREG r0, 0x1001910D; 78CHECKREG r1, 0x20011001; 79CHECKREG r2, 0x81C02001; 80CHECKREG r3, 0x910D81C0; 81CHECKREG r4, 0x2100910D; 82CHECKREG r5, 0x7F65910D; 83CHECKREG r6, 0x7006910D; 84CHECKREG r7, 0x1801910D; 85 86imm32 r0, 0xe1011001; 87imm32 r1, 0x4b002001; 88imm32 r2, 0x8fc01302; 89imm32 r3, 0x910d1403; 90imm32 r4, 0xb100e504; 91imm32 r5, 0x41007f65; 92imm32 r6, 0xaf007006; 93imm32 r7, 0x16001801; 94R0 = VIT_MAX( R4 , R0 ) (ASR); 95R1 = VIT_MAX( R5 , R1 ) (ASR); 96R2 = VIT_MAX( R6 , R2 ) (ASR); 97R3 = VIT_MAX( R7 , R3 ) (ASR); 98R4 = VIT_MAX( R0 , R4 ) (ASR); 99R5 = VIT_MAX( R1 , R5 ) (ASR); 100R6 = VIT_MAX( R2 , R6 ) (ASR); 101R7 = VIT_MAX( R3 , R7 ) (ASR); 102CHECKREG r0, 0xE5041001; 103CHECKREG r1, 0x7F654B00; 104CHECKREG r2, 0xAF008FC0; 105CHECKREG r3, 0x1801910D; 106CHECKREG r4, 0x1001E504; 107CHECKREG r5, 0x7F657F65; 108CHECKREG r6, 0xAF00AF00; 109CHECKREG r7, 0x910D1801; 110 111 112 113pass 114