xref: /netbsd-src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/c_dsp32shift_vmax.s (revision 8e33eff89e26cf71871ead62f0d5063e1313c33a) 
1//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
2// Spec Reference: dsp32shift vmax
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10imm32 r0, 0x11001001;
11imm32 r1, 0x11001001;
12imm32 r2, 0x12345678;
13imm32 r3, 0x11001003;
14imm32 r4, 0x11001004;
15imm32 r5, 0x11001005;
16imm32 r6, 0x11001006;
17imm32 r7, 0x11001007;
18A0 = R2;
19R0.L = VIT_MAX( R0 ) (ASL);
20R1.L = VIT_MAX( R1 ) (ASL);
21R2.L = VIT_MAX( R2 ) (ASL);
22R3.L = VIT_MAX( R3 ) (ASL);
23R4.L = VIT_MAX( R4 ) (ASL);
24R5.L = VIT_MAX( R5 ) (ASL);
25R6.L = VIT_MAX( R6 ) (ASL);
26R7.L = VIT_MAX( R7 ) (ASL);
27CHECKREG r0, 0x11001100;
28CHECKREG r1, 0x11001100;
29CHECKREG r2, 0x12345678;
30CHECKREG r3, 0x11001100;
31CHECKREG r4, 0x11001100;
32CHECKREG r5, 0x11001100;
33CHECKREG r6, 0x11001100;
34CHECKREG r7, 0x11001100;
35
36imm32 r0, 0xa1001001;
37imm32 r1, 0x1b001001;
38imm32 r2, 0x11c01002;
39imm32 r3, 0x110d1003;
40imm32 r4, 0x1100e004;
41imm32 r5, 0x11001f05;
42imm32 r6, 0x11001006;
43imm32 r7, 0x11001001;
44R1.L = VIT_MAX( R0 ) (ASL);
45R2.L = VIT_MAX( R1 ) (ASL);
46R3.L = VIT_MAX( R2 ) (ASL);
47R4.L = VIT_MAX( R3 ) (ASL);
48R5.L = VIT_MAX( R4 ) (ASL);
49R6.L = VIT_MAX( R5 ) (ASL);
50R7.L = VIT_MAX( R6 ) (ASL);
51R0.L = VIT_MAX( R7 ) (ASL);
52CHECKREG r0, 0xA1001B00;
53CHECKREG r1, 0x1B001001;
54CHECKREG r2, 0x11C01B00;
55CHECKREG r3, 0x110D1B00;
56CHECKREG r4, 0x11001B00;
57CHECKREG r5, 0x11001B00;
58CHECKREG r6, 0x11001B00;
59CHECKREG r7, 0x11001B00;
60
61
62imm32 r0, 0x20000000;
63imm32 r1, 0x4300c001;
64imm32 r2, 0x4040c002;
65imm32 r3, 0x40056003;
66imm32 r4, 0x4000c704;
67imm32 r5, 0x4000c085;
68imm32 r6, 0x4000c096;
69imm32 r7, 0x4000c000;
70R0.L = VIT_MAX( R0 ) (ASR);
71R1.L = VIT_MAX( R1 ) (ASR);
72R2.L = VIT_MAX( R2 ) (ASR);
73R3.L = VIT_MAX( R3 ) (ASR);
74R4.L = VIT_MAX( R4 ) (ASR);
75R5.L = VIT_MAX( R5 ) (ASR);
76R6.L = VIT_MAX( R6 ) (ASR);
77R7.L = VIT_MAX( R7 ) (ASR);
78CHECKREG r0, 0x20002000;
79CHECKREG r1, 0x4300C001;
80CHECKREG r2, 0x4040C002;
81CHECKREG r3, 0x40056003;
82CHECKREG r4, 0x40004000;
83CHECKREG r5, 0x40004000;
84CHECKREG r6, 0x40004000;
85CHECKREG r7, 0x4000C000;
86
87imm32 r0, 0x10000000;
88imm32 r1, 0x4200c001;
89imm32 r2, 0x4030c002;
90imm32 r3, 0x4004c003;
91imm32 r4, 0x40005004;
92imm32 r5, 0x4000c605;
93imm32 r6, 0x4000c076;
94imm32 r7, 0x4000c008;
95R2.L = VIT_MAX( R0 ) (ASR);
96R3.L = VIT_MAX( R1 ) (ASR);
97R4.L = VIT_MAX( R2 ) (ASR);
98R5.L = VIT_MAX( R3 ) (ASR);
99R6.L = VIT_MAX( R4 ) (ASR);
100R7.L = VIT_MAX( R5 ) (ASR);
101R0.L = VIT_MAX( R6 ) (ASR);
102R1.L = VIT_MAX( R7 ) (ASR);
103CHECKREG r0, 0x10004030;
104CHECKREG r1, 0x42004000;
105CHECKREG r2, 0x40301000;
106CHECKREG r3, 0x4004C001;
107CHECKREG r4, 0x40004030;
108CHECKREG r5, 0x4000C001;
109CHECKREG r6, 0x40004030;
110CHECKREG r7, 0x40004000;
111
112
113pass
114