1//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp 2// Spec Reference: dsp32shift align24 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8imm32 r0, 0x00000001; 9imm32 r1, 0x01000801; 10imm32 r2, 0x08200802; 11imm32 r3, 0x08030803; 12imm32 r4, 0x08004804; 13imm32 r5, 0x08000505; 14imm32 r6, 0x08000866; 15imm32 r7, 0x08000807; 16R1 = ALIGN24 ( R1 , R0 ); 17R2 = ALIGN24 ( R2 , R0 ); 18R3 = ALIGN24 ( R3 , R0 ); 19R4 = ALIGN24 ( R4 , R0 ); 20R5 = ALIGN24 ( R5 , R0 ); 21R6 = ALIGN24 ( R6 , R0 ); 22R7 = ALIGN24 ( R7 , R0 ); 23R0 = ALIGN24 ( R0 , R0 ); 24CHECKREG r0, 0x00000100; 25CHECKREG r1, 0x00080100; 26CHECKREG r2, 0x20080200; 27CHECKREG r3, 0x03080300; 28CHECKREG r4, 0x00480400; 29CHECKREG r5, 0x00050500; 30CHECKREG r6, 0x00086600; 31CHECKREG r7, 0x00080700; 32 33imm32 r0, 0x0900d001; 34imm32 r1, 0x09000002; 35imm32 r2, 0x09400002; 36imm32 r3, 0x09100003; 37imm32 r4, 0x09020004; 38imm32 r5, 0x09003005; 39imm32 r6, 0x09000406; 40imm32 r7, 0x09000057; 41R0 = ALIGN24 ( R0 , R1 ); 42R2 = ALIGN24 ( R2 , R1 ); 43R3 = ALIGN24 ( R3 , R1 ); 44R4 = ALIGN24 ( R4 , R1 ); 45R5 = ALIGN24 ( R5 , R1 ); 46R6 = ALIGN24 ( R6 , R1 ); 47R7 = ALIGN24 ( R7 , R1 ); 48R1 = ALIGN24 ( R1 , R1 ); 49CHECKREG r0, 0x00D00109; 50CHECKREG r1, 0x00000209; 51CHECKREG r2, 0x40000209; 52CHECKREG r3, 0x10000309; 53CHECKREG r4, 0x02000409; 54CHECKREG r5, 0x00300509; 55CHECKREG r6, 0x00040609; 56CHECKREG r7, 0x00005709; 57 58 59imm32 r0, 0x0a00e001; 60imm32 r1, 0x0a00e001; 61imm32 r2, 0x0a00000f; 62imm32 r3, 0x0a400010; 63imm32 r4, 0x0a05e004; 64imm32 r5, 0x0a006005; 65imm32 r6, 0x0a00e706; 66imm32 r7, 0x0a00e087; 67R0 = ALIGN24 ( R0 , R2 ); 68R1 = ALIGN24 ( R1 , R2 ); 69R3 = ALIGN24 ( R3 , R2 ); 70R4 = ALIGN24 ( R4 , R2 ); 71R5 = ALIGN24 ( R5 , R2 ); 72R6 = ALIGN24 ( R6 , R2 ); 73R7 = ALIGN24 ( R7 , R2 ); 74R2 = ALIGN24 ( R2 , R2 ); 75CHECKREG r0, 0x00E0010A; 76CHECKREG r1, 0x00E0010A; 77CHECKREG r2, 0x00000F0A; 78CHECKREG r3, 0x4000100A; 79CHECKREG r4, 0x05E0040A; 80CHECKREG r5, 0x0060050A; 81CHECKREG r6, 0x00E7060A; 82CHECKREG r7, 0x00E0870A; 83 84imm32 r0, 0x2b00f001; 85imm32 r1, 0x0300f001; 86imm32 r2, 0x0b40f002; 87imm32 r3, 0x0b050010; 88imm32 r4, 0x0b006004; 89imm32 r5, 0x0b00f705; 90imm32 r6, 0x0b00f086; 91imm32 r7, 0x0b00f009; 92R0 = ALIGN24 ( R0 , R3 ); 93R1 = ALIGN24 ( R1 , R3 ); 94R2 = ALIGN24 ( R2 , R3 ); 95R4 = ALIGN24 ( R4 , R3 ); 96R5 = ALIGN24 ( R5 , R3 ); 97R6 = ALIGN24 ( R6 , R3 ); 98R7 = ALIGN24 ( R7 , R3 ); 99R3 = ALIGN24 ( R3 , R3 ); 100CHECKREG r0, 0x00F0010B; 101CHECKREG r1, 0x00F0010B; 102CHECKREG r2, 0x40F0020B; 103CHECKREG r3, 0x0500100B; 104CHECKREG r4, 0x0060040B; 105CHECKREG r5, 0x00F7050B; 106CHECKREG r6, 0x00F0860B; 107CHECKREG r7, 0x00F0090B; 108 109imm32 r0, 0x4c0000c0; 110imm32 r1, 0x050100c0; 111imm32 r2, 0x0c6200c0; 112imm32 r3, 0x0c0700c0; 113imm32 r4, 0x0c04800c; 114imm32 r5, 0x0c0509c0; 115imm32 r6, 0x0c060000; 116imm32 r7, 0x0c0700ca; 117R0 = ALIGN24 ( R0 , R4 ); 118R1 = ALIGN24 ( R1 , R4 ); 119R2 = ALIGN24 ( R2 , R4 ); 120R3 = ALIGN24 ( R3 , R4 ); 121R5 = ALIGN24 ( R5 , R4 ); 122R6 = ALIGN24 ( R6 , R4 ); 123R7 = ALIGN24 ( R7 , R4 ); 124R4 = ALIGN24 ( R4 , R4 ); 125CHECKREG r0, 0x0000C00C; 126CHECKREG r1, 0x0100C00C; 127CHECKREG r2, 0x6200C00C; 128CHECKREG r3, 0x0700C00C; 129CHECKREG r4, 0x04800C0C; 130CHECKREG r5, 0x0509C00C; 131CHECKREG r6, 0x0600000C; 132CHECKREG r7, 0x0700CA0C; 133 134imm32 r0, 0xa00100d0; 135imm32 r1, 0xa00100d1; 136imm32 r2, 0xa00200d0; 137imm32 r3, 0xa00300d0; 138imm32 r4, 0xa00400d0; 139imm32 r5, 0xa0050007; 140imm32 r6, 0xa00600d0; 141imm32 r7, 0xa00700d0; 142R0 = ALIGN24 ( R0 , R5 ); 143R1 = ALIGN24 ( R1 , R5 ); 144R2 = ALIGN24 ( R2 , R5 ); 145R3 = ALIGN24 ( R3 , R5 ); 146R4 = ALIGN24 ( R4 , R5 ); 147R6 = ALIGN24 ( R6 , R5 ); 148R7 = ALIGN24 ( R7 , R5 ); 149R5 = ALIGN24 ( R5 , R5 ); 150CHECKREG r0, 0x0100D0A0; 151CHECKREG r1, 0x0100D1A0; 152CHECKREG r2, 0x0200D0A0; 153CHECKREG r3, 0x0300D0A0; 154CHECKREG r4, 0x0400D0A0; 155CHECKREG r5, 0x050007A0; 156CHECKREG r6, 0x0600D0A0; 157CHECKREG r7, 0x0700D0A0; 158 159imm32 r0, 0xb2010000; 160imm32 r1, 0xb0310000; 161imm32 r2, 0xb042000f; 162imm32 r3, 0xbf030000; 163imm32 r4, 0xba040000; 164imm32 r5, 0xbb050000; 165imm32 r6, 0xbc060009; 166imm32 r7, 0xb0e70000; 167R0 = ALIGN24 ( R0 , R6 ); 168R1 = ALIGN24 ( R1 , R6 ); 169R2 = ALIGN24 ( R2 , R6 ); 170R3 = ALIGN24 ( R3 , R6 ); 171R4 = ALIGN24 ( R4 , R6 ); 172R5 = ALIGN24 ( R5 , R6 ); 173R6 = ALIGN24 ( R6 , R6 ); 174R7 = ALIGN24 ( R7 , R6 ); 175CHECKREG r0, 0x010000BC; 176CHECKREG r1, 0x310000BC; 177CHECKREG r2, 0x42000FBC; 178CHECKREG r3, 0x030000BC; 179CHECKREG r4, 0x040000BC; 180CHECKREG r5, 0x050000BC; 181CHECKREG r6, 0x060009BC; 182CHECKREG r7, 0xE7000006; 183 184imm32 r0, 0xd23100e0; 185imm32 r1, 0xd04500e0; 186imm32 r2, 0xde32f0e0; 187imm32 r3, 0xd90300e0; 188imm32 r4, 0xd07400e0; 189imm32 r5, 0xdef500e0; 190imm32 r6, 0xd06600e0; 191imm32 r7, 0xd0080023; 192R1 = ALIGN24 ( R0 , R7 ); 193R2 = ALIGN24 ( R1 , R7 ); 194R3 = ALIGN24 ( R2 , R7 ); 195R4 = ALIGN24 ( R3 , R7 ); 196R5 = ALIGN24 ( R4 , R7 ); 197R6 = ALIGN24 ( R5 , R7 ); 198R7 = ALIGN24 ( R6 , R7 ); 199R0 = ALIGN24 ( R7 , R7 ); 200CHECKREG r0, 0xD0D0D0D0; 201CHECKREG r1, 0x3100E0D0; 202CHECKREG r2, 0x00E0D0D0; 203CHECKREG r3, 0xE0D0D0D0; 204CHECKREG r4, 0xD0D0D0D0; 205CHECKREG r5, 0xD0D0D0D0; 206CHECKREG r6, 0xD0D0D0D0; 207CHECKREG r7, 0xD0D0D0D0; 208 209 210pass 211