1 /* gdb.c --- sim interface to GDB. 2 3 Copyright (C) 2005-2015 Free Software Foundation, Inc. 4 Contributed by Red Hat, Inc. 5 6 This file is part of the GNU simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "config.h" 22 #include <stdio.h> 23 #include <assert.h> 24 #include <signal.h> 25 #include <stdlib.h> 26 #include <string.h> 27 #include <ctype.h> 28 29 #include "ansidecl.h" 30 #include "gdb/callback.h" 31 #include "gdb/remote-sim.h" 32 #include "gdb/signals.h" 33 #include "gdb/sim-m32c.h" 34 35 #include "cpu.h" 36 #include "mem.h" 37 #include "load.h" 38 #include "syscalls.h" 39 #ifdef TIMER_A 40 #include "timer_a.h" 41 #endif 42 43 /* I don't want to wrap up all the minisim's data structures in an 44 object and pass that around. That'd be a big change, and neither 45 GDB nor run needs that ability. 46 47 So we just have one instance, that lives in global variables, and 48 each time we open it, we re-initialize it. */ 49 struct sim_state 50 { 51 const char *message; 52 }; 53 54 static struct sim_state the_minisim = { 55 "This is the sole m32c minisim instance. See libsim.a's global variables." 56 }; 57 58 static int open; 59 60 SIM_DESC 61 sim_open (SIM_OPEN_KIND kind, 62 struct host_callback_struct *callback, 63 struct bfd *abfd, char **argv) 64 { 65 setbuf (stdout, 0); 66 if (open) 67 fprintf (stderr, "m32c minisim: re-opened sim\n"); 68 69 /* The 'run' interface doesn't use this function, so we don't care 70 about KIND; it's always SIM_OPEN_DEBUG. */ 71 if (kind != SIM_OPEN_DEBUG) 72 fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n", 73 kind); 74 75 if (abfd) 76 m32c_set_mach (bfd_get_mach (abfd)); 77 78 /* We can use ABFD, if non-NULL to select the appropriate 79 architecture. But we only support the r8c right now. */ 80 81 set_callbacks (callback); 82 83 /* We don't expect any command-line arguments. */ 84 85 init_mem (); 86 init_regs (); 87 88 open = 1; 89 return &the_minisim; 90 } 91 92 static void 93 check_desc (SIM_DESC sd) 94 { 95 if (sd != &the_minisim) 96 fprintf (stderr, "m32c minisim: desc != &the_minisim\n"); 97 } 98 99 void 100 sim_close (SIM_DESC sd, int quitting) 101 { 102 check_desc (sd); 103 104 /* Not much to do. At least free up our memory. */ 105 init_mem (); 106 107 open = 0; 108 } 109 110 static bfd * 111 open_objfile (const char *filename) 112 { 113 bfd *prog = bfd_openr (filename, 0); 114 115 if (!prog) 116 { 117 fprintf (stderr, "Can't read %s\n", filename); 118 return 0; 119 } 120 121 if (!bfd_check_format (prog, bfd_object)) 122 { 123 fprintf (stderr, "%s not a m32c program\n", filename); 124 return 0; 125 } 126 127 return prog; 128 } 129 130 131 SIM_RC 132 sim_load (SIM_DESC sd, const char *prog, struct bfd * abfd, int from_tty) 133 { 134 check_desc (sd); 135 136 if (!abfd) 137 abfd = open_objfile (prog); 138 if (!abfd) 139 return SIM_RC_FAIL; 140 141 m32c_load (abfd); 142 143 return SIM_RC_OK; 144 } 145 146 SIM_RC 147 sim_create_inferior (SIM_DESC sd, struct bfd * abfd, char **argv, char **env) 148 { 149 check_desc (sd); 150 151 if (abfd) 152 m32c_load (abfd); 153 154 return SIM_RC_OK; 155 } 156 157 int 158 sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) 159 { 160 check_desc (sd); 161 162 if (mem == 0) 163 return 0; 164 165 mem_get_blk ((int) mem, buf, length); 166 167 return length; 168 } 169 170 int 171 sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length) 172 { 173 check_desc (sd); 174 175 mem_put_blk ((int) mem, buf, length); 176 177 return length; 178 } 179 180 181 /* Read the LENGTH bytes at BUF as an little-endian value. */ 182 static DI 183 get_le (unsigned char *buf, int length) 184 { 185 DI acc = 0; 186 while (--length >= 0) 187 acc = (acc << 8) + buf[length]; 188 189 return acc; 190 } 191 192 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */ 193 static void 194 put_le (unsigned char *buf, int length, DI val) 195 { 196 int i; 197 198 for (i = 0; i < length; i++) 199 { 200 buf[i] = val & 0xff; 201 val >>= 8; 202 } 203 } 204 205 static int 206 check_regno (enum m32c_sim_reg regno) 207 { 208 return 0 <= regno && regno < m32c_sim_reg_num_regs; 209 } 210 211 static size_t 212 mask_size (int addr_mask) 213 { 214 switch (addr_mask) 215 { 216 case 0xffff: 217 return 2; 218 case 0xfffff: 219 case 0xffffff: 220 return 3; 221 default: 222 fprintf (stderr, 223 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n", 224 addr_mask); 225 return sizeof (addr_mask); 226 } 227 } 228 229 static size_t 230 reg_size (enum m32c_sim_reg regno) 231 { 232 switch (regno) 233 { 234 case m32c_sim_reg_r0_bank0: 235 case m32c_sim_reg_r1_bank0: 236 case m32c_sim_reg_r2_bank0: 237 case m32c_sim_reg_r3_bank0: 238 case m32c_sim_reg_r0_bank1: 239 case m32c_sim_reg_r1_bank1: 240 case m32c_sim_reg_r2_bank1: 241 case m32c_sim_reg_r3_bank1: 242 case m32c_sim_reg_flg: 243 case m32c_sim_reg_svf: 244 return 2; 245 246 case m32c_sim_reg_a0_bank0: 247 case m32c_sim_reg_a1_bank0: 248 case m32c_sim_reg_fb_bank0: 249 case m32c_sim_reg_sb_bank0: 250 case m32c_sim_reg_a0_bank1: 251 case m32c_sim_reg_a1_bank1: 252 case m32c_sim_reg_fb_bank1: 253 case m32c_sim_reg_sb_bank1: 254 case m32c_sim_reg_usp: 255 case m32c_sim_reg_isp: 256 return mask_size (addr_mask); 257 258 case m32c_sim_reg_pc: 259 case m32c_sim_reg_intb: 260 case m32c_sim_reg_svp: 261 case m32c_sim_reg_vct: 262 return mask_size (membus_mask); 263 264 case m32c_sim_reg_dmd0: 265 case m32c_sim_reg_dmd1: 266 return 1; 267 268 case m32c_sim_reg_dct0: 269 case m32c_sim_reg_dct1: 270 case m32c_sim_reg_drc0: 271 case m32c_sim_reg_drc1: 272 return 2; 273 274 case m32c_sim_reg_dma0: 275 case m32c_sim_reg_dma1: 276 case m32c_sim_reg_dsa0: 277 case m32c_sim_reg_dsa1: 278 case m32c_sim_reg_dra0: 279 case m32c_sim_reg_dra1: 280 return 3; 281 282 default: 283 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 284 regno); 285 return -1; 286 } 287 } 288 289 int 290 sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) 291 { 292 size_t size; 293 294 check_desc (sd); 295 296 if (!check_regno (regno)) 297 return 0; 298 299 size = reg_size (regno); 300 if (length == size) 301 { 302 DI val; 303 304 switch (regno) 305 { 306 case m32c_sim_reg_r0_bank0: 307 val = regs.r[0].r_r0; 308 break; 309 case m32c_sim_reg_r1_bank0: 310 val = regs.r[0].r_r1; 311 break; 312 case m32c_sim_reg_r2_bank0: 313 val = regs.r[0].r_r2; 314 break; 315 case m32c_sim_reg_r3_bank0: 316 val = regs.r[0].r_r3; 317 break; 318 case m32c_sim_reg_a0_bank0: 319 val = regs.r[0].r_a0; 320 break; 321 case m32c_sim_reg_a1_bank0: 322 val = regs.r[0].r_a1; 323 break; 324 case m32c_sim_reg_fb_bank0: 325 val = regs.r[0].r_fb; 326 break; 327 case m32c_sim_reg_sb_bank0: 328 val = regs.r[0].r_sb; 329 break; 330 case m32c_sim_reg_r0_bank1: 331 val = regs.r[1].r_r0; 332 break; 333 case m32c_sim_reg_r1_bank1: 334 val = regs.r[1].r_r1; 335 break; 336 case m32c_sim_reg_r2_bank1: 337 val = regs.r[1].r_r2; 338 break; 339 case m32c_sim_reg_r3_bank1: 340 val = regs.r[1].r_r3; 341 break; 342 case m32c_sim_reg_a0_bank1: 343 val = regs.r[1].r_a0; 344 break; 345 case m32c_sim_reg_a1_bank1: 346 val = regs.r[1].r_a1; 347 break; 348 case m32c_sim_reg_fb_bank1: 349 val = regs.r[1].r_fb; 350 break; 351 case m32c_sim_reg_sb_bank1: 352 val = regs.r[1].r_sb; 353 break; 354 355 case m32c_sim_reg_usp: 356 val = regs.r_usp; 357 break; 358 case m32c_sim_reg_isp: 359 val = regs.r_isp; 360 break; 361 case m32c_sim_reg_pc: 362 val = regs.r_pc; 363 break; 364 case m32c_sim_reg_intb: 365 val = regs.r_intbl * 65536 + regs.r_intbl; 366 break; 367 case m32c_sim_reg_flg: 368 val = regs.r_flags; 369 break; 370 371 /* These registers aren't implemented by the minisim. */ 372 case m32c_sim_reg_svf: 373 case m32c_sim_reg_svp: 374 case m32c_sim_reg_vct: 375 case m32c_sim_reg_dmd0: 376 case m32c_sim_reg_dmd1: 377 case m32c_sim_reg_dct0: 378 case m32c_sim_reg_dct1: 379 case m32c_sim_reg_drc0: 380 case m32c_sim_reg_drc1: 381 case m32c_sim_reg_dma0: 382 case m32c_sim_reg_dma1: 383 case m32c_sim_reg_dsa0: 384 case m32c_sim_reg_dsa1: 385 case m32c_sim_reg_dra0: 386 case m32c_sim_reg_dra1: 387 return 0; 388 389 default: 390 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 391 regno); 392 return -1; 393 } 394 395 put_le (buf, length, val); 396 } 397 398 return size; 399 } 400 401 int 402 sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) 403 { 404 size_t size; 405 406 check_desc (sd); 407 408 if (!check_regno (regno)) 409 return -1; 410 411 size = reg_size (regno); 412 413 if (length == size) 414 { 415 DI val = get_le (buf, length); 416 417 switch (regno) 418 { 419 case m32c_sim_reg_r0_bank0: 420 regs.r[0].r_r0 = val & 0xffff; 421 break; 422 case m32c_sim_reg_r1_bank0: 423 regs.r[0].r_r1 = val & 0xffff; 424 break; 425 case m32c_sim_reg_r2_bank0: 426 regs.r[0].r_r2 = val & 0xffff; 427 break; 428 case m32c_sim_reg_r3_bank0: 429 regs.r[0].r_r3 = val & 0xffff; 430 break; 431 case m32c_sim_reg_a0_bank0: 432 regs.r[0].r_a0 = val & addr_mask; 433 break; 434 case m32c_sim_reg_a1_bank0: 435 regs.r[0].r_a1 = val & addr_mask; 436 break; 437 case m32c_sim_reg_fb_bank0: 438 regs.r[0].r_fb = val & addr_mask; 439 break; 440 case m32c_sim_reg_sb_bank0: 441 regs.r[0].r_sb = val & addr_mask; 442 break; 443 case m32c_sim_reg_r0_bank1: 444 regs.r[1].r_r0 = val & 0xffff; 445 break; 446 case m32c_sim_reg_r1_bank1: 447 regs.r[1].r_r1 = val & 0xffff; 448 break; 449 case m32c_sim_reg_r2_bank1: 450 regs.r[1].r_r2 = val & 0xffff; 451 break; 452 case m32c_sim_reg_r3_bank1: 453 regs.r[1].r_r3 = val & 0xffff; 454 break; 455 case m32c_sim_reg_a0_bank1: 456 regs.r[1].r_a0 = val & addr_mask; 457 break; 458 case m32c_sim_reg_a1_bank1: 459 regs.r[1].r_a1 = val & addr_mask; 460 break; 461 case m32c_sim_reg_fb_bank1: 462 regs.r[1].r_fb = val & addr_mask; 463 break; 464 case m32c_sim_reg_sb_bank1: 465 regs.r[1].r_sb = val & addr_mask; 466 break; 467 468 case m32c_sim_reg_usp: 469 regs.r_usp = val & addr_mask; 470 break; 471 case m32c_sim_reg_isp: 472 regs.r_isp = val & addr_mask; 473 break; 474 case m32c_sim_reg_pc: 475 regs.r_pc = val & membus_mask; 476 break; 477 case m32c_sim_reg_intb: 478 regs.r_intbl = (val & membus_mask) & 0xffff; 479 regs.r_intbh = (val & membus_mask) >> 16; 480 break; 481 case m32c_sim_reg_flg: 482 regs.r_flags = val & 0xffff; 483 break; 484 485 /* These registers aren't implemented by the minisim. */ 486 case m32c_sim_reg_svf: 487 case m32c_sim_reg_svp: 488 case m32c_sim_reg_vct: 489 case m32c_sim_reg_dmd0: 490 case m32c_sim_reg_dmd1: 491 case m32c_sim_reg_dct0: 492 case m32c_sim_reg_dct1: 493 case m32c_sim_reg_drc0: 494 case m32c_sim_reg_drc1: 495 case m32c_sim_reg_dma0: 496 case m32c_sim_reg_dma1: 497 case m32c_sim_reg_dsa0: 498 case m32c_sim_reg_dsa1: 499 case m32c_sim_reg_dra0: 500 case m32c_sim_reg_dra1: 501 return 0; 502 503 default: 504 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 505 regno); 506 return 0; 507 } 508 } 509 510 return size; 511 } 512 513 static volatile int stop; 514 static enum sim_stop reason; 515 static int siggnal; 516 517 518 /* Given a signal number used by the M32C bsp (that is, newlib), 519 return a target signal number used by GDB. */ 520 static int 521 m32c_signal_to_target (int m32c) 522 { 523 switch (m32c) 524 { 525 case 4: 526 return GDB_SIGNAL_ILL; 527 528 case 5: 529 return GDB_SIGNAL_TRAP; 530 531 case 10: 532 return GDB_SIGNAL_BUS; 533 534 case 11: 535 return GDB_SIGNAL_SEGV; 536 537 case 24: 538 return GDB_SIGNAL_XCPU; 539 540 case 2: 541 return GDB_SIGNAL_INT; 542 543 case 8: 544 return GDB_SIGNAL_FPE; 545 546 case 6: 547 return GDB_SIGNAL_ABRT; 548 } 549 550 return 0; 551 } 552 553 554 /* Take a step return code RC and set up the variables consulted by 555 sim_stop_reason appropriately. */ 556 static void 557 handle_step (int rc) 558 { 559 if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc)) 560 { 561 reason = sim_stopped; 562 siggnal = GDB_SIGNAL_TRAP; 563 } 564 else if (M32C_STOPPED (rc)) 565 { 566 reason = sim_stopped; 567 siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc)); 568 } 569 else 570 { 571 assert (M32C_EXITED (rc)); 572 reason = sim_exited; 573 siggnal = M32C_EXIT_STATUS (rc); 574 } 575 } 576 577 578 void 579 sim_resume (SIM_DESC sd, int step, int sig_to_deliver) 580 { 581 check_desc (sd); 582 583 if (sig_to_deliver != 0) 584 { 585 fprintf (stderr, 586 "Warning: the m32c minisim does not implement " 587 "signal delivery yet.\n" "Resuming with no signal.\n"); 588 } 589 590 if (step) 591 { 592 handle_step (decode_opcode ()); 593 #ifdef TIMER_A 594 update_timer_a (); 595 #endif 596 } 597 else 598 { 599 /* We don't clear 'stop' here, because then we would miss 600 interrupts that arrived on the way here. Instead, we clear 601 the flag in sim_stop_reason, after GDB has disabled the 602 interrupt signal handler. */ 603 for (;;) 604 { 605 int rc; 606 607 if (stop) 608 { 609 stop = 0; 610 reason = sim_stopped; 611 siggnal = GDB_SIGNAL_INT; 612 break; 613 } 614 615 rc = decode_opcode (); 616 #ifdef TIMER_A 617 update_timer_a (); 618 #endif 619 620 if (!M32C_STEPPED (rc)) 621 { 622 handle_step (rc); 623 break; 624 } 625 } 626 } 627 m32c_sim_restore_console (); 628 } 629 630 int 631 sim_stop (SIM_DESC sd) 632 { 633 stop = 1; 634 635 return 1; 636 } 637 638 void 639 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p) 640 { 641 check_desc (sd); 642 643 *reason_p = reason; 644 *sigrc_p = siggnal; 645 } 646 647 void 648 sim_do_command (SIM_DESC sd, const char *cmd) 649 { 650 const char *args; 651 char *p = strdup (cmd); 652 653 check_desc (sd); 654 655 /* Skip leading whitespace. */ 656 while (isspace (*p)) 657 p++; 658 659 /* Find the extent of the command word. */ 660 for (p = cmd; *p; p++) 661 if (isspace (*p)) 662 break; 663 664 /* Null-terminate the command word, and record the start of any 665 further arguments. */ 666 if (*p) 667 { 668 *p = '\0'; 669 args = p + 1; 670 while (isspace (*args)) 671 args++; 672 } 673 else 674 args = p; 675 676 if (strcmp (cmd, "trace") == 0) 677 { 678 if (strcmp (args, "on") == 0) 679 trace = 1; 680 else if (strcmp (args, "off") == 0) 681 trace = 0; 682 else 683 printf ("The 'sim trace' command expects 'on' or 'off' " 684 "as an argument.\n"); 685 } 686 else if (strcmp (cmd, "verbose") == 0) 687 { 688 if (strcmp (args, "on") == 0) 689 verbose = 1; 690 else if (strcmp (args, "off") == 0) 691 verbose = 0; 692 else 693 printf ("The 'sim verbose' command expects 'on' or 'off'" 694 " as an argument.\n"); 695 } 696 else 697 printf ("The 'sim' command expects either 'trace' or 'verbose'" 698 " as a subcommand.\n"); 699 700 free (p); 701 } 702 703 char ** 704 sim_complete_command (SIM_DESC sd, const char *text, const char *word) 705 { 706 return NULL; 707 } 708