1 /* Simulation code for the CR16 processor. 2 Copyright (C) 2008-2015 Free Software Foundation, Inc. 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include <inttypes.h> 22 #include <signal.h> 23 #include <stdlib.h> 24 #include <string.h> 25 #include "bfd.h" 26 #include "gdb/callback.h" 27 #include "gdb/remote-sim.h" 28 29 #include "sim-main.h" 30 #include "sim-options.h" 31 32 #include "gdb/sim-cr16.h" 33 #include "gdb/signals.h" 34 #include "opcode/cr16.h" 35 36 int cr16_debug; 37 38 host_callback *cr16_callback; 39 40 uint32 OP[4]; 41 uint32 sign_flag; 42 43 static struct hash_entry *lookup_hash (uint64 ins, int size); 44 static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops); 45 static INLINE uint8 *map_memory (unsigned phys_addr); 46 47 #define MAX_HASH 16 48 49 struct hash_entry 50 { 51 struct hash_entry *next; 52 uint32 opcode; 53 uint32 mask; 54 int format; 55 int size; 56 struct simops *ops; 57 }; 58 59 struct hash_entry hash_table[MAX_HASH+1]; 60 61 INLINE static long 62 hash(unsigned long long insn, int format) 63 { 64 unsigned int i = 4, tmp; 65 if (format) 66 { 67 while ((insn >> i) != 0) i +=4; 68 69 return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key. */ 70 } 71 return ((insn & 0xF)); /* Use last 4 bits as hask key. */ 72 } 73 74 75 INLINE static struct hash_entry * 76 lookup_hash (uint64 ins, int size) 77 { 78 uint32 mask; 79 struct hash_entry *h; 80 81 h = &hash_table[hash(ins,1)]; 82 83 84 mask = (((1 << (32 - h->mask)) -1) << h->mask); 85 86 /* Adjuest mask for branch with 2 word instructions. */ 87 if ((h->ops->mnimonic != NULL) && 88 ((streq(h->ops->mnimonic,"b") && h->size == 2))) 89 mask = 0xff0f0000; 90 91 92 while ((ins & mask) != (BIN(h->opcode, h->mask))) 93 { 94 if (h->next == NULL) 95 { 96 State.exception = SIGILL; 97 State.pc_changed = 1; /* Don't increment the PC. */ 98 return NULL; 99 } 100 h = h->next; 101 102 mask = (((1 << (32 - h->mask)) -1) << h->mask); 103 /* Adjuest mask for branch with 2 word instructions. */ 104 if ((streq(h->ops->mnimonic,"b")) && h->size == 2) 105 mask = 0xff0f0000; 106 107 } 108 return (h); 109 } 110 111 INLINE static void 112 get_operands (operand_desc *s, uint64 ins, int isize, int nops) 113 { 114 uint32 i, opn = 0, start_bit = 0, op_type = 0; 115 int32 op_size = 0, mask = 0; 116 117 if (isize == 1) /* Trunkcate the extra 16 bits of INS. */ 118 ins = ins >> 16; 119 120 for (i=0; i < 4; ++i,++opn) 121 { 122 if (s[opn].op_type == dummy) break; 123 124 op_type = s[opn].op_type; 125 start_bit = s[opn].shift; 126 op_size = cr16_optab[op_type].bit_size; 127 128 switch (op_type) 129 { 130 case imm3: case imm4: case imm5: case imm6: 131 { 132 if (isize == 1) 133 OP[i] = ((ins >> 4) & ((1 << op_size) -1)); 134 else 135 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1)); 136 137 if (OP[i] & ((long)1 << (op_size -1))) 138 { 139 sign_flag = 1; 140 OP[i] = ~(OP[i]) + 1; 141 } 142 OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1)); 143 } 144 break; 145 146 case uimm3: case uimm3_1: case uimm4_1: 147 switch (isize) 148 { 149 case 1: 150 OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break; 151 case 2: 152 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break; 153 default: /* for case 3. */ 154 OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break; 155 break; 156 } 157 break; 158 159 case uimm4: 160 switch (isize) 161 { 162 case 1: 163 if (start_bit == 20) 164 OP[i] = ((ins >> 4) & ((1 << op_size) -1)); 165 else 166 OP[i] = (ins & ((1 << op_size) -1)); 167 break; 168 case 2: 169 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); 170 break; 171 case 3: 172 OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1)); 173 break; 174 default: 175 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1)); 176 break; 177 } 178 break; 179 180 case imm16: case uimm16: 181 OP[i] = ins & 0xFFFF; 182 break; 183 184 case uimm20: case imm20: 185 OP[i] = ins & (((long)1 << op_size) - 1); 186 break; 187 188 case imm32: case uimm32: 189 OP[i] = ins & 0xFFFFFFFF; 190 break; 191 192 case uimm5: break; /*NOT USED. */ 193 OP[i] = ins & ((1 << op_size) - 1); break; 194 195 case disps5: 196 OP[i] = (ins >> 4) & ((1 << 4) - 1); 197 OP[i] = (OP[i] * 2) + 2; 198 if (OP[i] & ((long)1 << 5)) 199 { 200 sign_flag = 1; 201 OP[i] = ~(OP[i]) + 1; 202 OP[i] = (unsigned long int)(OP[i] & 0x1F); 203 } 204 break; 205 206 case dispe9: 207 OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf)); 208 OP[i] <<= 1; 209 if (OP[i] & ((long)1 << 8)) 210 { 211 sign_flag = 1; 212 OP[i] = ~(OP[i]) + 1; 213 OP[i] = (unsigned long int)(OP[i] & 0xFF); 214 } 215 break; 216 217 case disps17: 218 OP[i] = (ins & 0xFFFF); 219 if (OP[i] & 1) 220 { 221 OP[i] = (OP[i] & 0xFFFE); 222 sign_flag = 1; 223 OP[i] = ~(OP[i]) + 1; 224 OP[i] = (unsigned long int)(OP[i] & 0xFFFF); 225 } 226 break; 227 228 case disps25: 229 if (isize == 2) 230 OP[i] = (ins & 0xFFFFFF); 231 else 232 OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) | 233 (((ins >> 16) & 0xf) << 20); 234 235 if (OP[i] & 1) 236 { 237 OP[i] = (OP[i] & 0xFFFFFE); 238 sign_flag = 1; 239 OP[i] = ~(OP[i]) + 1; 240 OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF); 241 } 242 break; 243 244 case abs20: 245 if (isize == 3) 246 OP[i] = (ins) & 0xFFFFF; 247 else 248 OP[i] = (ins >> start_bit) & 0xFFFFF; 249 break; 250 case abs24: 251 if (isize == 3) 252 OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20) 253 | (((ins >> 24) & 0xf) << 16)); 254 else 255 OP[i] = (ins >> 16) & 0xFFFFFF; 256 break; 257 258 case rra: 259 case rbase: break; /* NOT USED. */ 260 case rbase_disps20: case rbase_dispe20: 261 case rpbase_disps20: case rpindex_disps20: 262 OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF)); 263 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ 264 break; 265 case rpbase_disps0: 266 OP[i] = 0; /* 4 bit disp const. */ 267 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ 268 break; 269 case rpbase_dispe4: 270 OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */ 271 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ 272 break; 273 case rpbase_disps4: 274 OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */ 275 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */ 276 break; 277 case rpbase_disps16: 278 OP[i] = (ins) & 0xFFFF; 279 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ 280 break; 281 case rpindex_disps0: 282 OP[i] = 0; 283 OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */ 284 OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */ 285 break; 286 case rpindex_disps14: 287 OP[i] = (ins) & 0x3FFF; 288 OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */ 289 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ 290 case rindex7_abs20: 291 case rindex8_abs20: 292 OP[i] = (ins) & 0xFFFFF; 293 OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */ 294 OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */ 295 break; 296 case regr: case regp: case pregr: case pregrp: 297 switch(isize) 298 { 299 case 1: 300 if (start_bit == 20) OP[i] = (ins >> 4) & 0xF; 301 else if (start_bit == 16) OP[i] = ins & 0xF; 302 break; 303 case 2: OP[i] = (ins >> start_bit) & 0xF; break; 304 case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break; 305 } 306 break; 307 case cc: 308 { 309 if (isize == 1) OP[i] = (ins >> 4) & 0xF; 310 else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF; 311 else OP[i] = (ins >> (start_bit + 16)) & 0xF; 312 break; 313 } 314 default: break; 315 } 316 317 /* For ESC on uimm4_1 operand. */ 318 if (op_type == uimm4_1) 319 if (OP[i] == 9) 320 OP[i] = -1; 321 322 /* For increment by 1. */ 323 if ((op_type == pregr) || (op_type == pregrp)) 324 OP[i] += 1; 325 } 326 /* FIXME: for tracing, update values that need to be updated each 327 instruction decode cycle */ 328 State.trace.psw = PSR; 329 } 330 331 static int 332 do_run (SIM_DESC sd, uint64 mcode) 333 { 334 host_callback *cr16_callback = STATE_CALLBACK (sd); 335 struct simops *s= Simops; 336 struct hash_entry *h; 337 char func[12]="\0"; 338 uint8 *iaddr; 339 #ifdef DEBUG 340 if ((cr16_debug & DEBUG_INSTRUCTION) != 0) 341 (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode); 342 #endif 343 344 h = lookup_hash(mcode, 1); 345 346 if ((h == NULL) || (h->opcode == 0)) 347 return 0; 348 349 if (h->size == 3) 350 { 351 iaddr = imem_addr ((uint32)PC + 2); 352 mcode = (mcode << 16) | get_longword( iaddr ); 353 } 354 355 /* Re-set OP list. */ 356 OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0; 357 358 /* for push/pop/pushrtn with RA instructions. */ 359 if ((h->format & REG_LIST) && (mcode & 0x800000)) 360 OP[2] = 1; /* Set 1 for RA operand. */ 361 362 /* numops == 0 means, no operands. */ 363 if (((h->ops) != NULL) && (((h->ops)->numops) != 0)) 364 get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops); 365 366 //State.ins_type = h->flags; 367 368 (h->ops->func)(); 369 370 return h->size; 371 } 372 373 static void 374 sim_size (int power) 375 { 376 int i; 377 for (i = 0; i < IMEM_SEGMENTS; i++) 378 { 379 if (State.mem.insn[i]) 380 free (State.mem.insn[i]); 381 } 382 for (i = 0; i < DMEM_SEGMENTS; i++) 383 { 384 if (State.mem.data[i]) 385 free (State.mem.data[i]); 386 } 387 for (i = 0; i < UMEM_SEGMENTS; i++) 388 { 389 if (State.mem.unif[i]) 390 free (State.mem.unif[i]); 391 } 392 /* Always allocate dmem segment 0. This contains the IMAP and DMAP 393 registers. */ 394 State.mem.data[0] = calloc (1, SEGMENT_SIZE); 395 } 396 397 /* For tracing - leave info on last access around. */ 398 static char *last_segname = "invalid"; 399 static char *last_from = "invalid"; 400 static char *last_to = "invalid"; 401 402 enum 403 { 404 IMAP0_OFFSET = 0xff00, 405 DMAP0_OFFSET = 0xff08, 406 DMAP2_SHADDOW = 0xff04, 407 DMAP2_OFFSET = 0xff0c 408 }; 409 410 static unsigned long 411 dmap_register (void *regcache, int reg_nr) 412 { 413 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA 414 + DMAP0_OFFSET + 2 * reg_nr); 415 return READ_16 (raw); 416 } 417 418 static unsigned long 419 imap_register (void *regcache, int reg_nr) 420 { 421 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA 422 + IMAP0_OFFSET + 2 * reg_nr); 423 return READ_16 (raw); 424 } 425 426 /* Given a virtual address in the DMAP address space, translate it 427 into a physical address. */ 428 429 unsigned long 430 sim_cr16_translate_dmap_addr (unsigned long offset, 431 int nr_bytes, 432 unsigned long *phys, 433 void *regcache, 434 unsigned long (*dmap_register) (void *regcache, 435 int reg_nr)) 436 { 437 short map; 438 int regno; 439 last_from = "logical-data"; 440 if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS) 441 { 442 /* Logical address out side of data segments, not supported */ 443 return 0; 444 } 445 regno = (offset / DMAP_BLOCK_SIZE); 446 offset = (offset % DMAP_BLOCK_SIZE); 447 448 #if 1 449 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE) 450 { 451 /* Don't cross a BLOCK boundary */ 452 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE); 453 } 454 map = dmap_register (regcache, regno); 455 if (regno == 3) 456 { 457 /* Always maps to data memory */ 458 int iospi = (offset / 0x1000) % 4; 459 int iosp = (map >> (4 * (3 - iospi))) % 0x10; 460 last_to = "io-space"; 461 *phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset); 462 } 463 else 464 { 465 int sp = ((map & 0x3000) >> 12); 466 int segno = (map & 0x3ff); 467 switch (sp) 468 { 469 case 0: /* 00: Unified memory */ 470 *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; 471 last_to = "unified"; 472 break; 473 case 1: /* 01: Instruction Memory */ 474 *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; 475 last_to = "chip-insn"; 476 break; 477 case 2: /* 10: Internal data memory */ 478 *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; 479 last_to = "chip-data"; 480 break; 481 case 3: /* 11: Reserved */ 482 return 0; 483 } 484 } 485 #endif 486 return nr_bytes; 487 } 488 489 /* Given a virtual address in the IMAP address space, translate it 490 into a physical address. */ 491 492 unsigned long 493 sim_cr16_translate_imap_addr (unsigned long offset, 494 int nr_bytes, 495 unsigned long *phys, 496 void *regcache, 497 unsigned long (*imap_register) (void *regcache, 498 int reg_nr)) 499 { 500 short map; 501 int regno; 502 int sp; 503 int segno; 504 last_from = "logical-insn"; 505 if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS)) 506 { 507 /* Logical address outside of IMAP segments, not supported */ 508 return 0; 509 } 510 regno = (offset / IMAP_BLOCK_SIZE); 511 offset = (offset % IMAP_BLOCK_SIZE); 512 if (offset + nr_bytes > IMAP_BLOCK_SIZE) 513 { 514 /* Don't cross a BLOCK boundary */ 515 nr_bytes = IMAP_BLOCK_SIZE - offset; 516 } 517 map = imap_register (regcache, regno); 518 sp = (map & 0x3000) >> 12; 519 segno = (map & 0x007f); 520 switch (sp) 521 { 522 case 0: /* 00: unified memory */ 523 *phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset; 524 last_to = "unified"; 525 break; 526 case 1: /* 01: instruction memory */ 527 *phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset; 528 last_to = "chip-insn"; 529 break; 530 case 2: /*10*/ 531 /* Reserved. */ 532 return 0; 533 case 3: /* 11: for testing - instruction memory */ 534 offset = (offset % 0x800); 535 *phys = SIM_CR16_MEMORY_INSN + offset; 536 if (offset + nr_bytes > 0x800) 537 /* don't cross VM boundary */ 538 nr_bytes = 0x800 - offset; 539 last_to = "test-insn"; 540 break; 541 } 542 return nr_bytes; 543 } 544 545 unsigned long 546 sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes, 547 unsigned long *targ_addr, void *regcache, 548 unsigned long (*dmap_register) (void *regcache, 549 int reg_nr), 550 unsigned long (*imap_register) (void *regcache, 551 int reg_nr)) 552 { 553 unsigned long phys; 554 unsigned long seg; 555 unsigned long off; 556 557 last_from = "unknown"; 558 last_to = "unknown"; 559 560 seg = (memaddr >> 24); 561 off = (memaddr & 0xffffffL); 562 563 switch (seg) 564 { 565 case 0x00: /* Physical unified memory */ 566 last_from = "phys-unified"; 567 last_to = "unified"; 568 phys = SIM_CR16_MEMORY_UNIFIED + off; 569 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 570 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 571 break; 572 573 case 0x01: /* Physical instruction memory */ 574 last_from = "phys-insn"; 575 last_to = "chip-insn"; 576 phys = SIM_CR16_MEMORY_INSN + off; 577 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 578 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 579 break; 580 581 case 0x02: /* Physical data memory segment */ 582 last_from = "phys-data"; 583 last_to = "chip-data"; 584 phys = SIM_CR16_MEMORY_DATA + off; 585 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) 586 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); 587 break; 588 589 case 0x10: /* in logical data address segment */ 590 nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache, 591 dmap_register); 592 break; 593 594 case 0x11: /* in logical instruction address segment */ 595 nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache, 596 imap_register); 597 break; 598 599 default: 600 return 0; 601 } 602 603 *targ_addr = phys; 604 return nr_bytes; 605 } 606 607 /* Return a pointer into the raw buffer designated by phys_addr. It 608 is assumed that the client has already ensured that the access 609 isn't going to cross a segment boundary. */ 610 611 uint8 * 612 map_memory (unsigned phys_addr) 613 { 614 uint8 **memory; 615 uint8 *raw; 616 unsigned offset; 617 int segment = ((phys_addr >> 24) & 0xff); 618 619 switch (segment) 620 { 621 622 case 0x00: /* Unified memory */ 623 { 624 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; 625 last_segname = "umem"; 626 break; 627 } 628 629 case 0x01: /* On-chip insn memory */ 630 { 631 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; 632 last_segname = "imem"; 633 break; 634 } 635 636 case 0x02: /* On-chip data memory */ 637 { 638 if ((phys_addr & 0xff00) == 0xff00) 639 { 640 phys_addr = (phys_addr & 0xffff); 641 if (phys_addr == DMAP2_SHADDOW) 642 { 643 phys_addr = DMAP2_OFFSET; 644 last_segname = "dmap"; 645 } 646 else 647 last_segname = "reg"; 648 } 649 else 650 last_segname = "dmem"; 651 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; 652 break; 653 } 654 655 default: 656 /* OOPS! */ 657 last_segname = "scrap"; 658 return State.mem.fault; 659 } 660 661 if (*memory == NULL) 662 { 663 *memory = calloc (1, SEGMENT_SIZE); 664 if (*memory == NULL) 665 { 666 (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n"); 667 return State.mem.fault; 668 } 669 } 670 671 offset = (phys_addr % SEGMENT_SIZE); 672 raw = *memory + offset; 673 return raw; 674 } 675 676 /* Transfer data to/from simulated memory. Since a bug in either the 677 simulated program or in gdb or the simulator itself may cause a 678 bogus address to be passed in, we need to do some sanity checking 679 on addresses to make sure they are within bounds. When an address 680 fails the bounds check, treat it as a zero length read/write rather 681 than aborting the entire run. */ 682 683 static int 684 xfer_mem (SIM_DESC sd, SIM_ADDR virt, 685 unsigned char *buffer, 686 int size, 687 int write_p) 688 { 689 host_callback *cr16_callback = STATE_CALLBACK (sd); 690 uint8 *memory; 691 unsigned long phys; 692 int phys_size; 693 phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL, 694 dmap_register, imap_register); 695 if (phys_size == 0) 696 return 0; 697 698 memory = map_memory (phys); 699 700 #ifdef DEBUG 701 if ((cr16_debug & DEBUG_INSTRUCTION) != 0) 702 { 703 (*cr16_callback->printf_filtered) 704 (cr16_callback, 705 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", 706 (write_p ? "write" : "read"), 707 phys_size, virt, last_from, 708 phys, last_to, 709 (long) memory, last_segname); 710 } 711 #endif 712 713 if (write_p) 714 { 715 memcpy (memory, buffer, phys_size); 716 } 717 else 718 { 719 memcpy (buffer, memory, phys_size); 720 } 721 722 return phys_size; 723 } 724 725 726 int 727 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size) 728 { 729 /* FIXME: this should be performing a virtual transfer */ 730 return xfer_mem (sd, addr, buffer, size, 1); 731 } 732 733 int 734 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) 735 { 736 /* FIXME: this should be performing a virtual transfer */ 737 return xfer_mem (sd, addr, buffer, size, 0); 738 } 739 740 static sim_cia 741 cr16_pc_get (sim_cpu *cpu) 742 { 743 return PC; 744 } 745 746 static void 747 cr16_pc_set (sim_cpu *cpu, sim_cia pc) 748 { 749 SET_PC (pc); 750 } 751 752 static void 753 free_state (SIM_DESC sd) 754 { 755 if (STATE_MODULES (sd) != NULL) 756 sim_module_uninstall (sd); 757 sim_cpu_free_all (sd); 758 sim_state_free (sd); 759 } 760 761 SIM_DESC trace_sd = NULL; 762 763 SIM_DESC 764 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv) 765 { 766 struct simops *s; 767 struct hash_entry *h; 768 static int init_p = 0; 769 char **p; 770 int i; 771 SIM_DESC sd = sim_state_alloc (kind, cb); 772 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 773 774 /* The cpu data is kept in a separately allocated chunk of memory. */ 775 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) 776 { 777 free_state (sd); 778 return 0; 779 } 780 781 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 782 { 783 free_state (sd); 784 return 0; 785 } 786 787 /* getopt will print the error message so we just have to exit if this fails. 788 FIXME: Hmmm... in the case of gdb we need getopt to call 789 print_filtered. */ 790 if (sim_parse_args (sd, argv) != SIM_RC_OK) 791 { 792 free_state (sd); 793 return 0; 794 } 795 796 /* Check for/establish the a reference program image. */ 797 if (sim_analyze_program (sd, 798 (STATE_PROG_ARGV (sd) != NULL 799 ? *STATE_PROG_ARGV (sd) 800 : NULL), abfd) != SIM_RC_OK) 801 { 802 free_state (sd); 803 return 0; 804 } 805 806 /* Configure/verify the target byte order and other runtime 807 configuration options. */ 808 if (sim_config (sd) != SIM_RC_OK) 809 { 810 sim_module_uninstall (sd); 811 return 0; 812 } 813 814 if (sim_post_argv_init (sd) != SIM_RC_OK) 815 { 816 /* Uninstall the modules to avoid memory leaks, 817 file descriptor leaks, etc. */ 818 sim_module_uninstall (sd); 819 return 0; 820 } 821 822 /* CPU specific initialization. */ 823 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 824 { 825 SIM_CPU *cpu = STATE_CPU (sd, i); 826 827 CPU_PC_FETCH (cpu) = cr16_pc_get; 828 CPU_PC_STORE (cpu) = cr16_pc_set; 829 } 830 831 trace_sd = sd; 832 cr16_callback = cb; 833 834 /* put all the opcodes in the hash table. */ 835 if (!init_p++) 836 { 837 for (s = Simops; s->func; s++) 838 { 839 switch(32 - s->mask) 840 { 841 case 0x4: 842 h = &hash_table[hash(s->opcode, 0)]; 843 break; 844 845 case 0x7: 846 if (((s->opcode << 1) >> 4) != 0) 847 h = &hash_table[hash((s->opcode << 1) >> 4, 0)]; 848 else 849 h = &hash_table[hash((s->opcode << 1), 0)]; 850 break; 851 852 case 0x8: 853 if ((s->opcode >> 4) != 0) 854 h = &hash_table[hash(s->opcode >> 4, 0)]; 855 else 856 h = &hash_table[hash(s->opcode, 0)]; 857 break; 858 859 case 0x9: 860 if (((s->opcode >> 1) >> 4) != 0) 861 h = &hash_table[hash((s->opcode >>1) >> 4, 0)]; 862 else 863 h = &hash_table[hash((s->opcode >> 1), 0)]; 864 break; 865 866 case 0xa: 867 if ((s->opcode >> 8) != 0) 868 h = &hash_table[hash(s->opcode >> 8, 0)]; 869 else if ((s->opcode >> 4) != 0) 870 h = &hash_table[hash(s->opcode >> 4, 0)]; 871 else 872 h = &hash_table[hash(s->opcode, 0)]; 873 break; 874 875 case 0xc: 876 if ((s->opcode >> 8) != 0) 877 h = &hash_table[hash(s->opcode >> 8, 0)]; 878 else if ((s->opcode >> 4) != 0) 879 h = &hash_table[hash(s->opcode >> 4, 0)]; 880 else 881 h = &hash_table[hash(s->opcode, 0)]; 882 break; 883 884 case 0xd: 885 if (((s->opcode >> 1) >> 8) != 0) 886 h = &hash_table[hash((s->opcode >>1) >> 8, 0)]; 887 else if (((s->opcode >> 1) >> 4) != 0) 888 h = &hash_table[hash((s->opcode >>1) >> 4, 0)]; 889 else 890 h = &hash_table[hash((s->opcode >>1), 0)]; 891 break; 892 893 case 0x10: 894 if ((s->opcode >> 0xc) != 0) 895 h = &hash_table[hash(s->opcode >> 12, 0)]; 896 else if ((s->opcode >> 8) != 0) 897 h = &hash_table[hash(s->opcode >> 8, 0)]; 898 else if ((s->opcode >> 4) != 0) 899 h = &hash_table[hash(s->opcode >> 4, 0)]; 900 else 901 h = &hash_table[hash(s->opcode, 0)]; 902 break; 903 904 case 0x14: 905 if ((s->opcode >> 16) != 0) 906 h = &hash_table[hash(s->opcode >> 16, 0)]; 907 else if ((s->opcode >> 12) != 0) 908 h = &hash_table[hash(s->opcode >> 12, 0)]; 909 else if ((s->opcode >> 8) != 0) 910 h = &hash_table[hash(s->opcode >> 8, 0)]; 911 else if ((s->opcode >> 4) != 0) 912 h = &hash_table[hash(s->opcode >> 4, 0)]; 913 else 914 h = &hash_table[hash(s->opcode, 0)]; 915 break; 916 default: 917 break; 918 } 919 920 /* go to the last entry in the chain. */ 921 while (h->next) 922 h = h->next; 923 924 if (h->ops) 925 { 926 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); 927 if (!h->next) 928 perror ("malloc failure"); 929 930 h = h->next; 931 } 932 h->ops = s; 933 h->mask = s->mask; 934 h->opcode = s->opcode; 935 h->format = s->format; 936 h->size = s->size; 937 } 938 } 939 940 /* reset the processor state */ 941 if (!State.mem.data[0]) 942 sim_size (1); 943 sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL); 944 945 return sd; 946 } 947 948 949 void 950 sim_close (SIM_DESC sd, int quitting) 951 { 952 /* Nothing to do. */ 953 } 954 955 uint8 * 956 dmem_addr (uint32 offset) 957 { 958 unsigned long phys; 959 uint8 *mem; 960 int phys_size; 961 962 /* Note: DMEM address range is 0..0x10000. Calling code can compute 963 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type 964 is uint16 this is modulo'ed onto 0x0e5d. */ 965 966 phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL, 967 dmap_register); 968 if (phys_size == 0) 969 { 970 mem = State.mem.fault; 971 } 972 else 973 mem = map_memory (phys); 974 #ifdef DEBUG 975 if ((cr16_debug & DEBUG_MEMORY)) 976 { 977 (*cr16_callback->printf_filtered) 978 (cr16_callback, 979 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", 980 offset, last_from, 981 phys, phys_size, last_to, 982 (long) mem, last_segname); 983 } 984 #endif 985 return mem; 986 } 987 988 uint8 * 989 imem_addr (uint32 offset) 990 { 991 unsigned long phys; 992 uint8 *mem; 993 int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL, 994 imap_register); 995 if (phys_size == 0) 996 { 997 return State.mem.fault; 998 } 999 mem = map_memory (phys); 1000 #ifdef DEBUG 1001 if ((cr16_debug & DEBUG_MEMORY)) 1002 { 1003 (*cr16_callback->printf_filtered) 1004 (cr16_callback, 1005 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", 1006 offset, last_from, 1007 phys, phys_size, last_to, 1008 (long) mem, last_segname); 1009 } 1010 #endif 1011 return mem; 1012 } 1013 1014 static int stop_simulator = 0; 1015 1016 int 1017 sim_stop (SIM_DESC sd) 1018 { 1019 stop_simulator = 1; 1020 return 1; 1021 } 1022 1023 1024 /* Run (or resume) the program. */ 1025 void 1026 sim_resume (SIM_DESC sd, int step, int siggnal) 1027 { 1028 uint32 curr_ins_size = 0; 1029 uint64 mcode = 0; 1030 uint8 *iaddr; 1031 1032 #ifdef DEBUG 1033 // (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); 1034 #endif 1035 1036 State.exception = 0; 1037 if (step) 1038 sim_stop (sd); 1039 1040 switch (siggnal) 1041 { 1042 case 0: 1043 break; 1044 #ifdef SIGBUS 1045 case SIGBUS: 1046 #endif 1047 case SIGSEGV: 1048 SET_PC (PC); 1049 SET_PSR (PSR); 1050 JMP (AE_VECTOR_START); 1051 SLOT_FLUSH (); 1052 break; 1053 case SIGILL: 1054 SET_PC (PC); 1055 SET_PSR (PSR); 1056 SET_HW_PSR ((PSR & (PSR_C_BIT))); 1057 JMP (RIE_VECTOR_START); 1058 SLOT_FLUSH (); 1059 break; 1060 default: 1061 /* just ignore it */ 1062 break; 1063 } 1064 1065 do 1066 { 1067 iaddr = imem_addr ((uint32)PC); 1068 if (iaddr == State.mem.fault) 1069 { 1070 #ifdef SIGBUS 1071 State.exception = SIGBUS; 1072 #else 1073 State.exception = SIGSEGV; 1074 #endif 1075 break; 1076 } 1077 1078 mcode = get_longword( iaddr ); 1079 1080 State.pc_changed = 0; 1081 1082 curr_ins_size = do_run(sd, mcode); 1083 1084 #if CR16_DEBUG 1085 (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode); 1086 #endif 1087 1088 if (!State.pc_changed) 1089 { 1090 if (curr_ins_size == 0) 1091 { 1092 State.exception = SIG_CR16_EXIT; /* exit trap */ 1093 break; 1094 } 1095 else 1096 SET_PC (PC + (curr_ins_size * 2)); /* For word instructions. */ 1097 } 1098 1099 #if 0 1100 /* Check for a breakpoint trap on this instruction. This 1101 overrides any pending branches or loops */ 1102 if (PSR_DB && PC == DBS) 1103 { 1104 SET_BPC (PC); 1105 SET_BPSR (PSR); 1106 SET_PC (SDBT_VECTOR_START); 1107 } 1108 #endif 1109 1110 /* Writeback all the DATA / PC changes */ 1111 SLOT_FLUSH (); 1112 } 1113 while ( !State.exception && !stop_simulator); 1114 1115 if (step && !State.exception) 1116 State.exception = SIGTRAP; 1117 } 1118 1119 SIM_RC 1120 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) 1121 { 1122 bfd_vma start_address; 1123 1124 /* reset all state information */ 1125 memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs); 1126 1127 /* There was a hack here to copy the values of argc and argv into r0 1128 and r1. The values were also saved into some high memory that 1129 won't be overwritten by the stack (0x7C00). The reason for doing 1130 this was to allow the 'run' program to accept arguments. Without 1131 the hack, this is not possible anymore. If the simulator is run 1132 from the debugger, arguments cannot be passed in, so this makes 1133 no difference. */ 1134 1135 /* set PC */ 1136 if (abfd != NULL) 1137 start_address = bfd_get_start_address (abfd); 1138 else 1139 start_address = 0x0; 1140 #ifdef DEBUG 1141 if (cr16_debug) 1142 (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address); 1143 #endif 1144 SET_CREG (PC_CR, start_address); 1145 1146 SLOT_FLUSH (); 1147 return SIM_RC_OK; 1148 } 1149 1150 void 1151 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc) 1152 { 1153 /* (*cr16_callback->printf_filtered) (cr16_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */ 1154 1155 switch (State.exception) 1156 { 1157 case SIG_CR16_STOP: /* stop instruction */ 1158 *reason = sim_stopped; 1159 *sigrc = 0; 1160 break; 1161 1162 case SIG_CR16_EXIT: /* exit trap */ 1163 *reason = sim_exited; 1164 *sigrc = GPR (2); 1165 break; 1166 1167 case SIG_CR16_BUS: 1168 *reason = sim_stopped; 1169 *sigrc = GDB_SIGNAL_BUS; 1170 break; 1171 // 1172 // case SIG_CR16_IAD: 1173 // *reason = sim_stopped; 1174 // *sigrc = GDB_SIGNAL_IAD; 1175 // break; 1176 1177 default: /* some signal */ 1178 *reason = sim_stopped; 1179 if (stop_simulator && !State.exception) 1180 *sigrc = GDB_SIGNAL_INT; 1181 else 1182 *sigrc = State.exception; 1183 break; 1184 } 1185 1186 stop_simulator = 0; 1187 } 1188 1189 int 1190 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) 1191 { 1192 int size; 1193 switch ((enum sim_cr16_regs) rn) 1194 { 1195 case SIM_CR16_R0_REGNUM: 1196 case SIM_CR16_R1_REGNUM: 1197 case SIM_CR16_R2_REGNUM: 1198 case SIM_CR16_R3_REGNUM: 1199 case SIM_CR16_R4_REGNUM: 1200 case SIM_CR16_R5_REGNUM: 1201 case SIM_CR16_R6_REGNUM: 1202 case SIM_CR16_R7_REGNUM: 1203 case SIM_CR16_R8_REGNUM: 1204 case SIM_CR16_R9_REGNUM: 1205 case SIM_CR16_R10_REGNUM: 1206 case SIM_CR16_R11_REGNUM: 1207 WRITE_16 (memory, GPR (rn - SIM_CR16_R0_REGNUM)); 1208 size = 2; 1209 break; 1210 case SIM_CR16_R12_REGNUM: 1211 case SIM_CR16_R13_REGNUM: 1212 case SIM_CR16_R14_REGNUM: 1213 case SIM_CR16_R15_REGNUM: 1214 //WRITE_32 (memory, GPR (rn - SIM_CR16_R0_REGNUM)); 1215 write_longword (memory, GPR (rn - SIM_CR16_R0_REGNUM)); 1216 size = 4; 1217 break; 1218 case SIM_CR16_PC_REGNUM: 1219 case SIM_CR16_ISP_REGNUM: 1220 case SIM_CR16_USP_REGNUM: 1221 case SIM_CR16_INTBASE_REGNUM: 1222 case SIM_CR16_PSR_REGNUM: 1223 case SIM_CR16_CFG_REGNUM: 1224 case SIM_CR16_DBS_REGNUM: 1225 case SIM_CR16_DCR_REGNUM: 1226 case SIM_CR16_DSR_REGNUM: 1227 case SIM_CR16_CAR0_REGNUM: 1228 case SIM_CR16_CAR1_REGNUM: 1229 //WRITE_32 (memory, CREG (rn - SIM_CR16_PC_REGNUM)); 1230 write_longword (memory, CREG (rn - SIM_CR16_PC_REGNUM)); 1231 size = 4; 1232 break; 1233 default: 1234 size = 0; 1235 break; 1236 } 1237 return size; 1238 } 1239 1240 int 1241 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) 1242 { 1243 int size; 1244 switch ((enum sim_cr16_regs) rn) 1245 { 1246 case SIM_CR16_R0_REGNUM: 1247 case SIM_CR16_R1_REGNUM: 1248 case SIM_CR16_R2_REGNUM: 1249 case SIM_CR16_R3_REGNUM: 1250 case SIM_CR16_R4_REGNUM: 1251 case SIM_CR16_R5_REGNUM: 1252 case SIM_CR16_R6_REGNUM: 1253 case SIM_CR16_R7_REGNUM: 1254 case SIM_CR16_R8_REGNUM: 1255 case SIM_CR16_R9_REGNUM: 1256 case SIM_CR16_R10_REGNUM: 1257 case SIM_CR16_R11_REGNUM: 1258 SET_GPR (rn - SIM_CR16_R0_REGNUM, READ_16 (memory)); 1259 size = 2; 1260 break; 1261 case SIM_CR16_R12_REGNUM: 1262 case SIM_CR16_R13_REGNUM: 1263 case SIM_CR16_R14_REGNUM: 1264 case SIM_CR16_R15_REGNUM: 1265 SET_GPR32 (rn - SIM_CR16_R0_REGNUM, get_longword (memory)); 1266 size = 4; 1267 break; 1268 case SIM_CR16_PC_REGNUM: 1269 case SIM_CR16_ISP_REGNUM: 1270 case SIM_CR16_USP_REGNUM: 1271 case SIM_CR16_INTBASE_REGNUM: 1272 case SIM_CR16_PSR_REGNUM: 1273 case SIM_CR16_CFG_REGNUM: 1274 case SIM_CR16_DBS_REGNUM: 1275 case SIM_CR16_DCR_REGNUM: 1276 case SIM_CR16_DSR_REGNUM: 1277 case SIM_CR16_CAR0_REGNUM: 1278 case SIM_CR16_CAR1_REGNUM: 1279 SET_CREG (rn - SIM_CR16_PC_REGNUM, get_longword (memory)); 1280 size = 4; 1281 break; 1282 default: 1283 size = 0; 1284 break; 1285 } 1286 SLOT_FLUSH (); 1287 return size; 1288 } 1289