1 /* Blackfin Two Wire Interface (TWI) model 2 3 Copyright (C) 2010-2017 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "config.h" 22 23 #include "sim-main.h" 24 #include "devices.h" 25 #include "dv-bfin_twi.h" 26 27 /* XXX: This is merely a stub. */ 28 29 struct bfin_twi 30 { 31 /* This top portion matches common dv_bfin struct. */ 32 bu32 base; 33 struct hw *dma_master; 34 bool acked; 35 36 struct hw_event *handler; 37 char saved_byte; 38 int saved_count; 39 40 bu16 xmt_fifo, rcv_fifo; 41 42 /* Order after here is important -- matches hardware MMR layout. */ 43 bu16 BFIN_MMR_16(clkdiv); 44 bu16 BFIN_MMR_16(control); 45 bu16 BFIN_MMR_16(slave_ctl); 46 bu16 BFIN_MMR_16(slave_stat); 47 bu16 BFIN_MMR_16(slave_addr); 48 bu16 BFIN_MMR_16(master_ctl); 49 bu16 BFIN_MMR_16(master_stat); 50 bu16 BFIN_MMR_16(master_addr); 51 bu16 BFIN_MMR_16(int_stat); 52 bu16 BFIN_MMR_16(int_mask); 53 bu16 BFIN_MMR_16(fifo_ctl); 54 bu16 BFIN_MMR_16(fifo_stat); 55 bu32 _pad0[20]; 56 bu16 BFIN_MMR_16(xmt_data8); 57 bu16 BFIN_MMR_16(xmt_data16); 58 bu16 BFIN_MMR_16(rcv_data8); 59 bu16 BFIN_MMR_16(rcv_data16); 60 }; 61 #define mmr_base() offsetof(struct bfin_twi, clkdiv) 62 #define mmr_offset(mmr) (offsetof(struct bfin_twi, mmr) - mmr_base()) 63 #define mmr_idx(mmr) (mmr_offset (mmr) / 4) 64 65 static const char * const mmr_names[] = 66 { 67 "TWI_CLKDIV", "TWI_CONTROL", "TWI_SLAVE_CTL", "TWI_SLAVE_STAT", 68 "TWI_SLAVE_ADDR", "TWI_MASTER_CTL", "TWI_MASTER_STAT", "TWI_MASTER_ADDR", 69 "TWI_INT_STAT", "TWI_INT_MASK", "TWI_FIFO_CTL", "TWI_FIFO_STAT", 70 [mmr_idx (xmt_data8)] = "TWI_XMT_DATA8", "TWI_XMT_DATA16", "TWI_RCV_DATA8", 71 "TWI_RCV_DATA16", 72 }; 73 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") 74 75 static unsigned 76 bfin_twi_io_write_buffer (struct hw *me, const void *source, int space, 77 address_word addr, unsigned nr_bytes) 78 { 79 struct bfin_twi *twi = hw_data (me); 80 bu32 mmr_off; 81 bu32 value; 82 bu16 *valuep; 83 84 /* Invalid access mode is higher priority than missing register. */ 85 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) 86 return 0; 87 88 value = dv_load_2 (source); 89 mmr_off = addr - twi->base; 90 valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off); 91 92 HW_TRACE_WRITE (); 93 94 switch (mmr_off) 95 { 96 case mmr_offset(clkdiv): 97 case mmr_offset(control): 98 case mmr_offset(slave_ctl): 99 case mmr_offset(slave_addr): 100 case mmr_offset(master_ctl): 101 case mmr_offset(master_addr): 102 case mmr_offset(int_mask): 103 case mmr_offset(fifo_ctl): 104 *valuep = value; 105 break; 106 case mmr_offset(int_stat): 107 dv_w1c_2 (valuep, value, -1); 108 break; 109 case mmr_offset(master_stat): 110 dv_w1c_2 (valuep, value, BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB); 111 break; 112 case mmr_offset(slave_stat): 113 case mmr_offset(fifo_stat): 114 case mmr_offset(rcv_data8): 115 case mmr_offset(rcv_data16): 116 /* These are all RO. XXX: Does these throw error ? */ 117 break; 118 case mmr_offset(xmt_data8): 119 value &= 0xff; 120 case mmr_offset(xmt_data16): 121 twi->xmt_fifo = value; 122 break; 123 default: 124 dv_bfin_mmr_invalid (me, addr, nr_bytes, true); 125 return 0; 126 } 127 128 return nr_bytes; 129 } 130 131 static unsigned 132 bfin_twi_io_read_buffer (struct hw *me, void *dest, int space, 133 address_word addr, unsigned nr_bytes) 134 { 135 struct bfin_twi *twi = hw_data (me); 136 bu32 mmr_off; 137 bu16 *valuep; 138 139 /* Invalid access mode is higher priority than missing register. */ 140 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false)) 141 return 0; 142 143 mmr_off = addr - twi->base; 144 valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off); 145 146 HW_TRACE_READ (); 147 148 switch (mmr_off) 149 { 150 case mmr_offset(clkdiv): 151 case mmr_offset(control): 152 case mmr_offset(slave_ctl): 153 case mmr_offset(slave_stat): 154 case mmr_offset(slave_addr): 155 case mmr_offset(master_ctl): 156 case mmr_offset(master_stat): 157 case mmr_offset(master_addr): 158 case mmr_offset(int_stat): 159 case mmr_offset(int_mask): 160 case mmr_offset(fifo_ctl): 161 case mmr_offset(fifo_stat): 162 dv_store_2 (dest, *valuep); 163 break; 164 case mmr_offset(rcv_data8): 165 case mmr_offset(rcv_data16): 166 dv_store_2 (dest, twi->rcv_fifo); 167 break; 168 case mmr_offset(xmt_data8): 169 case mmr_offset(xmt_data16): 170 /* These always read as 0. */ 171 dv_store_2 (dest, 0); 172 break; 173 default: 174 dv_bfin_mmr_invalid (me, addr, nr_bytes, false); 175 return 0; 176 } 177 178 return nr_bytes; 179 } 180 181 static const struct hw_port_descriptor bfin_twi_ports[] = 182 { 183 { "stat", 0, 0, output_port, }, 184 { NULL, 0, 0, 0, }, 185 }; 186 187 static void 188 attach_bfin_twi_regs (struct hw *me, struct bfin_twi *twi) 189 { 190 address_word attach_address; 191 int attach_space; 192 unsigned attach_size; 193 reg_property_spec reg; 194 195 if (hw_find_property (me, "reg") == NULL) 196 hw_abort (me, "Missing \"reg\" property"); 197 198 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 199 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 200 201 hw_unit_address_to_attach_address (hw_parent (me), 202 ®.address, 203 &attach_space, &attach_address, me); 204 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 205 206 if (attach_size != BFIN_MMR_TWI_SIZE) 207 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_TWI_SIZE); 208 209 hw_attach_address (hw_parent (me), 210 0, attach_space, attach_address, attach_size, me); 211 212 twi->base = attach_address; 213 } 214 215 static void 216 bfin_twi_finish (struct hw *me) 217 { 218 struct bfin_twi *twi; 219 220 twi = HW_ZALLOC (me, struct bfin_twi); 221 222 set_hw_data (me, twi); 223 set_hw_io_read_buffer (me, bfin_twi_io_read_buffer); 224 set_hw_io_write_buffer (me, bfin_twi_io_write_buffer); 225 set_hw_ports (me, bfin_twi_ports); 226 227 attach_bfin_twi_regs (me, twi); 228 } 229 230 const struct hw_descriptor dv_bfin_twi_descriptor[] = 231 { 232 {"bfin_twi", bfin_twi_finish,}, 233 {NULL, NULL}, 234 }; 235