1 /* Blackfin Phase Lock Loop (PLL) model. 2 3 Copyright (C) 2010-2019 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "config.h" 22 23 #include "sim-main.h" 24 #include "machs.h" 25 #include "devices.h" 26 #include "dv-bfin_pll.h" 27 28 struct bfin_pll 29 { 30 bu32 base; 31 32 /* Order after here is important -- matches hardware MMR layout. */ 33 bu16 BFIN_MMR_16(pll_ctl); 34 bu16 BFIN_MMR_16(pll_div); 35 bu16 BFIN_MMR_16(vr_ctl); 36 bu16 BFIN_MMR_16(pll_stat); 37 bu16 BFIN_MMR_16(pll_lockcnt); 38 39 /* XXX: Not really the best place for this ... */ 40 bu32 chipid; 41 }; 42 #define mmr_base() offsetof(struct bfin_pll, pll_ctl) 43 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base()) 44 45 static const char * const mmr_names[] = 46 { 47 "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID", 48 }; 49 #define mmr_name(off) mmr_names[(off) / 4] 50 51 static unsigned 52 bfin_pll_io_write_buffer (struct hw *me, const void *source, 53 int space, address_word addr, unsigned nr_bytes) 54 { 55 struct bfin_pll *pll = hw_data (me); 56 bu32 mmr_off; 57 bu32 value; 58 bu16 *value16p; 59 bu32 *value32p; 60 void *valuep; 61 62 /* Invalid access mode is higher priority than missing register. */ 63 if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true)) 64 return 0; 65 66 if (nr_bytes == 4) 67 value = dv_load_4 (source); 68 else 69 value = dv_load_2 (source); 70 71 mmr_off = addr - pll->base; 72 valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off); 73 value16p = valuep; 74 value32p = valuep; 75 76 HW_TRACE_WRITE (); 77 78 switch (mmr_off) 79 { 80 case mmr_offset(pll_stat): 81 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) 82 return 0; 83 case mmr_offset(chipid): 84 /* Discard writes. */ 85 break; 86 default: 87 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) 88 return 0; 89 *value16p = value; 90 break; 91 } 92 93 return nr_bytes; 94 } 95 96 static unsigned 97 bfin_pll_io_read_buffer (struct hw *me, void *dest, 98 int space, address_word addr, unsigned nr_bytes) 99 { 100 struct bfin_pll *pll = hw_data (me); 101 bu32 mmr_off; 102 bu32 *value32p; 103 bu16 *value16p; 104 void *valuep; 105 106 /* Invalid access mode is higher priority than missing register. */ 107 if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false)) 108 return 0; 109 110 mmr_off = addr - pll->base; 111 valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off); 112 value16p = valuep; 113 value32p = valuep; 114 115 HW_TRACE_READ (); 116 117 switch (mmr_off) 118 { 119 case mmr_offset(chipid): 120 dv_store_4 (dest, *value32p); 121 break; 122 default: 123 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false)) 124 return 0; 125 dv_store_2 (dest, *value16p); 126 break; 127 } 128 129 return nr_bytes; 130 } 131 132 static const struct hw_port_descriptor bfin_pll_ports[] = 133 { 134 { "pll", 0, 0, output_port, }, 135 { NULL, 0, 0, 0, }, 136 }; 137 138 static void 139 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll) 140 { 141 address_word attach_address; 142 int attach_space; 143 unsigned attach_size; 144 reg_property_spec reg; 145 146 if (hw_find_property (me, "reg") == NULL) 147 hw_abort (me, "Missing \"reg\" property"); 148 149 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 150 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 151 152 hw_unit_address_to_attach_address (hw_parent (me), 153 ®.address, 154 &attach_space, &attach_address, me); 155 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 156 157 if (attach_size != BFIN_MMR_PLL_SIZE) 158 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE); 159 160 hw_attach_address (hw_parent (me), 161 0, attach_space, attach_address, attach_size, me); 162 163 pll->base = attach_address; 164 } 165 166 static void 167 bfin_pll_finish (struct hw *me) 168 { 169 struct bfin_pll *pll; 170 171 pll = HW_ZALLOC (me, struct bfin_pll); 172 173 set_hw_data (me, pll); 174 set_hw_io_read_buffer (me, bfin_pll_io_read_buffer); 175 set_hw_io_write_buffer (me, bfin_pll_io_write_buffer); 176 set_hw_ports (me, bfin_pll_ports); 177 178 attach_bfin_pll_regs (me, pll); 179 180 /* Initialize the PLL. */ 181 /* XXX: Depends on part ? */ 182 pll->pll_ctl = 0x1400; 183 pll->pll_div = 0x0005; 184 pll->vr_ctl = 0x40DB; 185 pll->pll_stat = 0x00A2; 186 pll->pll_lockcnt = 0x0200; 187 pll->chipid = bfin_model_get_chipid (hw_system (me)); 188 189 /* XXX: slow it down! */ 190 pll->pll_ctl = 0xa800; 191 pll->pll_div = 0x4; 192 pll->vr_ctl = 0x40fb; 193 pll->pll_stat = 0xa2; 194 pll->pll_lockcnt = 0x300; 195 } 196 197 const struct hw_descriptor dv_bfin_pll_descriptor[] = 198 { 199 {"bfin_pll", bfin_pll_finish,}, 200 {NULL, NULL}, 201 }; 202