1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Instruction building/extraction support for or1k. -*- C -*- 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 5 - the resultant file is machine generated, cgen-ibld.in isn't 6 7 Copyright (C) 1996-2019 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "or1k-desc.h" 35 #include "or1k-opc.h" 36 #include "cgen/basic-modes.h" 37 #include "opintl.h" 38 #include "safe-ctype.h" 39 40 #undef min 41 #define min(a,b) ((a) < (b) ? (a) : (b)) 42 #undef max 43 #define max(a,b) ((a) > (b) ? (a) : (b)) 44 45 /* Used by the ifield rtx function. */ 46 #define FLD(f) (fields->f) 47 48 static const char * insert_normal 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 51 static const char * insert_insn_normal 52 (CGEN_CPU_DESC, const CGEN_INSN *, 53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 54 static int extract_normal 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 56 unsigned int, unsigned int, unsigned int, unsigned int, 57 unsigned int, unsigned int, bfd_vma, long *); 58 static int extract_insn_normal 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 61 #if CGEN_INT_INSN_P 62 static void put_insn_int_value 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 64 #endif 65 #if ! CGEN_INT_INSN_P 66 static CGEN_INLINE void insert_1 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 68 static CGEN_INLINE int fill_cache 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 70 static CGEN_INLINE long extract_1 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 72 #endif 73 74 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift_within_word, shift_to_word, shift; 212 213 /* How to shift the value to BIT0 of the word. */ 214 shift_to_word = total_length - (word_offset + word_length); 215 216 /* How to shift the value to the field within the word. */ 217 if (CGEN_INSN_LSB0_P) 218 shift_within_word = start + 1 - length; 219 else 220 shift_within_word = word_length - start - length; 221 222 /* The total SHIFT, then mask in the value. */ 223 shift = shift_to_word + shift_within_word; 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 225 } 226 227 #else /* ! CGEN_INT_INSN_P */ 228 229 { 230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 231 232 insert_1 (cd, value, start, length, word_length, bufp); 233 } 234 235 #endif /* ! CGEN_INT_INSN_P */ 236 237 return NULL; 238 } 239 240 /* Default insn builder (insert handler). 241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 243 recorded in host byte order, otherwise BUFFER is an array of bytes 244 and the value is recorded in target byte order). 245 The result is an error message or NULL if success. */ 246 247 static const char * 248 insert_insn_normal (CGEN_CPU_DESC cd, 249 const CGEN_INSN * insn, 250 CGEN_FIELDS * fields, 251 CGEN_INSN_BYTES_PTR buffer, 252 bfd_vma pc) 253 { 254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 255 unsigned long value; 256 const CGEN_SYNTAX_CHAR_TYPE * syn; 257 258 CGEN_INIT_INSERT (cd); 259 value = CGEN_INSN_BASE_VALUE (insn); 260 261 /* If we're recording insns as numbers (rather than a string of bytes), 262 target byte order handling is deferred until later. */ 263 264 #if CGEN_INT_INSN_P 265 266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 267 CGEN_FIELDS_BITSIZE (fields), value); 268 269 #else 270 271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 272 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 273 value); 274 275 #endif /* ! CGEN_INT_INSN_P */ 276 277 /* ??? It would be better to scan the format's fields. 278 Still need to be able to insert a value based on the operand though; 279 e.g. storing a branch displacement that got resolved later. 280 Needs more thought first. */ 281 282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 283 { 284 const char *errmsg; 285 286 if (CGEN_SYNTAX_CHAR_P (* syn)) 287 continue; 288 289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 290 fields, buffer, pc); 291 if (errmsg) 292 return errmsg; 293 } 294 295 return NULL; 296 } 297 298 #if CGEN_INT_INSN_P 299 /* Cover function to store an insn value into an integral insn. Must go here 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 301 302 static void 303 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 304 CGEN_INSN_BYTES_PTR buf, 305 int length, 306 int insn_length, 307 CGEN_INSN_INT value) 308 { 309 /* For architectures with insns smaller than the base-insn-bitsize, 310 length may be too big. */ 311 if (length > insn_length) 312 *buf = value; 313 else 314 { 315 int shift = insn_length - length; 316 /* Written this way to avoid undefined behaviour. */ 317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 318 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 320 } 321 } 322 #endif 323 324 /* Operand extraction. */ 325 326 #if ! CGEN_INT_INSN_P 327 328 /* Subroutine of extract_normal. 329 Ensure sufficient bytes are cached in EX_INFO. 330 OFFSET is the offset in bytes from the start of the insn of the value. 331 BYTES is the length of the needed value. 332 Returns 1 for success, 0 for failure. */ 333 334 static CGEN_INLINE int 335 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 336 CGEN_EXTRACT_INFO *ex_info, 337 int offset, 338 int bytes, 339 bfd_vma pc) 340 { 341 /* It's doubtful that the middle part has already been fetched so 342 we don't optimize that case. kiss. */ 343 unsigned int mask; 344 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 345 346 /* First do a quick check. */ 347 mask = (1 << bytes) - 1; 348 if (((ex_info->valid >> offset) & mask) == mask) 349 return 1; 350 351 /* Search for the first byte we need to read. */ 352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 353 if (! (mask & ex_info->valid)) 354 break; 355 356 if (bytes) 357 { 358 int status; 359 360 pc += offset; 361 status = (*info->read_memory_func) 362 (pc, ex_info->insn_bytes + offset, bytes, info); 363 364 if (status != 0) 365 { 366 (*info->memory_error_func) (status, pc, info); 367 return 0; 368 } 369 370 ex_info->valid |= ((1 << bytes) - 1) << offset; 371 } 372 373 return 1; 374 } 375 376 /* Subroutine of extract_normal. */ 377 378 static CGEN_INLINE long 379 extract_1 (CGEN_CPU_DESC cd, 380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 381 int start, 382 int length, 383 int word_length, 384 unsigned char *bufp, 385 bfd_vma pc ATTRIBUTE_UNUSED) 386 { 387 unsigned long x; 388 int shift; 389 390 x = cgen_get_insn_value (cd, bufp, word_length); 391 392 if (CGEN_INSN_LSB0_P) 393 shift = (start + 1) - length; 394 else 395 shift = (word_length - (start + length)); 396 return x >> shift; 397 } 398 399 #endif /* ! CGEN_INT_INSN_P */ 400 401 /* Default extraction routine. 402 403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 404 or sometimes less for cases like the m32r where the base insn size is 32 405 but some insns are 16 bits. 406 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 407 but for generality we take a bitmask of all of them. 408 WORD_OFFSET is the offset in bits from the start of the insn of the value. 409 WORD_LENGTH is the length of the word in bits in which the value resides. 410 START is the starting bit number in the word, architecture origin. 411 LENGTH is the length of VALUE in bits. 412 TOTAL_LENGTH is the total length of the insn in bits. 413 414 Returns 1 for success, 0 for failure. */ 415 416 /* ??? The return code isn't properly used. wip. */ 417 418 /* ??? This doesn't handle bfd_vma's. Create another function when 419 necessary. */ 420 421 static int 422 extract_normal (CGEN_CPU_DESC cd, 423 #if ! CGEN_INT_INSN_P 424 CGEN_EXTRACT_INFO *ex_info, 425 #else 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 427 #endif 428 CGEN_INSN_INT insn_value, 429 unsigned int attrs, 430 unsigned int word_offset, 431 unsigned int start, 432 unsigned int length, 433 unsigned int word_length, 434 unsigned int total_length, 435 #if ! CGEN_INT_INSN_P 436 bfd_vma pc, 437 #else 438 bfd_vma pc ATTRIBUTE_UNUSED, 439 #endif 440 long *valuep) 441 { 442 long value, mask; 443 444 /* If LENGTH is zero, this operand doesn't contribute to the value 445 so give it a standard value of zero. */ 446 if (length == 0) 447 { 448 *valuep = 0; 449 return 1; 450 } 451 452 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 453 abort (); 454 455 /* For architectures with insns smaller than the insn-base-bitsize, 456 word_length may be too big. */ 457 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 458 { 459 if (word_offset + word_length > total_length) 460 word_length = total_length - word_offset; 461 } 462 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 464 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 466 { 467 if (CGEN_INSN_LSB0_P) 468 value = insn_value >> ((word_offset + start + 1) - length); 469 else 470 value = insn_value >> (total_length - ( word_offset + start + length)); 471 } 472 473 #if ! CGEN_INT_INSN_P 474 475 else 476 { 477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 478 479 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 480 abort (); 481 482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 483 return 0; 484 485 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 486 } 487 488 #endif /* ! CGEN_INT_INSN_P */ 489 490 /* Written this way to avoid undefined behaviour. */ 491 mask = (((1L << (length - 1)) - 1) << 1) | 1; 492 493 value &= mask; 494 /* sign extend? */ 495 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 496 && (value & (1L << (length - 1)))) 497 value |= ~mask; 498 499 *valuep = value; 500 501 return 1; 502 } 503 504 /* Default insn extractor. 505 506 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 507 The extracted fields are stored in FIELDS. 508 EX_INFO is used to handle reading variable length insns. 509 Return the length of the insn in bits, or 0 if no match, 510 or -1 if an error occurs fetching data (memory_error_func will have 511 been called). */ 512 513 static int 514 extract_insn_normal (CGEN_CPU_DESC cd, 515 const CGEN_INSN *insn, 516 CGEN_EXTRACT_INFO *ex_info, 517 CGEN_INSN_INT insn_value, 518 CGEN_FIELDS *fields, 519 bfd_vma pc) 520 { 521 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 522 const CGEN_SYNTAX_CHAR_TYPE *syn; 523 524 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 525 526 CGEN_INIT_EXTRACT (cd); 527 528 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 529 { 530 int length; 531 532 if (CGEN_SYNTAX_CHAR_P (*syn)) 533 continue; 534 535 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 536 ex_info, insn_value, fields, pc); 537 if (length <= 0) 538 return length; 539 } 540 541 /* We recognized and successfully extracted this insn. */ 542 return CGEN_INSN_BITSIZE (insn); 543 } 544 545 /* Machine generated code added here. */ 546 547 const char * or1k_cgen_insert_operand 548 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 549 550 /* Main entry point for operand insertion. 551 552 This function is basically just a big switch statement. Earlier versions 553 used tables to look up the function to use, but 554 - if the table contains both assembler and disassembler functions then 555 the disassembler contains much of the assembler and vice-versa, 556 - there's a lot of inlining possibilities as things grow, 557 - using a switch statement avoids the function call overhead. 558 559 This function could be moved into `parse_insn_normal', but keeping it 560 separate makes clear the interface between `parse_insn_normal' and each of 561 the handlers. It's also needed by GAS to insert operands that couldn't be 562 resolved during parsing. */ 563 564 const char * 565 or1k_cgen_insert_operand (CGEN_CPU_DESC cd, 566 int opindex, 567 CGEN_FIELDS * fields, 568 CGEN_INSN_BYTES_PTR buffer, 569 bfd_vma pc ATTRIBUTE_UNUSED) 570 { 571 const char * errmsg = NULL; 572 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 573 574 switch (opindex) 575 { 576 case OR1K_OPERAND_DISP21 : 577 { 578 long value = fields->f_disp21; 579 value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13)))); 580 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer); 581 } 582 break; 583 case OR1K_OPERAND_DISP26 : 584 { 585 long value = fields->f_disp26; 586 value = ((DI) (((value) - (pc))) >> (2)); 587 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); 588 } 589 break; 590 case OR1K_OPERAND_RA : 591 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 592 break; 593 case OR1K_OPERAND_RADF : 594 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 595 break; 596 case OR1K_OPERAND_RASF : 597 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 598 break; 599 case OR1K_OPERAND_RB : 600 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 601 break; 602 case OR1K_OPERAND_RBDF : 603 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 604 break; 605 case OR1K_OPERAND_RBSF : 606 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 607 break; 608 case OR1K_OPERAND_RD : 609 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 610 break; 611 case OR1K_OPERAND_RDDF : 612 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 613 break; 614 case OR1K_OPERAND_RDSF : 615 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 616 break; 617 case OR1K_OPERAND_SIMM16 : 618 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer); 619 break; 620 case OR1K_OPERAND_SIMM16_SPLIT : 621 { 622 { 623 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31)); 624 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047)); 625 } 626 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 627 if (errmsg) 628 break; 629 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 630 if (errmsg) 631 break; 632 } 633 break; 634 case OR1K_OPERAND_UIMM16 : 635 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); 636 break; 637 case OR1K_OPERAND_UIMM16_SPLIT : 638 { 639 { 640 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31)); 641 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047)); 642 } 643 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 644 if (errmsg) 645 break; 646 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 647 if (errmsg) 648 break; 649 } 650 break; 651 case OR1K_OPERAND_UIMM6 : 652 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer); 653 break; 654 655 default : 656 /* xgettext:c-format */ 657 opcodes_error_handler 658 (_("internal error: unrecognized field %d while building insn"), 659 opindex); 660 abort (); 661 } 662 663 return errmsg; 664 } 665 666 int or1k_cgen_extract_operand 667 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 668 669 /* Main entry point for operand extraction. 670 The result is <= 0 for error, >0 for success. 671 ??? Actual values aren't well defined right now. 672 673 This function is basically just a big switch statement. Earlier versions 674 used tables to look up the function to use, but 675 - if the table contains both assembler and disassembler functions then 676 the disassembler contains much of the assembler and vice-versa, 677 - there's a lot of inlining possibilities as things grow, 678 - using a switch statement avoids the function call overhead. 679 680 This function could be moved into `print_insn_normal', but keeping it 681 separate makes clear the interface between `print_insn_normal' and each of 682 the handlers. */ 683 684 int 685 or1k_cgen_extract_operand (CGEN_CPU_DESC cd, 686 int opindex, 687 CGEN_EXTRACT_INFO *ex_info, 688 CGEN_INSN_INT insn_value, 689 CGEN_FIELDS * fields, 690 bfd_vma pc) 691 { 692 /* Assume success (for those operands that are nops). */ 693 int length = 1; 694 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 695 696 switch (opindex) 697 { 698 case OR1K_OPERAND_DISP21 : 699 { 700 long value; 701 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value); 702 value = ((((value) + (((DI) (pc) >> (13))))) << (13)); 703 fields->f_disp21 = value; 704 } 705 break; 706 case OR1K_OPERAND_DISP26 : 707 { 708 long value; 709 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); 710 value = ((((value) << (2))) + (pc)); 711 fields->f_disp26 = value; 712 } 713 break; 714 case OR1K_OPERAND_RA : 715 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 716 break; 717 case OR1K_OPERAND_RADF : 718 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 719 break; 720 case OR1K_OPERAND_RASF : 721 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 722 break; 723 case OR1K_OPERAND_RB : 724 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 725 break; 726 case OR1K_OPERAND_RBDF : 727 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 728 break; 729 case OR1K_OPERAND_RBSF : 730 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 731 break; 732 case OR1K_OPERAND_RD : 733 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 734 break; 735 case OR1K_OPERAND_RDDF : 736 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 737 break; 738 case OR1K_OPERAND_RDSF : 739 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 740 break; 741 case OR1K_OPERAND_SIMM16 : 742 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 743 break; 744 case OR1K_OPERAND_SIMM16_SPLIT : 745 { 746 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 747 if (length <= 0) break; 748 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 749 if (length <= 0) break; 750 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 751 } 752 break; 753 case OR1K_OPERAND_UIMM16 : 754 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); 755 break; 756 case OR1K_OPERAND_UIMM16_SPLIT : 757 { 758 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 759 if (length <= 0) break; 760 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 761 if (length <= 0) break; 762 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 763 } 764 break; 765 case OR1K_OPERAND_UIMM6 : 766 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6); 767 break; 768 769 default : 770 /* xgettext:c-format */ 771 opcodes_error_handler 772 (_("internal error: unrecognized field %d while decoding insn"), 773 opindex); 774 abort (); 775 } 776 777 return length; 778 } 779 780 cgen_insert_fn * const or1k_cgen_insert_handlers[] = 781 { 782 insert_insn_normal, 783 }; 784 785 cgen_extract_fn * const or1k_cgen_extract_handlers[] = 786 { 787 extract_insn_normal, 788 }; 789 790 int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 791 bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 792 793 /* Getting values from cgen_fields is handled by a collection of functions. 794 They are distinguished by the type of the VALUE argument they return. 795 TODO: floating point, inlining support, remove cases where result type 796 not appropriate. */ 797 798 int 799 or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 800 int opindex, 801 const CGEN_FIELDS * fields) 802 { 803 int value; 804 805 switch (opindex) 806 { 807 case OR1K_OPERAND_DISP21 : 808 value = fields->f_disp21; 809 break; 810 case OR1K_OPERAND_DISP26 : 811 value = fields->f_disp26; 812 break; 813 case OR1K_OPERAND_RA : 814 value = fields->f_r2; 815 break; 816 case OR1K_OPERAND_RADF : 817 value = fields->f_r1; 818 break; 819 case OR1K_OPERAND_RASF : 820 value = fields->f_r2; 821 break; 822 case OR1K_OPERAND_RB : 823 value = fields->f_r3; 824 break; 825 case OR1K_OPERAND_RBDF : 826 value = fields->f_r1; 827 break; 828 case OR1K_OPERAND_RBSF : 829 value = fields->f_r3; 830 break; 831 case OR1K_OPERAND_RD : 832 value = fields->f_r1; 833 break; 834 case OR1K_OPERAND_RDDF : 835 value = fields->f_r1; 836 break; 837 case OR1K_OPERAND_RDSF : 838 value = fields->f_r1; 839 break; 840 case OR1K_OPERAND_SIMM16 : 841 value = fields->f_simm16; 842 break; 843 case OR1K_OPERAND_SIMM16_SPLIT : 844 value = fields->f_simm16_split; 845 break; 846 case OR1K_OPERAND_UIMM16 : 847 value = fields->f_uimm16; 848 break; 849 case OR1K_OPERAND_UIMM16_SPLIT : 850 value = fields->f_uimm16_split; 851 break; 852 case OR1K_OPERAND_UIMM6 : 853 value = fields->f_uimm6; 854 break; 855 856 default : 857 /* xgettext:c-format */ 858 opcodes_error_handler 859 (_("internal error: unrecognized field %d while getting int operand"), 860 opindex); 861 abort (); 862 } 863 864 return value; 865 } 866 867 bfd_vma 868 or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 869 int opindex, 870 const CGEN_FIELDS * fields) 871 { 872 bfd_vma value; 873 874 switch (opindex) 875 { 876 case OR1K_OPERAND_DISP21 : 877 value = fields->f_disp21; 878 break; 879 case OR1K_OPERAND_DISP26 : 880 value = fields->f_disp26; 881 break; 882 case OR1K_OPERAND_RA : 883 value = fields->f_r2; 884 break; 885 case OR1K_OPERAND_RADF : 886 value = fields->f_r1; 887 break; 888 case OR1K_OPERAND_RASF : 889 value = fields->f_r2; 890 break; 891 case OR1K_OPERAND_RB : 892 value = fields->f_r3; 893 break; 894 case OR1K_OPERAND_RBDF : 895 value = fields->f_r1; 896 break; 897 case OR1K_OPERAND_RBSF : 898 value = fields->f_r3; 899 break; 900 case OR1K_OPERAND_RD : 901 value = fields->f_r1; 902 break; 903 case OR1K_OPERAND_RDDF : 904 value = fields->f_r1; 905 break; 906 case OR1K_OPERAND_RDSF : 907 value = fields->f_r1; 908 break; 909 case OR1K_OPERAND_SIMM16 : 910 value = fields->f_simm16; 911 break; 912 case OR1K_OPERAND_SIMM16_SPLIT : 913 value = fields->f_simm16_split; 914 break; 915 case OR1K_OPERAND_UIMM16 : 916 value = fields->f_uimm16; 917 break; 918 case OR1K_OPERAND_UIMM16_SPLIT : 919 value = fields->f_uimm16_split; 920 break; 921 case OR1K_OPERAND_UIMM6 : 922 value = fields->f_uimm6; 923 break; 924 925 default : 926 /* xgettext:c-format */ 927 opcodes_error_handler 928 (_("internal error: unrecognized field %d while getting vma operand"), 929 opindex); 930 abort (); 931 } 932 933 return value; 934 } 935 936 void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 937 void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 938 939 /* Stuffing values in cgen_fields is handled by a collection of functions. 940 They are distinguished by the type of the VALUE argument they accept. 941 TODO: floating point, inlining support, remove cases where argument type 942 not appropriate. */ 943 944 void 945 or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 946 int opindex, 947 CGEN_FIELDS * fields, 948 int value) 949 { 950 switch (opindex) 951 { 952 case OR1K_OPERAND_DISP21 : 953 fields->f_disp21 = value; 954 break; 955 case OR1K_OPERAND_DISP26 : 956 fields->f_disp26 = value; 957 break; 958 case OR1K_OPERAND_RA : 959 fields->f_r2 = value; 960 break; 961 case OR1K_OPERAND_RADF : 962 fields->f_r1 = value; 963 break; 964 case OR1K_OPERAND_RASF : 965 fields->f_r2 = value; 966 break; 967 case OR1K_OPERAND_RB : 968 fields->f_r3 = value; 969 break; 970 case OR1K_OPERAND_RBDF : 971 fields->f_r1 = value; 972 break; 973 case OR1K_OPERAND_RBSF : 974 fields->f_r3 = value; 975 break; 976 case OR1K_OPERAND_RD : 977 fields->f_r1 = value; 978 break; 979 case OR1K_OPERAND_RDDF : 980 fields->f_r1 = value; 981 break; 982 case OR1K_OPERAND_RDSF : 983 fields->f_r1 = value; 984 break; 985 case OR1K_OPERAND_SIMM16 : 986 fields->f_simm16 = value; 987 break; 988 case OR1K_OPERAND_SIMM16_SPLIT : 989 fields->f_simm16_split = value; 990 break; 991 case OR1K_OPERAND_UIMM16 : 992 fields->f_uimm16 = value; 993 break; 994 case OR1K_OPERAND_UIMM16_SPLIT : 995 fields->f_uimm16_split = value; 996 break; 997 case OR1K_OPERAND_UIMM6 : 998 fields->f_uimm6 = value; 999 break; 1000 1001 default : 1002 /* xgettext:c-format */ 1003 opcodes_error_handler 1004 (_("internal error: unrecognized field %d while setting int operand"), 1005 opindex); 1006 abort (); 1007 } 1008 } 1009 1010 void 1011 or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1012 int opindex, 1013 CGEN_FIELDS * fields, 1014 bfd_vma value) 1015 { 1016 switch (opindex) 1017 { 1018 case OR1K_OPERAND_DISP21 : 1019 fields->f_disp21 = value; 1020 break; 1021 case OR1K_OPERAND_DISP26 : 1022 fields->f_disp26 = value; 1023 break; 1024 case OR1K_OPERAND_RA : 1025 fields->f_r2 = value; 1026 break; 1027 case OR1K_OPERAND_RADF : 1028 fields->f_r1 = value; 1029 break; 1030 case OR1K_OPERAND_RASF : 1031 fields->f_r2 = value; 1032 break; 1033 case OR1K_OPERAND_RB : 1034 fields->f_r3 = value; 1035 break; 1036 case OR1K_OPERAND_RBDF : 1037 fields->f_r1 = value; 1038 break; 1039 case OR1K_OPERAND_RBSF : 1040 fields->f_r3 = value; 1041 break; 1042 case OR1K_OPERAND_RD : 1043 fields->f_r1 = value; 1044 break; 1045 case OR1K_OPERAND_RDDF : 1046 fields->f_r1 = value; 1047 break; 1048 case OR1K_OPERAND_RDSF : 1049 fields->f_r1 = value; 1050 break; 1051 case OR1K_OPERAND_SIMM16 : 1052 fields->f_simm16 = value; 1053 break; 1054 case OR1K_OPERAND_SIMM16_SPLIT : 1055 fields->f_simm16_split = value; 1056 break; 1057 case OR1K_OPERAND_UIMM16 : 1058 fields->f_uimm16 = value; 1059 break; 1060 case OR1K_OPERAND_UIMM16_SPLIT : 1061 fields->f_uimm16_split = value; 1062 break; 1063 case OR1K_OPERAND_UIMM6 : 1064 fields->f_uimm6 = value; 1065 break; 1066 1067 default : 1068 /* xgettext:c-format */ 1069 opcodes_error_handler 1070 (_("internal error: unrecognized field %d while setting vma operand"), 1071 opindex); 1072 abort (); 1073 } 1074 } 1075 1076 /* Function to call before using the instruction builder tables. */ 1077 1078 void 1079 or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1080 { 1081 cd->insert_handlers = & or1k_cgen_insert_handlers[0]; 1082 cd->extract_handlers = & or1k_cgen_extract_handlers[0]; 1083 1084 cd->insert_operand = or1k_cgen_insert_operand; 1085 cd->extract_operand = or1k_cgen_extract_operand; 1086 1087 cd->get_int_operand = or1k_cgen_get_int_operand; 1088 cd->set_int_operand = or1k_cgen_set_int_operand; 1089 cd->get_vma_operand = or1k_cgen_get_vma_operand; 1090 cd->set_vma_operand = or1k_cgen_set_vma_operand; 1091 } 1092