1 /* CPU data header for fr30. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2017 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef FR30_CPU_H 26 #define FR30_CPU_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #define CGEN_ARCH fr30 33 34 /* Given symbol S, return fr30_cgen_<S>. */ 35 #define CGEN_SYM(s) fr30##_cgen_##s 36 37 38 /* Selected cpu families. */ 39 #define HAVE_CPU_FR30BF 40 41 #define CGEN_INSN_LSB0_P 0 42 43 /* Minimum size of any insn (in bytes). */ 44 #define CGEN_MIN_INSN_SIZE 2 45 46 /* Maximum size of any insn (in bytes). */ 47 #define CGEN_MAX_INSN_SIZE 6 48 49 #define CGEN_INT_INSN_P 0 50 51 /* Maximum number of syntax elements in an instruction. */ 52 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 53 54 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 55 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 56 we can't hash on everything up to the space. */ 57 #define CGEN_MNEMONIC_OPERANDS 58 59 /* Maximum number of fields in an instruction. */ 60 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 61 62 /* Enums. */ 63 64 /* Enum declaration for insn op1 enums. */ 65 typedef enum insn_op1 { 66 OP1_0, OP1_1, OP1_2, OP1_3 67 , OP1_4, OP1_5, OP1_6, OP1_7 68 , OP1_8, OP1_9, OP1_A, OP1_B 69 , OP1_C, OP1_D, OP1_E, OP1_F 70 } INSN_OP1; 71 72 /* Enum declaration for insn op2 enums. */ 73 typedef enum insn_op2 { 74 OP2_0, OP2_1, OP2_2, OP2_3 75 , OP2_4, OP2_5, OP2_6, OP2_7 76 , OP2_8, OP2_9, OP2_A, OP2_B 77 , OP2_C, OP2_D, OP2_E, OP2_F 78 } INSN_OP2; 79 80 /* Enum declaration for insn op3 enums. */ 81 typedef enum insn_op3 { 82 OP3_0, OP3_1, OP3_2, OP3_3 83 , OP3_4, OP3_5, OP3_6, OP3_7 84 , OP3_8, OP3_9, OP3_A, OP3_B 85 , OP3_C, OP3_D, OP3_E, OP3_F 86 } INSN_OP3; 87 88 /* Enum declaration for insn op4 enums. */ 89 typedef enum insn_op4 { 90 OP4_0 91 } INSN_OP4; 92 93 /* Enum declaration for insn op5 enums. */ 94 typedef enum insn_op5 { 95 OP5_0, OP5_1 96 } INSN_OP5; 97 98 /* Enum declaration for insn cc enums. */ 99 typedef enum insn_cc { 100 CC_RA, CC_NO, CC_EQ, CC_NE 101 , CC_C, CC_NC, CC_N, CC_P 102 , CC_V, CC_NV, CC_LT, CC_GE 103 , CC_LE, CC_GT, CC_LS, CC_HI 104 } INSN_CC; 105 106 /* Enum declaration for . */ 107 typedef enum gr_names { 108 H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 109 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 110 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 111 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 113 } GR_NAMES; 114 115 /* Enum declaration for . */ 116 typedef enum cr_names { 117 H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 118 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 119 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 120 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 121 } CR_NAMES; 122 123 /* Enum declaration for . */ 124 typedef enum dr_names { 125 H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP 126 , H_DR_MDH, H_DR_MDL 127 } DR_NAMES; 128 129 /* Attributes. */ 130 131 /* Enum declaration for machine type selection. */ 132 typedef enum mach_attr { 133 MACH_BASE, MACH_FR30, MACH_MAX 134 } MACH_ATTR; 135 136 /* Enum declaration for instruction set selection. */ 137 typedef enum isa_attr { 138 ISA_FR30, ISA_MAX 139 } ISA_ATTR; 140 141 /* Number of architecture variants. */ 142 #define MAX_ISAS 1 143 #define MAX_MACHS ((int) MACH_MAX) 144 145 /* Ifield support. */ 146 147 /* Ifield attribute indices. */ 148 149 /* Enum declaration for cgen_ifld attrs. */ 150 typedef enum cgen_ifld_attr { 151 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 152 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 153 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 154 } CGEN_IFLD_ATTR; 155 156 /* Number of non-boolean elements in cgen_ifld_attr. */ 157 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 158 159 /* cgen_ifld attribute accessor macros. */ 160 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 161 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 162 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 163 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 164 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 165 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 166 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 167 168 /* Enum declaration for fr30 ifield types. */ 169 typedef enum ifield_type { 170 FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 171 , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC 172 , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 173 , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ 174 , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 175 , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 176 , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 177 , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 178 , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 179 , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST 180 , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX 181 } IFIELD_TYPE; 182 183 #define MAX_IFLD ((int) FR30_F_MAX) 184 185 /* Hardware attribute indices. */ 186 187 /* Enum declaration for cgen_hw attrs. */ 188 typedef enum cgen_hw_attr { 189 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 190 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 191 } CGEN_HW_ATTR; 192 193 /* Number of non-boolean elements in cgen_hw_attr. */ 194 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 195 196 /* cgen_hw attribute accessor macros. */ 197 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 198 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 199 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 200 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 201 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 202 203 /* Enum declaration for fr30 hardware types. */ 204 typedef enum cgen_hw_type { 205 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 206 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR 207 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 208 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT 209 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT 210 , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR 211 , HW_H_ILM, HW_MAX 212 } CGEN_HW_TYPE; 213 214 #define MAX_HW ((int) HW_MAX) 215 216 /* Operand attribute indices. */ 217 218 /* Enum declaration for cgen_operand attrs. */ 219 typedef enum cgen_operand_attr { 220 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 221 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 222 , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 223 , CGEN_OPERAND_END_NBOOLS 224 } CGEN_OPERAND_ATTR; 225 226 /* Number of non-boolean elements in cgen_operand_attr. */ 227 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 228 229 /* cgen_operand attribute accessor macros. */ 230 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 231 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 232 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 233 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 234 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 235 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 236 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 237 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 238 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 239 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) 240 241 /* Enum declaration for fr30 operand types. */ 242 typedef enum cgen_operand_type { 243 FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC 244 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 245 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 246 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 247 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 248 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 249 , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 250 , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD 251 , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC 252 , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT 253 , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT 254 , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR 255 , FR30_OPERAND_ILM, FR30_OPERAND_MAX 256 } CGEN_OPERAND_TYPE; 257 258 /* Number of operands types. */ 259 #define MAX_OPERANDS 49 260 261 /* Maximum number of operands referenced by any insn. */ 262 #define MAX_OPERAND_INSTANCES 8 263 264 /* Insn attribute indices. */ 265 266 /* Enum declaration for cgen_insn attrs. */ 267 typedef enum cgen_insn_attr { 268 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 269 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 270 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS 271 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 272 } CGEN_INSN_ATTR; 273 274 /* Number of non-boolean elements in cgen_insn_attr. */ 275 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 276 277 /* cgen_insn attribute accessor macros. */ 278 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 279 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 280 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 281 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 282 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 283 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 284 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 285 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 286 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 287 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 288 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 289 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) 290 291 /* cgen.h uses things we just defined. */ 292 #include "opcode/cgen.h" 293 294 extern const struct cgen_ifld fr30_cgen_ifld_table[]; 295 296 /* Attributes. */ 297 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[]; 298 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[]; 299 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; 300 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; 301 302 /* Hardware decls. */ 303 304 extern CGEN_KEYWORD fr30_cgen_opval_gr_names; 305 extern CGEN_KEYWORD fr30_cgen_opval_cr_names; 306 extern CGEN_KEYWORD fr30_cgen_opval_dr_names; 307 extern CGEN_KEYWORD fr30_cgen_opval_h_ps; 308 extern CGEN_KEYWORD fr30_cgen_opval_h_r13; 309 extern CGEN_KEYWORD fr30_cgen_opval_h_r14; 310 extern CGEN_KEYWORD fr30_cgen_opval_h_r15; 311 312 extern const CGEN_HW_ENTRY fr30_cgen_hw_table[]; 313 314 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif /* FR30_CPU_H */ 321