1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2019 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith@cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 25 #include "disassemble.h" 26 #include "opcode/arm.h" 27 #include "opintl.h" 28 #include "safe-ctype.h" 29 #include "libiberty.h" 30 #include "floatformat.h" 31 32 /* FIXME: This shouldn't be done here. */ 33 #include "coff/internal.h" 34 #include "libcoff.h" 35 #include "bfd.h" 36 #include "elf-bfd.h" 37 #include "elf/internal.h" 38 #include "elf/arm.h" 39 #include "mach-o.h" 40 41 /* FIXME: Belongs in global header. */ 42 #ifndef strneq 43 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 44 #endif 45 46 /* Cached mapping symbol state. */ 47 enum map_type 48 { 49 MAP_ARM, 50 MAP_THUMB, 51 MAP_DATA 52 }; 53 54 struct arm_private_data 55 { 56 /* The features to use when disassembling optional instructions. */ 57 arm_feature_set features; 58 59 /* Whether any mapping symbols are present in the provided symbol 60 table. -1 if we do not know yet, otherwise 0 or 1. */ 61 int has_mapping_symbols; 62 63 /* Track the last type (although this doesn't seem to be useful) */ 64 enum map_type last_type; 65 66 /* Tracking symbol table information */ 67 int last_mapping_sym; 68 bfd_vma last_mapping_addr; 69 }; 70 71 struct opcode32 72 { 73 arm_feature_set arch; /* Architecture defining this insn. */ 74 unsigned long value; /* If arch is 0 then value is a sentinel. */ 75 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 76 const char * assembler; /* How to disassemble this insn. */ 77 }; 78 79 struct opcode16 80 { 81 arm_feature_set arch; /* Architecture defining this insn. */ 82 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 83 const char *assembler; /* How to disassemble this insn. */ 84 }; 85 86 /* print_insn_coprocessor recognizes the following format control codes: 87 88 %% % 89 90 %c print condition code (always bits 28-31 in ARM mode) 91 %q print shifter argument 92 %u print condition code (unconditional in ARM mode, 93 UNPREDICTABLE if not AL in Thumb) 94 %A print address for ldc/stc/ldf/stf instruction 95 %B print vstm/vldm register list 96 %I print cirrus signed shift immediate: bits 0..3|4..6 97 %F print the COUNT field of a LFM/SFM instruction. 98 %P print floating point precision in arithmetic insn 99 %Q print floating point precision in ldf/stf insn 100 %R print floating point rounding mode 101 102 %<bitfield>c print as a condition code (for vsel) 103 %<bitfield>r print as an ARM register 104 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 105 %<bitfield>ru as %<>r but each u register must be unique. 106 %<bitfield>d print the bitfield in decimal 107 %<bitfield>k print immediate for VFPv3 conversion instruction 108 %<bitfield>x print the bitfield in hex 109 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 110 %<bitfield>f print a floating point constant if >7 else a 111 floating point register 112 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 113 %<bitfield>g print as an iWMMXt 64-bit register 114 %<bitfield>G print as an iWMMXt general purpose or control register 115 %<bitfield>D print as a NEON D register 116 %<bitfield>Q print as a NEON Q register 117 %<bitfield>V print as a NEON D or Q register 118 %<bitfield>E print a quarter-float immediate value 119 120 %y<code> print a single precision VFP reg. 121 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 122 %z<code> print a double precision VFP reg 123 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 124 125 %<bitfield>'c print specified char iff bitfield is all ones 126 %<bitfield>`c print specified char iff bitfield is all zeroes 127 %<bitfield>?ab... select from array of values in big endian order 128 129 %L print as an iWMMXt N/M width field. 130 %Z print the Immediate of a WSHUFH instruction. 131 %l like 'A' except use byte offsets for 'B' & 'H' 132 versions. 133 %i print 5-bit immediate in bits 8,3..0 134 (print "32" when 0) 135 %r print register offset address for wldt/wstr instruction. */ 136 137 enum opcode_sentinel_enum 138 { 139 SENTINEL_IWMMXT_START = 1, 140 SENTINEL_IWMMXT_END, 141 SENTINEL_GENERIC_START 142 } opcode_sentinels; 143 144 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 145 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x" 146 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x" 147 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 148 149 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 150 151 static const struct opcode32 coprocessor_opcodes[] = 152 { 153 /* XScale instructions. */ 154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 155 0x0e200010, 0x0fff0ff0, 156 "mia%c\tacc0, %0-3r, %12-15r"}, 157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 158 0x0e280010, 0x0fff0ff0, 159 "miaph%c\tacc0, %0-3r, %12-15r"}, 160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 161 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 163 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 165 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 166 167 /* Intel Wireless MMX technology instructions. */ 168 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 169 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 170 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 172 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 174 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 176 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 178 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 180 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 182 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 184 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 186 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 188 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 190 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 192 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 194 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 196 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 198 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 200 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 202 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 204 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 206 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 208 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 210 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 212 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 214 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 216 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 218 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 220 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 222 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 224 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 226 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 228 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 230 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 232 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 234 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 236 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 238 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 240 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 242 0x0e800120, 0x0f800ff0, 243 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 245 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 247 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 249 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 251 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 253 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 255 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 257 0x0e8000a0, 0x0f800ff0, 258 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 260 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 262 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 264 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 266 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 268 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 270 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 272 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 274 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 276 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 278 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 280 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 282 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 284 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 286 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 288 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 290 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 292 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 294 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 296 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 298 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 300 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 302 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 304 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 306 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 308 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 310 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 312 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 314 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 316 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 318 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 319 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 320 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 321 {ARM_FEATURE_CORE_LOW (0), 322 SENTINEL_IWMMXT_END, 0, "" }, 323 324 /* Floating point coprocessor (FPA) instructions. */ 325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 326 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 328 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 330 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 332 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 334 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 336 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 338 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 340 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 342 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 344 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 346 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 348 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 350 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 352 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 354 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 356 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 358 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 360 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 362 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 364 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 366 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 368 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 370 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 372 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 374 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 376 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 378 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 380 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 382 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 384 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 386 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 388 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 390 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 392 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 394 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 396 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 398 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 400 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 402 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 404 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 406 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 408 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 409 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 410 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 411 412 /* ARMv8-M Mainline Security Extensions instructions. */ 413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 414 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 416 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 417 418 /* Register load/store. */ 419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 420 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 422 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 424 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 426 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 428 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 430 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 432 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 434 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 436 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 438 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 440 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 442 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 444 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 446 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 448 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 450 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 451 452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 453 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 455 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 457 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 458 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 459 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 460 461 /* Data transfer between ARM and NEON registers. */ 462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 463 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 465 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 467 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 469 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 471 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 473 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 475 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 477 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 479 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 481 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 483 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 485 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 487 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 489 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 490 /* Half-precision conversion instructions. */ 491 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 492 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 494 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 496 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 498 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 499 500 /* Floating point coprocessor (VFP) instructions. */ 501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 502 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 504 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 506 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 508 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 510 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 512 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 514 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 516 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 518 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 520 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 522 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 524 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 526 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 528 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 530 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 532 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 534 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 536 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 538 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 540 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 542 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 544 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 546 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 548 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 550 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 552 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 554 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 556 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 558 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 560 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 562 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 564 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 566 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 568 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 570 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 572 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 574 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 576 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 578 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 580 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 582 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 584 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 586 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 588 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 590 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 592 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 594 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 596 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 598 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 600 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 602 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 604 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 606 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 608 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 610 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 612 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 614 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 616 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 618 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 620 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 622 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 624 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 626 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 627 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 628 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 629 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 630 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 631 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 632 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 633 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 634 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 635 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 636 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 637 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 638 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 639 640 /* Cirrus coprocessor instructions. */ 641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 642 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 644 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 646 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 648 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 650 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 652 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 654 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 656 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 658 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 660 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 662 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 664 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 666 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 668 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 670 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 672 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 674 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 676 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 678 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 680 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 682 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 684 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 686 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 688 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 690 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 692 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 694 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 696 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 698 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 700 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 702 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 704 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 706 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 708 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 710 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 712 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 714 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 716 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 718 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 720 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 722 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 724 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 726 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 728 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 730 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 732 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 734 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 736 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 738 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 740 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 742 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 744 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 746 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 748 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 750 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 752 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 754 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 756 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 758 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 760 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 762 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 764 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 766 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 768 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 770 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 772 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 774 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 776 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 778 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 780 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 782 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 784 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 786 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 788 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 790 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 792 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 794 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 796 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 798 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 800 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 802 0x0e000600, 0x0ff00f10, 803 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 805 0x0e100600, 0x0ff00f10, 806 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 808 0x0e200600, 0x0ff00f10, 809 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 810 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 811 0x0e300600, 0x0ff00f10, 812 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 813 814 /* VFP Fused multiply add instructions. */ 815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 816 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 818 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 819 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 820 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 822 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 824 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 826 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 827 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 828 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 830 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 831 832 /* FP v5. */ 833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 834 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 836 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 838 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 840 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 842 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 844 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 845 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 846 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 847 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 848 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 849 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 850 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 851 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 852 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 853 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 854 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 855 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 856 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 857 858 /* Generic coprocessor instructions. */ 859 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 861 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 863 0x0c500000, 0x0ff00000, 864 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 866 0x0e000000, 0x0f000010, 867 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 869 0x0e10f010, 0x0f10f010, 870 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 872 0x0e100010, 0x0f100010, 873 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 875 0x0e000010, 0x0f100010, 876 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 878 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 880 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 881 882 /* V6 coprocessor instructions. */ 883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 884 0xfc500000, 0xfff00000, 885 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 887 0xfc400000, 0xfff00000, 888 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 889 890 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 891 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 892 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 894 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 896 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 898 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 900 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 902 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 904 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 906 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, 907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 908 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 910 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, 911 912 /* Dot Product instructions in the space of coprocessor 13. */ 913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 914 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 916 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, 917 918 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 920 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 922 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 924 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 926 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 928 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 930 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 932 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 934 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 935 936 /* V5 coprocessor instructions. */ 937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 938 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 940 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 942 0xfe000000, 0xff000010, 943 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 945 0xfe000010, 0xff100010, 946 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 948 0xfe100010, 0xff100010, 949 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 950 951 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 952 cp_num: bit <11:8> == 0b1001. 953 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 955 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 957 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 959 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 961 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 963 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 965 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 967 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 969 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 971 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 973 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 975 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 977 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 979 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 981 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 983 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 985 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 987 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 989 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 991 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 993 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 995 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 997 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 999 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1000 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1001 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1003 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 1004 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1005 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1006 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1007 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1009 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1010 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1011 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1012 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1013 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1015 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1016 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1017 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1018 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1019 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1021 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1022 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1023 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1024 1025 /* ARMv8.3 javascript conversion instruction. */ 1026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1027 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1028 1029 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1030 }; 1031 1032 /* Neon opcode table: This does not encode the top byte -- that is 1033 checked by the print_insn_neon routine, as it depends on whether we are 1034 doing thumb32 or arm32 disassembly. */ 1035 1036 /* print_insn_neon recognizes the following format control codes: 1037 1038 %% % 1039 1040 %c print condition code 1041 %u print condition code (unconditional in ARM mode, 1042 UNPREDICTABLE if not AL in Thumb) 1043 %A print v{st,ld}[1234] operands 1044 %B print v{st,ld}[1234] any one operands 1045 %C print v{st,ld}[1234] single->all operands 1046 %D print scalar 1047 %E print vmov, vmvn, vorr, vbic encoded constant 1048 %F print vtbl,vtbx register list 1049 1050 %<bitfield>r print as an ARM register 1051 %<bitfield>d print the bitfield in decimal 1052 %<bitfield>e print the 2^N - bitfield in decimal 1053 %<bitfield>D print as a NEON D register 1054 %<bitfield>Q print as a NEON Q register 1055 %<bitfield>R print as a NEON D or Q register 1056 %<bitfield>Sn print byte scaled width limited by n 1057 %<bitfield>Tn print short scaled width limited by n 1058 %<bitfield>Un print long scaled width limited by n 1059 1060 %<bitfield>'c print specified char iff bitfield is all ones 1061 %<bitfield>`c print specified char iff bitfield is all zeroes 1062 %<bitfield>?ab... select from array of values in big endian order. */ 1063 1064 static const struct opcode32 neon_opcodes[] = 1065 { 1066 /* Extract. */ 1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1068 0xf2b00840, 0xffb00850, 1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1071 0xf2b00000, 0xffb00810, 1072 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1073 1074 /* Move data element to all lanes. */ 1075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1076 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1078 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1079 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1080 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1081 1082 /* Table lookup. */ 1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1084 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1086 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1087 1088 /* Half-precision conversions. */ 1089 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1090 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1091 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1092 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1093 1094 /* NEON fused multiply add instructions. */ 1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1096 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1098 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1100 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1101 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1102 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1103 1104 /* Two registers, miscellaneous. */ 1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1106 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1108 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1110 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1112 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1113 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1114 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1115 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1116 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1117 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1118 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1119 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1120 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1121 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1122 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1123 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1124 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1125 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1126 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1128 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1130 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1132 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1134 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1136 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1138 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1140 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1142 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1144 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1146 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1148 0xf3b20300, 0xffb30fd0, 1149 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1151 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1153 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1155 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1157 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1159 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1161 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1163 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1165 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1167 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1169 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1171 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1173 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1175 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1177 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1179 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1181 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1183 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1185 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1187 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1189 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1191 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1193 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1195 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1197 0xf3bb0600, 0xffbf0e10, 1198 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1200 0xf3b70600, 0xffbf0e10, 1201 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1202 1203 /* Three registers of the same length. */ 1204 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1205 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1206 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1207 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1208 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1209 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1210 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1211 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1212 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1213 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1214 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1215 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1216 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1217 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1219 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1220 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1221 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1223 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1225 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1227 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1229 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1231 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1233 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1235 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1237 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1239 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1241 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1243 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1245 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1247 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1249 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1251 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1253 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1255 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1257 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1259 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1261 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1263 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1265 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1267 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1269 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1271 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1273 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1275 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1277 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1279 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1281 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1283 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1285 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1287 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1289 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1291 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1293 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1295 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1297 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1299 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1301 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1303 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1305 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1307 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1309 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1311 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1313 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1315 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1317 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1319 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1321 0xf2000b00, 0xff800f10, 1322 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1324 0xf2000b10, 0xff800f10, 1325 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1327 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1329 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1331 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1333 0xf3000b00, 0xff800f10, 1334 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1336 0xf2000000, 0xfe800f10, 1337 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1339 0xf2000010, 0xfe800f10, 1340 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1342 0xf2000100, 0xfe800f10, 1343 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1345 0xf2000200, 0xfe800f10, 1346 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1348 0xf2000210, 0xfe800f10, 1349 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1351 0xf2000300, 0xfe800f10, 1352 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1354 0xf2000310, 0xfe800f10, 1355 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1357 0xf2000400, 0xfe800f10, 1358 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1360 0xf2000410, 0xfe800f10, 1361 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1363 0xf2000500, 0xfe800f10, 1364 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1366 0xf2000510, 0xfe800f10, 1367 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1369 0xf2000600, 0xfe800f10, 1370 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1372 0xf2000610, 0xfe800f10, 1373 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1375 0xf2000700, 0xfe800f10, 1376 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1378 0xf2000710, 0xfe800f10, 1379 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1381 0xf2000910, 0xfe800f10, 1382 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf2000a00, 0xfe800f10, 1385 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1387 0xf2000a10, 0xfe800f10, 1388 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1390 0xf3000b10, 0xff800f10, 1391 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1393 0xf3000c10, 0xff800f10, 1394 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1395 1396 /* One register and an immediate value. */ 1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1398 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1400 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1402 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1404 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1406 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1408 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1410 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1412 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1414 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1416 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1418 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1420 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1422 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1423 1424 /* Two registers and a shift amount. */ 1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1426 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1428 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1430 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1432 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1434 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1436 0xf2880950, 0xfeb80fd0, 1437 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1439 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1441 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1443 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1445 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1447 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1449 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1451 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1453 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1455 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1457 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1459 0xf2900950, 0xfeb00fd0, 1460 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1462 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1464 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1466 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1468 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1470 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1472 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1474 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1476 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1478 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1480 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1482 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1484 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1486 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1488 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1490 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1492 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1494 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1496 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1498 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1500 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1502 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1504 0xf2a00950, 0xfea00fd0, 1505 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1507 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1509 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1511 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1517 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1519 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1521 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1523 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1525 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1527 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1529 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1531 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1533 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1535 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1537 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1539 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1541 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1543 0xf2a00e10, 0xfea00e90, 1544 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1546 0xf2a00c10, 0xfea00e90, 1547 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 1548 1549 /* Three registers of different lengths. */ 1550 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1551 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1553 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2800400, 0xff800f50, 1556 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2800600, 0xff800f50, 1559 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1561 0xf2800900, 0xff800f50, 1562 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2800b00, 0xff800f50, 1565 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf2800d00, 0xff800f50, 1568 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1570 0xf3800400, 0xff800f50, 1571 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1573 0xf3800600, 0xff800f50, 1574 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2800000, 0xfe800f50, 1577 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1579 0xf2800100, 0xfe800f50, 1580 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1582 0xf2800200, 0xfe800f50, 1583 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1585 0xf2800300, 0xfe800f50, 1586 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1588 0xf2800500, 0xfe800f50, 1589 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2800700, 0xfe800f50, 1592 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1594 0xf2800800, 0xfe800f50, 1595 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf2800a00, 0xfe800f50, 1598 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1600 0xf2800c00, 0xfe800f50, 1601 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1602 1603 /* Two registers and a scalar. */ 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1607 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1608 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1609 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1613 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1615 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1616 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1617 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1619 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1621 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1624 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1625 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1627 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1629 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1631 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1633 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1635 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1636 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1637 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1639 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1641 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1642 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1643 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1645 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1647 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1648 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1649 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1651 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1653 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf2800240, 0xfe800f50, 1656 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1658 0xf2800640, 0xfe800f50, 1659 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1661 0xf2800a40, 0xfe800f50, 1662 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1664 0xf2800e40, 0xff800f50, 1665 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1667 0xf2800f40, 0xff800f50, 1668 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1670 0xf3800e40, 0xff800f50, 1671 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1673 0xf3800f40, 0xff800f50, 1674 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1675 }, 1676 1677 /* Element and structure load/store. */ 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1679 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1681 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1683 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1685 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1687 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1689 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1691 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1693 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1695 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1697 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1699 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1701 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1703 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1705 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1707 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1709 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1711 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1713 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1715 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1716 1717 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1718 }; 1719 1720 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 1721 ordered: they must be searched linearly from the top to obtain a correct 1722 match. */ 1723 1724 /* print_insn_arm recognizes the following format control codes: 1725 1726 %% % 1727 1728 %a print address for ldr/str instruction 1729 %s print address for ldr/str halfword/signextend instruction 1730 %S like %s but allow UNPREDICTABLE addressing 1731 %b print branch destination 1732 %c print condition code (always bits 28-31) 1733 %m print register mask for ldm/stm instruction 1734 %o print operand2 (immediate or register + shift) 1735 %p print 'p' iff bits 12-15 are 15 1736 %t print 't' iff bit 21 set and bit 24 clear 1737 %B print arm BLX(1) destination 1738 %C print the PSR sub type. 1739 %U print barrier type. 1740 %P print address for pli instruction. 1741 1742 %<bitfield>r print as an ARM register 1743 %<bitfield>T print as an ARM register + 1 1744 %<bitfield>R as %r but r15 is UNPREDICTABLE 1745 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 1746 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 1747 %<bitfield>d print the bitfield in decimal 1748 %<bitfield>W print the bitfield plus one in decimal 1749 %<bitfield>x print the bitfield in hex 1750 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 1751 1752 %<bitfield>'c print specified char iff bitfield is all ones 1753 %<bitfield>`c print specified char iff bitfield is all zeroes 1754 %<bitfield>?ab... select from array of values in big endian order 1755 1756 %e print arm SMI operand (bits 0..7,8..19). 1757 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 1758 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 1759 %R print the SPSR/CPSR or banked register of an MRS. */ 1760 1761 static const struct opcode32 arm_opcodes[] = 1762 { 1763 /* ARM instructions. */ 1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1765 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1767 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 1768 1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 1770 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1772 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1774 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 1776 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1778 0x00800090, 0x0fa000f0, 1779 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1781 0x00a00090, 0x0fa000f0, 1782 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1783 1784 /* V8.2 RAS extension instructions. */ 1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 1786 0xe320f010, 0xffffffff, "esb"}, 1787 1788 /* V8 instructions. */ 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1790 0x0320f005, 0x0fffffff, "sevl"}, 1791 /* Defined in V8 but is in NOP space so available to all arch. */ 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1793 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 1794 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 1795 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 1796 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1797 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1799 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1801 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1803 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1805 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 1806 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1807 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 1808 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1809 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 1810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1811 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1813 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 1814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1815 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1817 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 1818 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1819 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 1820 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1821 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 1822 /* CRC32 instructions. */ 1823 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1824 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 1825 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1826 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 1827 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1828 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 1829 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1830 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 1831 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1832 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 1833 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1834 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 1835 1836 /* Privileged Access Never extension instructions. */ 1837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 1838 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 1839 1840 /* Virtualization Extension instructions. */ 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 1843 1844 /* Integer Divide Extension instructions. */ 1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1846 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1848 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 1849 1850 /* MP Extension instructions. */ 1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 1852 1853 /* Speculation Barriers. */ 1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 1857 1858 /* V7 instructions. */ 1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 1867 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 1868 1869 /* ARM V6T2 instructions. */ 1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1871 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1873 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1875 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1877 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 1878 1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1880 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1882 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 1883 1884 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1885 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 1886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1887 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1889 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1891 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 1892 1893 /* ARM Security extension instructions. */ 1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 1895 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 1896 1897 /* ARM V6K instructions. */ 1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1899 0xf57ff01f, 0xffffffff, "clrex"}, 1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1901 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1903 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1905 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1907 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1909 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1911 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 1912 1913 /* ARMv8.5-A instructions. */ 1914 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 1915 1916 /* ARM V6K NOP hints. */ 1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1918 0x0320f001, 0x0fffffff, "yield%c"}, 1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1920 0x0320f002, 0x0fffffff, "wfe%c"}, 1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1922 0x0320f003, 0x0fffffff, "wfi%c"}, 1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1924 0x0320f004, 0x0fffffff, "sev%c"}, 1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1926 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 1927 1928 /* ARM V6 instructions. */ 1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1930 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1932 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1934 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1936 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1938 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1940 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1942 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1944 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1946 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1948 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1950 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1952 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1954 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1956 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1958 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1960 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1962 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1964 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1966 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1968 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1970 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1972 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1974 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1976 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1978 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1980 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1982 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1984 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1986 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1988 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1990 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1992 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1994 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1996 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1998 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2000 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2002 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2004 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2006 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2008 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2010 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2012 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2014 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2016 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2018 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2020 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2022 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2024 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2026 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2028 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2030 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2032 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2034 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2036 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2038 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2040 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2042 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2044 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2046 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2048 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2050 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2052 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2054 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2056 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2058 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2060 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2062 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2064 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2066 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2068 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2070 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2072 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2074 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2076 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2078 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2080 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2082 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2084 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2086 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2088 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2090 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2092 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2094 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2096 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2098 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2100 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2102 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2104 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2106 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2108 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2110 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2112 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2114 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2116 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2118 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2120 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2122 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2124 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2126 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2128 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2130 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2132 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2134 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2136 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2138 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2140 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2142 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2144 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2146 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2148 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2150 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2152 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2154 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2156 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2158 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2160 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2162 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2164 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2166 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2168 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2170 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2172 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 2173 2174 /* V5J instruction. */ 2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 2176 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 2177 2178 /* V5 Instructions. */ 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2180 0xe1200070, 0xfff000f0, 2181 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2183 0xfa000000, 0xfe000000, "blx\t%B"}, 2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2185 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2187 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 2188 2189 /* V5E "El Segundo" Instructions. */ 2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2191 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2193 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2195 0xf450f000, 0xfc70f000, "pld\t%a"}, 2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2197 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2199 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2201 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2203 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 2204 2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2206 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2208 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 2209 2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2211 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2213 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2215 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2217 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2218 2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2220 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2222 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2224 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2226 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 2227 2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2229 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2231 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 2232 2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2234 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2236 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2238 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2240 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 2241 2242 /* ARM Instructions. */ 2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2244 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 2245 2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2247 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2249 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2251 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2253 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2255 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2257 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 2258 2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2260 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2262 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2264 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2266 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 2267 2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2269 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2271 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2273 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2275 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2276 2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2278 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2280 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2282 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 2283 2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2285 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2287 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2289 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 2290 2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2292 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2294 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2296 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 2297 2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2299 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2301 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2303 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 2304 2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2306 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2308 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2310 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 2311 2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2313 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2315 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2317 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 2318 2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2320 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2322 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2324 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 2325 2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2327 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2329 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2331 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 2332 2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 2334 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2336 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2338 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 2339 2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2341 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2343 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2345 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 2346 2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2348 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2350 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2352 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 2353 2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2355 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2357 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2359 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 2360 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2362 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2364 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2366 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 2367 2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2369 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2371 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2373 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 2374 2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2376 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2378 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2380 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2382 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2384 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2386 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2388 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 2389 2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2391 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2393 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2395 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 2396 2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2398 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2400 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2402 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 2403 2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2405 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2407 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 2408 2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2410 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 2411 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2413 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2415 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 2416 2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2418 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2420 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2422 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2424 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2426 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2428 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2430 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2432 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2434 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2436 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2438 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2440 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2442 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2444 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2446 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2448 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2450 0x092d0000, 0x0fff0000, "push%c\t%m"}, 2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2452 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2454 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2455 2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2457 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2459 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2461 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2463 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2465 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2467 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2469 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2471 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2473 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2475 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2477 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2479 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2481 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2483 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2485 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2487 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2489 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2491 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2493 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2494 2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2496 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2498 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 2499 2500 /* The rest. */ 2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 2502 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2504 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 2505 {ARM_FEATURE_CORE_LOW (0), 2506 0x00000000, 0x00000000, 0} 2507 }; 2508 2509 /* print_insn_thumb16 recognizes the following format control codes: 2510 2511 %S print Thumb register (bits 3..5 as high number if bit 6 set) 2512 %D print Thumb register (bits 0..2 as high number if bit 7 set) 2513 %<bitfield>I print bitfield as a signed decimal 2514 (top bit of range being the sign bit) 2515 %N print Thumb register mask (with LR) 2516 %O print Thumb register mask (with PC) 2517 %M print Thumb register mask 2518 %b print CZB's 6-bit unsigned branch destination 2519 %s print Thumb right-shift immediate (6..10; 0 == 32). 2520 %c print the condition code 2521 %C print the condition code, or "s" if not conditional 2522 %x print warning if conditional an not at end of IT block" 2523 %X print "\t; unpredictable <IT:code>" if conditional 2524 %I print IT instruction suffix and operands 2525 %W print Thumb Writeback indicator for LDMIA 2526 %<bitfield>r print bitfield as an ARM register 2527 %<bitfield>d print bitfield as a decimal 2528 %<bitfield>H print (bitfield * 2) as a decimal 2529 %<bitfield>W print (bitfield * 4) as a decimal 2530 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 2531 %<bitfield>B print Thumb branch destination (signed displacement) 2532 %<bitfield>c print bitfield as a condition code 2533 %<bitnum>'c print specified char iff bit is one 2534 %<bitnum>?ab print a if bit is one else print b. */ 2535 2536 static const struct opcode16 thumb_opcodes[] = 2537 { 2538 /* Thumb instructions. */ 2539 2540 /* ARMv8-M Security Extensions instructions. */ 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 2542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 2543 2544 /* ARM V8 instructions. */ 2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 2548 2549 /* ARM V6K no-argument instructions. */ 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 2556 2557 /* ARM V6T2 instructions. */ 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2559 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 2560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2561 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 2563 2564 /* ARM V6. */ 2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 2576 2577 /* ARM V5 ISA extends Thumb. */ 2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2579 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 2580 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2582 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 2583 /* ARM V4T ISA (Thumb v1). */ 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2585 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 2586 /* Format 4. */ 2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 2603 /* format 13 */ 2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 2606 /* format 5 */ 2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 2611 /* format 14 */ 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 2614 /* format 2 */ 2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2616 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2618 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2620 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2622 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 2623 /* format 8 */ 2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2625 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2627 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2629 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 2630 /* format 7 */ 2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2632 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2634 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2635 /* format 1 */ 2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2638 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 2641 /* format 3 */ 2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 2646 /* format 6 */ 2647 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2649 0x4800, 0xF800, 2650 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 2651 /* format 9 */ 2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2653 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2655 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2657 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2659 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2660 /* format 10 */ 2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2662 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2664 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2665 /* format 11 */ 2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2667 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2669 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 2670 /* format 12 */ 2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2672 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2674 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 2675 /* format 15 */ 2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 2678 /* format 17 */ 2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 2680 /* format 16 */ 2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 2684 /* format 18 */ 2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 2686 2687 /* The E800 .. FFFF range is unconditionally redirected to the 2688 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 2689 are processed via that table. Thus, we can never encounter a 2690 bare "second half of BL/BLX(1)" instruction here. */ 2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 2692 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 2693 }; 2694 2695 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 2696 We adopt the convention that hw1 is the high 16 bits of .value and 2697 .mask, hw2 the low 16 bits. 2698 2699 print_insn_thumb32 recognizes the following format control codes: 2700 2701 %% % 2702 2703 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 2704 %M print a modified 12-bit immediate (same location) 2705 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 2706 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 2707 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 2708 %S print a possibly-shifted Rm 2709 2710 %L print address for a ldrd/strd instruction 2711 %a print the address of a plain load/store 2712 %w print the width and signedness of a core load/store 2713 %m print register mask for ldm/stm 2714 2715 %E print the lsb and width fields of a bfc/bfi instruction 2716 %F print the lsb and width fields of a sbfx/ubfx instruction 2717 %b print a conditional branch offset 2718 %B print an unconditional branch offset 2719 %s print the shift field of an SSAT instruction 2720 %R print the rotation field of an SXT instruction 2721 %U print barrier type. 2722 %P print address for pli instruction. 2723 %c print the condition code 2724 %x print warning if conditional an not at end of IT block" 2725 %X print "\t; unpredictable <IT:code>" if conditional 2726 2727 %<bitfield>d print bitfield in decimal 2728 %<bitfield>D print bitfield plus one in decimal 2729 %<bitfield>W print bitfield*4 in decimal 2730 %<bitfield>r print bitfield as an ARM register 2731 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 2732 %<bitfield>c print bitfield as a condition code 2733 2734 %<bitfield>'c print specified char iff bitfield is all ones 2735 %<bitfield>`c print specified char iff bitfield is all zeroes 2736 %<bitfield>?ab... select from array of values in big endian order 2737 2738 With one exception at the bottom (done because BL and BLX(1) need 2739 to come dead last), this table was machine-sorted first in 2740 decreasing order of number of bits set in the mask, then in 2741 increasing numeric order of mask, then in increasing numeric order 2742 of opcode. This order is not the clearest for a human reader, but 2743 is guaranteed never to catch a special-case bit pattern with a more 2744 general mask, which is important, because this instruction encoding 2745 makes heavy use of special-case bit patterns. */ 2746 static const struct opcode32 thumb32_opcodes[] = 2747 { 2748 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 2749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2751 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2753 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2755 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2757 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 2758 2759 /* ARM V8.2 RAS extension instructions. */ 2760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 2761 0xf3af8010, 0xffffffff, "esb"}, 2762 2763 /* V8 instructions. */ 2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2765 0xf3af8005, 0xffffffff, "sevl%c.w"}, 2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2767 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2769 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2771 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2773 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2775 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2777 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2779 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2781 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2783 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2785 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2787 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2789 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2791 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2793 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2795 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 2796 2797 /* CRC32 instructions. */ 2798 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2799 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 2800 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2801 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 2802 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2803 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 2804 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2805 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 2806 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2807 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 2808 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2809 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 2810 2811 /* Speculation Barriers. */ 2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 2815 2816 /* V7 instructions. */ 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2825 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2827 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 2828 2829 /* Virtualization Extension instructions. */ 2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 2831 /* We skip ERET as that is SUBS pc, lr, #0. */ 2832 2833 /* MP Extension instructions. */ 2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 2835 2836 /* Security extension instructions. */ 2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 2838 2839 /* ARMv8.5-A instructions. */ 2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 2841 2842 /* Instructions defined in the basic V6T2 set. */ 2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2849 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 2851 2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2853 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2855 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2857 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2859 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2861 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2863 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2865 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2867 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2869 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2871 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2873 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2875 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2877 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2879 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 2880 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2881 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 2882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2883 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2885 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2887 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2889 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2891 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2893 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2895 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2897 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2899 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2901 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2903 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2905 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2907 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2909 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2911 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2913 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2915 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2917 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2919 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2921 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2923 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2925 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2927 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2929 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2931 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2933 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2935 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2937 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2939 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2941 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2943 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2945 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2947 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2949 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2951 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2953 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2955 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2957 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2959 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2961 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2963 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2965 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2967 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2969 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2971 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2973 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2975 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2977 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2979 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2981 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2983 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2985 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2987 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2989 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2991 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2993 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2995 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2997 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2999 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3001 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3003 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3005 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3007 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3009 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3011 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3013 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3015 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3017 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3019 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3021 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3023 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3025 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3027 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3029 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3031 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3033 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3035 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3037 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3039 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3041 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3043 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3045 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3047 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3049 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3051 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3053 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3055 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3057 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3059 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3061 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3063 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3065 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3067 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3069 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3071 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3073 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3075 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3077 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3079 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3081 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3083 0xf810f000, 0xff70f000, "pld%c\t%a"}, 3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3085 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3087 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3089 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3091 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3093 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3095 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3097 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3099 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3101 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3103 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3105 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3107 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3109 0xfb100000, 0xfff000c0, 3110 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3112 0xfbc00080, 0xfff000c0, 3113 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3115 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3117 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3119 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3121 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3123 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 3124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3125 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3127 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 3128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3129 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3131 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3133 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3135 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3137 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3139 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3141 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3143 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3145 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3147 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3149 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3151 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3153 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3155 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3157 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3159 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3161 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3163 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3165 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3167 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3169 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3171 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3173 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3175 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3177 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3179 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3181 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3183 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3185 0xe9400000, 0xff500000, 3186 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3188 0xe9500000, 0xff500000, 3189 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3191 0xe8600000, 0xff700000, 3192 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3194 0xe8700000, 0xff700000, 3195 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3197 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3199 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 3200 3201 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3203 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3205 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3207 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3209 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 3210 3211 /* These have been 32-bit since the invention of Thumb. */ 3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3213 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3215 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 3216 3217 /* Fallback. */ 3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3219 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 3220 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 3221 }; 3222 3223 static const char *const arm_conditional[] = 3224 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 3225 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 3226 3227 static const char *const arm_fp_const[] = 3228 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 3229 3230 static const char *const arm_shift[] = 3231 {"lsl", "lsr", "asr", "ror"}; 3232 3233 typedef struct 3234 { 3235 const char *name; 3236 const char *description; 3237 const char *reg_names[16]; 3238 } 3239 arm_regname; 3240 3241 static const arm_regname regnames[] = 3242 { 3243 { "reg-names-raw", N_("Select raw register names"), 3244 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 3245 { "reg-names-gcc", N_("Select register names used by GCC"), 3246 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3247 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 3248 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 3249 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 3250 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 3251 { "reg-names-apcs", N_("Select register names used in the APCS"), 3252 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3253 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 3254 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 3255 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 3256 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 3257 }; 3258 3259 static const char *const iwmmxt_wwnames[] = 3260 {"b", "h", "w", "d"}; 3261 3262 static const char *const iwmmxt_wwssnames[] = 3263 {"b", "bus", "bc", "bss", 3264 "h", "hus", "hc", "hss", 3265 "w", "wus", "wc", "wss", 3266 "d", "dus", "dc", "dss" 3267 }; 3268 3269 static const char *const iwmmxt_regnames[] = 3270 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 3271 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 3272 }; 3273 3274 static const char *const iwmmxt_cregnames[] = 3275 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 3276 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 3277 }; 3278 3279 /* Default to GCC register name set. */ 3280 static unsigned int regname_selected = 1; 3281 3282 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 3283 #define arm_regnames regnames[regname_selected].reg_names 3284 3285 static bfd_boolean force_thumb = FALSE; 3286 3287 /* Current IT instruction state. This contains the same state as the IT 3288 bits in the CPSR. */ 3289 static unsigned int ifthen_state; 3290 /* IT state for the next instruction. */ 3291 static unsigned int ifthen_next_state; 3292 /* The address of the insn for which the IT state is valid. */ 3293 static bfd_vma ifthen_address; 3294 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 3295 /* Indicates that the current Conditional state is unconditional or outside 3296 an IT block. */ 3297 #define COND_UNCOND 16 3298 3299 3300 /* Functions. */ 3301 3302 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 3303 Returns pointer to following character of the format string and 3304 fills in *VALUEP and *WIDTHP with the extracted value and number of 3305 bits extracted. WIDTHP can be NULL. */ 3306 3307 static const char * 3308 arm_decode_bitfield (const char *ptr, 3309 unsigned long insn, 3310 unsigned long *valuep, 3311 int *widthp) 3312 { 3313 unsigned long value = 0; 3314 int width = 0; 3315 3316 do 3317 { 3318 int start, end; 3319 int bits; 3320 3321 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 3322 start = start * 10 + *ptr - '0'; 3323 if (*ptr == '-') 3324 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 3325 end = end * 10 + *ptr - '0'; 3326 else 3327 end = start; 3328 bits = end - start; 3329 if (bits < 0) 3330 abort (); 3331 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 3332 width += bits + 1; 3333 } 3334 while (*ptr++ == ','); 3335 *valuep = value; 3336 if (widthp) 3337 *widthp = width; 3338 return ptr - 1; 3339 } 3340 3341 static void 3342 arm_decode_shift (long given, fprintf_ftype func, void *stream, 3343 bfd_boolean print_shift) 3344 { 3345 func (stream, "%s", arm_regnames[given & 0xf]); 3346 3347 if ((given & 0xff0) != 0) 3348 { 3349 if ((given & 0x10) == 0) 3350 { 3351 int amount = (given & 0xf80) >> 7; 3352 int shift = (given & 0x60) >> 5; 3353 3354 if (amount == 0) 3355 { 3356 if (shift == 3) 3357 { 3358 func (stream, ", rrx"); 3359 return; 3360 } 3361 3362 amount = 32; 3363 } 3364 3365 if (print_shift) 3366 func (stream, ", %s #%d", arm_shift[shift], amount); 3367 else 3368 func (stream, ", #%d", amount); 3369 } 3370 else if ((given & 0x80) == 0x80) 3371 func (stream, "\t; <illegal shifter operand>"); 3372 else if (print_shift) 3373 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 3374 arm_regnames[(given & 0xf00) >> 8]); 3375 else 3376 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 3377 } 3378 } 3379 3380 #define W_BIT 21 3381 #define I_BIT 22 3382 #define U_BIT 23 3383 #define P_BIT 24 3384 3385 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 3386 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 3387 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 3388 #define PRE_BIT_SET (given & (1 << P_BIT)) 3389 3390 /* Print one coprocessor instruction on INFO->STREAM. 3391 Return TRUE if the instuction matched, FALSE if this is not a 3392 recognised coprocessor instruction. */ 3393 3394 static bfd_boolean 3395 print_insn_coprocessor (bfd_vma pc, 3396 struct disassemble_info *info, 3397 long given, 3398 bfd_boolean thumb) 3399 { 3400 const struct opcode32 *insn; 3401 void *stream = info->stream; 3402 fprintf_ftype func = info->fprintf_func; 3403 unsigned long mask; 3404 unsigned long value = 0; 3405 int cond; 3406 int cp_num; 3407 struct arm_private_data *private_data = info->private_data; 3408 arm_feature_set allowed_arches = ARM_ARCH_NONE; 3409 3410 allowed_arches = private_data->features; 3411 3412 for (insn = coprocessor_opcodes; insn->assembler; insn++) 3413 { 3414 unsigned long u_reg = 16; 3415 bfd_boolean is_unpredictable = FALSE; 3416 signed long value_in_comment = 0; 3417 const char *c; 3418 3419 if (ARM_FEATURE_ZERO (insn->arch)) 3420 switch (insn->value) 3421 { 3422 case SENTINEL_IWMMXT_START: 3423 if (info->mach != bfd_mach_arm_XScale 3424 && info->mach != bfd_mach_arm_iWMMXt 3425 && info->mach != bfd_mach_arm_iWMMXt2) 3426 do 3427 insn++; 3428 while ((! ARM_FEATURE_ZERO (insn->arch)) 3429 && insn->value != SENTINEL_IWMMXT_END); 3430 continue; 3431 3432 case SENTINEL_IWMMXT_END: 3433 continue; 3434 3435 case SENTINEL_GENERIC_START: 3436 allowed_arches = private_data->features; 3437 continue; 3438 3439 default: 3440 abort (); 3441 } 3442 3443 mask = insn->mask; 3444 value = insn->value; 3445 cp_num = (given >> 8) & 0xf; 3446 3447 if (thumb) 3448 { 3449 /* The high 4 bits are 0xe for Arm conditional instructions, and 3450 0xe for arm unconditional instructions. The rest of the 3451 encoding is the same. */ 3452 mask |= 0xf0000000; 3453 value |= 0xe0000000; 3454 if (ifthen_state) 3455 cond = IFTHEN_COND; 3456 else 3457 cond = COND_UNCOND; 3458 } 3459 else 3460 { 3461 /* Only match unconditional instuctions against unconditional 3462 patterns. */ 3463 if ((given & 0xf0000000) == 0xf0000000) 3464 { 3465 mask |= 0xf0000000; 3466 cond = COND_UNCOND; 3467 } 3468 else 3469 { 3470 cond = (given >> 28) & 0xf; 3471 if (cond == 0xe) 3472 cond = COND_UNCOND; 3473 } 3474 } 3475 3476 if ((given & mask) != value) 3477 continue; 3478 3479 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 3480 continue; 3481 3482 if (insn->value == 0xfe000010 /* mcr2 */ 3483 || insn->value == 0xfe100010 /* mrc2 */ 3484 || insn->value == 0xfc100000 /* ldc2 */ 3485 || insn->value == 0xfc000000) /* stc2 */ 3486 { 3487 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3488 is_unpredictable = TRUE; 3489 } 3490 else if (insn->value == 0x0e000000 /* cdp */ 3491 || insn->value == 0xfe000000 /* cdp2 */ 3492 || insn->value == 0x0e000010 /* mcr */ 3493 || insn->value == 0x0e100010 /* mrc */ 3494 || insn->value == 0x0c100000 /* ldc */ 3495 || insn->value == 0x0c000000) /* stc */ 3496 { 3497 /* Floating-point instructions. */ 3498 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3499 continue; 3500 } 3501 3502 for (c = insn->assembler; *c; c++) 3503 { 3504 if (*c == '%') 3505 { 3506 switch (*++c) 3507 { 3508 case '%': 3509 func (stream, "%%"); 3510 break; 3511 3512 case 'A': 3513 { 3514 int rn = (given >> 16) & 0xf; 3515 bfd_vma offset = given & 0xff; 3516 3517 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3518 3519 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 3520 { 3521 /* Not unindexed. The offset is scaled. */ 3522 if (cp_num == 9) 3523 /* vldr.16/vstr.16 will shift the address 3524 left by 1 bit only. */ 3525 offset = offset * 2; 3526 else 3527 offset = offset * 4; 3528 3529 if (NEGATIVE_BIT_SET) 3530 offset = - offset; 3531 if (rn != 15) 3532 value_in_comment = offset; 3533 } 3534 3535 if (PRE_BIT_SET) 3536 { 3537 if (offset) 3538 func (stream, ", #%d]%s", 3539 (int) offset, 3540 WRITEBACK_BIT_SET ? "!" : ""); 3541 else if (NEGATIVE_BIT_SET) 3542 func (stream, ", #-0]"); 3543 else 3544 func (stream, "]"); 3545 } 3546 else 3547 { 3548 func (stream, "]"); 3549 3550 if (WRITEBACK_BIT_SET) 3551 { 3552 if (offset) 3553 func (stream, ", #%d", (int) offset); 3554 else if (NEGATIVE_BIT_SET) 3555 func (stream, ", #-0"); 3556 } 3557 else 3558 { 3559 func (stream, ", {%s%d}", 3560 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 3561 (int) offset); 3562 value_in_comment = offset; 3563 } 3564 } 3565 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 3566 { 3567 func (stream, "\t; "); 3568 /* For unaligned PCs, apply off-by-alignment 3569 correction. */ 3570 info->print_address_func (offset + pc 3571 + info->bytes_per_chunk * 2 3572 - (pc & 3), 3573 info); 3574 } 3575 } 3576 break; 3577 3578 case 'B': 3579 { 3580 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 3581 int offset = (given >> 1) & 0x3f; 3582 3583 if (offset == 1) 3584 func (stream, "{d%d}", regno); 3585 else if (regno + offset > 32) 3586 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 3587 else 3588 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 3589 } 3590 break; 3591 3592 case 'u': 3593 if (cond != COND_UNCOND) 3594 is_unpredictable = TRUE; 3595 3596 /* Fall through. */ 3597 case 'c': 3598 if (cond != COND_UNCOND && cp_num == 9) 3599 is_unpredictable = TRUE; 3600 3601 func (stream, "%s", arm_conditional[cond]); 3602 break; 3603 3604 case 'I': 3605 /* Print a Cirrus/DSP shift immediate. */ 3606 /* Immediates are 7bit signed ints with bits 0..3 in 3607 bits 0..3 of opcode and bits 4..6 in bits 5..7 3608 of opcode. */ 3609 { 3610 int imm; 3611 3612 imm = (given & 0xf) | ((given & 0xe0) >> 1); 3613 3614 /* Is ``imm'' a negative number? */ 3615 if (imm & 0x40) 3616 imm -= 0x80; 3617 3618 func (stream, "%d", imm); 3619 } 3620 3621 break; 3622 3623 case 'F': 3624 switch (given & 0x00408000) 3625 { 3626 case 0: 3627 func (stream, "4"); 3628 break; 3629 case 0x8000: 3630 func (stream, "1"); 3631 break; 3632 case 0x00400000: 3633 func (stream, "2"); 3634 break; 3635 default: 3636 func (stream, "3"); 3637 } 3638 break; 3639 3640 case 'P': 3641 switch (given & 0x00080080) 3642 { 3643 case 0: 3644 func (stream, "s"); 3645 break; 3646 case 0x80: 3647 func (stream, "d"); 3648 break; 3649 case 0x00080000: 3650 func (stream, "e"); 3651 break; 3652 default: 3653 func (stream, _("<illegal precision>")); 3654 break; 3655 } 3656 break; 3657 3658 case 'Q': 3659 switch (given & 0x00408000) 3660 { 3661 case 0: 3662 func (stream, "s"); 3663 break; 3664 case 0x8000: 3665 func (stream, "d"); 3666 break; 3667 case 0x00400000: 3668 func (stream, "e"); 3669 break; 3670 default: 3671 func (stream, "p"); 3672 break; 3673 } 3674 break; 3675 3676 case 'R': 3677 switch (given & 0x60) 3678 { 3679 case 0: 3680 break; 3681 case 0x20: 3682 func (stream, "p"); 3683 break; 3684 case 0x40: 3685 func (stream, "m"); 3686 break; 3687 default: 3688 func (stream, "z"); 3689 break; 3690 } 3691 break; 3692 3693 case '0': case '1': case '2': case '3': case '4': 3694 case '5': case '6': case '7': case '8': case '9': 3695 { 3696 int width; 3697 3698 c = arm_decode_bitfield (c, given, &value, &width); 3699 3700 switch (*c) 3701 { 3702 case 'R': 3703 if (value == 15) 3704 is_unpredictable = TRUE; 3705 /* Fall through. */ 3706 case 'r': 3707 if (c[1] == 'u') 3708 { 3709 /* Eat the 'u' character. */ 3710 ++ c; 3711 3712 if (u_reg == value) 3713 is_unpredictable = TRUE; 3714 u_reg = value; 3715 } 3716 func (stream, "%s", arm_regnames[value]); 3717 break; 3718 case 'V': 3719 if (given & (1 << 6)) 3720 goto Q; 3721 /* FALLTHROUGH */ 3722 case 'D': 3723 func (stream, "d%ld", value); 3724 break; 3725 case 'Q': 3726 Q: 3727 if (value & 1) 3728 func (stream, "<illegal reg q%ld.5>", value >> 1); 3729 else 3730 func (stream, "q%ld", value >> 1); 3731 break; 3732 case 'd': 3733 func (stream, "%ld", value); 3734 value_in_comment = value; 3735 break; 3736 case 'E': 3737 { 3738 /* Converts immediate 8 bit back to float value. */ 3739 unsigned floatVal = (value & 0x80) << 24 3740 | (value & 0x3F) << 19 3741 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 3742 3743 /* Quarter float have a maximum value of 31.0. 3744 Get floating point value multiplied by 1e7. 3745 The maximum value stays in limit of a 32-bit int. */ 3746 unsigned decVal = 3747 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 3748 (16 + (value & 0xF)); 3749 3750 if (!(decVal % 1000000)) 3751 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 3752 floatVal, value & 0x80 ? '-' : ' ', 3753 decVal / 10000000, 3754 decVal % 10000000 / 1000000); 3755 else if (!(decVal % 10000)) 3756 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 3757 floatVal, value & 0x80 ? '-' : ' ', 3758 decVal / 10000000, 3759 decVal % 10000000 / 10000); 3760 else 3761 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 3762 floatVal, value & 0x80 ? '-' : ' ', 3763 decVal / 10000000, decVal % 10000000); 3764 break; 3765 } 3766 case 'k': 3767 { 3768 int from = (given & (1 << 7)) ? 32 : 16; 3769 func (stream, "%ld", from - value); 3770 } 3771 break; 3772 3773 case 'f': 3774 if (value > 7) 3775 func (stream, "#%s", arm_fp_const[value & 7]); 3776 else 3777 func (stream, "f%ld", value); 3778 break; 3779 3780 case 'w': 3781 if (width == 2) 3782 func (stream, "%s", iwmmxt_wwnames[value]); 3783 else 3784 func (stream, "%s", iwmmxt_wwssnames[value]); 3785 break; 3786 3787 case 'g': 3788 func (stream, "%s", iwmmxt_regnames[value]); 3789 break; 3790 case 'G': 3791 func (stream, "%s", iwmmxt_cregnames[value]); 3792 break; 3793 3794 case 'x': 3795 func (stream, "0x%lx", (value & 0xffffffffUL)); 3796 break; 3797 3798 case 'c': 3799 switch (value) 3800 { 3801 case 0: 3802 func (stream, "eq"); 3803 break; 3804 3805 case 1: 3806 func (stream, "vs"); 3807 break; 3808 3809 case 2: 3810 func (stream, "ge"); 3811 break; 3812 3813 case 3: 3814 func (stream, "gt"); 3815 break; 3816 3817 default: 3818 func (stream, "??"); 3819 break; 3820 } 3821 break; 3822 3823 case '`': 3824 c++; 3825 if (value == 0) 3826 func (stream, "%c", *c); 3827 break; 3828 case '\'': 3829 c++; 3830 if (value == ((1ul << width) - 1)) 3831 func (stream, "%c", *c); 3832 break; 3833 case '?': 3834 func (stream, "%c", c[(1 << width) - (int) value]); 3835 c += 1 << width; 3836 break; 3837 default: 3838 abort (); 3839 } 3840 break; 3841 3842 case 'y': 3843 case 'z': 3844 { 3845 int single = *c++ == 'y'; 3846 int regno; 3847 3848 switch (*c) 3849 { 3850 case '4': /* Sm pair */ 3851 case '0': /* Sm, Dm */ 3852 regno = given & 0x0000000f; 3853 if (single) 3854 { 3855 regno <<= 1; 3856 regno += (given >> 5) & 1; 3857 } 3858 else 3859 regno += ((given >> 5) & 1) << 4; 3860 break; 3861 3862 case '1': /* Sd, Dd */ 3863 regno = (given >> 12) & 0x0000000f; 3864 if (single) 3865 { 3866 regno <<= 1; 3867 regno += (given >> 22) & 1; 3868 } 3869 else 3870 regno += ((given >> 22) & 1) << 4; 3871 break; 3872 3873 case '2': /* Sn, Dn */ 3874 regno = (given >> 16) & 0x0000000f; 3875 if (single) 3876 { 3877 regno <<= 1; 3878 regno += (given >> 7) & 1; 3879 } 3880 else 3881 regno += ((given >> 7) & 1) << 4; 3882 break; 3883 3884 case '3': /* List */ 3885 func (stream, "{"); 3886 regno = (given >> 12) & 0x0000000f; 3887 if (single) 3888 { 3889 regno <<= 1; 3890 regno += (given >> 22) & 1; 3891 } 3892 else 3893 regno += ((given >> 22) & 1) << 4; 3894 break; 3895 3896 default: 3897 abort (); 3898 } 3899 3900 func (stream, "%c%d", single ? 's' : 'd', regno); 3901 3902 if (*c == '3') 3903 { 3904 int count = given & 0xff; 3905 3906 if (single == 0) 3907 count >>= 1; 3908 3909 if (--count) 3910 { 3911 func (stream, "-%c%d", 3912 single ? 's' : 'd', 3913 regno + count); 3914 } 3915 3916 func (stream, "}"); 3917 } 3918 else if (*c == '4') 3919 func (stream, ", %c%d", single ? 's' : 'd', 3920 regno + 1); 3921 } 3922 break; 3923 3924 case 'L': 3925 switch (given & 0x00400100) 3926 { 3927 case 0x00000000: func (stream, "b"); break; 3928 case 0x00400000: func (stream, "h"); break; 3929 case 0x00000100: func (stream, "w"); break; 3930 case 0x00400100: func (stream, "d"); break; 3931 default: 3932 break; 3933 } 3934 break; 3935 3936 case 'Z': 3937 { 3938 /* given (20, 23) | given (0, 3) */ 3939 value = ((given >> 16) & 0xf0) | (given & 0xf); 3940 func (stream, "%d", (int) value); 3941 } 3942 break; 3943 3944 case 'l': 3945 /* This is like the 'A' operator, except that if 3946 the width field "M" is zero, then the offset is 3947 *not* multiplied by four. */ 3948 { 3949 int offset = given & 0xff; 3950 int multiplier = (given & 0x00000100) ? 4 : 1; 3951 3952 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3953 3954 if (multiplier > 1) 3955 { 3956 value_in_comment = offset * multiplier; 3957 if (NEGATIVE_BIT_SET) 3958 value_in_comment = - value_in_comment; 3959 } 3960 3961 if (offset) 3962 { 3963 if (PRE_BIT_SET) 3964 func (stream, ", #%s%d]%s", 3965 NEGATIVE_BIT_SET ? "-" : "", 3966 offset * multiplier, 3967 WRITEBACK_BIT_SET ? "!" : ""); 3968 else 3969 func (stream, "], #%s%d", 3970 NEGATIVE_BIT_SET ? "-" : "", 3971 offset * multiplier); 3972 } 3973 else 3974 func (stream, "]"); 3975 } 3976 break; 3977 3978 case 'r': 3979 { 3980 int imm4 = (given >> 4) & 0xf; 3981 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 3982 int ubit = ! NEGATIVE_BIT_SET; 3983 const char *rm = arm_regnames [given & 0xf]; 3984 const char *rn = arm_regnames [(given >> 16) & 0xf]; 3985 3986 switch (puw_bits) 3987 { 3988 case 1: 3989 case 3: 3990 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 3991 if (imm4) 3992 func (stream, ", lsl #%d", imm4); 3993 break; 3994 3995 case 4: 3996 case 5: 3997 case 6: 3998 case 7: 3999 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 4000 if (imm4 > 0) 4001 func (stream, ", lsl #%d", imm4); 4002 func (stream, "]"); 4003 if (puw_bits == 5 || puw_bits == 7) 4004 func (stream, "!"); 4005 break; 4006 4007 default: 4008 func (stream, "INVALID"); 4009 } 4010 } 4011 break; 4012 4013 case 'i': 4014 { 4015 long imm5; 4016 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 4017 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 4018 } 4019 break; 4020 4021 default: 4022 abort (); 4023 } 4024 } 4025 } 4026 else 4027 func (stream, "%c", *c); 4028 } 4029 4030 if (value_in_comment > 32 || value_in_comment < -16) 4031 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 4032 4033 if (is_unpredictable) 4034 func (stream, UNPREDICTABLE_INSTRUCTION); 4035 4036 return TRUE; 4037 } 4038 return FALSE; 4039 } 4040 4041 /* Decodes and prints ARM addressing modes. Returns the offset 4042 used in the address, if any, if it is worthwhile printing the 4043 offset as a hexadecimal value in a comment at the end of the 4044 line of disassembly. */ 4045 4046 static signed long 4047 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 4048 { 4049 void *stream = info->stream; 4050 fprintf_ftype func = info->fprintf_func; 4051 bfd_vma offset = 0; 4052 4053 if (((given & 0x000f0000) == 0x000f0000) 4054 && ((given & 0x02000000) == 0)) 4055 { 4056 offset = given & 0xfff; 4057 4058 func (stream, "[pc"); 4059 4060 if (PRE_BIT_SET) 4061 { 4062 /* Pre-indexed. Elide offset of positive zero when 4063 non-writeback. */ 4064 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4065 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4066 4067 if (NEGATIVE_BIT_SET) 4068 offset = -offset; 4069 4070 offset += pc + 8; 4071 4072 /* Cope with the possibility of write-back 4073 being used. Probably a very dangerous thing 4074 for the programmer to do, but who are we to 4075 argue ? */ 4076 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 4077 } 4078 else /* Post indexed. */ 4079 { 4080 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4081 4082 /* Ie ignore the offset. */ 4083 offset = pc + 8; 4084 } 4085 4086 func (stream, "\t; "); 4087 info->print_address_func (offset, info); 4088 offset = 0; 4089 } 4090 else 4091 { 4092 func (stream, "[%s", 4093 arm_regnames[(given >> 16) & 0xf]); 4094 4095 if (PRE_BIT_SET) 4096 { 4097 if ((given & 0x02000000) == 0) 4098 { 4099 /* Elide offset of positive zero when non-writeback. */ 4100 offset = given & 0xfff; 4101 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4102 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4103 } 4104 else 4105 { 4106 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 4107 arm_decode_shift (given, func, stream, TRUE); 4108 } 4109 4110 func (stream, "]%s", 4111 WRITEBACK_BIT_SET ? "!" : ""); 4112 } 4113 else 4114 { 4115 if ((given & 0x02000000) == 0) 4116 { 4117 /* Always show offset. */ 4118 offset = given & 0xfff; 4119 func (stream, "], #%s%d", 4120 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4121 } 4122 else 4123 { 4124 func (stream, "], %s", 4125 NEGATIVE_BIT_SET ? "-" : ""); 4126 arm_decode_shift (given, func, stream, TRUE); 4127 } 4128 } 4129 if (NEGATIVE_BIT_SET) 4130 offset = -offset; 4131 } 4132 4133 return (signed long) offset; 4134 } 4135 4136 /* Print one neon instruction on INFO->STREAM. 4137 Return TRUE if the instuction matched, FALSE if this is not a 4138 recognised neon instruction. */ 4139 4140 static bfd_boolean 4141 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 4142 { 4143 const struct opcode32 *insn; 4144 void *stream = info->stream; 4145 fprintf_ftype func = info->fprintf_func; 4146 4147 if (thumb) 4148 { 4149 if ((given & 0xef000000) == 0xef000000) 4150 { 4151 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 4152 unsigned long bit28 = given & (1 << 28); 4153 4154 given &= 0x00ffffff; 4155 if (bit28) 4156 given |= 0xf3000000; 4157 else 4158 given |= 0xf2000000; 4159 } 4160 else if ((given & 0xff000000) == 0xf9000000) 4161 given ^= 0xf9000000 ^ 0xf4000000; 4162 else 4163 return FALSE; 4164 } 4165 4166 for (insn = neon_opcodes; insn->assembler; insn++) 4167 { 4168 if ((given & insn->mask) == insn->value) 4169 { 4170 signed long value_in_comment = 0; 4171 bfd_boolean is_unpredictable = FALSE; 4172 const char *c; 4173 4174 for (c = insn->assembler; *c; c++) 4175 { 4176 if (*c == '%') 4177 { 4178 switch (*++c) 4179 { 4180 case '%': 4181 func (stream, "%%"); 4182 break; 4183 4184 case 'u': 4185 if (thumb && ifthen_state) 4186 is_unpredictable = TRUE; 4187 4188 /* Fall through. */ 4189 case 'c': 4190 if (thumb && ifthen_state) 4191 func (stream, "%s", arm_conditional[IFTHEN_COND]); 4192 break; 4193 4194 case 'A': 4195 { 4196 static const unsigned char enc[16] = 4197 { 4198 0x4, 0x14, /* st4 0,1 */ 4199 0x4, /* st1 2 */ 4200 0x4, /* st2 3 */ 4201 0x3, /* st3 4 */ 4202 0x13, /* st3 5 */ 4203 0x3, /* st1 6 */ 4204 0x1, /* st1 7 */ 4205 0x2, /* st2 8 */ 4206 0x12, /* st2 9 */ 4207 0x2, /* st1 10 */ 4208 0, 0, 0, 0, 0 4209 }; 4210 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4211 int rn = ((given >> 16) & 0xf); 4212 int rm = ((given >> 0) & 0xf); 4213 int align = ((given >> 4) & 0x3); 4214 int type = ((given >> 8) & 0xf); 4215 int n = enc[type] & 0xf; 4216 int stride = (enc[type] >> 4) + 1; 4217 int ix; 4218 4219 func (stream, "{"); 4220 if (stride > 1) 4221 for (ix = 0; ix != n; ix++) 4222 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 4223 else if (n == 1) 4224 func (stream, "d%d", rd); 4225 else 4226 func (stream, "d%d-d%d", rd, rd + n - 1); 4227 func (stream, "}, [%s", arm_regnames[rn]); 4228 if (align) 4229 func (stream, " :%d", 32 << align); 4230 func (stream, "]"); 4231 if (rm == 0xd) 4232 func (stream, "!"); 4233 else if (rm != 0xf) 4234 func (stream, ", %s", arm_regnames[rm]); 4235 } 4236 break; 4237 4238 case 'B': 4239 { 4240 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4241 int rn = ((given >> 16) & 0xf); 4242 int rm = ((given >> 0) & 0xf); 4243 int idx_align = ((given >> 4) & 0xf); 4244 int align = 0; 4245 int size = ((given >> 10) & 0x3); 4246 int idx = idx_align >> (size + 1); 4247 int length = ((given >> 8) & 3) + 1; 4248 int stride = 1; 4249 int i; 4250 4251 if (length > 1 && size > 0) 4252 stride = (idx_align & (1 << size)) ? 2 : 1; 4253 4254 switch (length) 4255 { 4256 case 1: 4257 { 4258 int amask = (1 << size) - 1; 4259 if ((idx_align & (1 << size)) != 0) 4260 return FALSE; 4261 if (size > 0) 4262 { 4263 if ((idx_align & amask) == amask) 4264 align = 8 << size; 4265 else if ((idx_align & amask) != 0) 4266 return FALSE; 4267 } 4268 } 4269 break; 4270 4271 case 2: 4272 if (size == 2 && (idx_align & 2) != 0) 4273 return FALSE; 4274 align = (idx_align & 1) ? 16 << size : 0; 4275 break; 4276 4277 case 3: 4278 if ((size == 2 && (idx_align & 3) != 0) 4279 || (idx_align & 1) != 0) 4280 return FALSE; 4281 break; 4282 4283 case 4: 4284 if (size == 2) 4285 { 4286 if ((idx_align & 3) == 3) 4287 return FALSE; 4288 align = (idx_align & 3) * 64; 4289 } 4290 else 4291 align = (idx_align & 1) ? 32 << size : 0; 4292 break; 4293 4294 default: 4295 abort (); 4296 } 4297 4298 func (stream, "{"); 4299 for (i = 0; i < length; i++) 4300 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 4301 rd + i * stride, idx); 4302 func (stream, "}, [%s", arm_regnames[rn]); 4303 if (align) 4304 func (stream, " :%d", align); 4305 func (stream, "]"); 4306 if (rm == 0xd) 4307 func (stream, "!"); 4308 else if (rm != 0xf) 4309 func (stream, ", %s", arm_regnames[rm]); 4310 } 4311 break; 4312 4313 case 'C': 4314 { 4315 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4316 int rn = ((given >> 16) & 0xf); 4317 int rm = ((given >> 0) & 0xf); 4318 int align = ((given >> 4) & 0x1); 4319 int size = ((given >> 6) & 0x3); 4320 int type = ((given >> 8) & 0x3); 4321 int n = type + 1; 4322 int stride = ((given >> 5) & 0x1); 4323 int ix; 4324 4325 if (stride && (n == 1)) 4326 n++; 4327 else 4328 stride++; 4329 4330 func (stream, "{"); 4331 if (stride > 1) 4332 for (ix = 0; ix != n; ix++) 4333 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 4334 else if (n == 1) 4335 func (stream, "d%d[]", rd); 4336 else 4337 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 4338 func (stream, "}, [%s", arm_regnames[rn]); 4339 if (align) 4340 { 4341 align = (8 * (type + 1)) << size; 4342 if (type == 3) 4343 align = (size > 1) ? align >> 1 : align; 4344 if (type == 2 || (type == 0 && !size)) 4345 func (stream, " :<bad align %d>", align); 4346 else 4347 func (stream, " :%d", align); 4348 } 4349 func (stream, "]"); 4350 if (rm == 0xd) 4351 func (stream, "!"); 4352 else if (rm != 0xf) 4353 func (stream, ", %s", arm_regnames[rm]); 4354 } 4355 break; 4356 4357 case 'D': 4358 { 4359 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 4360 int size = (given >> 20) & 3; 4361 int reg = raw_reg & ((4 << size) - 1); 4362 int ix = raw_reg >> size >> 2; 4363 4364 func (stream, "d%d[%d]", reg, ix); 4365 } 4366 break; 4367 4368 case 'E': 4369 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 4370 { 4371 int bits = 0; 4372 int cmode = (given >> 8) & 0xf; 4373 int op = (given >> 5) & 0x1; 4374 unsigned long value = 0, hival = 0; 4375 unsigned shift; 4376 int size = 0; 4377 int isfloat = 0; 4378 4379 bits |= ((given >> 24) & 1) << 7; 4380 bits |= ((given >> 16) & 7) << 4; 4381 bits |= ((given >> 0) & 15) << 0; 4382 4383 if (cmode < 8) 4384 { 4385 shift = (cmode >> 1) & 3; 4386 value = (unsigned long) bits << (8 * shift); 4387 size = 32; 4388 } 4389 else if (cmode < 12) 4390 { 4391 shift = (cmode >> 1) & 1; 4392 value = (unsigned long) bits << (8 * shift); 4393 size = 16; 4394 } 4395 else if (cmode < 14) 4396 { 4397 shift = (cmode & 1) + 1; 4398 value = (unsigned long) bits << (8 * shift); 4399 value |= (1ul << (8 * shift)) - 1; 4400 size = 32; 4401 } 4402 else if (cmode == 14) 4403 { 4404 if (op) 4405 { 4406 /* Bit replication into bytes. */ 4407 int ix; 4408 unsigned long mask; 4409 4410 value = 0; 4411 hival = 0; 4412 for (ix = 7; ix >= 0; ix--) 4413 { 4414 mask = ((bits >> ix) & 1) ? 0xff : 0; 4415 if (ix <= 3) 4416 value = (value << 8) | mask; 4417 else 4418 hival = (hival << 8) | mask; 4419 } 4420 size = 64; 4421 } 4422 else 4423 { 4424 /* Byte replication. */ 4425 value = (unsigned long) bits; 4426 size = 8; 4427 } 4428 } 4429 else if (!op) 4430 { 4431 /* Floating point encoding. */ 4432 int tmp; 4433 4434 value = (unsigned long) (bits & 0x7f) << 19; 4435 value |= (unsigned long) (bits & 0x80) << 24; 4436 tmp = bits & 0x40 ? 0x3c : 0x40; 4437 value |= (unsigned long) tmp << 24; 4438 size = 32; 4439 isfloat = 1; 4440 } 4441 else 4442 { 4443 func (stream, "<illegal constant %.8x:%x:%x>", 4444 bits, cmode, op); 4445 size = 32; 4446 break; 4447 } 4448 switch (size) 4449 { 4450 case 8: 4451 func (stream, "#%ld\t; 0x%.2lx", value, value); 4452 break; 4453 4454 case 16: 4455 func (stream, "#%ld\t; 0x%.4lx", value, value); 4456 break; 4457 4458 case 32: 4459 if (isfloat) 4460 { 4461 unsigned char valbytes[4]; 4462 double fvalue; 4463 4464 /* Do this a byte at a time so we don't have to 4465 worry about the host's endianness. */ 4466 valbytes[0] = value & 0xff; 4467 valbytes[1] = (value >> 8) & 0xff; 4468 valbytes[2] = (value >> 16) & 0xff; 4469 valbytes[3] = (value >> 24) & 0xff; 4470 4471 floatformat_to_double 4472 (& floatformat_ieee_single_little, valbytes, 4473 & fvalue); 4474 4475 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 4476 value); 4477 } 4478 else 4479 func (stream, "#%ld\t; 0x%.8lx", 4480 (long) (((value & 0x80000000L) != 0) 4481 ? value | ~0xffffffffL : value), 4482 value); 4483 break; 4484 4485 case 64: 4486 func (stream, "#0x%.8lx%.8lx", hival, value); 4487 break; 4488 4489 default: 4490 abort (); 4491 } 4492 } 4493 break; 4494 4495 case 'F': 4496 { 4497 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 4498 int num = (given >> 8) & 0x3; 4499 4500 if (!num) 4501 func (stream, "{d%d}", regno); 4502 else if (num + regno >= 32) 4503 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 4504 else 4505 func (stream, "{d%d-d%d}", regno, regno + num); 4506 } 4507 break; 4508 4509 4510 case '0': case '1': case '2': case '3': case '4': 4511 case '5': case '6': case '7': case '8': case '9': 4512 { 4513 int width; 4514 unsigned long value; 4515 4516 c = arm_decode_bitfield (c, given, &value, &width); 4517 4518 switch (*c) 4519 { 4520 case 'r': 4521 func (stream, "%s", arm_regnames[value]); 4522 break; 4523 case 'd': 4524 func (stream, "%ld", value); 4525 value_in_comment = value; 4526 break; 4527 case 'e': 4528 func (stream, "%ld", (1ul << width) - value); 4529 break; 4530 4531 case 'S': 4532 case 'T': 4533 case 'U': 4534 /* Various width encodings. */ 4535 { 4536 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 4537 int limit; 4538 unsigned low, high; 4539 4540 c++; 4541 if (*c >= '0' && *c <= '9') 4542 limit = *c - '0'; 4543 else if (*c >= 'a' && *c <= 'f') 4544 limit = *c - 'a' + 10; 4545 else 4546 abort (); 4547 low = limit >> 2; 4548 high = limit & 3; 4549 4550 if (value < low || value > high) 4551 func (stream, "<illegal width %d>", base << value); 4552 else 4553 func (stream, "%d", base << value); 4554 } 4555 break; 4556 case 'R': 4557 if (given & (1 << 6)) 4558 goto Q; 4559 /* FALLTHROUGH */ 4560 case 'D': 4561 func (stream, "d%ld", value); 4562 break; 4563 case 'Q': 4564 Q: 4565 if (value & 1) 4566 func (stream, "<illegal reg q%ld.5>", value >> 1); 4567 else 4568 func (stream, "q%ld", value >> 1); 4569 break; 4570 4571 case '`': 4572 c++; 4573 if (value == 0) 4574 func (stream, "%c", *c); 4575 break; 4576 case '\'': 4577 c++; 4578 if (value == ((1ul << width) - 1)) 4579 func (stream, "%c", *c); 4580 break; 4581 case '?': 4582 func (stream, "%c", c[(1 << width) - (int) value]); 4583 c += 1 << width; 4584 break; 4585 default: 4586 abort (); 4587 } 4588 break; 4589 4590 default: 4591 abort (); 4592 } 4593 } 4594 } 4595 else 4596 func (stream, "%c", *c); 4597 } 4598 4599 if (value_in_comment > 32 || value_in_comment < -16) 4600 func (stream, "\t; 0x%lx", value_in_comment); 4601 4602 if (is_unpredictable) 4603 func (stream, UNPREDICTABLE_INSTRUCTION); 4604 4605 return TRUE; 4606 } 4607 } 4608 return FALSE; 4609 } 4610 4611 /* Return the name of a v7A special register. */ 4612 4613 static const char * 4614 banked_regname (unsigned reg) 4615 { 4616 switch (reg) 4617 { 4618 case 15: return "CPSR"; 4619 case 32: return "R8_usr"; 4620 case 33: return "R9_usr"; 4621 case 34: return "R10_usr"; 4622 case 35: return "R11_usr"; 4623 case 36: return "R12_usr"; 4624 case 37: return "SP_usr"; 4625 case 38: return "LR_usr"; 4626 case 40: return "R8_fiq"; 4627 case 41: return "R9_fiq"; 4628 case 42: return "R10_fiq"; 4629 case 43: return "R11_fiq"; 4630 case 44: return "R12_fiq"; 4631 case 45: return "SP_fiq"; 4632 case 46: return "LR_fiq"; 4633 case 48: return "LR_irq"; 4634 case 49: return "SP_irq"; 4635 case 50: return "LR_svc"; 4636 case 51: return "SP_svc"; 4637 case 52: return "LR_abt"; 4638 case 53: return "SP_abt"; 4639 case 54: return "LR_und"; 4640 case 55: return "SP_und"; 4641 case 60: return "LR_mon"; 4642 case 61: return "SP_mon"; 4643 case 62: return "ELR_hyp"; 4644 case 63: return "SP_hyp"; 4645 case 79: return "SPSR"; 4646 case 110: return "SPSR_fiq"; 4647 case 112: return "SPSR_irq"; 4648 case 114: return "SPSR_svc"; 4649 case 116: return "SPSR_abt"; 4650 case 118: return "SPSR_und"; 4651 case 124: return "SPSR_mon"; 4652 case 126: return "SPSR_hyp"; 4653 default: return NULL; 4654 } 4655 } 4656 4657 /* Return the name of the DMB/DSB option. */ 4658 static const char * 4659 data_barrier_option (unsigned option) 4660 { 4661 switch (option & 0xf) 4662 { 4663 case 0xf: return "sy"; 4664 case 0xe: return "st"; 4665 case 0xd: return "ld"; 4666 case 0xb: return "ish"; 4667 case 0xa: return "ishst"; 4668 case 0x9: return "ishld"; 4669 case 0x7: return "un"; 4670 case 0x6: return "unst"; 4671 case 0x5: return "nshld"; 4672 case 0x3: return "osh"; 4673 case 0x2: return "oshst"; 4674 case 0x1: return "oshld"; 4675 default: return NULL; 4676 } 4677 } 4678 4679 /* Print one ARM instruction from PC on INFO->STREAM. */ 4680 4681 static void 4682 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 4683 { 4684 const struct opcode32 *insn; 4685 void *stream = info->stream; 4686 fprintf_ftype func = info->fprintf_func; 4687 struct arm_private_data *private_data = info->private_data; 4688 4689 if (print_insn_coprocessor (pc, info, given, FALSE)) 4690 return; 4691 4692 if (print_insn_neon (info, given, FALSE)) 4693 return; 4694 4695 for (insn = arm_opcodes; insn->assembler; insn++) 4696 { 4697 if ((given & insn->mask) != insn->value) 4698 continue; 4699 4700 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 4701 continue; 4702 4703 /* Special case: an instruction with all bits set in the condition field 4704 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 4705 or by the catchall at the end of the table. */ 4706 if ((given & 0xF0000000) != 0xF0000000 4707 || (insn->mask & 0xF0000000) == 0xF0000000 4708 || (insn->mask == 0 && insn->value == 0)) 4709 { 4710 unsigned long u_reg = 16; 4711 unsigned long U_reg = 16; 4712 bfd_boolean is_unpredictable = FALSE; 4713 signed long value_in_comment = 0; 4714 const char *c; 4715 4716 for (c = insn->assembler; *c; c++) 4717 { 4718 if (*c == '%') 4719 { 4720 bfd_boolean allow_unpredictable = FALSE; 4721 4722 switch (*++c) 4723 { 4724 case '%': 4725 func (stream, "%%"); 4726 break; 4727 4728 case 'a': 4729 value_in_comment = print_arm_address (pc, info, given); 4730 break; 4731 4732 case 'P': 4733 /* Set P address bit and use normal address 4734 printing routine. */ 4735 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 4736 break; 4737 4738 case 'S': 4739 allow_unpredictable = TRUE; 4740 /* Fall through. */ 4741 case 's': 4742 if ((given & 0x004f0000) == 0x004f0000) 4743 { 4744 /* PC relative with immediate offset. */ 4745 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 4746 4747 if (PRE_BIT_SET) 4748 { 4749 /* Elide positive zero offset. */ 4750 if (offset || NEGATIVE_BIT_SET) 4751 func (stream, "[pc, #%s%d]\t; ", 4752 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4753 else 4754 func (stream, "[pc]\t; "); 4755 if (NEGATIVE_BIT_SET) 4756 offset = -offset; 4757 info->print_address_func (offset + pc + 8, info); 4758 } 4759 else 4760 { 4761 /* Always show the offset. */ 4762 func (stream, "[pc], #%s%d", 4763 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4764 if (! allow_unpredictable) 4765 is_unpredictable = TRUE; 4766 } 4767 } 4768 else 4769 { 4770 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 4771 4772 func (stream, "[%s", 4773 arm_regnames[(given >> 16) & 0xf]); 4774 4775 if (PRE_BIT_SET) 4776 { 4777 if (IMMEDIATE_BIT_SET) 4778 { 4779 /* Elide offset for non-writeback 4780 positive zero. */ 4781 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 4782 || offset) 4783 func (stream, ", #%s%d", 4784 NEGATIVE_BIT_SET ? "-" : "", offset); 4785 4786 if (NEGATIVE_BIT_SET) 4787 offset = -offset; 4788 4789 value_in_comment = offset; 4790 } 4791 else 4792 { 4793 /* Register Offset or Register Pre-Indexed. */ 4794 func (stream, ", %s%s", 4795 NEGATIVE_BIT_SET ? "-" : "", 4796 arm_regnames[given & 0xf]); 4797 4798 /* Writing back to the register that is the source/ 4799 destination of the load/store is unpredictable. */ 4800 if (! allow_unpredictable 4801 && WRITEBACK_BIT_SET 4802 && ((given & 0xf) == ((given >> 12) & 0xf))) 4803 is_unpredictable = TRUE; 4804 } 4805 4806 func (stream, "]%s", 4807 WRITEBACK_BIT_SET ? "!" : ""); 4808 } 4809 else 4810 { 4811 if (IMMEDIATE_BIT_SET) 4812 { 4813 /* Immediate Post-indexed. */ 4814 /* PR 10924: Offset must be printed, even if it is zero. */ 4815 func (stream, "], #%s%d", 4816 NEGATIVE_BIT_SET ? "-" : "", offset); 4817 if (NEGATIVE_BIT_SET) 4818 offset = -offset; 4819 value_in_comment = offset; 4820 } 4821 else 4822 { 4823 /* Register Post-indexed. */ 4824 func (stream, "], %s%s", 4825 NEGATIVE_BIT_SET ? "-" : "", 4826 arm_regnames[given & 0xf]); 4827 4828 /* Writing back to the register that is the source/ 4829 destination of the load/store is unpredictable. */ 4830 if (! allow_unpredictable 4831 && (given & 0xf) == ((given >> 12) & 0xf)) 4832 is_unpredictable = TRUE; 4833 } 4834 4835 if (! allow_unpredictable) 4836 { 4837 /* Writeback is automatically implied by post- addressing. 4838 Setting the W bit is unnecessary and ARM specify it as 4839 being unpredictable. */ 4840 if (WRITEBACK_BIT_SET 4841 /* Specifying the PC register as the post-indexed 4842 registers is also unpredictable. */ 4843 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 4844 is_unpredictable = TRUE; 4845 } 4846 } 4847 } 4848 break; 4849 4850 case 'b': 4851 { 4852 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 4853 info->print_address_func (disp * 4 + pc + 8, info); 4854 } 4855 break; 4856 4857 case 'c': 4858 if (((given >> 28) & 0xf) != 0xe) 4859 func (stream, "%s", 4860 arm_conditional [(given >> 28) & 0xf]); 4861 break; 4862 4863 case 'm': 4864 { 4865 int started = 0; 4866 int reg; 4867 4868 func (stream, "{"); 4869 for (reg = 0; reg < 16; reg++) 4870 if ((given & (1 << reg)) != 0) 4871 { 4872 if (started) 4873 func (stream, ", "); 4874 started = 1; 4875 func (stream, "%s", arm_regnames[reg]); 4876 } 4877 func (stream, "}"); 4878 if (! started) 4879 is_unpredictable = TRUE; 4880 } 4881 break; 4882 4883 case 'q': 4884 arm_decode_shift (given, func, stream, FALSE); 4885 break; 4886 4887 case 'o': 4888 if ((given & 0x02000000) != 0) 4889 { 4890 unsigned int rotate = (given & 0xf00) >> 7; 4891 unsigned int immed = (given & 0xff); 4892 unsigned int a, i; 4893 4894 a = (((immed << (32 - rotate)) 4895 | (immed >> rotate)) & 0xffffffff); 4896 /* If there is another encoding with smaller rotate, 4897 the rotate should be specified directly. */ 4898 for (i = 0; i < 32; i += 2) 4899 if ((a << i | a >> (32 - i)) <= 0xff) 4900 break; 4901 4902 if (i != rotate) 4903 func (stream, "#%d, %d", immed, rotate); 4904 else 4905 func (stream, "#%d", a); 4906 value_in_comment = a; 4907 } 4908 else 4909 arm_decode_shift (given, func, stream, TRUE); 4910 break; 4911 4912 case 'p': 4913 if ((given & 0x0000f000) == 0x0000f000) 4914 { 4915 arm_feature_set arm_ext_v6 = 4916 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 4917 4918 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 4919 mechanism for setting PSR flag bits. They are 4920 obsolete in V6 onwards. */ 4921 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 4922 arm_ext_v6)) 4923 func (stream, "p"); 4924 else 4925 is_unpredictable = TRUE; 4926 } 4927 break; 4928 4929 case 't': 4930 if ((given & 0x01200000) == 0x00200000) 4931 func (stream, "t"); 4932 break; 4933 4934 case 'A': 4935 { 4936 int offset = given & 0xff; 4937 4938 value_in_comment = offset * 4; 4939 if (NEGATIVE_BIT_SET) 4940 value_in_comment = - value_in_comment; 4941 4942 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 4943 4944 if (PRE_BIT_SET) 4945 { 4946 if (offset) 4947 func (stream, ", #%d]%s", 4948 (int) value_in_comment, 4949 WRITEBACK_BIT_SET ? "!" : ""); 4950 else 4951 func (stream, "]"); 4952 } 4953 else 4954 { 4955 func (stream, "]"); 4956 4957 if (WRITEBACK_BIT_SET) 4958 { 4959 if (offset) 4960 func (stream, ", #%d", (int) value_in_comment); 4961 } 4962 else 4963 { 4964 func (stream, ", {%d}", (int) offset); 4965 value_in_comment = offset; 4966 } 4967 } 4968 } 4969 break; 4970 4971 case 'B': 4972 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 4973 { 4974 bfd_vma address; 4975 bfd_vma offset = 0; 4976 4977 if (! NEGATIVE_BIT_SET) 4978 /* Is signed, hi bits should be ones. */ 4979 offset = (-1) ^ 0x00ffffff; 4980 4981 /* Offset is (SignExtend(offset field)<<2). */ 4982 offset += given & 0x00ffffff; 4983 offset <<= 2; 4984 address = offset + pc + 8; 4985 4986 if (given & 0x01000000) 4987 /* H bit allows addressing to 2-byte boundaries. */ 4988 address += 2; 4989 4990 info->print_address_func (address, info); 4991 } 4992 break; 4993 4994 case 'C': 4995 if ((given & 0x02000200) == 0x200) 4996 { 4997 const char * name; 4998 unsigned sysm = (given & 0x004f0000) >> 16; 4999 5000 sysm |= (given & 0x300) >> 4; 5001 name = banked_regname (sysm); 5002 5003 if (name != NULL) 5004 func (stream, "%s", name); 5005 else 5006 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5007 } 5008 else 5009 { 5010 func (stream, "%cPSR_", 5011 (given & 0x00400000) ? 'S' : 'C'); 5012 if (given & 0x80000) 5013 func (stream, "f"); 5014 if (given & 0x40000) 5015 func (stream, "s"); 5016 if (given & 0x20000) 5017 func (stream, "x"); 5018 if (given & 0x10000) 5019 func (stream, "c"); 5020 } 5021 break; 5022 5023 case 'U': 5024 if ((given & 0xf0) == 0x60) 5025 { 5026 switch (given & 0xf) 5027 { 5028 case 0xf: func (stream, "sy"); break; 5029 default: 5030 func (stream, "#%d", (int) given & 0xf); 5031 break; 5032 } 5033 } 5034 else 5035 { 5036 const char * opt = data_barrier_option (given & 0xf); 5037 if (opt != NULL) 5038 func (stream, "%s", opt); 5039 else 5040 func (stream, "#%d", (int) given & 0xf); 5041 } 5042 break; 5043 5044 case '0': case '1': case '2': case '3': case '4': 5045 case '5': case '6': case '7': case '8': case '9': 5046 { 5047 int width; 5048 unsigned long value; 5049 5050 c = arm_decode_bitfield (c, given, &value, &width); 5051 5052 switch (*c) 5053 { 5054 case 'R': 5055 if (value == 15) 5056 is_unpredictable = TRUE; 5057 /* Fall through. */ 5058 case 'r': 5059 case 'T': 5060 /* We want register + 1 when decoding T. */ 5061 if (*c == 'T') 5062 ++value; 5063 5064 if (c[1] == 'u') 5065 { 5066 /* Eat the 'u' character. */ 5067 ++ c; 5068 5069 if (u_reg == value) 5070 is_unpredictable = TRUE; 5071 u_reg = value; 5072 } 5073 if (c[1] == 'U') 5074 { 5075 /* Eat the 'U' character. */ 5076 ++ c; 5077 5078 if (U_reg == value) 5079 is_unpredictable = TRUE; 5080 U_reg = value; 5081 } 5082 func (stream, "%s", arm_regnames[value]); 5083 break; 5084 case 'd': 5085 func (stream, "%ld", value); 5086 value_in_comment = value; 5087 break; 5088 case 'b': 5089 func (stream, "%ld", value * 8); 5090 value_in_comment = value * 8; 5091 break; 5092 case 'W': 5093 func (stream, "%ld", value + 1); 5094 value_in_comment = value + 1; 5095 break; 5096 case 'x': 5097 func (stream, "0x%08lx", value); 5098 5099 /* Some SWI instructions have special 5100 meanings. */ 5101 if ((given & 0x0fffffff) == 0x0FF00000) 5102 func (stream, "\t; IMB"); 5103 else if ((given & 0x0fffffff) == 0x0FF00001) 5104 func (stream, "\t; IMBRange"); 5105 break; 5106 case 'X': 5107 func (stream, "%01lx", value & 0xf); 5108 value_in_comment = value; 5109 break; 5110 case '`': 5111 c++; 5112 if (value == 0) 5113 func (stream, "%c", *c); 5114 break; 5115 case '\'': 5116 c++; 5117 if (value == ((1ul << width) - 1)) 5118 func (stream, "%c", *c); 5119 break; 5120 case '?': 5121 func (stream, "%c", c[(1 << width) - (int) value]); 5122 c += 1 << width; 5123 break; 5124 default: 5125 abort (); 5126 } 5127 break; 5128 5129 case 'e': 5130 { 5131 int imm; 5132 5133 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 5134 func (stream, "%d", imm); 5135 value_in_comment = imm; 5136 } 5137 break; 5138 5139 case 'E': 5140 /* LSB and WIDTH fields of BFI or BFC. The machine- 5141 language instruction encodes LSB and MSB. */ 5142 { 5143 long msb = (given & 0x001f0000) >> 16; 5144 long lsb = (given & 0x00000f80) >> 7; 5145 long w = msb - lsb + 1; 5146 5147 if (w > 0) 5148 func (stream, "#%lu, #%lu", lsb, w); 5149 else 5150 func (stream, "(invalid: %lu:%lu)", lsb, msb); 5151 } 5152 break; 5153 5154 case 'R': 5155 /* Get the PSR/banked register name. */ 5156 { 5157 const char * name; 5158 unsigned sysm = (given & 0x004f0000) >> 16; 5159 5160 sysm |= (given & 0x300) >> 4; 5161 name = banked_regname (sysm); 5162 5163 if (name != NULL) 5164 func (stream, "%s", name); 5165 else 5166 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5167 } 5168 break; 5169 5170 case 'V': 5171 /* 16-bit unsigned immediate from a MOVT or MOVW 5172 instruction, encoded in bits 0:11 and 15:19. */ 5173 { 5174 long hi = (given & 0x000f0000) >> 4; 5175 long lo = (given & 0x00000fff); 5176 long imm16 = hi | lo; 5177 5178 func (stream, "#%lu", imm16); 5179 value_in_comment = imm16; 5180 } 5181 break; 5182 5183 default: 5184 abort (); 5185 } 5186 } 5187 } 5188 else 5189 func (stream, "%c", *c); 5190 } 5191 5192 if (value_in_comment > 32 || value_in_comment < -16) 5193 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 5194 5195 if (is_unpredictable) 5196 func (stream, UNPREDICTABLE_INSTRUCTION); 5197 5198 return; 5199 } 5200 } 5201 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 5202 return; 5203 } 5204 5205 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 5206 5207 static void 5208 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 5209 { 5210 const struct opcode16 *insn; 5211 void *stream = info->stream; 5212 fprintf_ftype func = info->fprintf_func; 5213 5214 for (insn = thumb_opcodes; insn->assembler; insn++) 5215 if ((given & insn->mask) == insn->value) 5216 { 5217 signed long value_in_comment = 0; 5218 const char *c = insn->assembler; 5219 5220 for (; *c; c++) 5221 { 5222 int domaskpc = 0; 5223 int domasklr = 0; 5224 5225 if (*c != '%') 5226 { 5227 func (stream, "%c", *c); 5228 continue; 5229 } 5230 5231 switch (*++c) 5232 { 5233 case '%': 5234 func (stream, "%%"); 5235 break; 5236 5237 case 'c': 5238 if (ifthen_state) 5239 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5240 break; 5241 5242 case 'C': 5243 if (ifthen_state) 5244 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5245 else 5246 func (stream, "s"); 5247 break; 5248 5249 case 'I': 5250 { 5251 unsigned int tmp; 5252 5253 ifthen_next_state = given & 0xff; 5254 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 5255 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 5256 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 5257 } 5258 break; 5259 5260 case 'x': 5261 if (ifthen_next_state) 5262 func (stream, "\t; unpredictable branch in IT block\n"); 5263 break; 5264 5265 case 'X': 5266 if (ifthen_state) 5267 func (stream, "\t; unpredictable <IT:%s>", 5268 arm_conditional[IFTHEN_COND]); 5269 break; 5270 5271 case 'S': 5272 { 5273 long reg; 5274 5275 reg = (given >> 3) & 0x7; 5276 if (given & (1 << 6)) 5277 reg += 8; 5278 5279 func (stream, "%s", arm_regnames[reg]); 5280 } 5281 break; 5282 5283 case 'D': 5284 { 5285 long reg; 5286 5287 reg = given & 0x7; 5288 if (given & (1 << 7)) 5289 reg += 8; 5290 5291 func (stream, "%s", arm_regnames[reg]); 5292 } 5293 break; 5294 5295 case 'N': 5296 if (given & (1 << 8)) 5297 domasklr = 1; 5298 /* Fall through. */ 5299 case 'O': 5300 if (*c == 'O' && (given & (1 << 8))) 5301 domaskpc = 1; 5302 /* Fall through. */ 5303 case 'M': 5304 { 5305 int started = 0; 5306 int reg; 5307 5308 func (stream, "{"); 5309 5310 /* It would be nice if we could spot 5311 ranges, and generate the rS-rE format: */ 5312 for (reg = 0; (reg < 8); reg++) 5313 if ((given & (1 << reg)) != 0) 5314 { 5315 if (started) 5316 func (stream, ", "); 5317 started = 1; 5318 func (stream, "%s", arm_regnames[reg]); 5319 } 5320 5321 if (domasklr) 5322 { 5323 if (started) 5324 func (stream, ", "); 5325 started = 1; 5326 func (stream, "%s", arm_regnames[14] /* "lr" */); 5327 } 5328 5329 if (domaskpc) 5330 { 5331 if (started) 5332 func (stream, ", "); 5333 func (stream, "%s", arm_regnames[15] /* "pc" */); 5334 } 5335 5336 func (stream, "}"); 5337 } 5338 break; 5339 5340 case 'W': 5341 /* Print writeback indicator for a LDMIA. We are doing a 5342 writeback if the base register is not in the register 5343 mask. */ 5344 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 5345 func (stream, "!"); 5346 break; 5347 5348 case 'b': 5349 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 5350 { 5351 bfd_vma address = (pc + 4 5352 + ((given & 0x00f8) >> 2) 5353 + ((given & 0x0200) >> 3)); 5354 info->print_address_func (address, info); 5355 } 5356 break; 5357 5358 case 's': 5359 /* Right shift immediate -- bits 6..10; 1-31 print 5360 as themselves, 0 prints as 32. */ 5361 { 5362 long imm = (given & 0x07c0) >> 6; 5363 if (imm == 0) 5364 imm = 32; 5365 func (stream, "#%ld", imm); 5366 } 5367 break; 5368 5369 case '0': case '1': case '2': case '3': case '4': 5370 case '5': case '6': case '7': case '8': case '9': 5371 { 5372 int bitstart = *c++ - '0'; 5373 int bitend = 0; 5374 5375 while (*c >= '0' && *c <= '9') 5376 bitstart = (bitstart * 10) + *c++ - '0'; 5377 5378 switch (*c) 5379 { 5380 case '-': 5381 { 5382 bfd_vma reg; 5383 5384 c++; 5385 while (*c >= '0' && *c <= '9') 5386 bitend = (bitend * 10) + *c++ - '0'; 5387 if (!bitend) 5388 abort (); 5389 reg = given >> bitstart; 5390 reg &= (2 << (bitend - bitstart)) - 1; 5391 5392 switch (*c) 5393 { 5394 case 'r': 5395 func (stream, "%s", arm_regnames[reg]); 5396 break; 5397 5398 case 'd': 5399 func (stream, "%ld", (long) reg); 5400 value_in_comment = reg; 5401 break; 5402 5403 case 'H': 5404 func (stream, "%ld", (long) (reg << 1)); 5405 value_in_comment = reg << 1; 5406 break; 5407 5408 case 'W': 5409 func (stream, "%ld", (long) (reg << 2)); 5410 value_in_comment = reg << 2; 5411 break; 5412 5413 case 'a': 5414 /* PC-relative address -- the bottom two 5415 bits of the address are dropped 5416 before the calculation. */ 5417 info->print_address_func 5418 (((pc + 4) & ~3) + (reg << 2), info); 5419 value_in_comment = 0; 5420 break; 5421 5422 case 'x': 5423 func (stream, "0x%04lx", (long) reg); 5424 break; 5425 5426 case 'B': 5427 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 5428 info->print_address_func (reg * 2 + pc + 4, info); 5429 value_in_comment = 0; 5430 break; 5431 5432 case 'c': 5433 func (stream, "%s", arm_conditional [reg]); 5434 break; 5435 5436 default: 5437 abort (); 5438 } 5439 } 5440 break; 5441 5442 case '\'': 5443 c++; 5444 if ((given & (1 << bitstart)) != 0) 5445 func (stream, "%c", *c); 5446 break; 5447 5448 case '?': 5449 ++c; 5450 if ((given & (1 << bitstart)) != 0) 5451 func (stream, "%c", *c++); 5452 else 5453 func (stream, "%c", *++c); 5454 break; 5455 5456 default: 5457 abort (); 5458 } 5459 } 5460 break; 5461 5462 default: 5463 abort (); 5464 } 5465 } 5466 5467 if (value_in_comment > 32 || value_in_comment < -16) 5468 func (stream, "\t; 0x%lx", value_in_comment); 5469 return; 5470 } 5471 5472 /* No match. */ 5473 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given); 5474 return; 5475 } 5476 5477 /* Return the name of an V7M special register. */ 5478 5479 static const char * 5480 psr_name (int regno) 5481 { 5482 switch (regno) 5483 { 5484 case 0x0: return "APSR"; 5485 case 0x1: return "IAPSR"; 5486 case 0x2: return "EAPSR"; 5487 case 0x3: return "PSR"; 5488 case 0x5: return "IPSR"; 5489 case 0x6: return "EPSR"; 5490 case 0x7: return "IEPSR"; 5491 case 0x8: return "MSP"; 5492 case 0x9: return "PSP"; 5493 case 0xa: return "MSPLIM"; 5494 case 0xb: return "PSPLIM"; 5495 case 0x10: return "PRIMASK"; 5496 case 0x11: return "BASEPRI"; 5497 case 0x12: return "BASEPRI_MAX"; 5498 case 0x13: return "FAULTMASK"; 5499 case 0x14: return "CONTROL"; 5500 case 0x88: return "MSP_NS"; 5501 case 0x89: return "PSP_NS"; 5502 case 0x8a: return "MSPLIM_NS"; 5503 case 0x8b: return "PSPLIM_NS"; 5504 case 0x90: return "PRIMASK_NS"; 5505 case 0x91: return "BASEPRI_NS"; 5506 case 0x93: return "FAULTMASK_NS"; 5507 case 0x94: return "CONTROL_NS"; 5508 case 0x98: return "SP_NS"; 5509 default: return "<unknown>"; 5510 } 5511 } 5512 5513 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 5514 5515 static void 5516 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 5517 { 5518 const struct opcode32 *insn; 5519 void *stream = info->stream; 5520 fprintf_ftype func = info->fprintf_func; 5521 5522 if (print_insn_coprocessor (pc, info, given, TRUE)) 5523 return; 5524 5525 if (print_insn_neon (info, given, TRUE)) 5526 return; 5527 5528 for (insn = thumb32_opcodes; insn->assembler; insn++) 5529 if ((given & insn->mask) == insn->value) 5530 { 5531 bfd_boolean is_unpredictable = FALSE; 5532 signed long value_in_comment = 0; 5533 const char *c = insn->assembler; 5534 5535 for (; *c; c++) 5536 { 5537 if (*c != '%') 5538 { 5539 func (stream, "%c", *c); 5540 continue; 5541 } 5542 5543 switch (*++c) 5544 { 5545 case '%': 5546 func (stream, "%%"); 5547 break; 5548 5549 case 'c': 5550 if (ifthen_state) 5551 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5552 break; 5553 5554 case 'x': 5555 if (ifthen_next_state) 5556 func (stream, "\t; unpredictable branch in IT block\n"); 5557 break; 5558 5559 case 'X': 5560 if (ifthen_state) 5561 func (stream, "\t; unpredictable <IT:%s>", 5562 arm_conditional[IFTHEN_COND]); 5563 break; 5564 5565 case 'I': 5566 { 5567 unsigned int imm12 = 0; 5568 5569 imm12 |= (given & 0x000000ffu); 5570 imm12 |= (given & 0x00007000u) >> 4; 5571 imm12 |= (given & 0x04000000u) >> 15; 5572 func (stream, "#%u", imm12); 5573 value_in_comment = imm12; 5574 } 5575 break; 5576 5577 case 'M': 5578 { 5579 unsigned int bits = 0, imm, imm8, mod; 5580 5581 bits |= (given & 0x000000ffu); 5582 bits |= (given & 0x00007000u) >> 4; 5583 bits |= (given & 0x04000000u) >> 15; 5584 imm8 = (bits & 0x0ff); 5585 mod = (bits & 0xf00) >> 8; 5586 switch (mod) 5587 { 5588 case 0: imm = imm8; break; 5589 case 1: imm = ((imm8 << 16) | imm8); break; 5590 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 5591 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 5592 default: 5593 mod = (bits & 0xf80) >> 7; 5594 imm8 = (bits & 0x07f) | 0x80; 5595 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 5596 } 5597 func (stream, "#%u", imm); 5598 value_in_comment = imm; 5599 } 5600 break; 5601 5602 case 'J': 5603 { 5604 unsigned int imm = 0; 5605 5606 imm |= (given & 0x000000ffu); 5607 imm |= (given & 0x00007000u) >> 4; 5608 imm |= (given & 0x04000000u) >> 15; 5609 imm |= (given & 0x000f0000u) >> 4; 5610 func (stream, "#%u", imm); 5611 value_in_comment = imm; 5612 } 5613 break; 5614 5615 case 'K': 5616 { 5617 unsigned int imm = 0; 5618 5619 imm |= (given & 0x000f0000u) >> 16; 5620 imm |= (given & 0x00000ff0u) >> 0; 5621 imm |= (given & 0x0000000fu) << 12; 5622 func (stream, "#%u", imm); 5623 value_in_comment = imm; 5624 } 5625 break; 5626 5627 case 'H': 5628 { 5629 unsigned int imm = 0; 5630 5631 imm |= (given & 0x000f0000u) >> 4; 5632 imm |= (given & 0x00000fffu) >> 0; 5633 func (stream, "#%u", imm); 5634 value_in_comment = imm; 5635 } 5636 break; 5637 5638 case 'V': 5639 { 5640 unsigned int imm = 0; 5641 5642 imm |= (given & 0x00000fffu); 5643 imm |= (given & 0x000f0000u) >> 4; 5644 func (stream, "#%u", imm); 5645 value_in_comment = imm; 5646 } 5647 break; 5648 5649 case 'S': 5650 { 5651 unsigned int reg = (given & 0x0000000fu); 5652 unsigned int stp = (given & 0x00000030u) >> 4; 5653 unsigned int imm = 0; 5654 imm |= (given & 0x000000c0u) >> 6; 5655 imm |= (given & 0x00007000u) >> 10; 5656 5657 func (stream, "%s", arm_regnames[reg]); 5658 switch (stp) 5659 { 5660 case 0: 5661 if (imm > 0) 5662 func (stream, ", lsl #%u", imm); 5663 break; 5664 5665 case 1: 5666 if (imm == 0) 5667 imm = 32; 5668 func (stream, ", lsr #%u", imm); 5669 break; 5670 5671 case 2: 5672 if (imm == 0) 5673 imm = 32; 5674 func (stream, ", asr #%u", imm); 5675 break; 5676 5677 case 3: 5678 if (imm == 0) 5679 func (stream, ", rrx"); 5680 else 5681 func (stream, ", ror #%u", imm); 5682 } 5683 } 5684 break; 5685 5686 case 'a': 5687 { 5688 unsigned int Rn = (given & 0x000f0000) >> 16; 5689 unsigned int U = ! NEGATIVE_BIT_SET; 5690 unsigned int op = (given & 0x00000f00) >> 8; 5691 unsigned int i12 = (given & 0x00000fff); 5692 unsigned int i8 = (given & 0x000000ff); 5693 bfd_boolean writeback = FALSE, postind = FALSE; 5694 bfd_vma offset = 0; 5695 5696 func (stream, "[%s", arm_regnames[Rn]); 5697 if (U) /* 12-bit positive immediate offset. */ 5698 { 5699 offset = i12; 5700 if (Rn != 15) 5701 value_in_comment = offset; 5702 } 5703 else if (Rn == 15) /* 12-bit negative immediate offset. */ 5704 offset = - (int) i12; 5705 else if (op == 0x0) /* Shifted register offset. */ 5706 { 5707 unsigned int Rm = (i8 & 0x0f); 5708 unsigned int sh = (i8 & 0x30) >> 4; 5709 5710 func (stream, ", %s", arm_regnames[Rm]); 5711 if (sh) 5712 func (stream, ", lsl #%u", sh); 5713 func (stream, "]"); 5714 break; 5715 } 5716 else switch (op) 5717 { 5718 case 0xE: /* 8-bit positive immediate offset. */ 5719 offset = i8; 5720 break; 5721 5722 case 0xC: /* 8-bit negative immediate offset. */ 5723 offset = -i8; 5724 break; 5725 5726 case 0xF: /* 8-bit + preindex with wb. */ 5727 offset = i8; 5728 writeback = TRUE; 5729 break; 5730 5731 case 0xD: /* 8-bit - preindex with wb. */ 5732 offset = -i8; 5733 writeback = TRUE; 5734 break; 5735 5736 case 0xB: /* 8-bit + postindex. */ 5737 offset = i8; 5738 postind = TRUE; 5739 break; 5740 5741 case 0x9: /* 8-bit - postindex. */ 5742 offset = -i8; 5743 postind = TRUE; 5744 break; 5745 5746 default: 5747 func (stream, ", <undefined>]"); 5748 goto skip; 5749 } 5750 5751 if (postind) 5752 func (stream, "], #%d", (int) offset); 5753 else 5754 { 5755 if (offset) 5756 func (stream, ", #%d", (int) offset); 5757 func (stream, writeback ? "]!" : "]"); 5758 } 5759 5760 if (Rn == 15) 5761 { 5762 func (stream, "\t; "); 5763 info->print_address_func (((pc + 4) & ~3) + offset, info); 5764 } 5765 } 5766 skip: 5767 break; 5768 5769 case 'A': 5770 { 5771 unsigned int U = ! NEGATIVE_BIT_SET; 5772 unsigned int W = WRITEBACK_BIT_SET; 5773 unsigned int Rn = (given & 0x000f0000) >> 16; 5774 unsigned int off = (given & 0x000000ff); 5775 5776 func (stream, "[%s", arm_regnames[Rn]); 5777 5778 if (PRE_BIT_SET) 5779 { 5780 if (off || !U) 5781 { 5782 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 5783 value_in_comment = off * 4 * (U ? 1 : -1); 5784 } 5785 func (stream, "]"); 5786 if (W) 5787 func (stream, "!"); 5788 } 5789 else 5790 { 5791 func (stream, "], "); 5792 if (W) 5793 { 5794 func (stream, "#%c%u", U ? '+' : '-', off * 4); 5795 value_in_comment = off * 4 * (U ? 1 : -1); 5796 } 5797 else 5798 { 5799 func (stream, "{%u}", off); 5800 value_in_comment = off; 5801 } 5802 } 5803 } 5804 break; 5805 5806 case 'w': 5807 { 5808 unsigned int Sbit = (given & 0x01000000) >> 24; 5809 unsigned int type = (given & 0x00600000) >> 21; 5810 5811 switch (type) 5812 { 5813 case 0: func (stream, Sbit ? "sb" : "b"); break; 5814 case 1: func (stream, Sbit ? "sh" : "h"); break; 5815 case 2: 5816 if (Sbit) 5817 func (stream, "??"); 5818 break; 5819 case 3: 5820 func (stream, "??"); 5821 break; 5822 } 5823 } 5824 break; 5825 5826 case 'm': 5827 { 5828 int started = 0; 5829 int reg; 5830 5831 func (stream, "{"); 5832 for (reg = 0; reg < 16; reg++) 5833 if ((given & (1 << reg)) != 0) 5834 { 5835 if (started) 5836 func (stream, ", "); 5837 started = 1; 5838 func (stream, "%s", arm_regnames[reg]); 5839 } 5840 func (stream, "}"); 5841 } 5842 break; 5843 5844 case 'E': 5845 { 5846 unsigned int msb = (given & 0x0000001f); 5847 unsigned int lsb = 0; 5848 5849 lsb |= (given & 0x000000c0u) >> 6; 5850 lsb |= (given & 0x00007000u) >> 10; 5851 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 5852 } 5853 break; 5854 5855 case 'F': 5856 { 5857 unsigned int width = (given & 0x0000001f) + 1; 5858 unsigned int lsb = 0; 5859 5860 lsb |= (given & 0x000000c0u) >> 6; 5861 lsb |= (given & 0x00007000u) >> 10; 5862 func (stream, "#%u, #%u", lsb, width); 5863 } 5864 break; 5865 5866 case 'b': 5867 { 5868 unsigned int S = (given & 0x04000000u) >> 26; 5869 unsigned int J1 = (given & 0x00002000u) >> 13; 5870 unsigned int J2 = (given & 0x00000800u) >> 11; 5871 bfd_vma offset = 0; 5872 5873 offset |= !S << 20; 5874 offset |= J2 << 19; 5875 offset |= J1 << 18; 5876 offset |= (given & 0x003f0000) >> 4; 5877 offset |= (given & 0x000007ff) << 1; 5878 offset -= (1 << 20); 5879 5880 info->print_address_func (pc + 4 + offset, info); 5881 } 5882 break; 5883 5884 case 'B': 5885 { 5886 unsigned int S = (given & 0x04000000u) >> 26; 5887 unsigned int I1 = (given & 0x00002000u) >> 13; 5888 unsigned int I2 = (given & 0x00000800u) >> 11; 5889 bfd_vma offset = 0; 5890 5891 offset |= !S << 24; 5892 offset |= !(I1 ^ S) << 23; 5893 offset |= !(I2 ^ S) << 22; 5894 offset |= (given & 0x03ff0000u) >> 4; 5895 offset |= (given & 0x000007ffu) << 1; 5896 offset -= (1 << 24); 5897 offset += pc + 4; 5898 5899 /* BLX target addresses are always word aligned. */ 5900 if ((given & 0x00001000u) == 0) 5901 offset &= ~2u; 5902 5903 info->print_address_func (offset, info); 5904 } 5905 break; 5906 5907 case 's': 5908 { 5909 unsigned int shift = 0; 5910 5911 shift |= (given & 0x000000c0u) >> 6; 5912 shift |= (given & 0x00007000u) >> 10; 5913 if (WRITEBACK_BIT_SET) 5914 func (stream, ", asr #%u", shift); 5915 else if (shift) 5916 func (stream, ", lsl #%u", shift); 5917 /* else print nothing - lsl #0 */ 5918 } 5919 break; 5920 5921 case 'R': 5922 { 5923 unsigned int rot = (given & 0x00000030) >> 4; 5924 5925 if (rot) 5926 func (stream, ", ror #%u", rot * 8); 5927 } 5928 break; 5929 5930 case 'U': 5931 if ((given & 0xf0) == 0x60) 5932 { 5933 switch (given & 0xf) 5934 { 5935 case 0xf: func (stream, "sy"); break; 5936 default: 5937 func (stream, "#%d", (int) given & 0xf); 5938 break; 5939 } 5940 } 5941 else 5942 { 5943 const char * opt = data_barrier_option (given & 0xf); 5944 if (opt != NULL) 5945 func (stream, "%s", opt); 5946 else 5947 func (stream, "#%d", (int) given & 0xf); 5948 } 5949 break; 5950 5951 case 'C': 5952 if ((given & 0xff) == 0) 5953 { 5954 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 5955 if (given & 0x800) 5956 func (stream, "f"); 5957 if (given & 0x400) 5958 func (stream, "s"); 5959 if (given & 0x200) 5960 func (stream, "x"); 5961 if (given & 0x100) 5962 func (stream, "c"); 5963 } 5964 else if ((given & 0x20) == 0x20) 5965 { 5966 char const* name; 5967 unsigned sysm = (given & 0xf00) >> 8; 5968 5969 sysm |= (given & 0x30); 5970 sysm |= (given & 0x00100000) >> 14; 5971 name = banked_regname (sysm); 5972 5973 if (name != NULL) 5974 func (stream, "%s", name); 5975 else 5976 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5977 } 5978 else 5979 { 5980 func (stream, "%s", psr_name (given & 0xff)); 5981 } 5982 break; 5983 5984 case 'D': 5985 if (((given & 0xff) == 0) 5986 || ((given & 0x20) == 0x20)) 5987 { 5988 char const* name; 5989 unsigned sm = (given & 0xf0000) >> 16; 5990 5991 sm |= (given & 0x30); 5992 sm |= (given & 0x00100000) >> 14; 5993 name = banked_regname (sm); 5994 5995 if (name != NULL) 5996 func (stream, "%s", name); 5997 else 5998 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 5999 } 6000 else 6001 func (stream, "%s", psr_name (given & 0xff)); 6002 break; 6003 6004 case '0': case '1': case '2': case '3': case '4': 6005 case '5': case '6': case '7': case '8': case '9': 6006 { 6007 int width; 6008 unsigned long val; 6009 6010 c = arm_decode_bitfield (c, given, &val, &width); 6011 6012 switch (*c) 6013 { 6014 case 'd': 6015 func (stream, "%lu", val); 6016 value_in_comment = val; 6017 break; 6018 6019 case 'D': 6020 func (stream, "%lu", val + 1); 6021 value_in_comment = val + 1; 6022 break; 6023 6024 case 'W': 6025 func (stream, "%lu", val * 4); 6026 value_in_comment = val * 4; 6027 break; 6028 6029 case 'R': 6030 if (val == 15) 6031 is_unpredictable = TRUE; 6032 /* Fall through. */ 6033 case 'r': 6034 func (stream, "%s", arm_regnames[val]); 6035 break; 6036 6037 case 'c': 6038 func (stream, "%s", arm_conditional[val]); 6039 break; 6040 6041 case '\'': 6042 c++; 6043 if (val == ((1ul << width) - 1)) 6044 func (stream, "%c", *c); 6045 break; 6046 6047 case '`': 6048 c++; 6049 if (val == 0) 6050 func (stream, "%c", *c); 6051 break; 6052 6053 case '?': 6054 func (stream, "%c", c[(1 << width) - (int) val]); 6055 c += 1 << width; 6056 break; 6057 6058 case 'x': 6059 func (stream, "0x%lx", val & 0xffffffffUL); 6060 break; 6061 6062 default: 6063 abort (); 6064 } 6065 } 6066 break; 6067 6068 case 'L': 6069 /* PR binutils/12534 6070 If we have a PC relative offset in an LDRD or STRD 6071 instructions then display the decoded address. */ 6072 if (((given >> 16) & 0xf) == 0xf) 6073 { 6074 bfd_vma offset = (given & 0xff) * 4; 6075 6076 if ((given & (1 << 23)) == 0) 6077 offset = - offset; 6078 func (stream, "\t; "); 6079 info->print_address_func ((pc & ~3) + 4 + offset, info); 6080 } 6081 break; 6082 6083 default: 6084 abort (); 6085 } 6086 } 6087 6088 if (value_in_comment > 32 || value_in_comment < -16) 6089 func (stream, "\t; 0x%lx", value_in_comment); 6090 6091 if (is_unpredictable) 6092 func (stream, UNPREDICTABLE_INSTRUCTION); 6093 6094 return; 6095 } 6096 6097 /* No match. */ 6098 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 6099 return; 6100 } 6101 6102 /* Print data bytes on INFO->STREAM. */ 6103 6104 static void 6105 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 6106 struct disassemble_info *info, 6107 long given) 6108 { 6109 switch (info->bytes_per_chunk) 6110 { 6111 case 1: 6112 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 6113 break; 6114 case 2: 6115 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 6116 break; 6117 case 4: 6118 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 6119 break; 6120 default: 6121 abort (); 6122 } 6123 } 6124 6125 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 6126 being displayed in symbol relative addresses. 6127 6128 Also disallow private symbol, with __tagsym$$ prefix, 6129 from ARM RVCT toolchain being displayed. */ 6130 6131 bfd_boolean 6132 arm_symbol_is_valid (asymbol * sym, 6133 struct disassemble_info * info ATTRIBUTE_UNUSED) 6134 { 6135 const char * name; 6136 6137 if (sym == NULL) 6138 return FALSE; 6139 6140 name = bfd_asymbol_name (sym); 6141 6142 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 6143 } 6144 6145 /* Parse the string of disassembler options. */ 6146 6147 static void 6148 parse_arm_disassembler_options (const char *options) 6149 { 6150 const char *opt; 6151 6152 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 6153 { 6154 if (CONST_STRNEQ (opt, "reg-names-")) 6155 { 6156 unsigned int i; 6157 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6158 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 6159 { 6160 regname_selected = i; 6161 break; 6162 } 6163 6164 if (i >= NUM_ARM_OPTIONS) 6165 /* xgettext: c-format */ 6166 opcodes_error_handler (_("unrecognised register name set: %s"), 6167 opt); 6168 } 6169 else if (CONST_STRNEQ (opt, "force-thumb")) 6170 force_thumb = 1; 6171 else if (CONST_STRNEQ (opt, "no-force-thumb")) 6172 force_thumb = 0; 6173 else 6174 /* xgettext: c-format */ 6175 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 6176 } 6177 6178 return; 6179 } 6180 6181 static bfd_boolean 6182 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6183 enum map_type *map_symbol); 6184 6185 /* Search back through the insn stream to determine if this instruction is 6186 conditionally executed. */ 6187 6188 static void 6189 find_ifthen_state (bfd_vma pc, 6190 struct disassemble_info *info, 6191 bfd_boolean little) 6192 { 6193 unsigned char b[2]; 6194 unsigned int insn; 6195 int status; 6196 /* COUNT is twice the number of instructions seen. It will be odd if we 6197 just crossed an instruction boundary. */ 6198 int count; 6199 int it_count; 6200 unsigned int seen_it; 6201 bfd_vma addr; 6202 6203 ifthen_address = pc; 6204 ifthen_state = 0; 6205 6206 addr = pc; 6207 count = 1; 6208 it_count = 0; 6209 seen_it = 0; 6210 /* Scan backwards looking for IT instructions, keeping track of where 6211 instruction boundaries are. We don't know if something is actually an 6212 IT instruction until we find a definite instruction boundary. */ 6213 for (;;) 6214 { 6215 if (addr == 0 || info->symbol_at_address_func (addr, info)) 6216 { 6217 /* A symbol must be on an instruction boundary, and will not 6218 be within an IT block. */ 6219 if (seen_it && (count & 1)) 6220 break; 6221 6222 return; 6223 } 6224 addr -= 2; 6225 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 6226 if (status) 6227 return; 6228 6229 if (little) 6230 insn = (b[0]) | (b[1] << 8); 6231 else 6232 insn = (b[1]) | (b[0] << 8); 6233 if (seen_it) 6234 { 6235 if ((insn & 0xf800) < 0xe800) 6236 { 6237 /* Addr + 2 is an instruction boundary. See if this matches 6238 the expected boundary based on the position of the last 6239 IT candidate. */ 6240 if (count & 1) 6241 break; 6242 seen_it = 0; 6243 } 6244 } 6245 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 6246 { 6247 enum map_type type = MAP_ARM; 6248 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 6249 6250 if (!found || (found && type == MAP_THUMB)) 6251 { 6252 /* This could be an IT instruction. */ 6253 seen_it = insn; 6254 it_count = count >> 1; 6255 } 6256 } 6257 if ((insn & 0xf800) >= 0xe800) 6258 count++; 6259 else 6260 count = (count + 2) | 1; 6261 /* IT blocks contain at most 4 instructions. */ 6262 if (count >= 8 && !seen_it) 6263 return; 6264 } 6265 /* We found an IT instruction. */ 6266 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 6267 if ((ifthen_state & 0xf) == 0) 6268 ifthen_state = 0; 6269 } 6270 6271 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 6272 mapping symbol. */ 6273 6274 static int 6275 is_mapping_symbol (struct disassemble_info *info, int n, 6276 enum map_type *map_type) 6277 { 6278 const char *name; 6279 6280 name = bfd_asymbol_name (info->symtab[n]); 6281 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 6282 && (name[2] == 0 || name[2] == '.')) 6283 { 6284 *map_type = ((name[1] == 'a') ? MAP_ARM 6285 : (name[1] == 't') ? MAP_THUMB 6286 : MAP_DATA); 6287 return TRUE; 6288 } 6289 6290 return FALSE; 6291 } 6292 6293 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 6294 Returns nonzero if *MAP_TYPE was set. */ 6295 6296 static int 6297 get_map_sym_type (struct disassemble_info *info, 6298 int n, 6299 enum map_type *map_type) 6300 { 6301 /* If the symbol is in a different section, ignore it. */ 6302 if (info->section != NULL && info->section != info->symtab[n]->section) 6303 return FALSE; 6304 6305 return is_mapping_symbol (info, n, map_type); 6306 } 6307 6308 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 6309 Returns nonzero if *MAP_TYPE was set. */ 6310 6311 static int 6312 get_sym_code_type (struct disassemble_info *info, 6313 int n, 6314 enum map_type *map_type) 6315 { 6316 elf_symbol_type *es; 6317 unsigned int type; 6318 6319 /* If the symbol is in a different section, ignore it. */ 6320 if (info->section != NULL && info->section != info->symtab[n]->section) 6321 return FALSE; 6322 6323 es = *(elf_symbol_type **)(info->symtab + n); 6324 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6325 6326 /* If the symbol has function type then use that. */ 6327 if (type == STT_FUNC || type == STT_GNU_IFUNC) 6328 { 6329 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6330 == ST_BRANCH_TO_THUMB) 6331 *map_type = MAP_THUMB; 6332 else 6333 *map_type = MAP_ARM; 6334 return TRUE; 6335 } 6336 6337 return FALSE; 6338 } 6339 6340 /* Search the mapping symbol state for instruction at pc. This is only 6341 applicable for elf target. 6342 6343 There is an assumption Here, info->private_data contains the correct AND 6344 up-to-date information about current scan process. The information will be 6345 used to speed this search process. 6346 6347 Return TRUE if the mapping state can be determined, and map_symbol 6348 will be updated accordingly. Otherwise, return FALSE. */ 6349 6350 static bfd_boolean 6351 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6352 enum map_type *map_symbol) 6353 { 6354 bfd_vma addr; 6355 int n, start = 0; 6356 bfd_boolean found = FALSE; 6357 enum map_type type = MAP_ARM; 6358 struct arm_private_data *private_data; 6359 6360 if (info->private_data == NULL || info->symtab_size == 0 6361 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 6362 return FALSE; 6363 6364 private_data = info->private_data; 6365 if (pc == 0) 6366 start = 0; 6367 else 6368 start = private_data->last_mapping_sym; 6369 6370 start = (start == -1)? 0 : start; 6371 addr = bfd_asymbol_value (info->symtab[start]); 6372 6373 if (pc >= addr) 6374 { 6375 if (get_map_sym_type (info, start, &type)) 6376 found = TRUE; 6377 } 6378 else 6379 { 6380 for (n = start - 1; n >= 0; n--) 6381 { 6382 if (get_map_sym_type (info, n, &type)) 6383 { 6384 found = TRUE; 6385 break; 6386 } 6387 } 6388 } 6389 6390 /* No mapping symbols were found. A leading $d may be 6391 omitted for sections which start with data; but for 6392 compatibility with legacy and stripped binaries, only 6393 assume the leading $d if there is at least one mapping 6394 symbol in the file. */ 6395 if (!found && private_data->has_mapping_symbols == 1) 6396 { 6397 type = MAP_DATA; 6398 found = TRUE; 6399 } 6400 6401 *map_symbol = type; 6402 return found; 6403 } 6404 6405 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 6406 of the supplied arm_feature_set structure with bitmasks indicating 6407 the supported base architectures and coprocessor extensions. 6408 6409 FIXME: This could more efficiently implemented as a constant array, 6410 although it would also be less robust. */ 6411 6412 static void 6413 select_arm_features (unsigned long mach, 6414 arm_feature_set * features) 6415 { 6416 arm_feature_set arch_fset; 6417 const arm_feature_set fpu_any = FPU_ANY; 6418 6419 #undef ARM_SET_FEATURES 6420 #define ARM_SET_FEATURES(FSET) \ 6421 { \ 6422 const arm_feature_set fset = FSET; \ 6423 arch_fset = fset; \ 6424 } 6425 6426 /* When several architecture versions share the same bfd_mach_arm_XXX value 6427 the most featureful is chosen. */ 6428 switch (mach) 6429 { 6430 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 6431 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 6432 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 6433 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 6434 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 6435 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 6436 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 6437 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 6438 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 6439 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 6440 case bfd_mach_arm_ep9312: 6441 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 6442 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 6443 break; 6444 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 6445 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 6446 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 6447 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 6448 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 6449 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 6450 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 6451 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 6452 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 6453 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 6454 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 6455 case bfd_mach_arm_8: 6456 { 6457 /* Add bits for extensions that Armv8.5-A recognizes. */ 6458 arm_feature_set armv8_5_ext_fset 6459 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 6460 ARM_SET_FEATURES (ARM_ARCH_V8_5A); 6461 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset); 6462 break; 6463 } 6464 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; 6465 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 6466 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 6467 /* If the machine type is unknown allow all architecture types and all 6468 extensions. */ 6469 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; 6470 default: 6471 abort (); 6472 } 6473 #undef ARM_SET_FEATURES 6474 6475 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 6476 and thus on bfd_mach_arm_XXX value. Therefore for a given 6477 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 6478 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 6479 } 6480 6481 6482 /* NOTE: There are no checks in these routines that 6483 the relevant number of data bytes exist. */ 6484 6485 static int 6486 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 6487 { 6488 unsigned char b[4]; 6489 long given; 6490 int status; 6491 int is_thumb = FALSE; 6492 int is_data = FALSE; 6493 int little_code; 6494 unsigned int size = 4; 6495 void (*printer) (bfd_vma, struct disassemble_info *, long); 6496 bfd_boolean found = FALSE; 6497 struct arm_private_data *private_data; 6498 6499 if (info->disassembler_options) 6500 { 6501 parse_arm_disassembler_options (info->disassembler_options); 6502 6503 /* To avoid repeated parsing of these options, we remove them here. */ 6504 info->disassembler_options = NULL; 6505 } 6506 6507 /* PR 10288: Control which instructions will be disassembled. */ 6508 if (info->private_data == NULL) 6509 { 6510 static struct arm_private_data private; 6511 6512 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 6513 /* If the user did not use the -m command line switch then default to 6514 disassembling all types of ARM instruction. 6515 6516 The info->mach value has to be ignored as this will be based on 6517 the default archictecture for the target and/or hints in the notes 6518 section, but it will never be greater than the current largest arm 6519 machine value (iWMMXt2), which is only equivalent to the V5TE 6520 architecture. ARM architectures have advanced beyond the machine 6521 value encoding, and these newer architectures would be ignored if 6522 the machine value was used. 6523 6524 Ie the -m switch is used to restrict which instructions will be 6525 disassembled. If it is necessary to use the -m switch to tell 6526 objdump that an ARM binary is being disassembled, eg because the 6527 input is a raw binary file, but it is also desired to disassemble 6528 all ARM instructions then use "-marm". This will select the 6529 "unknown" arm architecture which is compatible with any ARM 6530 instruction. */ 6531 info->mach = bfd_mach_arm_unknown; 6532 6533 /* Compute the architecture bitmask from the machine number. 6534 Note: This assumes that the machine number will not change 6535 during disassembly.... */ 6536 select_arm_features (info->mach, & private.features); 6537 6538 private.has_mapping_symbols = -1; 6539 private.last_mapping_sym = -1; 6540 private.last_mapping_addr = 0; 6541 6542 info->private_data = & private; 6543 } 6544 6545 private_data = info->private_data; 6546 6547 /* Decide if our code is going to be little-endian, despite what the 6548 function argument might say. */ 6549 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 6550 6551 /* For ELF, consult the symbol table to determine what kind of code 6552 or data we have. */ 6553 if (info->symtab_size != 0 6554 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 6555 { 6556 bfd_vma addr; 6557 int n, start; 6558 int last_sym = -1; 6559 enum map_type type = MAP_ARM; 6560 6561 /* Start scanning at the start of the function, or wherever 6562 we finished last time. */ 6563 /* PR 14006. When the address is 0 we are either at the start of the 6564 very first function, or else the first function in a new, unlinked 6565 executable section (eg because of -ffunction-sections). Either way 6566 start scanning from the beginning of the symbol table, not where we 6567 left off last time. */ 6568 if (pc == 0) 6569 start = 0; 6570 else 6571 { 6572 start = info->symtab_pos + 1; 6573 if (start < private_data->last_mapping_sym) 6574 start = private_data->last_mapping_sym; 6575 } 6576 found = FALSE; 6577 6578 /* First, look for mapping symbols. */ 6579 if (private_data->has_mapping_symbols != 0) 6580 { 6581 /* Scan up to the location being disassembled. */ 6582 for (n = start; n < info->symtab_size; n++) 6583 { 6584 addr = bfd_asymbol_value (info->symtab[n]); 6585 if (addr > pc) 6586 break; 6587 if (get_map_sym_type (info, n, &type)) 6588 { 6589 last_sym = n; 6590 found = TRUE; 6591 } 6592 } 6593 6594 if (!found) 6595 { 6596 /* No mapping symbol found at this address. Look backwards 6597 for a preceding one. */ 6598 for (n = start - 1; n >= 0; n--) 6599 { 6600 if (get_map_sym_type (info, n, &type)) 6601 { 6602 last_sym = n; 6603 found = TRUE; 6604 break; 6605 } 6606 } 6607 } 6608 6609 if (found) 6610 private_data->has_mapping_symbols = 1; 6611 6612 /* No mapping symbols were found. A leading $d may be 6613 omitted for sections which start with data; but for 6614 compatibility with legacy and stripped binaries, only 6615 assume the leading $d if there is at least one mapping 6616 symbol in the file. */ 6617 if (!found && private_data->has_mapping_symbols == -1) 6618 { 6619 /* Look for mapping symbols, in any section. */ 6620 for (n = 0; n < info->symtab_size; n++) 6621 if (is_mapping_symbol (info, n, &type)) 6622 { 6623 private_data->has_mapping_symbols = 1; 6624 break; 6625 } 6626 if (private_data->has_mapping_symbols == -1) 6627 private_data->has_mapping_symbols = 0; 6628 } 6629 6630 if (!found && private_data->has_mapping_symbols == 1) 6631 { 6632 type = MAP_DATA; 6633 found = TRUE; 6634 } 6635 } 6636 6637 /* Next search for function symbols to separate ARM from Thumb 6638 in binaries without mapping symbols. */ 6639 if (!found) 6640 { 6641 /* Scan up to the location being disassembled. */ 6642 for (n = start; n < info->symtab_size; n++) 6643 { 6644 addr = bfd_asymbol_value (info->symtab[n]); 6645 if (addr > pc) 6646 break; 6647 if (get_sym_code_type (info, n, &type)) 6648 { 6649 last_sym = n; 6650 found = TRUE; 6651 } 6652 } 6653 6654 if (!found) 6655 { 6656 /* No mapping symbol found at this address. Look backwards 6657 for a preceding one. */ 6658 for (n = start - 1; n >= 0; n--) 6659 { 6660 if (get_sym_code_type (info, n, &type)) 6661 { 6662 last_sym = n; 6663 found = TRUE; 6664 break; 6665 } 6666 } 6667 } 6668 } 6669 6670 private_data->last_mapping_sym = last_sym; 6671 private_data->last_type = type; 6672 is_thumb = (private_data->last_type == MAP_THUMB); 6673 is_data = (private_data->last_type == MAP_DATA); 6674 6675 /* Look a little bit ahead to see if we should print out 6676 two or four bytes of data. If there's a symbol, 6677 mapping or otherwise, after two bytes then don't 6678 print more. */ 6679 if (is_data) 6680 { 6681 size = 4 - (pc & 3); 6682 for (n = last_sym + 1; n < info->symtab_size; n++) 6683 { 6684 addr = bfd_asymbol_value (info->symtab[n]); 6685 if (addr > pc 6686 && (info->section == NULL 6687 || info->section == info->symtab[n]->section)) 6688 { 6689 if (addr - pc < size) 6690 size = addr - pc; 6691 break; 6692 } 6693 } 6694 /* If the next symbol is after three bytes, we need to 6695 print only part of the data, so that we can use either 6696 .byte or .short. */ 6697 if (size == 3) 6698 size = (pc & 1) ? 1 : 2; 6699 } 6700 } 6701 6702 if (info->symbols != NULL) 6703 { 6704 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 6705 { 6706 coff_symbol_type * cs; 6707 6708 cs = coffsymbol (*info->symbols); 6709 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 6710 || cs->native->u.syment.n_sclass == C_THUMBSTAT 6711 || cs->native->u.syment.n_sclass == C_THUMBLABEL 6712 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 6713 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 6714 } 6715 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 6716 && !found) 6717 { 6718 /* If no mapping symbol has been found then fall back to the type 6719 of the function symbol. */ 6720 elf_symbol_type * es; 6721 unsigned int type; 6722 6723 es = *(elf_symbol_type **)(info->symbols); 6724 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6725 6726 is_thumb = 6727 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6728 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 6729 } 6730 else if (bfd_asymbol_flavour (*info->symbols) 6731 == bfd_target_mach_o_flavour) 6732 { 6733 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 6734 6735 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 6736 } 6737 } 6738 6739 if (force_thumb) 6740 is_thumb = TRUE; 6741 6742 if (is_data) 6743 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6744 else 6745 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6746 6747 info->bytes_per_line = 4; 6748 6749 /* PR 10263: Disassemble data if requested to do so by the user. */ 6750 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 6751 { 6752 int i; 6753 6754 /* Size was already set above. */ 6755 info->bytes_per_chunk = size; 6756 printer = print_insn_data; 6757 6758 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 6759 given = 0; 6760 if (little) 6761 for (i = size - 1; i >= 0; i--) 6762 given = b[i] | (given << 8); 6763 else 6764 for (i = 0; i < (int) size; i++) 6765 given = b[i] | (given << 8); 6766 } 6767 else if (!is_thumb) 6768 { 6769 /* In ARM mode endianness is a straightforward issue: the instruction 6770 is four bytes long and is either ordered 0123 or 3210. */ 6771 printer = print_insn_arm; 6772 info->bytes_per_chunk = 4; 6773 size = 4; 6774 6775 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 6776 if (little_code) 6777 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 6778 else 6779 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 6780 } 6781 else 6782 { 6783 /* In Thumb mode we have the additional wrinkle of two 6784 instruction lengths. Fortunately, the bits that determine 6785 the length of the current instruction are always to be found 6786 in the first two bytes. */ 6787 printer = print_insn_thumb16; 6788 info->bytes_per_chunk = 2; 6789 size = 2; 6790 6791 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 6792 if (little_code) 6793 given = (b[0]) | (b[1] << 8); 6794 else 6795 given = (b[1]) | (b[0] << 8); 6796 6797 if (!status) 6798 { 6799 /* These bit patterns signal a four-byte Thumb 6800 instruction. */ 6801 if ((given & 0xF800) == 0xF800 6802 || (given & 0xF800) == 0xF000 6803 || (given & 0xF800) == 0xE800) 6804 { 6805 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 6806 if (little_code) 6807 given = (b[0]) | (b[1] << 8) | (given << 16); 6808 else 6809 given = (b[1]) | (b[0] << 8) | (given << 16); 6810 6811 printer = print_insn_thumb32; 6812 size = 4; 6813 } 6814 } 6815 6816 if (ifthen_address != pc) 6817 find_ifthen_state (pc, info, little_code); 6818 6819 if (ifthen_state) 6820 { 6821 if ((ifthen_state & 0xf) == 0x8) 6822 ifthen_next_state = 0; 6823 else 6824 ifthen_next_state = (ifthen_state & 0xe0) 6825 | ((ifthen_state & 0xf) << 1); 6826 } 6827 } 6828 6829 if (status) 6830 { 6831 info->memory_error_func (status, pc, info); 6832 return -1; 6833 } 6834 if (info->flags & INSN_HAS_RELOC) 6835 /* If the instruction has a reloc associated with it, then 6836 the offset field in the instruction will actually be the 6837 addend for the reloc. (We are using REL type relocs). 6838 In such cases, we can ignore the pc when computing 6839 addresses, since the addend is not currently pc-relative. */ 6840 pc = 0; 6841 6842 printer (pc, info, given); 6843 6844 if (is_thumb) 6845 { 6846 ifthen_state = ifthen_next_state; 6847 ifthen_address += size; 6848 } 6849 return size; 6850 } 6851 6852 int 6853 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 6854 { 6855 /* Detect BE8-ness and record it in the disassembler info. */ 6856 if (info->flavour == bfd_target_elf_flavour 6857 && info->section != NULL 6858 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 6859 info->endian_code = BFD_ENDIAN_LITTLE; 6860 6861 return print_insn (pc, info, FALSE); 6862 } 6863 6864 int 6865 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 6866 { 6867 return print_insn (pc, info, TRUE); 6868 } 6869 6870 const disasm_options_and_args_t * 6871 disassembler_options_arm (void) 6872 { 6873 static disasm_options_and_args_t *opts_and_args; 6874 6875 if (opts_and_args == NULL) 6876 { 6877 disasm_options_t *opts; 6878 unsigned int i; 6879 6880 opts_and_args = XNEW (disasm_options_and_args_t); 6881 opts_and_args->args = NULL; 6882 6883 opts = &opts_and_args->options; 6884 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6885 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6886 opts->arg = NULL; 6887 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6888 { 6889 opts->name[i] = regnames[i].name; 6890 if (regnames[i].description != NULL) 6891 opts->description[i] = _(regnames[i].description); 6892 else 6893 opts->description[i] = NULL; 6894 } 6895 /* The array we return must be NULL terminated. */ 6896 opts->name[i] = NULL; 6897 opts->description[i] = NULL; 6898 } 6899 6900 return opts_and_args; 6901 } 6902 6903 void 6904 print_arm_disassembler_options (FILE *stream) 6905 { 6906 unsigned int i, max_len = 0; 6907 fprintf (stream, _("\n\ 6908 The following ARM specific disassembler options are supported for use with\n\ 6909 the -M switch:\n")); 6910 6911 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6912 { 6913 unsigned int len = strlen (regnames[i].name); 6914 if (max_len < len) 6915 max_len = len; 6916 } 6917 6918 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 6919 fprintf (stream, " %s%*c %s\n", 6920 regnames[i].name, 6921 (int)(max_len - strlen (regnames[i].name)), ' ', 6922 _(regnames[i].description)); 6923 } 6924