1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c. 2 Copyright (C) 2012-2019 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef OPCODES_AARCH64_OPC_H 22 #define OPCODES_AARCH64_OPC_H 23 24 #include <string.h> 25 #include "opcode/aarch64.h" 26 27 /* Instruction fields. 28 Keep synced with fields. */ 29 enum aarch64_field_kind 30 { 31 FLD_NIL, 32 FLD_cond2, 33 FLD_nzcv, 34 FLD_defgh, 35 FLD_abc, 36 FLD_imm19, 37 FLD_immhi, 38 FLD_immlo, 39 FLD_size, 40 FLD_vldst_size, 41 FLD_op, 42 FLD_Q, 43 FLD_Rt, 44 FLD_Rd, 45 FLD_Rn, 46 FLD_Rt2, 47 FLD_Ra, 48 FLD_op2, 49 FLD_CRm, 50 FLD_CRn, 51 FLD_op1, 52 FLD_op0, 53 FLD_imm3, 54 FLD_cond, 55 FLD_opcode, 56 FLD_cmode, 57 FLD_asisdlso_opcode, 58 FLD_len, 59 FLD_Rm, 60 FLD_Rs, 61 FLD_option, 62 FLD_S, 63 FLD_hw, 64 FLD_opc, 65 FLD_opc1, 66 FLD_shift, 67 FLD_type, 68 FLD_ldst_size, 69 FLD_imm6, 70 FLD_imm6_2, 71 FLD_imm4, 72 FLD_imm4_2, 73 FLD_imm4_3, 74 FLD_imm5, 75 FLD_imm7, 76 FLD_imm8, 77 FLD_imm9, 78 FLD_imm12, 79 FLD_imm14, 80 FLD_imm16, 81 FLD_imm26, 82 FLD_imms, 83 FLD_immr, 84 FLD_immb, 85 FLD_immh, 86 FLD_S_imm10, 87 FLD_N, 88 FLD_index, 89 FLD_index2, 90 FLD_sf, 91 FLD_lse_sz, 92 FLD_H, 93 FLD_L, 94 FLD_M, 95 FLD_b5, 96 FLD_b40, 97 FLD_scale, 98 FLD_SVE_M_4, 99 FLD_SVE_M_14, 100 FLD_SVE_M_16, 101 FLD_SVE_N, 102 FLD_SVE_Pd, 103 FLD_SVE_Pg3, 104 FLD_SVE_Pg4_5, 105 FLD_SVE_Pg4_10, 106 FLD_SVE_Pg4_16, 107 FLD_SVE_Pm, 108 FLD_SVE_Pn, 109 FLD_SVE_Pt, 110 FLD_SVE_Rm, 111 FLD_SVE_Rn, 112 FLD_SVE_Vd, 113 FLD_SVE_Vm, 114 FLD_SVE_Vn, 115 FLD_SVE_Za_5, 116 FLD_SVE_Za_16, 117 FLD_SVE_Zd, 118 FLD_SVE_Zm_5, 119 FLD_SVE_Zm_16, 120 FLD_SVE_Zn, 121 FLD_SVE_Zt, 122 FLD_SVE_i1, 123 FLD_SVE_i3h, 124 FLD_SVE_imm3, 125 FLD_SVE_imm4, 126 FLD_SVE_imm5, 127 FLD_SVE_imm5b, 128 FLD_SVE_imm6, 129 FLD_SVE_imm7, 130 FLD_SVE_imm8, 131 FLD_SVE_imm9, 132 FLD_SVE_immr, 133 FLD_SVE_imms, 134 FLD_SVE_msz, 135 FLD_SVE_pattern, 136 FLD_SVE_prfop, 137 FLD_SVE_rot1, 138 FLD_SVE_rot2, 139 FLD_SVE_sz, 140 FLD_SVE_tsz, 141 FLD_SVE_tszh, 142 FLD_SVE_tszl_8, 143 FLD_SVE_tszl_19, 144 FLD_SVE_xs_14, 145 FLD_SVE_xs_22, 146 FLD_rotate1, 147 FLD_rotate2, 148 FLD_rotate3, 149 FLD_SM3_imm2, 150 FLD_sz 151 }; 152 153 /* Field description. */ 154 struct aarch64_field 155 { 156 int lsb; 157 int width; 158 }; 159 160 typedef struct aarch64_field aarch64_field; 161 162 extern const aarch64_field fields[]; 163 164 /* Operand description. */ 165 166 struct aarch64_operand 167 { 168 enum aarch64_operand_class op_class; 169 170 /* Name of the operand code; used mainly for the purpose of internal 171 debugging. */ 172 const char *name; 173 174 unsigned int flags; 175 176 /* The associated instruction bit-fields; no operand has more than 4 177 bit-fields */ 178 enum aarch64_field_kind fields[4]; 179 180 /* Brief description */ 181 const char *desc; 182 }; 183 184 typedef struct aarch64_operand aarch64_operand; 185 186 extern const aarch64_operand aarch64_operands[]; 187 188 enum err_type 189 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, 190 bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*); 191 192 /* Operand flags. */ 193 194 #define OPD_F_HAS_INSERTER 0x00000001 195 #define OPD_F_HAS_EXTRACTOR 0x00000002 196 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */ 197 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field 198 value by 2 to get the value 199 of an immediate operand. */ 200 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */ 201 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */ 202 #define OPD_F_OD_LSB 5 203 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */ 204 #define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field 205 value by 4 to get the value 206 of an immediate operand. */ 207 208 209 /* Register flags. */ 210 211 #undef F_DEPRECATED 212 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */ 213 214 #undef F_ARCHEXT 215 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */ 216 217 #undef F_HASXT 218 #define F_HASXT (1 << 2) /* System instruction register <Xt> 219 operand. */ 220 221 #undef F_REG_READ 222 #define F_REG_READ (1 << 3) /* Register can only be used to read values 223 out of. */ 224 225 #undef F_REG_WRITE 226 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not 227 read from. */ 228 229 /* HINT operand flags. */ 230 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */ 231 232 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */ 233 #define HINT_ENCODE(flag, val) ((flag << 8) | val) 234 #define HINT_FLAG(val) (val >> 8) 235 #define HINT_VAL(val) (val & 0xff) 236 237 static inline bfd_boolean 238 operand_has_inserter (const aarch64_operand *operand) 239 { 240 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE; 241 } 242 243 static inline bfd_boolean 244 operand_has_extractor (const aarch64_operand *operand) 245 { 246 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE; 247 } 248 249 static inline bfd_boolean 250 operand_need_sign_extension (const aarch64_operand *operand) 251 { 252 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE; 253 } 254 255 static inline bfd_boolean 256 operand_need_shift_by_two (const aarch64_operand *operand) 257 { 258 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE; 259 } 260 261 static inline bfd_boolean 262 operand_need_shift_by_four (const aarch64_operand *operand) 263 { 264 return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE; 265 } 266 267 static inline bfd_boolean 268 operand_maybe_stack_pointer (const aarch64_operand *operand) 269 { 270 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE; 271 } 272 273 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */ 274 static inline unsigned int 275 get_operand_specific_data (const aarch64_operand *operand) 276 { 277 return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB; 278 } 279 280 /* Return the width of field number N of operand *OPERAND. */ 281 static inline unsigned 282 get_operand_field_width (const aarch64_operand *operand, unsigned n) 283 { 284 assert (operand->fields[n] != FLD_NIL); 285 return fields[operand->fields[n]].width; 286 } 287 288 /* Return the total width of the operand *OPERAND. */ 289 static inline unsigned 290 get_operand_fields_width (const aarch64_operand *operand) 291 { 292 int i = 0; 293 unsigned width = 0; 294 while (operand->fields[i] != FLD_NIL) 295 width += fields[operand->fields[i++]].width; 296 assert (width > 0 && width < 32); 297 return width; 298 } 299 300 static inline const aarch64_operand * 301 get_operand_from_code (enum aarch64_opnd code) 302 { 303 return aarch64_operands + code; 304 } 305 306 /* Operand qualifier and operand constraint checking. */ 307 308 int aarch64_match_operands_constraint (aarch64_inst *, 309 aarch64_operand_error *); 310 311 /* Operand qualifier related functions. */ 312 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t); 313 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t); 314 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t); 315 int aarch64_find_best_match (const aarch64_inst *, 316 const aarch64_opnd_qualifier_seq_t *, 317 int, aarch64_opnd_qualifier_t *); 318 319 static inline void 320 reset_operand_qualifier (aarch64_inst *inst, int idx) 321 { 322 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode)); 323 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; 324 } 325 326 /* Inline functions operating on instruction bit-field(s). */ 327 328 /* Generate a mask that has WIDTH number of consecutive 1s. */ 329 330 static inline aarch64_insn 331 gen_mask (int width) 332 { 333 return ((aarch64_insn) 1 << width) - 1; 334 } 335 336 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */ 337 static inline int 338 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret) 339 { 340 const aarch64_field *field = &fields[kind]; 341 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) 342 return 0; 343 ret->lsb = field->lsb + lsb_rel; 344 ret->width = width; 345 return 1; 346 } 347 348 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask 349 of the opcode. */ 350 351 static inline void 352 insert_field_2 (const aarch64_field *field, aarch64_insn *code, 353 aarch64_insn value, aarch64_insn mask) 354 { 355 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0 356 && field->lsb + field->width <= 32); 357 value &= gen_mask (field->width); 358 value <<= field->lsb; 359 /* In some opcodes, field can be part of the base opcode, e.g. the size 360 field in FADD. The following helps avoid corrupt the base opcode. */ 361 value &= ~mask; 362 *code |= value; 363 } 364 365 /* Extract FIELD of CODE and return the value. MASK can be zero or the base 366 mask of the opcode. */ 367 368 static inline aarch64_insn 369 extract_field_2 (const aarch64_field *field, aarch64_insn code, 370 aarch64_insn mask) 371 { 372 aarch64_insn value; 373 /* Clear any bit that is a part of the base opcode. */ 374 code &= ~mask; 375 value = (code >> field->lsb) & gen_mask (field->width); 376 return value; 377 } 378 379 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask 380 of the opcode. */ 381 382 static inline void 383 insert_field (enum aarch64_field_kind kind, aarch64_insn *code, 384 aarch64_insn value, aarch64_insn mask) 385 { 386 insert_field_2 (&fields[kind], code, value, mask); 387 } 388 389 /* Extract field KIND of CODE and return the value. MASK can be zero or the 390 base mask of the opcode. */ 391 392 static inline aarch64_insn 393 extract_field (enum aarch64_field_kind kind, aarch64_insn code, 394 aarch64_insn mask) 395 { 396 return extract_field_2 (&fields[kind], code, mask); 397 } 398 399 extern aarch64_insn 400 extract_fields (aarch64_insn code, aarch64_insn mask, ...); 401 402 /* Inline functions selecting operand to do the encoding/decoding for a 403 certain instruction bit-field. */ 404 405 /* Select the operand to do the encoding/decoding of the 'sf' field. 406 The heuristic-based rule is that the result operand is respected more. */ 407 408 static inline int 409 select_operand_for_sf_field_coding (const aarch64_opcode *opcode) 410 { 411 int idx = -1; 412 if (aarch64_get_operand_class (opcode->operands[0]) 413 == AARCH64_OPND_CLASS_INT_REG) 414 /* normal case. */ 415 idx = 0; 416 else if (aarch64_get_operand_class (opcode->operands[1]) 417 == AARCH64_OPND_CLASS_INT_REG) 418 /* e.g. float2fix. */ 419 idx = 1; 420 else 421 { assert (0); abort (); } 422 return idx; 423 } 424 425 /* Select the operand to do the encoding/decoding of the 'type' field in 426 the floating-point instructions. 427 The heuristic-based rule is that the source operand is respected more. */ 428 429 static inline int 430 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode) 431 { 432 int idx; 433 if (aarch64_get_operand_class (opcode->operands[1]) 434 == AARCH64_OPND_CLASS_FP_REG) 435 /* normal case. */ 436 idx = 1; 437 else if (aarch64_get_operand_class (opcode->operands[0]) 438 == AARCH64_OPND_CLASS_FP_REG) 439 /* e.g. float2fix. */ 440 idx = 0; 441 else 442 { assert (0); abort (); } 443 return idx; 444 } 445 446 /* Select the operand to do the encoding/decoding of the 'size' field in 447 the AdvSIMD scalar instructions. 448 The heuristic-based rule is that the destination operand is respected 449 more. */ 450 451 static inline int 452 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode) 453 { 454 int src_size = 0, dst_size = 0; 455 if (aarch64_get_operand_class (opcode->operands[0]) 456 == AARCH64_OPND_CLASS_SISD_REG) 457 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]); 458 if (aarch64_get_operand_class (opcode->operands[1]) 459 == AARCH64_OPND_CLASS_SISD_REG) 460 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]); 461 if (src_size == dst_size && src_size == 0) 462 { assert (0); abort (); } 463 /* When the result is not a sisd register or it is a long operantion. */ 464 if (dst_size == 0 || dst_size == src_size << 1) 465 return 1; 466 else 467 return 0; 468 } 469 470 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in 471 the AdvSIMD instructions. */ 472 473 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *); 474 475 /* Miscellaneous. */ 476 477 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind); 478 enum aarch64_modifier_kind 479 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean); 480 481 482 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *); 483 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *); 484 int aarch64_shrink_expanded_imm8 (uint64_t); 485 486 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */ 487 static inline void 488 copy_operand_info (aarch64_inst *inst, int dst, int src) 489 { 490 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM 491 && src < AARCH64_MAX_OPND_NUM); 492 memcpy (&inst->operands[dst], &inst->operands[src], 493 sizeof (aarch64_opnd_info)); 494 inst->operands[dst].idx = dst; 495 } 496 497 /* A primitive log caculator. */ 498 499 static inline unsigned int 500 get_logsz (unsigned int size) 501 { 502 const unsigned char ls[16] = 503 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4}; 504 if (size > 16) 505 { 506 assert (0); 507 return -1; 508 } 509 assert (ls[size - 1] != (unsigned char)-1); 510 return ls[size - 1]; 511 } 512 513 #endif /* OPCODES_AARCH64_OPC_H */ 514