1 /* Opcode table for the ARC. 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 4 Contributed by Claudiu Zissulescu (claziss@synopsys.com) 5 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 7 the GNU Binutils. 8 9 GAS/GDB is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS/GDB is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS or GDB; see the file COPYING3. If not, write to 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #ifndef OPCODE_ARC_H 25 #define OPCODE_ARC_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #ifndef MAX_INSN_ARGS 32 #define MAX_INSN_ARGS 16 33 #endif 34 35 #ifndef MAX_INSN_FLGS 36 #define MAX_INSN_FLGS 3 37 #endif 38 39 /* Instruction Class. */ 40 typedef enum 41 { 42 ACL, 43 ARITH, 44 AUXREG, 45 BITOP, 46 BMU, 47 BRANCH, 48 CONTROL, 49 DPI, 50 DSP, 51 FLOAT, 52 INVALID, 53 JUMP, 54 KERNEL, 55 LOGICAL, 56 MEMORY, 57 NET, 58 PMU 59 } insn_class_t; 60 61 /* Instruction Subclass. */ 62 typedef enum 63 { 64 NONE, 65 CVT, 66 BTSCN, 67 CD1, 68 CD2, 69 COND, 70 DIV, 71 DP, 72 DPA, 73 DPX, 74 MPY1E, 75 MPY6E, 76 MPY7E, 77 MPY8E, 78 MPY9E, 79 NPS400, 80 QUARKSE, 81 SHFT1, 82 SHFT2, 83 SWAP, 84 SP, 85 SPX 86 } insn_subclass_t; 87 88 /* Flags class. */ 89 typedef enum 90 { 91 F_CLASS_NONE = 0, 92 93 /* At most one flag from the set of flags can appear in the 94 instruction. */ 95 F_CLASS_OPTIONAL = (1 << 0), 96 97 /* Exactly one from from the set of flags must appear in the 98 instruction. */ 99 F_CLASS_REQUIRED = (1 << 1), 100 101 /* The conditional code can be extended over the standard variants 102 via .extCondCode pseudo-op. */ 103 F_CLASS_EXTEND = (1 << 2), 104 105 /* Condition code flag. */ 106 F_CLASS_COND = (1 << 3) 107 } flag_class_t; 108 109 /* The opcode table is an array of struct arc_opcode. */ 110 struct arc_opcode 111 { 112 /* The opcode name. */ 113 const char *name; 114 115 /* The opcode itself. Those bits which will be filled in with 116 operands are zeroes. */ 117 unsigned opcode; 118 119 /* The opcode mask. This is used by the disassembler. This is a 120 mask containing ones indicating those bits which must match the 121 opcode field, and zeroes indicating those bits which need not 122 match (and are presumably filled in by operands). */ 123 unsigned mask; 124 125 /* One bit flags for the opcode. These are primarily used to 126 indicate specific processors and environments support the 127 instructions. The defined values are listed below. */ 128 unsigned cpu; 129 130 /* The instruction class. This is used by gdb. */ 131 insn_class_t insn_class; 132 133 /* The instruction subclass. */ 134 insn_subclass_t subclass; 135 136 /* An array of operand codes. Each code is an index into the 137 operand table. They appear in the order which the operands must 138 appear in assembly code, and are terminated by a zero. */ 139 unsigned char operands[MAX_INSN_ARGS + 1]; 140 141 /* An array of flag codes. Each code is an index into the flag 142 table. They appear in the order which the flags must appear in 143 assembly code, and are terminated by a zero. */ 144 unsigned char flags[MAX_INSN_FLGS + 1]; 145 }; 146 147 /* Structure used to describe 48 and 64 bit instructions. */ 148 struct arc_long_opcode 149 { 150 /* The base instruction is either 16 or 32 bits, and is described like a 151 normal instruction. */ 152 struct arc_opcode base_opcode; 153 154 /* The template value for the 32-bit LIMM extension. Used by the 155 assembler and disassembler in the same way as the 'opcode' field of 156 'struct arc_opcode'. */ 157 unsigned limm_template; 158 159 /* The mask value for the 32-bit LIMM extension. Used by the 160 disassembler just like the 'mask' field in 'struct arc_opcode'. */ 161 unsigned limm_mask; 162 163 /* Array of operand codes similar to the 'operands' array in 'struct 164 arc_opcode'. These operands are used to fill in the LIMM value. */ 165 unsigned char operands[MAX_INSN_ARGS + 1]; 166 }; 167 168 extern const struct arc_long_opcode arc_long_opcodes[]; 169 extern const unsigned arc_num_long_opcodes; 170 171 /* The table itself is sorted by major opcode number, and is otherwise 172 in the order in which the disassembler should consider 173 instructions. */ 174 extern const struct arc_opcode arc_opcodes[]; 175 176 /* CPU Availability. */ 177 #define ARC_OPCODE_NONE 0x0000 178 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ 179 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ 180 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ 181 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ 182 183 /* CPU combi. */ 184 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ 185 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) 186 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) 187 188 /* CPU extensions. */ 189 #define ARC_EA 0x0001 190 #define ARC_CD 0x0001 /* Mutual exclusive with EA. */ 191 #define ARC_LLOCK 0x0002 192 #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ 193 #define ARC_MPY 0x0004 194 #define ARC_MULT 0x0004 195 #define ARC_NPS400 0x0008 196 197 /* Floating point support. */ 198 #define ARC_DPFP 0x0010 199 #define ARC_SPFP 0x0020 200 #define ARC_FPU 0x0030 201 #define ARC_FPUDA 0x0040 202 203 /* NORM & SWAP. */ 204 #define ARC_SWAP 0x0100 205 #define ARC_NORM 0x0200 206 #define ARC_BSCAN 0x0200 207 208 /* A7 specific. */ 209 #define ARC_UIX 0x1000 210 #define ARC_TSTAMP 0x1000 211 212 /* A6 specific. */ 213 #define ARC_VBFDW 0x1000 214 #define ARC_BARREL 0x1000 215 #define ARC_DSPA 0x1000 216 217 /* EM specific. */ 218 #define ARC_SHIFT 0x1000 219 220 /* V2 specific. */ 221 #define ARC_INTR 0x1000 222 #define ARC_DIV 0x1000 223 224 /* V1 specific. */ 225 #define ARC_XMAC 0x1000 226 #define ARC_CRC 0x1000 227 228 /* A macro to check for short instructions. */ 229 #define ARC_SHORT(mask) \ 230 (((mask) & 0xFFFF0000) ? 0 : 1) 231 232 /* The operands table is an array of struct arc_operand. */ 233 struct arc_operand 234 { 235 /* The number of bits in the operand. */ 236 unsigned int bits; 237 238 /* How far the operand is left shifted in the instruction. */ 239 unsigned int shift; 240 241 /* The default relocation type for this operand. */ 242 signed int default_reloc; 243 244 /* One bit syntax flags. */ 245 unsigned int flags; 246 247 /* Insertion function. This is used by the assembler. To insert an 248 operand value into an instruction, check this field. 249 250 If it is NULL, execute 251 i |= (op & ((1 << o->bits) - 1)) << o->shift; 252 (i is the instruction which we are filling in, o is a pointer to 253 this structure, and op is the opcode value; this assumes twos 254 complement arithmetic). 255 256 If this field is not NULL, then simply call it with the 257 instruction and the operand value. It will return the new value 258 of the instruction. If the ERRMSG argument is not NULL, then if 259 the operand value is illegal, *ERRMSG will be set to a warning 260 string (the operand will be inserted in any case). If the 261 operand value is legal, *ERRMSG will be unchanged (most operands 262 can accept any value). */ 263 unsigned (*insert) (unsigned instruction, int op, const char **errmsg); 264 265 /* Extraction function. This is used by the disassembler. To 266 extract this operand type from an instruction, check this field. 267 268 If it is NULL, compute 269 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 270 if ((o->flags & ARC_OPERAND_SIGNED) != 0 271 && (op & (1 << (o->bits - 1))) != 0) 272 op -= 1 << o->bits; 273 (i is the instruction, o is a pointer to this structure, and op 274 is the result; this assumes twos complement arithmetic). 275 276 If this field is not NULL, then simply call it with the 277 instruction value. It will return the value of the operand. If 278 the INVALID argument is not NULL, *INVALID will be set to 279 TRUE if this operand type can not actually be extracted from 280 this operand (i.e., the instruction does not match). If the 281 operand is valid, *INVALID will not be changed. */ 282 int (*extract) (unsigned instruction, bfd_boolean *invalid); 283 }; 284 285 /* Elements in the table are retrieved by indexing with values from 286 the operands field of the arc_opcodes table. */ 287 extern const struct arc_operand arc_operands[]; 288 extern const unsigned arc_num_operands; 289 extern const unsigned arc_Toperand; 290 extern const unsigned arc_NToperand; 291 292 /* Values defined for the flags field of a struct arc_operand. */ 293 294 /* This operand does not actually exist in the assembler input. This 295 is used to support extended mnemonics, for which two operands fields 296 are identical. The assembler should call the insert function with 297 any op value. The disassembler should call the extract function, 298 ignore the return value, and check the value placed in the invalid 299 argument. */ 300 #define ARC_OPERAND_FAKE 0x0001 301 302 /* This operand names an integer register. */ 303 #define ARC_OPERAND_IR 0x0002 304 305 /* This operand takes signed values. */ 306 #define ARC_OPERAND_SIGNED 0x0004 307 308 /* This operand takes unsigned values. This exists primarily so that 309 a flags value of 0 can be treated as end-of-arguments. */ 310 #define ARC_OPERAND_UNSIGNED 0x0008 311 312 /* This operand takes long immediate values. */ 313 #define ARC_OPERAND_LIMM 0x0010 314 315 /* This operand is identical like the previous one. */ 316 #define ARC_OPERAND_DUPLICATE 0x0020 317 318 /* This operand is PC relative. Used for internal relocs. */ 319 #define ARC_OPERAND_PCREL 0x0040 320 321 /* This operand is truncated. The truncation is done accordingly to 322 operand alignment attribute. */ 323 #define ARC_OPERAND_TRUNCATE 0x0080 324 325 /* This operand is 16bit aligned. */ 326 #define ARC_OPERAND_ALIGNED16 0x0100 327 328 /* This operand is 32bit aligned. */ 329 #define ARC_OPERAND_ALIGNED32 0x0200 330 331 /* This operand can be ignored by matching process if it is not 332 present. */ 333 #define ARC_OPERAND_IGNORE 0x0400 334 335 /* Don't check the range when matching. */ 336 #define ARC_OPERAND_NCHK 0x0800 337 338 /* Mark the braket possition. */ 339 #define ARC_OPERAND_BRAKET 0x1000 340 341 /* Address type operand for NPS400. */ 342 #define ARC_OPERAND_ADDRTYPE 0x2000 343 344 /* Mark the colon position. */ 345 #define ARC_OPERAND_COLON 0x4000 346 347 /* Mask for selecting the type for typecheck purposes. */ 348 #define ARC_OPERAND_TYPECHECK_MASK \ 349 (ARC_OPERAND_IR \ 350 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ 351 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \ 352 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON) 353 354 /* Macro to determine if an operand is a fake operand. */ 355 #define ARC_OPERAND_IS_FAKE(op) \ 356 ((operand->flags & ARC_OPERAND_FAKE) \ 357 && !((operand->flags & ARC_OPERAND_BRAKET) \ 358 || (operand->flags & ARC_OPERAND_COLON))) 359 360 /* The flags structure. */ 361 struct arc_flag_operand 362 { 363 /* The flag name. */ 364 const char *name; 365 366 /* The flag code. */ 367 unsigned code; 368 369 /* The number of bits in the operand. */ 370 unsigned int bits; 371 372 /* How far the operand is left shifted in the instruction. */ 373 unsigned int shift; 374 375 /* Available for disassembler. */ 376 unsigned char favail; 377 }; 378 379 /* The flag operands table. */ 380 extern const struct arc_flag_operand arc_flag_operands[]; 381 extern const unsigned arc_num_flag_operands; 382 383 /* The flag's class structure. */ 384 struct arc_flag_class 385 { 386 /* Flag class. */ 387 flag_class_t flag_class; 388 389 /* List of valid flags (codes). */ 390 unsigned flags[256]; 391 }; 392 393 extern const struct arc_flag_class arc_flag_classes[]; 394 395 /* Structure for special cases. */ 396 struct arc_flag_special 397 { 398 /* Name of special case instruction. */ 399 const char *name; 400 401 /* List of flags applicable for special case instruction. */ 402 unsigned flags[32]; 403 }; 404 405 extern const struct arc_flag_special arc_flag_special_cases[]; 406 extern const unsigned arc_num_flag_special; 407 408 /* Relocation equivalence structure. */ 409 struct arc_reloc_equiv_tab 410 { 411 const char * name; /* String to lookup. */ 412 const char * mnemonic; /* Extra matching condition. */ 413 unsigned flags[32]; /* Extra matching condition. */ 414 signed int oldreloc; /* Old relocation. */ 415 signed int newreloc; /* New relocation. */ 416 }; 417 418 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; 419 extern const unsigned arc_num_equiv_tab; 420 421 /* Structure for operand operations for pseudo/alias instructions. */ 422 struct arc_operand_operation 423 { 424 /* The index for operand from operand array. */ 425 unsigned operand_idx; 426 427 /* Defines if it needs the operand inserted by the assembler or 428 whether this operand comes from the pseudo instruction's 429 operands. */ 430 unsigned char needs_insert; 431 432 /* Count we have to add to the operand. Use negative number to 433 subtract from the operand. Also use this number to add to 0 if 434 the operand needs to be inserted (i.e. needs_insert == 1). */ 435 int count; 436 437 /* Index of the operand to swap with. To be done AFTER applying 438 inc_count. */ 439 unsigned swap_operand_idx; 440 }; 441 442 /* Structure for pseudo/alias instructions. */ 443 struct arc_pseudo_insn 444 { 445 /* Mnemonic for pseudo/alias insn. */ 446 const char *mnemonic_p; 447 448 /* Mnemonic for real instruction. */ 449 const char *mnemonic_r; 450 451 /* Flag that will have to be added (if any). */ 452 const char *flag_r; 453 454 /* Amount of operands. */ 455 unsigned operand_cnt; 456 457 /* Array of operand operations. */ 458 struct arc_operand_operation operand[6]; 459 }; 460 461 extern const struct arc_pseudo_insn arc_pseudo_insns[]; 462 extern const unsigned arc_num_pseudo_insn; 463 464 /* Structure for AUXILIARY registers. */ 465 struct arc_aux_reg 466 { 467 /* Register address. */ 468 int address; 469 470 /* One bit flags for the opcode. These are primarily used to 471 indicate specific processors and environments support the 472 instructions. */ 473 unsigned cpu; 474 475 /* AUX register subclass. */ 476 insn_subclass_t subclass; 477 478 /* Register name. */ 479 const char *name; 480 481 /* Size of the string. */ 482 size_t length; 483 }; 484 485 extern const struct arc_aux_reg arc_aux_regs[]; 486 extern const unsigned arc_num_aux_regs; 487 488 extern const struct arc_opcode arc_relax_opcodes[]; 489 extern const unsigned arc_num_relax_opcodes; 490 491 /* Macro used for generating one class of NPS instructions. */ 492 #define NPS_CMEM_HIGH_VALUE 0x57f0 493 494 /* Macros to help generating regular pattern instructions. */ 495 #define FIELDA(word) (word & 0x3F) 496 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12)) 497 #define FIELDC(word) ((word & 0x3F) << 6) 498 #define FIELDF (0x01 << 15) 499 #define FIELDQ (0x1F) 500 501 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) 502 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) 503 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) 504 505 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP)) 506 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62)) 507 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62)) 508 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 509 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62)) 510 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62)) 511 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62)) 512 #define INSN3OP_0LL(MOP,SOP) \ 513 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62)) 514 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22)) 515 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 516 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22)) 517 #define INSN3OP_0LU(MOP,SOP) \ 518 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62)) 519 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22)) 520 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62)) 521 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22)) 522 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62)) 523 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62)) 524 #define INSN3OP_C0LL(MOP,SOP) \ 525 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62)) 526 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5)) 527 #define INSN3OP_C0LU(MOP,SOP) \ 528 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62)) 529 530 #define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) 531 #define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63))) 532 #define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63))) 533 #define MINSN3OP_ALL (~(FIELDF | FIELDA (63))) 534 #define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63))) 535 #define MINSN3OP_0LC (~(FIELDF | FIELDC (63))) 536 #define MINSN3OP_0BL (~(FIELDF | FIELDB (63))) 537 #define MINSN3OP_0LL (~(FIELDF)) 538 #define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) 539 #define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63))) 540 #define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63))) 541 #define MINSN3OP_0LU (~(FIELDF | FIELDC (63))) 542 #define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))) 543 #define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63))) 544 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))) 545 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63))) 546 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63))) 547 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ)) 548 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))) 549 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63))) 550 551 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP)) 552 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62)) 553 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)) 554 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 555 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22)) 556 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 557 558 #define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63))) 559 #define MINSN2OP_BL (~(FIELDF | FIELDB (63))) 560 #define MINSN2OP_0C (~(FIELDF | FIELDC (63))) 561 #define MINSN2OP_0L (~(FIELDF)) 562 #define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63))) 563 #define MINSN2OP_0U (~(FIELDF | FIELDC (63))) 564 565 /* Various constants used when defining an extension instruction. */ 566 #define ARC_SYNTAX_3OP (1 << 0) 567 #define ARC_SYNTAX_2OP (1 << 1) 568 #define ARC_SYNTAX_1OP (1 << 2) 569 #define ARC_SYNTAX_NOP (1 << 3) 570 #define ARC_SYNTAX_MASK (0x0F) 571 572 #define ARC_OP1_MUST_BE_IMM (1 << 0) 573 #define ARC_OP1_IMM_IMPLIED (1 << 1) 574 575 #define ARC_SUFFIX_NONE (1 << 0) 576 #define ARC_SUFFIX_COND (1 << 1) 577 #define ARC_SUFFIX_FLAG (1 << 2) 578 579 #define ARC_REGISTER_READONLY (1 << 0) 580 #define ARC_REGISTER_WRITEONLY (1 << 1) 581 #define ARC_REGISTER_NOSHORT_CUT (1 << 2) 582 583 /* Constants needed to initialize extension instructions. */ 584 extern const unsigned char flags_none[MAX_INSN_FLGS + 1]; 585 extern const unsigned char flags_f[MAX_INSN_FLGS + 1]; 586 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1]; 587 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1]; 588 589 extern const unsigned char arg_none[MAX_INSN_ARGS + 1]; 590 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1]; 591 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1]; 592 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1]; 593 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1]; 594 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1]; 595 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1]; 596 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1]; 597 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1]; 598 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1]; 599 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1]; 600 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1]; 601 602 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1]; 603 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1]; 604 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1]; 605 606 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1]; 607 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1]; 608 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1]; 609 610 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1]; 611 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1]; 612 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1]; 613 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1]; 614 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1]; 615 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1]; 616 617 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1]; 618 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1]; 619 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1]; 620 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1]; 621 622 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1]; 623 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1]; 624 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1]; 625 626 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP 627 Instruction Set Reference Manual v2.4 for a description of address types. */ 628 629 typedef enum 630 { 631 /* Addresses in memory. */ 632 633 /* Buffer descriptor. */ 634 ARC_NPS400_ADDRTYPE_BD, 635 636 /* Job identifier. */ 637 ARC_NPS400_ADDRTYPE_JID, 638 639 /* Linked Buffer Descriptor. */ 640 ARC_NPS400_ADDRTYPE_LBD, 641 642 /* Multicast Buffer Descriptor. */ 643 ARC_NPS400_ADDRTYPE_MBD, 644 645 /* Summarized Address. */ 646 ARC_NPS400_ADDRTYPE_SD, 647 648 /* SMEM Security Context Local Memory. */ 649 ARC_NPS400_ADDRTYPE_SM, 650 651 /* Extended Address. */ 652 ARC_NPS400_ADDRTYPE_XA, 653 654 /* Extended Summarized Address. */ 655 ARC_NPS400_ADDRTYPE_XD, 656 657 /* CMEM offset addresses. */ 658 659 /* On-demand Counter Descriptor. */ 660 ARC_NPS400_ADDRTYPE_CD, 661 662 /* CMEM Buffer Descriptor. */ 663 ARC_NPS400_ADDRTYPE_CBD, 664 665 /* CMEM Job Identifier. */ 666 ARC_NPS400_ADDRTYPE_CJID, 667 668 /* CMEM Linked Buffer Descriptor. */ 669 ARC_NPS400_ADDRTYPE_CLBD, 670 671 /* CMEM Offset. */ 672 ARC_NPS400_ADDRTYPE_CM, 673 674 /* CMEM Summarized Address. */ 675 ARC_NPS400_ADDRTYPE_CSD, 676 677 /* CMEM Extended Address. */ 678 ARC_NPS400_ADDRTYPE_CXA, 679 680 /* CMEM Extended Summarized Address. */ 681 ARC_NPS400_ADDRTYPE_CXD 682 683 } arc_nps_address_type; 684 685 #define ARC_NUM_ADDRTYPES 16 686 687 #ifdef __cplusplus 688 } 689 #endif 690 691 #endif /* OPCODE_ARC_H */ 692