1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "frame.h" 22 #include "solib-svr4.h" 23 #include "symtab.h" 24 #include "symfile.h" 25 #include "objfiles.h" 26 #include "gdbtypes.h" 27 #include "gdbcore.h" 28 #include "value.h" 29 #include "dis-asm.h" 30 #include "inferior.h" 31 #include "osabi.h" 32 #include "regcache.h" 33 #include "reggroups.h" 34 #include "regset.h" 35 36 #include "dummy-frame.h" 37 #include "dwarf2.h" 38 #include "dwarf2-frame.h" 39 #include "dwarf2loc.h" 40 #include "frame-base.h" 41 #include "frame-unwind.h" 42 43 #include "arch-utils.h" 44 #include "gdbarch.h" 45 #include "remote.h" 46 #include "serial.h" 47 48 #include "command.h" 49 #include "gdbcmd.h" 50 51 #include "xtensa-isa.h" 52 #include "xtensa-tdep.h" 53 #include "xtensa-config.h" 54 #include <algorithm> 55 56 57 static unsigned int xtensa_debug_level = 0; 58 59 #define DEBUGWARN(args...) \ 60 if (xtensa_debug_level > 0) \ 61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args) 62 63 #define DEBUGINFO(args...) \ 64 if (xtensa_debug_level > 1) \ 65 fprintf_unfiltered (gdb_stdlog, "(info ) " args) 66 67 #define DEBUGTRACE(args...) \ 68 if (xtensa_debug_level > 2) \ 69 fprintf_unfiltered (gdb_stdlog, "(trace) " args) 70 71 #define DEBUGVERB(args...) \ 72 if (xtensa_debug_level > 3) \ 73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args) 74 75 76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ 77 #define SP_ALIGNMENT 16 78 79 80 /* On Windowed ABI, we use a6 through a11 for passing arguments 81 to a function called by GDB because CALL4 is used. */ 82 #define ARGS_NUM_REGS 6 83 #define REGISTER_SIZE 4 84 85 86 /* Extract the call size from the return address or PS register. */ 87 #define PS_CALLINC_SHIFT 16 88 #define PS_CALLINC_MASK 0x00030000 89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) 90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) 91 92 /* On TX, hardware can be configured without Exception Option. 93 There is no PS register in this case. Inside XT-GDB, let us treat 94 it as a virtual read-only register always holding the same value. */ 95 #define TX_PS 0x20 96 97 /* ABI-independent macros. */ 98 #define ARG_NOF(gdbarch) \ 99 (gdbarch_tdep (gdbarch)->call_abi \ 100 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) 101 #define ARG_1ST(gdbarch) \ 102 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ 103 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ 104 : (gdbarch_tdep (gdbarch)->a0_base + 6)) 105 106 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction 107 indicates that the instruction is an ENTRY instruction. */ 108 109 #define XTENSA_IS_ENTRY(gdbarch, op1) \ 110 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ 111 ? ((op1) == 0x6c) : ((op1) == 0x36)) 112 113 #define XTENSA_ENTRY_LENGTH 3 114 115 /* windowing_enabled() returns true, if windowing is enabled. 116 WOE must be set to 1; EXCM to 0. 117 Note: We assume that EXCM is always 0 for XEA1. */ 118 119 #define PS_WOE (1<<18) 120 #define PS_EXC (1<<4) 121 122 /* Big enough to hold the size of the largest register in bytes. */ 123 #define XTENSA_MAX_REGISTER_SIZE 64 124 125 static int 126 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) 127 { 128 /* If we know CALL0 ABI is set explicitly, say it is Call0. */ 129 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) 130 return 0; 131 132 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); 133 } 134 135 /* Convert a live A-register number to the corresponding AR-register 136 number. */ 137 static int 138 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) 139 { 140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 141 int arreg; 142 143 arreg = a_regnum - tdep->a0_base; 144 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; 145 arreg &= tdep->num_aregs - 1; 146 147 return arreg + tdep->ar_base; 148 } 149 150 /* Convert a live AR-register number to the corresponding A-register order 151 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ 152 static int 153 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) 154 { 155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 156 int areg; 157 158 areg = ar_regnum - tdep->ar_base; 159 if (areg < 0 || areg >= tdep->num_aregs) 160 return -1; 161 areg = (areg - wb * 4) & (tdep->num_aregs - 1); 162 return (areg > 15) ? -1 : areg; 163 } 164 165 /* Read Xtensa register directly from the hardware. */ 166 static unsigned long 167 xtensa_read_register (int regnum) 168 { 169 ULONGEST value; 170 171 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); 172 return (unsigned long) value; 173 } 174 175 /* Write Xtensa register directly to the hardware. */ 176 static void 177 xtensa_write_register (int regnum, ULONGEST value) 178 { 179 regcache_raw_write_unsigned (get_current_regcache (), regnum, value); 180 } 181 182 /* Return the window size of the previous call to the function from which we 183 have just returned. 184 185 This function is used to extract the return value after a called function 186 has returned to the caller. On Xtensa, the register that holds the return 187 value (from the perspective of the caller) depends on what call 188 instruction was used. For now, we are assuming that the call instruction 189 precedes the current address, so we simply analyze the call instruction. 190 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' 191 method to call the inferior function. */ 192 193 static int 194 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) 195 { 196 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 197 int winsize = 4; 198 int insn; 199 gdb_byte buf[4]; 200 201 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); 202 203 /* Read the previous instruction (should be a call[x]{4|8|12}. */ 204 read_memory (pc-3, buf, 3); 205 insn = extract_unsigned_integer (buf, 3, byte_order); 206 207 /* Decode call instruction: 208 Little Endian 209 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 210 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 211 Big Endian 212 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET 213 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ 214 215 if (byte_order == BFD_ENDIAN_LITTLE) 216 { 217 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) 218 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ 219 } 220 else 221 { 222 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) 223 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ 224 } 225 return winsize; 226 } 227 228 229 /* REGISTER INFORMATION */ 230 231 /* Find register by name. */ 232 static int 233 xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name) 234 { 235 int i; 236 237 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) 238 239 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0) 240 return i; 241 242 return -1; 243 } 244 245 /* Returns the name of a register. */ 246 static const char * 247 xtensa_register_name (struct gdbarch *gdbarch, int regnum) 248 { 249 /* Return the name stored in the register map. */ 250 if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) 251 return gdbarch_tdep (gdbarch)->regmap[regnum].name; 252 253 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); 254 return 0; 255 } 256 257 /* Return the type of a register. Create a new type, if necessary. */ 258 259 static struct type * 260 xtensa_register_type (struct gdbarch *gdbarch, int regnum) 261 { 262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 263 264 /* Return signed integer for ARx and Ax registers. */ 265 if ((regnum >= tdep->ar_base 266 && regnum < tdep->ar_base + tdep->num_aregs) 267 || (regnum >= tdep->a0_base 268 && regnum < tdep->a0_base + 16)) 269 return builtin_type (gdbarch)->builtin_int; 270 271 if (regnum == gdbarch_pc_regnum (gdbarch) 272 || regnum == tdep->a0_base + 1) 273 return builtin_type (gdbarch)->builtin_data_ptr; 274 275 /* Return the stored type for all other registers. */ 276 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) 277 { 278 xtensa_register_t* reg = &tdep->regmap[regnum]; 279 280 /* Set ctype for this register (only the first time). */ 281 282 if (reg->ctype == 0) 283 { 284 struct ctype_cache *tp; 285 int size = reg->byte_size; 286 287 /* We always use the memory representation, 288 even if the register width is smaller. */ 289 switch (size) 290 { 291 case 1: 292 reg->ctype = builtin_type (gdbarch)->builtin_uint8; 293 break; 294 295 case 2: 296 reg->ctype = builtin_type (gdbarch)->builtin_uint16; 297 break; 298 299 case 4: 300 reg->ctype = builtin_type (gdbarch)->builtin_uint32; 301 break; 302 303 case 8: 304 reg->ctype = builtin_type (gdbarch)->builtin_uint64; 305 break; 306 307 case 16: 308 reg->ctype = builtin_type (gdbarch)->builtin_uint128; 309 break; 310 311 default: 312 for (tp = tdep->type_entries; tp != NULL; tp = tp->next) 313 if (tp->size == size) 314 break; 315 316 if (tp == NULL) 317 { 318 std::string name = string_printf ("int%d", size * 8); 319 320 tp = XNEW (struct ctype_cache); 321 tp->next = tdep->type_entries; 322 tdep->type_entries = tp; 323 tp->size = size; 324 tp->virtual_type 325 = arch_integer_type (gdbarch, size * 8, 1, name.c_str ()); 326 } 327 328 reg->ctype = tp->virtual_type; 329 } 330 } 331 return reg->ctype; 332 } 333 334 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); 335 return 0; 336 } 337 338 339 /* Return the 'local' register number for stubs, dwarf2, etc. 340 The debugging information enumerates registers starting from 0 for A0 341 to n for An. So, we only have to add the base number for A0. */ 342 343 static int 344 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) 345 { 346 int i; 347 348 if (regnum >= 0 && regnum < 16) 349 return gdbarch_tdep (gdbarch)->a0_base + regnum; 350 351 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) 352 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) 353 return i; 354 355 return -1; 356 } 357 358 359 /* Write the bits of a masked register to the various registers. 360 Only the masked areas of these registers are modified; the other 361 fields are untouched. The size of masked registers is always less 362 than or equal to 32 bits. */ 363 364 static void 365 xtensa_register_write_masked (struct regcache *regcache, 366 xtensa_register_t *reg, const gdb_byte *buffer) 367 { 368 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; 369 const xtensa_mask_t *mask = reg->mask; 370 371 int shift = 0; /* Shift for next mask (mod 32). */ 372 int start, size; /* Start bit and size of current mask. */ 373 374 unsigned int *ptr = value; 375 unsigned int regval, m, mem = 0; 376 377 int bytesize = reg->byte_size; 378 int bitsize = bytesize * 8; 379 int i, r; 380 381 DEBUGTRACE ("xtensa_register_write_masked ()\n"); 382 383 /* Copy the masked register to host byte-order. */ 384 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) 385 for (i = 0; i < bytesize; i++) 386 { 387 mem >>= 8; 388 mem |= (buffer[bytesize - i - 1] << 24); 389 if ((i & 3) == 3) 390 *ptr++ = mem; 391 } 392 else 393 for (i = 0; i < bytesize; i++) 394 { 395 mem >>= 8; 396 mem |= (buffer[i] << 24); 397 if ((i & 3) == 3) 398 *ptr++ = mem; 399 } 400 401 /* We might have to shift the final value: 402 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, 403 bytesize & 3 == x -> shift (4-x) * 8. */ 404 405 *ptr = mem >> (((0 - bytesize) & 3) * 8); 406 ptr = value; 407 mem = *ptr; 408 409 /* Write the bits to the masked areas of the other registers. */ 410 for (i = 0; i < mask->count; i++) 411 { 412 start = mask->mask[i].bit_start; 413 size = mask->mask[i].bit_size; 414 regval = mem >> shift; 415 416 if ((shift += size) > bitsize) 417 error (_("size of all masks is larger than the register")); 418 419 if (shift >= 32) 420 { 421 mem = *(++ptr); 422 shift -= 32; 423 bitsize -= 32; 424 425 if (shift > 0) 426 regval |= mem << (size - shift); 427 } 428 429 /* Make sure we have a valid register. */ 430 r = mask->mask[i].reg_num; 431 if (r >= 0 && size > 0) 432 { 433 /* Don't overwrite the unmasked areas. */ 434 ULONGEST old_val; 435 regcache_cooked_read_unsigned (regcache, r, &old_val); 436 m = 0xffffffff >> (32 - size) << start; 437 regval <<= start; 438 regval = (regval & m) | (old_val & ~m); 439 regcache_cooked_write_unsigned (regcache, r, regval); 440 } 441 } 442 } 443 444 445 /* Read a tie state or mapped registers. Read the masked areas 446 of the registers and assemble them into a single value. */ 447 448 static enum register_status 449 xtensa_register_read_masked (readable_regcache *regcache, 450 xtensa_register_t *reg, gdb_byte *buffer) 451 { 452 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; 453 const xtensa_mask_t *mask = reg->mask; 454 455 int shift = 0; 456 int start, size; 457 458 unsigned int *ptr = value; 459 unsigned int regval, mem = 0; 460 461 int bytesize = reg->byte_size; 462 int bitsize = bytesize * 8; 463 int i; 464 465 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", 466 reg->name == 0 ? "" : reg->name); 467 468 /* Assemble the register from the masked areas of other registers. */ 469 for (i = 0; i < mask->count; i++) 470 { 471 int r = mask->mask[i].reg_num; 472 if (r >= 0) 473 { 474 enum register_status status; 475 ULONGEST val; 476 477 status = regcache->cooked_read (r, &val); 478 if (status != REG_VALID) 479 return status; 480 regval = (unsigned int) val; 481 } 482 else 483 regval = 0; 484 485 start = mask->mask[i].bit_start; 486 size = mask->mask[i].bit_size; 487 488 regval >>= start; 489 490 if (size < 32) 491 regval &= (0xffffffff >> (32 - size)); 492 493 mem |= regval << shift; 494 495 if ((shift += size) > bitsize) 496 error (_("size of all masks is larger than the register")); 497 498 if (shift >= 32) 499 { 500 *ptr++ = mem; 501 bitsize -= 32; 502 shift -= 32; 503 504 if (shift == 0) 505 mem = 0; 506 else 507 mem = regval >> (size - shift); 508 } 509 } 510 511 if (shift > 0) 512 *ptr = mem; 513 514 /* Copy value to target byte order. */ 515 ptr = value; 516 mem = *ptr; 517 518 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) 519 for (i = 0; i < bytesize; i++) 520 { 521 if ((i & 3) == 0) 522 mem = *ptr++; 523 buffer[bytesize - i - 1] = mem & 0xff; 524 mem >>= 8; 525 } 526 else 527 for (i = 0; i < bytesize; i++) 528 { 529 if ((i & 3) == 0) 530 mem = *ptr++; 531 buffer[i] = mem & 0xff; 532 mem >>= 8; 533 } 534 535 return REG_VALID; 536 } 537 538 539 /* Read pseudo registers. */ 540 541 static enum register_status 542 xtensa_pseudo_register_read (struct gdbarch *gdbarch, 543 readable_regcache *regcache, 544 int regnum, 545 gdb_byte *buffer) 546 { 547 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", 548 regnum, xtensa_register_name (gdbarch, regnum)); 549 550 /* Read aliases a0..a15, if this is a Windowed ABI. */ 551 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers 552 && (regnum >= gdbarch_tdep (gdbarch)->a0_base) 553 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) 554 { 555 ULONGEST value; 556 enum register_status status; 557 558 status = regcache->raw_read (gdbarch_tdep (gdbarch)->wb_regnum, 559 &value); 560 if (status != REG_VALID) 561 return status; 562 regnum = arreg_number (gdbarch, regnum, value); 563 } 564 565 /* We can always read non-pseudo registers. */ 566 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 567 return regcache->raw_read (regnum, buffer); 568 569 /* We have to find out how to deal with priveleged registers. 570 Let's treat them as pseudo-registers, but we cannot read/write them. */ 571 572 else if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only 573 || regnum < gdbarch_tdep (gdbarch)->a0_base) 574 { 575 buffer[0] = (gdb_byte)0; 576 buffer[1] = (gdb_byte)0; 577 buffer[2] = (gdb_byte)0; 578 buffer[3] = (gdb_byte)0; 579 return REG_VALID; 580 } 581 /* Pseudo registers. */ 582 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) 583 { 584 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; 585 xtensa_register_type_t type = reg->type; 586 int flags = gdbarch_tdep (gdbarch)->target_flags; 587 588 /* We cannot read Unknown or Unmapped registers. */ 589 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) 590 { 591 if ((flags & xtTargetFlagsNonVisibleRegs) == 0) 592 { 593 warning (_("cannot read register %s"), 594 xtensa_register_name (gdbarch, regnum)); 595 return REG_VALID; 596 } 597 } 598 599 /* Some targets cannot read TIE register files. */ 600 else if (type == xtRegisterTypeTieRegfile) 601 { 602 /* Use 'fetch' to get register? */ 603 if (flags & xtTargetFlagsUseFetchStore) 604 { 605 warning (_("cannot read register")); 606 return REG_VALID; 607 } 608 609 /* On some targets (esp. simulators), we can always read the reg. */ 610 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) 611 { 612 warning (_("cannot read register")); 613 return REG_VALID; 614 } 615 } 616 617 /* We can always read mapped registers. */ 618 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) 619 return xtensa_register_read_masked (regcache, reg, buffer); 620 621 /* Assume that we can read the register. */ 622 return regcache->raw_read (regnum, buffer); 623 } 624 else 625 internal_error (__FILE__, __LINE__, 626 _("invalid register number %d"), regnum); 627 } 628 629 630 /* Write pseudo registers. */ 631 632 static void 633 xtensa_pseudo_register_write (struct gdbarch *gdbarch, 634 struct regcache *regcache, 635 int regnum, 636 const gdb_byte *buffer) 637 { 638 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", 639 regnum, xtensa_register_name (gdbarch, regnum)); 640 641 /* Renumber register, if aliase a0..a15 on Windowed ABI. */ 642 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers 643 && (regnum >= gdbarch_tdep (gdbarch)->a0_base) 644 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) 645 { 646 ULONGEST value; 647 regcache_raw_read_unsigned (regcache, 648 gdbarch_tdep (gdbarch)->wb_regnum, &value); 649 regnum = arreg_number (gdbarch, regnum, value); 650 } 651 652 /* We can always write 'core' registers. 653 Note: We might have converted Ax->ARy. */ 654 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 655 regcache->raw_write (regnum, buffer); 656 657 /* We have to find out how to deal with priveleged registers. 658 Let's treat them as pseudo-registers, but we cannot read/write them. */ 659 660 else if (regnum < gdbarch_tdep (gdbarch)->a0_base) 661 { 662 return; 663 } 664 /* Pseudo registers. */ 665 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) 666 { 667 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; 668 xtensa_register_type_t type = reg->type; 669 int flags = gdbarch_tdep (gdbarch)->target_flags; 670 671 /* On most targets, we cannot write registers 672 of type "Unknown" or "Unmapped". */ 673 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) 674 { 675 if ((flags & xtTargetFlagsNonVisibleRegs) == 0) 676 { 677 warning (_("cannot write register %s"), 678 xtensa_register_name (gdbarch, regnum)); 679 return; 680 } 681 } 682 683 /* Some targets cannot read TIE register files. */ 684 else if (type == xtRegisterTypeTieRegfile) 685 { 686 /* Use 'store' to get register? */ 687 if (flags & xtTargetFlagsUseFetchStore) 688 { 689 warning (_("cannot write register")); 690 return; 691 } 692 693 /* On some targets (esp. simulators), we can always write 694 the register. */ 695 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) 696 { 697 warning (_("cannot write register")); 698 return; 699 } 700 } 701 702 /* We can always write mapped registers. */ 703 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) 704 { 705 xtensa_register_write_masked (regcache, reg, buffer); 706 return; 707 } 708 709 /* Assume that we can write the register. */ 710 regcache->raw_write (regnum, buffer); 711 } 712 else 713 internal_error (__FILE__, __LINE__, 714 _("invalid register number %d"), regnum); 715 } 716 717 static struct reggroup *xtensa_ar_reggroup; 718 static struct reggroup *xtensa_user_reggroup; 719 static struct reggroup *xtensa_vectra_reggroup; 720 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; 721 722 static void 723 xtensa_init_reggroups (void) 724 { 725 int i; 726 727 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); 728 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); 729 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); 730 731 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) 732 xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i), USER_REGGROUP); 733 } 734 735 static void 736 xtensa_add_reggroups (struct gdbarch *gdbarch) 737 { 738 int i; 739 740 /* Predefined groups. */ 741 reggroup_add (gdbarch, all_reggroup); 742 reggroup_add (gdbarch, save_reggroup); 743 reggroup_add (gdbarch, restore_reggroup); 744 reggroup_add (gdbarch, system_reggroup); 745 reggroup_add (gdbarch, vector_reggroup); 746 reggroup_add (gdbarch, general_reggroup); 747 reggroup_add (gdbarch, float_reggroup); 748 749 /* Xtensa-specific groups. */ 750 reggroup_add (gdbarch, xtensa_ar_reggroup); 751 reggroup_add (gdbarch, xtensa_user_reggroup); 752 reggroup_add (gdbarch, xtensa_vectra_reggroup); 753 754 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) 755 reggroup_add (gdbarch, xtensa_cp[i]); 756 } 757 758 static int 759 xtensa_coprocessor_register_group (struct reggroup *group) 760 { 761 int i; 762 763 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) 764 if (group == xtensa_cp[i]) 765 return i; 766 767 return -1; 768 } 769 770 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ 771 | XTENSA_REGISTER_FLAGS_WRITABLE \ 772 | XTENSA_REGISTER_FLAGS_VOLATILE) 773 774 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ 775 | XTENSA_REGISTER_FLAGS_WRITABLE) 776 777 static int 778 xtensa_register_reggroup_p (struct gdbarch *gdbarch, 779 int regnum, 780 struct reggroup *group) 781 { 782 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; 783 xtensa_register_type_t type = reg->type; 784 xtensa_register_group_t rg = reg->group; 785 int cp_number; 786 787 if (group == save_reggroup) 788 /* Every single register should be included into the list of registers 789 to be watched for changes while using -data-list-changed-registers. */ 790 return 1; 791 792 /* First, skip registers that are not visible to this target 793 (unknown and unmapped registers when not using ISS). */ 794 795 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) 796 return 0; 797 if (group == all_reggroup) 798 return 1; 799 if (group == xtensa_ar_reggroup) 800 return rg & xtRegisterGroupAddrReg; 801 if (group == xtensa_user_reggroup) 802 return rg & xtRegisterGroupUser; 803 if (group == float_reggroup) 804 return rg & xtRegisterGroupFloat; 805 if (group == general_reggroup) 806 return rg & xtRegisterGroupGeneral; 807 if (group == system_reggroup) 808 return rg & xtRegisterGroupState; 809 if (group == vector_reggroup || group == xtensa_vectra_reggroup) 810 return rg & xtRegisterGroupVectra; 811 if (group == restore_reggroup) 812 return (regnum < gdbarch_num_regs (gdbarch) 813 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); 814 cp_number = xtensa_coprocessor_register_group (group); 815 if (cp_number >= 0) 816 return rg & (xtRegisterGroupCP0 << cp_number); 817 else 818 return 1; 819 } 820 821 822 /* Supply register REGNUM from the buffer specified by GREGS and LEN 823 in the general-purpose register set REGSET to register cache 824 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ 825 826 static void 827 xtensa_supply_gregset (const struct regset *regset, 828 struct regcache *rc, 829 int regnum, 830 const void *gregs, 831 size_t len) 832 { 833 const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs; 834 struct gdbarch *gdbarch = rc->arch (); 835 int i; 836 837 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); 838 839 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) 840 rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); 841 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) 842 rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); 843 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) 844 rc->raw_supply (gdbarch_tdep (gdbarch)->wb_regnum, 845 (char *) ®s->windowbase); 846 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) 847 rc->raw_supply (gdbarch_tdep (gdbarch)->ws_regnum, 848 (char *) ®s->windowstart); 849 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) 850 rc->raw_supply (gdbarch_tdep (gdbarch)->lbeg_regnum, 851 (char *) ®s->lbeg); 852 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) 853 rc->raw_supply (gdbarch_tdep (gdbarch)->lend_regnum, 854 (char *) ®s->lend); 855 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) 856 rc->raw_supply (gdbarch_tdep (gdbarch)->lcount_regnum, 857 (char *) ®s->lcount); 858 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) 859 rc->raw_supply (gdbarch_tdep (gdbarch)->sar_regnum, 860 (char *) ®s->sar); 861 if (regnum >=gdbarch_tdep (gdbarch)->ar_base 862 && regnum < gdbarch_tdep (gdbarch)->ar_base 863 + gdbarch_tdep (gdbarch)->num_aregs) 864 rc->raw_supply 865 (regnum, (char *) ®s->ar[regnum - gdbarch_tdep (gdbarch)->ar_base]); 866 else if (regnum == -1) 867 { 868 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) 869 rc->raw_supply (gdbarch_tdep (gdbarch)->ar_base + i, 870 (char *) ®s->ar[i]); 871 } 872 } 873 874 875 /* Xtensa register set. */ 876 877 static struct regset 878 xtensa_gregset = 879 { 880 NULL, 881 xtensa_supply_gregset 882 }; 883 884 885 /* Iterate over supported core file register note sections. */ 886 887 static void 888 xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch, 889 iterate_over_regset_sections_cb *cb, 890 void *cb_data, 891 const struct regcache *regcache) 892 { 893 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n"); 894 895 cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t), 896 &xtensa_gregset, NULL, cb_data); 897 } 898 899 900 /* Handling frames. */ 901 902 /* Number of registers to save in case of Windowed ABI. */ 903 #define XTENSA_NUM_SAVED_AREGS 12 904 905 /* Frame cache part for Windowed ABI. */ 906 typedef struct xtensa_windowed_frame_cache 907 { 908 int wb; /* WINDOWBASE of the previous frame. */ 909 int callsize; /* Call size of this frame. */ 910 int ws; /* WINDOWSTART of the previous frame. It keeps track of 911 life windows only. If there is no bit set for the 912 window, that means it had been already spilled 913 because of window overflow. */ 914 915 /* Addresses of spilled A-registers. 916 AREGS[i] == -1, if corresponding AR is alive. */ 917 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; 918 } xtensa_windowed_frame_cache_t; 919 920 /* Call0 ABI Definitions. */ 921 922 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue 923 analysis. */ 924 #define C0_CLESV 12 /* Callee-saved registers are here and up. */ 925 #define C0_SP 1 /* Register used as SP. */ 926 #define C0_FP 15 /* Register used as FP. */ 927 #define C0_RA 0 /* Register used as return address. */ 928 #define C0_ARGS 2 /* Register used as first arg/retval. */ 929 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ 930 931 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each 932 A-register where the current content of the reg came from (in terms 933 of an original reg and a constant). Negative values of c0_rt[n].fp_reg 934 mean that the orignal content of the register was saved to the stack. 935 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't 936 know where SP will end up until the entire prologue has been analyzed. */ 937 938 #define C0_CONST -1 /* fr_reg value if register contains a constant. */ 939 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ 940 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ 941 942 extern xtensa_isa xtensa_default_isa; 943 944 typedef struct xtensa_c0reg 945 { 946 int fr_reg; /* original register from which register content 947 is derived, or C0_CONST, or C0_INEXP. */ 948 int fr_ofs; /* constant offset from reg, or immediate value. */ 949 int to_stk; /* offset from original SP to register (4-byte aligned), 950 or C0_NOSTK if register has not been saved. */ 951 } xtensa_c0reg_t; 952 953 /* Frame cache part for Call0 ABI. */ 954 typedef struct xtensa_call0_frame_cache 955 { 956 int c0_frmsz; /* Stack frame size. */ 957 int c0_hasfp; /* Current frame uses frame pointer. */ 958 int fp_regnum; /* A-register used as FP. */ 959 int c0_fp; /* Actual value of frame pointer. */ 960 int c0_fpalign; /* Dinamic adjustment for the stack 961 pointer. It's an AND mask. Zero, 962 if alignment was not adjusted. */ 963 int c0_old_sp; /* In case of dynamic adjustment, it is 964 a register holding unaligned sp. 965 C0_INEXP, when undefined. */ 966 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a 967 stack offset. C0_NOSTK otherwise. */ 968 969 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ 970 } xtensa_call0_frame_cache_t; 971 972 typedef struct xtensa_frame_cache 973 { 974 CORE_ADDR base; /* Stack pointer of this frame. */ 975 CORE_ADDR pc; /* PC of this frame at the function entry point. */ 976 CORE_ADDR ra; /* The raw return address of this frame. */ 977 CORE_ADDR ps; /* The PS register of the previous (older) frame. */ 978 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */ 979 int call0; /* It's a call0 framework (else windowed). */ 980 union 981 { 982 xtensa_windowed_frame_cache_t wd; /* call0 == false. */ 983 xtensa_call0_frame_cache_t c0; /* call0 == true. */ 984 }; 985 } xtensa_frame_cache_t; 986 987 988 static struct xtensa_frame_cache * 989 xtensa_alloc_frame_cache (int windowed) 990 { 991 xtensa_frame_cache_t *cache; 992 int i; 993 994 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); 995 996 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); 997 998 cache->base = 0; 999 cache->pc = 0; 1000 cache->ra = 0; 1001 cache->ps = 0; 1002 cache->prev_sp = 0; 1003 cache->call0 = !windowed; 1004 if (cache->call0) 1005 { 1006 cache->c0.c0_frmsz = -1; 1007 cache->c0.c0_hasfp = 0; 1008 cache->c0.fp_regnum = -1; 1009 cache->c0.c0_fp = -1; 1010 cache->c0.c0_fpalign = 0; 1011 cache->c0.c0_old_sp = C0_INEXP; 1012 cache->c0.c0_sp_ofs = C0_NOSTK; 1013 1014 for (i = 0; i < C0_NREGS; i++) 1015 { 1016 cache->c0.c0_rt[i].fr_reg = i; 1017 cache->c0.c0_rt[i].fr_ofs = 0; 1018 cache->c0.c0_rt[i].to_stk = C0_NOSTK; 1019 } 1020 } 1021 else 1022 { 1023 cache->wd.wb = 0; 1024 cache->wd.ws = 0; 1025 cache->wd.callsize = -1; 1026 1027 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) 1028 cache->wd.aregs[i] = -1; 1029 } 1030 return cache; 1031 } 1032 1033 1034 static CORE_ADDR 1035 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 1036 { 1037 return address & ~15; 1038 } 1039 1040 1041 static CORE_ADDR 1042 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1043 { 1044 gdb_byte buf[8]; 1045 CORE_ADDR pc; 1046 1047 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", 1048 host_address_to_string (next_frame)); 1049 1050 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); 1051 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1052 1053 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); 1054 1055 return pc; 1056 } 1057 1058 1059 static struct frame_id 1060 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1061 { 1062 CORE_ADDR pc, fp; 1063 1064 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ 1065 1066 pc = get_frame_pc (this_frame); 1067 fp = get_frame_register_unsigned 1068 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); 1069 1070 /* Make dummy frame ID unique by adding a constant. */ 1071 return frame_id_build (fp + SP_ALIGNMENT, pc); 1072 } 1073 1074 /* Returns true, if instruction to execute next is unique to Xtensa Window 1075 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */ 1076 1077 static int 1078 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc) 1079 { 1080 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1081 unsigned int insn = read_memory_integer (pc, 4, byte_order); 1082 unsigned int code; 1083 1084 if (byte_order == BFD_ENDIAN_BIG) 1085 { 1086 /* Check, if this is L32E or S32E. */ 1087 code = insn & 0xf000ff00; 1088 if ((code == 0x00009000) || (code == 0x00009400)) 1089 return 1; 1090 /* Check, if this is RFWU or RFWO. */ 1091 code = insn & 0xffffff00; 1092 return ((code == 0x00430000) || (code == 0x00530000)); 1093 } 1094 else 1095 { 1096 /* Check, if this is L32E or S32E. */ 1097 code = insn & 0x00ff000f; 1098 if ((code == 0x090000) || (code == 0x490000)) 1099 return 1; 1100 /* Check, if this is RFWU or RFWO. */ 1101 code = insn & 0x00ffffff; 1102 return ((code == 0x00003400) || (code == 0x00003500)); 1103 } 1104 } 1105 1106 /* Returns the best guess about which register is a frame pointer 1107 for the function containing CURRENT_PC. */ 1108 1109 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ 1110 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ 1111 1112 static unsigned int 1113 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) 1114 { 1115 #define RETURN_FP goto done 1116 1117 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; 1118 CORE_ADDR start_addr; 1119 xtensa_isa isa; 1120 xtensa_insnbuf ins, slot; 1121 gdb_byte ibuf[XTENSA_ISA_BSZ]; 1122 CORE_ADDR ia, bt, ba; 1123 xtensa_format ifmt; 1124 int ilen, islots, is; 1125 xtensa_opcode opc; 1126 const char *opcname; 1127 1128 find_pc_partial_function (current_pc, NULL, &start_addr, NULL); 1129 if (start_addr == 0) 1130 return fp_regnum; 1131 1132 isa = xtensa_default_isa; 1133 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); 1134 ins = xtensa_insnbuf_alloc (isa); 1135 slot = xtensa_insnbuf_alloc (isa); 1136 ba = 0; 1137 1138 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) 1139 { 1140 if (ia + xtensa_isa_maxlength (isa) > bt) 1141 { 1142 ba = ia; 1143 bt = (ba + XTENSA_ISA_BSZ) < current_pc 1144 ? ba + XTENSA_ISA_BSZ : current_pc; 1145 if (target_read_memory (ba, ibuf, bt - ba) != 0) 1146 RETURN_FP; 1147 } 1148 1149 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); 1150 ifmt = xtensa_format_decode (isa, ins); 1151 if (ifmt == XTENSA_UNDEFINED) 1152 RETURN_FP; 1153 ilen = xtensa_format_length (isa, ifmt); 1154 if (ilen == XTENSA_UNDEFINED) 1155 RETURN_FP; 1156 islots = xtensa_format_num_slots (isa, ifmt); 1157 if (islots == XTENSA_UNDEFINED) 1158 RETURN_FP; 1159 1160 for (is = 0; is < islots; ++is) 1161 { 1162 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) 1163 RETURN_FP; 1164 1165 opc = xtensa_opcode_decode (isa, ifmt, is, slot); 1166 if (opc == XTENSA_UNDEFINED) 1167 RETURN_FP; 1168 1169 opcname = xtensa_opcode_name (isa, opc); 1170 1171 if (strcasecmp (opcname, "mov.n") == 0 1172 || strcasecmp (opcname, "or") == 0) 1173 { 1174 unsigned int register_operand; 1175 1176 /* Possible candidate for setting frame pointer 1177 from A1. This is what we are looking for. */ 1178 1179 if (xtensa_operand_get_field (isa, opc, 1, ifmt, 1180 is, slot, ®ister_operand) != 0) 1181 RETURN_FP; 1182 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) 1183 RETURN_FP; 1184 if (register_operand == 1) /* Mov{.n} FP A1. */ 1185 { 1186 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, 1187 ®ister_operand) != 0) 1188 RETURN_FP; 1189 if (xtensa_operand_decode (isa, opc, 0, 1190 ®ister_operand) != 0) 1191 RETURN_FP; 1192 1193 fp_regnum 1194 = gdbarch_tdep (gdbarch)->a0_base + register_operand; 1195 RETURN_FP; 1196 } 1197 } 1198 1199 if ( 1200 /* We have problems decoding the memory. */ 1201 opcname == NULL 1202 || strcasecmp (opcname, "ill") == 0 1203 || strcasecmp (opcname, "ill.n") == 0 1204 /* Hit planted breakpoint. */ 1205 || strcasecmp (opcname, "break") == 0 1206 || strcasecmp (opcname, "break.n") == 0 1207 /* Flow control instructions finish prologue. */ 1208 || xtensa_opcode_is_branch (isa, opc) > 0 1209 || xtensa_opcode_is_jump (isa, opc) > 0 1210 || xtensa_opcode_is_loop (isa, opc) > 0 1211 || xtensa_opcode_is_call (isa, opc) > 0 1212 || strcasecmp (opcname, "simcall") == 0 1213 || strcasecmp (opcname, "syscall") == 0) 1214 /* Can not continue analysis. */ 1215 RETURN_FP; 1216 } 1217 } 1218 done: 1219 xtensa_insnbuf_free(isa, slot); 1220 xtensa_insnbuf_free(isa, ins); 1221 return fp_regnum; 1222 } 1223 1224 /* The key values to identify the frame using "cache" are 1225 1226 cache->base = SP (or best guess about FP) of this frame; 1227 cache->pc = entry-PC (entry point of the frame function); 1228 cache->prev_sp = SP of the previous frame. */ 1229 1230 static void 1231 call0_frame_cache (struct frame_info *this_frame, 1232 xtensa_frame_cache_t *cache, CORE_ADDR pc); 1233 1234 static void 1235 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, 1236 xtensa_frame_cache_t *cache, 1237 CORE_ADDR pc); 1238 1239 static struct xtensa_frame_cache * 1240 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) 1241 { 1242 xtensa_frame_cache_t *cache; 1243 CORE_ADDR ra, wb, ws, pc, sp, ps; 1244 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1245 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1246 unsigned int fp_regnum; 1247 int windowed, ps_regnum; 1248 1249 if (*this_cache) 1250 return (struct xtensa_frame_cache *) *this_cache; 1251 1252 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); 1253 ps_regnum = gdbarch_ps_regnum (gdbarch); 1254 ps = (ps_regnum >= 0 1255 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS); 1256 1257 windowed = windowing_enabled (gdbarch, ps); 1258 1259 /* Get pristine xtensa-frame. */ 1260 cache = xtensa_alloc_frame_cache (windowed); 1261 *this_cache = cache; 1262 1263 if (windowed) 1264 { 1265 LONGEST op1; 1266 1267 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ 1268 wb = get_frame_register_unsigned (this_frame, 1269 gdbarch_tdep (gdbarch)->wb_regnum); 1270 ws = get_frame_register_unsigned (this_frame, 1271 gdbarch_tdep (gdbarch)->ws_regnum); 1272 1273 if (safe_read_memory_integer (pc, 1, byte_order, &op1) 1274 && XTENSA_IS_ENTRY (gdbarch, op1)) 1275 { 1276 int callinc = CALLINC (ps); 1277 ra = get_frame_register_unsigned 1278 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); 1279 1280 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ 1281 cache->wd.callsize = 0; 1282 cache->wd.wb = wb; 1283 cache->wd.ws = ws; 1284 cache->prev_sp = get_frame_register_unsigned 1285 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); 1286 1287 /* This only can be the outermost frame since we are 1288 just about to execute ENTRY. SP hasn't been set yet. 1289 We can assume any frame size, because it does not 1290 matter, and, let's fake frame base in cache. */ 1291 cache->base = cache->prev_sp - 16; 1292 1293 cache->pc = pc; 1294 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); 1295 cache->ps = (ps & ~PS_CALLINC_MASK) 1296 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); 1297 1298 return cache; 1299 } 1300 else 1301 { 1302 fp_regnum = xtensa_scan_prologue (gdbarch, pc); 1303 ra = get_frame_register_unsigned (this_frame, 1304 gdbarch_tdep (gdbarch)->a0_base); 1305 cache->wd.callsize = WINSIZE (ra); 1306 cache->wd.wb = (wb - cache->wd.callsize / 4) 1307 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); 1308 cache->wd.ws = ws & ~(1 << wb); 1309 1310 cache->pc = get_frame_func (this_frame); 1311 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); 1312 cache->ps = (ps & ~PS_CALLINC_MASK) 1313 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); 1314 } 1315 1316 if (cache->wd.ws == 0) 1317 { 1318 int i; 1319 1320 /* Set A0...A3. */ 1321 sp = get_frame_register_unsigned 1322 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; 1323 1324 for (i = 0; i < 4; i++, sp += 4) 1325 { 1326 cache->wd.aregs[i] = sp; 1327 } 1328 1329 if (cache->wd.callsize > 4) 1330 { 1331 /* Set A4...A7/A11. */ 1332 /* Get the SP of the frame previous to the previous one. 1333 To achieve this, we have to dereference SP twice. */ 1334 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); 1335 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); 1336 sp -= cache->wd.callsize * 4; 1337 1338 for ( i = 4; i < cache->wd.callsize; i++, sp += 4) 1339 { 1340 cache->wd.aregs[i] = sp; 1341 } 1342 } 1343 } 1344 1345 if ((cache->prev_sp == 0) && ( ra != 0 )) 1346 /* If RA is equal to 0 this frame is an outermost frame. Leave 1347 cache->prev_sp unchanged marking the boundary of the frame stack. */ 1348 { 1349 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) 1350 { 1351 /* Register window overflow already happened. 1352 We can read caller's SP from the proper spill loction. */ 1353 sp = get_frame_register_unsigned 1354 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); 1355 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); 1356 } 1357 else 1358 { 1359 /* Read caller's frame SP directly from the previous window. */ 1360 int regnum = arreg_number 1361 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, 1362 cache->wd.wb); 1363 1364 cache->prev_sp = xtensa_read_register (regnum); 1365 } 1366 } 1367 } 1368 else if (xtensa_window_interrupt_insn (gdbarch, pc)) 1369 { 1370 /* Execution stopped inside Xtensa Window Interrupt Handler. */ 1371 1372 xtensa_window_interrupt_frame_cache (this_frame, cache, pc); 1373 /* Everything was set already, including cache->base. */ 1374 return cache; 1375 } 1376 else /* Call0 framework. */ 1377 { 1378 call0_frame_cache (this_frame, cache, pc); 1379 fp_regnum = cache->c0.fp_regnum; 1380 } 1381 1382 cache->base = get_frame_register_unsigned (this_frame, fp_regnum); 1383 1384 return cache; 1385 } 1386 1387 static int xtensa_session_once_reported = 1; 1388 1389 /* Report a problem with prologue analysis while doing backtracing. 1390 But, do it only once to avoid annoyng repeated messages. */ 1391 1392 static void 1393 warning_once (void) 1394 { 1395 if (xtensa_session_once_reported == 0) 1396 warning (_("\ 1397 \nUnrecognised function prologue. Stack trace cannot be resolved. \ 1398 This message will not be repeated in this session.\n")); 1399 1400 xtensa_session_once_reported = 1; 1401 } 1402 1403 1404 static void 1405 xtensa_frame_this_id (struct frame_info *this_frame, 1406 void **this_cache, 1407 struct frame_id *this_id) 1408 { 1409 struct xtensa_frame_cache *cache = 1410 xtensa_frame_cache (this_frame, this_cache); 1411 1412 if (cache->prev_sp == 0) 1413 return; 1414 1415 (*this_id) = frame_id_build (cache->prev_sp, cache->pc); 1416 } 1417 1418 static struct value * 1419 xtensa_frame_prev_register (struct frame_info *this_frame, 1420 void **this_cache, 1421 int regnum) 1422 { 1423 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1424 struct xtensa_frame_cache *cache; 1425 ULONGEST saved_reg = 0; 1426 int done = 1; 1427 1428 if (*this_cache == NULL) 1429 *this_cache = xtensa_frame_cache (this_frame, this_cache); 1430 cache = (struct xtensa_frame_cache *) *this_cache; 1431 1432 if (regnum ==gdbarch_pc_regnum (gdbarch)) 1433 saved_reg = cache->ra; 1434 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) 1435 saved_reg = cache->prev_sp; 1436 else if (!cache->call0) 1437 { 1438 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) 1439 saved_reg = cache->wd.ws; 1440 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) 1441 saved_reg = cache->wd.wb; 1442 else if (regnum == gdbarch_ps_regnum (gdbarch)) 1443 saved_reg = cache->ps; 1444 else 1445 done = 0; 1446 } 1447 else 1448 done = 0; 1449 1450 if (done) 1451 return frame_unwind_got_constant (this_frame, regnum, saved_reg); 1452 1453 if (!cache->call0) /* Windowed ABI. */ 1454 { 1455 /* Convert A-register numbers to AR-register numbers, 1456 if we deal with A-register. */ 1457 if (regnum >= gdbarch_tdep (gdbarch)->a0_base 1458 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) 1459 regnum = arreg_number (gdbarch, regnum, cache->wd.wb); 1460 1461 /* Check, if we deal with AR-register saved on stack. */ 1462 if (regnum >= gdbarch_tdep (gdbarch)->ar_base 1463 && regnum <= (gdbarch_tdep (gdbarch)->ar_base 1464 + gdbarch_tdep (gdbarch)->num_aregs)) 1465 { 1466 int areg = areg_number (gdbarch, regnum, cache->wd.wb); 1467 1468 if (areg >= 0 1469 && areg < XTENSA_NUM_SAVED_AREGS 1470 && cache->wd.aregs[areg] != -1) 1471 return frame_unwind_got_memory (this_frame, regnum, 1472 cache->wd.aregs[areg]); 1473 } 1474 } 1475 else /* Call0 ABI. */ 1476 { 1477 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base 1478 && regnum <= (gdbarch_tdep (gdbarch)->ar_base 1479 + C0_NREGS)) 1480 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; 1481 1482 if (reg < C0_NREGS) 1483 { 1484 CORE_ADDR spe; 1485 int stkofs; 1486 1487 /* If register was saved in the prologue, retrieve it. */ 1488 stkofs = cache->c0.c0_rt[reg].to_stk; 1489 if (stkofs != C0_NOSTK) 1490 { 1491 /* Determine SP on entry based on FP. */ 1492 spe = cache->c0.c0_fp 1493 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; 1494 1495 return frame_unwind_got_memory (this_frame, regnum, 1496 spe + stkofs); 1497 } 1498 } 1499 } 1500 1501 /* All other registers have been either saved to 1502 the stack or are still alive in the processor. */ 1503 1504 return frame_unwind_got_register (this_frame, regnum, regnum); 1505 } 1506 1507 1508 static const struct frame_unwind 1509 xtensa_unwind = 1510 { 1511 NORMAL_FRAME, 1512 default_frame_unwind_stop_reason, 1513 xtensa_frame_this_id, 1514 xtensa_frame_prev_register, 1515 NULL, 1516 default_frame_sniffer 1517 }; 1518 1519 static CORE_ADDR 1520 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) 1521 { 1522 struct xtensa_frame_cache *cache = 1523 xtensa_frame_cache (this_frame, this_cache); 1524 1525 return cache->base; 1526 } 1527 1528 static const struct frame_base 1529 xtensa_frame_base = 1530 { 1531 &xtensa_unwind, 1532 xtensa_frame_base_address, 1533 xtensa_frame_base_address, 1534 xtensa_frame_base_address 1535 }; 1536 1537 1538 static void 1539 xtensa_extract_return_value (struct type *type, 1540 struct regcache *regcache, 1541 void *dst) 1542 { 1543 struct gdbarch *gdbarch = regcache->arch (); 1544 bfd_byte *valbuf = (bfd_byte *) dst; 1545 int len = TYPE_LENGTH (type); 1546 ULONGEST pc, wb; 1547 int callsize, areg; 1548 int offset = 0; 1549 1550 DEBUGTRACE ("xtensa_extract_return_value (...)\n"); 1551 1552 gdb_assert(len > 0); 1553 1554 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) 1555 { 1556 /* First, we have to find the caller window in the register file. */ 1557 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); 1558 callsize = extract_call_winsize (gdbarch, pc); 1559 1560 /* On Xtensa, we can return up to 4 words (or 2 for call12). */ 1561 if (len > (callsize > 8 ? 8 : 16)) 1562 internal_error (__FILE__, __LINE__, 1563 _("cannot extract return value of %d bytes long"), 1564 len); 1565 1566 /* Get the register offset of the return 1567 register (A2) in the caller window. */ 1568 regcache_raw_read_unsigned 1569 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); 1570 areg = arreg_number (gdbarch, 1571 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); 1572 } 1573 else 1574 { 1575 /* No windowing hardware - Call0 ABI. */ 1576 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; 1577 } 1578 1579 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); 1580 1581 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1582 offset = 4 - len; 1583 1584 for (; len > 0; len -= 4, areg++, valbuf += 4) 1585 { 1586 if (len < 4) 1587 regcache->raw_read_part (areg, offset, len, valbuf); 1588 else 1589 regcache->raw_read (areg, valbuf); 1590 } 1591 } 1592 1593 1594 static void 1595 xtensa_store_return_value (struct type *type, 1596 struct regcache *regcache, 1597 const void *dst) 1598 { 1599 struct gdbarch *gdbarch = regcache->arch (); 1600 const bfd_byte *valbuf = (const bfd_byte *) dst; 1601 unsigned int areg; 1602 ULONGEST pc, wb; 1603 int callsize; 1604 int len = TYPE_LENGTH (type); 1605 int offset = 0; 1606 1607 DEBUGTRACE ("xtensa_store_return_value (...)\n"); 1608 1609 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) 1610 { 1611 regcache_raw_read_unsigned 1612 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); 1613 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); 1614 callsize = extract_call_winsize (gdbarch, pc); 1615 1616 if (len > (callsize > 8 ? 8 : 16)) 1617 internal_error (__FILE__, __LINE__, 1618 _("unimplemented for this length: %d"), 1619 TYPE_LENGTH (type)); 1620 areg = arreg_number (gdbarch, 1621 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); 1622 1623 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", 1624 callsize, (int) wb); 1625 } 1626 else 1627 { 1628 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; 1629 } 1630 1631 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1632 offset = 4 - len; 1633 1634 for (; len > 0; len -= 4, areg++, valbuf += 4) 1635 { 1636 if (len < 4) 1637 regcache->raw_write_part (areg, offset, len, valbuf); 1638 else 1639 regcache->raw_write (areg, valbuf); 1640 } 1641 } 1642 1643 1644 static enum return_value_convention 1645 xtensa_return_value (struct gdbarch *gdbarch, 1646 struct value *function, 1647 struct type *valtype, 1648 struct regcache *regcache, 1649 gdb_byte *readbuf, 1650 const gdb_byte *writebuf) 1651 { 1652 /* Structures up to 16 bytes are returned in registers. */ 1653 1654 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT 1655 || TYPE_CODE (valtype) == TYPE_CODE_UNION 1656 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) 1657 && TYPE_LENGTH (valtype) > 16); 1658 1659 if (struct_return) 1660 return RETURN_VALUE_STRUCT_CONVENTION; 1661 1662 DEBUGTRACE ("xtensa_return_value(...)\n"); 1663 1664 if (writebuf != NULL) 1665 { 1666 xtensa_store_return_value (valtype, regcache, writebuf); 1667 } 1668 1669 if (readbuf != NULL) 1670 { 1671 gdb_assert (!struct_return); 1672 xtensa_extract_return_value (valtype, regcache, readbuf); 1673 } 1674 return RETURN_VALUE_REGISTER_CONVENTION; 1675 } 1676 1677 1678 /* DUMMY FRAME */ 1679 1680 static CORE_ADDR 1681 xtensa_push_dummy_call (struct gdbarch *gdbarch, 1682 struct value *function, 1683 struct regcache *regcache, 1684 CORE_ADDR bp_addr, 1685 int nargs, 1686 struct value **args, 1687 CORE_ADDR sp, 1688 function_call_return_method return_method, 1689 CORE_ADDR struct_addr) 1690 { 1691 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1692 int size, onstack_size; 1693 gdb_byte *buf = (gdb_byte *) alloca (16); 1694 CORE_ADDR ra, ps; 1695 struct argument_info 1696 { 1697 const bfd_byte *contents; 1698 int length; 1699 int onstack; /* onstack == 0 => in reg */ 1700 int align; /* alignment */ 1701 union 1702 { 1703 int offset; /* stack offset if on stack. */ 1704 int regno; /* regno if in register. */ 1705 } u; 1706 }; 1707 1708 struct argument_info *arg_info = 1709 (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); 1710 1711 CORE_ADDR osp = sp; 1712 1713 DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); 1714 1715 if (xtensa_debug_level > 3) 1716 { 1717 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); 1718 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, " 1719 "struct_addr=0x%x\n", 1720 (int) sp, (int) return_method, (int) struct_addr); 1721 1722 for (int i = 0; i < nargs; i++) 1723 { 1724 struct value *arg = args[i]; 1725 struct type *arg_type = check_typedef (value_type (arg)); 1726 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i, 1727 host_address_to_string (arg), 1728 TYPE_LENGTH (arg_type)); 1729 switch (TYPE_CODE (arg_type)) 1730 { 1731 case TYPE_CODE_INT: 1732 fprintf_unfiltered (gdb_stdlog, "int"); 1733 break; 1734 case TYPE_CODE_STRUCT: 1735 fprintf_unfiltered (gdb_stdlog, "struct"); 1736 break; 1737 default: 1738 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); 1739 break; 1740 } 1741 fprintf_unfiltered (gdb_stdlog, " %s\n", 1742 host_address_to_string (value_contents (arg))); 1743 } 1744 } 1745 1746 /* First loop: collect information. 1747 Cast into type_long. (This shouldn't happen often for C because 1748 GDB already does this earlier.) It's possible that GDB could 1749 do it all the time but it's harmless to leave this code here. */ 1750 1751 size = 0; 1752 onstack_size = 0; 1753 1754 if (return_method == return_method_struct) 1755 size = REGISTER_SIZE; 1756 1757 for (int i = 0; i < nargs; i++) 1758 { 1759 struct argument_info *info = &arg_info[i]; 1760 struct value *arg = args[i]; 1761 struct type *arg_type = check_typedef (value_type (arg)); 1762 1763 switch (TYPE_CODE (arg_type)) 1764 { 1765 case TYPE_CODE_INT: 1766 case TYPE_CODE_BOOL: 1767 case TYPE_CODE_CHAR: 1768 case TYPE_CODE_RANGE: 1769 case TYPE_CODE_ENUM: 1770 1771 /* Cast argument to long if necessary as the mask does it too. */ 1772 if (TYPE_LENGTH (arg_type) 1773 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) 1774 { 1775 arg_type = builtin_type (gdbarch)->builtin_long; 1776 arg = value_cast (arg_type, arg); 1777 } 1778 /* Aligment is equal to the type length for the basic types. */ 1779 info->align = TYPE_LENGTH (arg_type); 1780 break; 1781 1782 case TYPE_CODE_FLT: 1783 1784 /* Align doubles correctly. */ 1785 if (TYPE_LENGTH (arg_type) 1786 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) 1787 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); 1788 else 1789 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); 1790 break; 1791 1792 case TYPE_CODE_STRUCT: 1793 default: 1794 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); 1795 break; 1796 } 1797 info->length = TYPE_LENGTH (arg_type); 1798 info->contents = value_contents (arg); 1799 1800 /* Align size and onstack_size. */ 1801 size = (size + info->align - 1) & ~(info->align - 1); 1802 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); 1803 1804 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) 1805 { 1806 info->onstack = 1; 1807 info->u.offset = onstack_size; 1808 onstack_size += info->length; 1809 } 1810 else 1811 { 1812 info->onstack = 0; 1813 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; 1814 } 1815 size += info->length; 1816 } 1817 1818 /* Adjust the stack pointer and align it. */ 1819 sp = align_down (sp - onstack_size, SP_ALIGNMENT); 1820 1821 /* Simulate MOVSP, if Windowed ABI. */ 1822 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) 1823 && (sp != osp)) 1824 { 1825 read_memory (osp - 16, buf, 16); 1826 write_memory (sp - 16, buf, 16); 1827 } 1828 1829 /* Second Loop: Load arguments. */ 1830 1831 if (return_method == return_method_struct) 1832 { 1833 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); 1834 regcache->cooked_write (ARG_1ST (gdbarch), buf); 1835 } 1836 1837 for (int i = 0; i < nargs; i++) 1838 { 1839 struct argument_info *info = &arg_info[i]; 1840 1841 if (info->onstack) 1842 { 1843 int n = info->length; 1844 CORE_ADDR offset = sp + info->u.offset; 1845 1846 /* Odd-sized structs are aligned to the lower side of a memory 1847 word in big-endian mode and require a shift. This only 1848 applies for structures smaller than one word. */ 1849 1850 if (n < REGISTER_SIZE 1851 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1852 offset += (REGISTER_SIZE - n); 1853 1854 write_memory (offset, info->contents, info->length); 1855 1856 } 1857 else 1858 { 1859 int n = info->length; 1860 const bfd_byte *cp = info->contents; 1861 int r = info->u.regno; 1862 1863 /* Odd-sized structs are aligned to the lower side of registers in 1864 big-endian mode and require a shift. The odd-sized leftover will 1865 be at the end. Note that this is only true for structures smaller 1866 than REGISTER_SIZE; for larger odd-sized structures the excess 1867 will be left-aligned in the register on both endiannesses. */ 1868 1869 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) 1870 { 1871 ULONGEST v; 1872 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); 1873 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); 1874 1875 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); 1876 regcache->cooked_write (r, buf); 1877 1878 cp += REGISTER_SIZE; 1879 n -= REGISTER_SIZE; 1880 r++; 1881 } 1882 else 1883 while (n > 0) 1884 { 1885 regcache->cooked_write (r, cp); 1886 1887 cp += REGISTER_SIZE; 1888 n -= REGISTER_SIZE; 1889 r++; 1890 } 1891 } 1892 } 1893 1894 /* Set the return address of dummy frame to the dummy address. 1895 The return address for the current function (in A0) is 1896 saved in the dummy frame, so we can savely overwrite A0 here. */ 1897 1898 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) 1899 { 1900 ULONGEST val; 1901 1902 ra = (bp_addr & 0x3fffffff) | 0x40000000; 1903 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val); 1904 ps = (unsigned long) val & ~0x00030000; 1905 regcache_cooked_write_unsigned 1906 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); 1907 regcache_cooked_write_unsigned (regcache, 1908 gdbarch_ps_regnum (gdbarch), 1909 ps | 0x00010000); 1910 1911 /* All the registers have been saved. After executing 1912 dummy call, they all will be restored. So it's safe 1913 to modify WINDOWSTART register to make it look like there 1914 is only one register window corresponding to WINDOWEBASE. */ 1915 1916 regcache->raw_read (gdbarch_tdep (gdbarch)->wb_regnum, buf); 1917 regcache_cooked_write_unsigned 1918 (regcache, gdbarch_tdep (gdbarch)->ws_regnum, 1919 1 << extract_unsigned_integer (buf, 4, byte_order)); 1920 } 1921 else 1922 { 1923 /* Simulate CALL0: write RA into A0 register. */ 1924 regcache_cooked_write_unsigned 1925 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); 1926 } 1927 1928 /* Set new stack pointer and return it. */ 1929 regcache_cooked_write_unsigned (regcache, 1930 gdbarch_tdep (gdbarch)->a0_base + 1, sp); 1931 /* Make dummy frame ID unique by adding a constant. */ 1932 return sp + SP_ALIGNMENT; 1933 } 1934 1935 /* Implement the breakpoint_kind_from_pc gdbarch method. */ 1936 1937 static int 1938 xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 1939 { 1940 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) 1941 return 2; 1942 else 1943 return 4; 1944 } 1945 1946 /* Return a breakpoint for the current location of PC. We always use 1947 the density version if we have density instructions (regardless of the 1948 current instruction at PC), and use regular instructions otherwise. */ 1949 1950 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } 1951 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } 1952 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } 1953 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } 1954 1955 /* Implement the sw_breakpoint_from_kind gdbarch method. */ 1956 1957 static const gdb_byte * 1958 xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 1959 { 1960 *size = kind; 1961 1962 if (kind == 4) 1963 { 1964 static unsigned char big_breakpoint[] = BIG_BREAKPOINT; 1965 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; 1966 1967 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1968 return big_breakpoint; 1969 else 1970 return little_breakpoint; 1971 } 1972 else 1973 { 1974 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; 1975 static unsigned char density_little_breakpoint[] 1976 = DENSITY_LITTLE_BREAKPOINT; 1977 1978 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1979 return density_big_breakpoint; 1980 else 1981 return density_little_breakpoint; 1982 } 1983 } 1984 1985 /* Call0 ABI support routines. */ 1986 1987 /* Return true, if PC points to "ret" or "ret.n". */ 1988 1989 static int 1990 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc) 1991 { 1992 #define RETURN_RET goto done 1993 xtensa_isa isa; 1994 xtensa_insnbuf ins, slot; 1995 gdb_byte ibuf[XTENSA_ISA_BSZ]; 1996 CORE_ADDR ia, bt, ba; 1997 xtensa_format ifmt; 1998 int ilen, islots, is; 1999 xtensa_opcode opc; 2000 const char *opcname; 2001 int found_ret = 0; 2002 2003 isa = xtensa_default_isa; 2004 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); 2005 ins = xtensa_insnbuf_alloc (isa); 2006 slot = xtensa_insnbuf_alloc (isa); 2007 ba = 0; 2008 2009 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen) 2010 { 2011 if (ia + xtensa_isa_maxlength (isa) > bt) 2012 { 2013 ba = ia; 2014 bt = (ba + XTENSA_ISA_BSZ) < finish_pc 2015 ? ba + XTENSA_ISA_BSZ : finish_pc; 2016 if (target_read_memory (ba, ibuf, bt - ba) != 0 ) 2017 RETURN_RET; 2018 } 2019 2020 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); 2021 ifmt = xtensa_format_decode (isa, ins); 2022 if (ifmt == XTENSA_UNDEFINED) 2023 RETURN_RET; 2024 ilen = xtensa_format_length (isa, ifmt); 2025 if (ilen == XTENSA_UNDEFINED) 2026 RETURN_RET; 2027 islots = xtensa_format_num_slots (isa, ifmt); 2028 if (islots == XTENSA_UNDEFINED) 2029 RETURN_RET; 2030 2031 for (is = 0; is < islots; ++is) 2032 { 2033 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) 2034 RETURN_RET; 2035 2036 opc = xtensa_opcode_decode (isa, ifmt, is, slot); 2037 if (opc == XTENSA_UNDEFINED) 2038 RETURN_RET; 2039 2040 opcname = xtensa_opcode_name (isa, opc); 2041 2042 if ((strcasecmp (opcname, "ret.n") == 0) 2043 || (strcasecmp (opcname, "ret") == 0)) 2044 { 2045 found_ret = 1; 2046 RETURN_RET; 2047 } 2048 } 2049 } 2050 done: 2051 xtensa_insnbuf_free(isa, slot); 2052 xtensa_insnbuf_free(isa, ins); 2053 return found_ret; 2054 } 2055 2056 /* Call0 opcode class. Opcodes are preclassified according to what they 2057 mean for Call0 prologue analysis, and their number of significant operands. 2058 The purpose of this is to simplify prologue analysis by separating 2059 instruction decoding (libisa) from the semantics of prologue analysis. */ 2060 2061 typedef enum 2062 { 2063 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ 2064 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ 2065 c0opc_flow, /* Flow control insn. */ 2066 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ 2067 c0opc_break, /* Debugger software breakpoints. */ 2068 c0opc_add, /* Adding two registers. */ 2069 c0opc_addi, /* Adding a register and an immediate. */ 2070 c0opc_and, /* Bitwise "and"-ing two registers. */ 2071 c0opc_sub, /* Subtracting a register from a register. */ 2072 c0opc_mov, /* Moving a register to a register. */ 2073 c0opc_movi, /* Moving an immediate to a register. */ 2074 c0opc_l32r, /* Loading a literal. */ 2075 c0opc_s32i, /* Storing word at fixed offset from a base register. */ 2076 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */ 2077 c0opc_l32e, /* L32E instruction. */ 2078 c0opc_s32e, /* S32E instruction. */ 2079 c0opc_rfwo, /* RFWO instruction. */ 2080 c0opc_rfwu, /* RFWU instruction. */ 2081 c0opc_NrOf /* Number of opcode classifications. */ 2082 } xtensa_insn_kind; 2083 2084 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */ 2085 2086 static int 2087 rwx_special_register (const char *opcname) 2088 { 2089 char ch = *opcname++; 2090 2091 if ((ch != 'r') && (ch != 'w') && (ch != 'x')) 2092 return 0; 2093 if (*opcname++ != 's') 2094 return 0; 2095 if (*opcname++ != 'r') 2096 return 0; 2097 if (*opcname++ != '.') 2098 return 0; 2099 2100 return 1; 2101 } 2102 2103 /* Classify an opcode based on what it means for Call0 prologue analysis. */ 2104 2105 static xtensa_insn_kind 2106 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) 2107 { 2108 const char *opcname; 2109 xtensa_insn_kind opclass = c0opc_uninteresting; 2110 2111 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); 2112 2113 /* Get opcode name and handle special classifications. */ 2114 2115 opcname = xtensa_opcode_name (isa, opc); 2116 2117 if (opcname == NULL 2118 || strcasecmp (opcname, "ill") == 0 2119 || strcasecmp (opcname, "ill.n") == 0) 2120 opclass = c0opc_illegal; 2121 else if (strcasecmp (opcname, "break") == 0 2122 || strcasecmp (opcname, "break.n") == 0) 2123 opclass = c0opc_break; 2124 else if (strcasecmp (opcname, "entry") == 0) 2125 opclass = c0opc_entry; 2126 else if (strcasecmp (opcname, "rfwo") == 0) 2127 opclass = c0opc_rfwo; 2128 else if (strcasecmp (opcname, "rfwu") == 0) 2129 opclass = c0opc_rfwu; 2130 else if (xtensa_opcode_is_branch (isa, opc) > 0 2131 || xtensa_opcode_is_jump (isa, opc) > 0 2132 || xtensa_opcode_is_loop (isa, opc) > 0 2133 || xtensa_opcode_is_call (isa, opc) > 0 2134 || strcasecmp (opcname, "simcall") == 0 2135 || strcasecmp (opcname, "syscall") == 0) 2136 opclass = c0opc_flow; 2137 2138 /* Also, classify specific opcodes that need to be tracked. */ 2139 else if (strcasecmp (opcname, "add") == 0 2140 || strcasecmp (opcname, "add.n") == 0) 2141 opclass = c0opc_add; 2142 else if (strcasecmp (opcname, "and") == 0) 2143 opclass = c0opc_and; 2144 else if (strcasecmp (opcname, "addi") == 0 2145 || strcasecmp (opcname, "addi.n") == 0 2146 || strcasecmp (opcname, "addmi") == 0) 2147 opclass = c0opc_addi; 2148 else if (strcasecmp (opcname, "sub") == 0) 2149 opclass = c0opc_sub; 2150 else if (strcasecmp (opcname, "mov.n") == 0 2151 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ 2152 opclass = c0opc_mov; 2153 else if (strcasecmp (opcname, "movi") == 0 2154 || strcasecmp (opcname, "movi.n") == 0) 2155 opclass = c0opc_movi; 2156 else if (strcasecmp (opcname, "l32r") == 0) 2157 opclass = c0opc_l32r; 2158 else if (strcasecmp (opcname, "s32i") == 0 2159 || strcasecmp (opcname, "s32i.n") == 0) 2160 opclass = c0opc_s32i; 2161 else if (strcasecmp (opcname, "l32e") == 0) 2162 opclass = c0opc_l32e; 2163 else if (strcasecmp (opcname, "s32e") == 0) 2164 opclass = c0opc_s32e; 2165 else if (rwx_special_register (opcname)) 2166 opclass = c0opc_rwxsr; 2167 2168 return opclass; 2169 } 2170 2171 /* Tracks register movement/mutation for a given operation, which may 2172 be within a bundle. Updates the destination register tracking info 2173 accordingly. The pc is needed only for pc-relative load instructions 2174 (eg. l32r). The SP register number is needed to identify stores to 2175 the stack frame. Returns 0, if analysis was succesfull, non-zero 2176 otherwise. */ 2177 2178 static int 2179 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], 2180 xtensa_insn_kind opclass, int nods, unsigned odv[], 2181 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache) 2182 { 2183 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2184 unsigned litbase, litaddr, litval; 2185 2186 switch (opclass) 2187 { 2188 case c0opc_addi: 2189 /* 3 operands: dst, src, imm. */ 2190 gdb_assert (nods == 3); 2191 dst[odv[0]].fr_reg = src[odv[1]].fr_reg; 2192 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; 2193 break; 2194 case c0opc_add: 2195 /* 3 operands: dst, src1, src2. */ 2196 gdb_assert (nods == 3); 2197 if (src[odv[1]].fr_reg == C0_CONST) 2198 { 2199 dst[odv[0]].fr_reg = src[odv[2]].fr_reg; 2200 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; 2201 } 2202 else if (src[odv[2]].fr_reg == C0_CONST) 2203 { 2204 dst[odv[0]].fr_reg = src[odv[1]].fr_reg; 2205 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; 2206 } 2207 else dst[odv[0]].fr_reg = C0_INEXP; 2208 break; 2209 case c0opc_and: 2210 /* 3 operands: dst, src1, src2. */ 2211 gdb_assert (nods == 3); 2212 if (cache->c0.c0_fpalign == 0) 2213 { 2214 /* Handle dynamic stack alignment. */ 2215 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg)) 2216 { 2217 if (src[odv[2]].fr_reg == C0_CONST) 2218 cache->c0.c0_fpalign = src[odv[2]].fr_ofs; 2219 break; 2220 } 2221 else if ((src[odv[0]].fr_reg == spreg) 2222 && (src[odv[2]].fr_reg == spreg)) 2223 { 2224 if (src[odv[1]].fr_reg == C0_CONST) 2225 cache->c0.c0_fpalign = src[odv[1]].fr_ofs; 2226 break; 2227 } 2228 /* else fall through. */ 2229 } 2230 if (src[odv[1]].fr_reg == C0_CONST) 2231 { 2232 dst[odv[0]].fr_reg = src[odv[2]].fr_reg; 2233 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs; 2234 } 2235 else if (src[odv[2]].fr_reg == C0_CONST) 2236 { 2237 dst[odv[0]].fr_reg = src[odv[1]].fr_reg; 2238 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs; 2239 } 2240 else dst[odv[0]].fr_reg = C0_INEXP; 2241 break; 2242 case c0opc_sub: 2243 /* 3 operands: dst, src1, src2. */ 2244 gdb_assert (nods == 3); 2245 if (src[odv[2]].fr_reg == C0_CONST) 2246 { 2247 dst[odv[0]].fr_reg = src[odv[1]].fr_reg; 2248 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; 2249 } 2250 else dst[odv[0]].fr_reg = C0_INEXP; 2251 break; 2252 case c0opc_mov: 2253 /* 2 operands: dst, src [, src]. */ 2254 gdb_assert (nods == 2); 2255 /* First, check if it's a special case of saving unaligned SP 2256 to a spare register in case of dynamic stack adjustment. 2257 But, only do it one time. The second time could be initializing 2258 frame pointer. We don't want to overwrite the first one. */ 2259 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP)) 2260 cache->c0.c0_old_sp = odv[0]; 2261 2262 dst[odv[0]].fr_reg = src[odv[1]].fr_reg; 2263 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; 2264 break; 2265 case c0opc_movi: 2266 /* 2 operands: dst, imm. */ 2267 gdb_assert (nods == 2); 2268 dst[odv[0]].fr_reg = C0_CONST; 2269 dst[odv[0]].fr_ofs = odv[1]; 2270 break; 2271 case c0opc_l32r: 2272 /* 2 operands: dst, literal offset. */ 2273 gdb_assert (nods == 2); 2274 /* litbase = xtensa_get_litbase (pc); can be also used. */ 2275 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1) 2276 ? 0 : xtensa_read_register 2277 (gdbarch_tdep (gdbarch)->litbase_regnum); 2278 litaddr = litbase & 1 2279 ? (litbase & ~1) + (signed)odv[1] 2280 : (pc + 3 + (signed)odv[1]) & ~3; 2281 litval = read_memory_integer (litaddr, 4, byte_order); 2282 dst[odv[0]].fr_reg = C0_CONST; 2283 dst[odv[0]].fr_ofs = litval; 2284 break; 2285 case c0opc_s32i: 2286 /* 3 operands: value, base, offset. */ 2287 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); 2288 /* First, check if it's a spill for saved unaligned SP, 2289 when dynamic stack adjustment was applied to this frame. */ 2290 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */ 2291 && (odv[1] == spreg) /* SP usage indicates spill. */ 2292 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */ 2293 cache->c0.c0_sp_ofs = odv[2]; 2294 2295 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ 2296 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ 2297 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ 2298 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ 2299 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ 2300 { 2301 /* ISA encoding guarantees alignment. But, check it anyway. */ 2302 gdb_assert ((odv[2] & 3) == 0); 2303 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; 2304 } 2305 break; 2306 /* If we end up inside Window Overflow / Underflow interrupt handler 2307 report an error because these handlers should have been handled 2308 already in a different way. */ 2309 case c0opc_l32e: 2310 case c0opc_s32e: 2311 case c0opc_rfwo: 2312 case c0opc_rfwu: 2313 return 1; 2314 default: 2315 return 1; 2316 } 2317 return 0; 2318 } 2319 2320 /* Analyze prologue of the function at start address to determine if it uses 2321 the Call0 ABI, and if so track register moves and linear modifications 2322 in the prologue up to the PC or just beyond the prologue, whichever is 2323 first. An 'entry' instruction indicates non-Call0 ABI and the end of the 2324 prologue. The prologue may overlap non-prologue instructions but is 2325 guaranteed to end by the first flow-control instruction (jump, branch, 2326 call or return). Since an optimized function may move information around 2327 and change the stack frame arbitrarily during the prologue, the information 2328 is guaranteed valid only at the point in the function indicated by the PC. 2329 May be used to skip the prologue or identify the ABI, w/o tracking. 2330 2331 Returns: Address of first instruction after prologue, or PC (whichever 2332 is first), or 0, if decoding failed (in libisa). 2333 Input args: 2334 start Start address of function/prologue. 2335 pc Program counter to stop at. Use 0 to continue to end of prologue. 2336 If 0, avoids infinite run-on in corrupt code memory by bounding 2337 the scan to the end of the function if that can be determined. 2338 nregs Number of general registers to track. 2339 InOut args: 2340 cache Xtensa frame cache. 2341 2342 Note that these may produce useful results even if decoding fails 2343 because they begin with default assumptions that analysis may change. */ 2344 2345 static CORE_ADDR 2346 call0_analyze_prologue (struct gdbarch *gdbarch, 2347 CORE_ADDR start, CORE_ADDR pc, 2348 int nregs, xtensa_frame_cache_t *cache) 2349 { 2350 CORE_ADDR ia; /* Current insn address in prologue. */ 2351 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ 2352 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ 2353 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ 2354 xtensa_isa isa; /* libisa ISA handle. */ 2355 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ 2356 xtensa_format ifmt; /* libisa instruction format. */ 2357 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ 2358 xtensa_opcode opc; /* Opcode in current slot. */ 2359 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ 2360 int nods; /* Opcode number of operands. */ 2361 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ 2362 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ 2363 int j; /* General loop counter. */ 2364 int fail = 0; /* Set non-zero and exit, if decoding fails. */ 2365 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ 2366 CORE_ADDR end_pc; /* The PC for the lust function insn. */ 2367 2368 struct symtab_and_line prologue_sal; 2369 2370 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", 2371 (int)start, (int)pc); 2372 2373 /* Try to limit the scan to the end of the function if a non-zero pc 2374 arg was not supplied to avoid probing beyond the end of valid memory. 2375 If memory is full of garbage that classifies as c0opc_uninteresting. 2376 If this fails (eg. if no symbols) pc ends up 0 as it was. 2377 Initialize the Call0 frame and register tracking info. 2378 Assume it's Call0 until an 'entry' instruction is encountered. 2379 Assume we may be in the prologue until we hit a flow control instr. */ 2380 2381 rtmp = NULL; 2382 body_pc = UINT_MAX; 2383 end_pc = 0; 2384 2385 /* Find out, if we have an information about the prologue from DWARF. */ 2386 prologue_sal = find_pc_line (start, 0); 2387 if (prologue_sal.line != 0) /* Found debug info. */ 2388 body_pc = prologue_sal.end; 2389 2390 /* If we are going to analyze the prologue in general without knowing about 2391 the current PC, make the best assumtion for the end of the prologue. */ 2392 if (pc == 0) 2393 { 2394 find_pc_partial_function (start, 0, NULL, &end_pc); 2395 body_pc = std::min (end_pc, body_pc); 2396 } 2397 else 2398 body_pc = std::min (pc, body_pc); 2399 2400 cache->call0 = 1; 2401 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); 2402 2403 isa = xtensa_default_isa; 2404 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); 2405 ins = xtensa_insnbuf_alloc (isa); 2406 slot = xtensa_insnbuf_alloc (isa); 2407 2408 for (ia = start, bt = ia; ia < body_pc ; ia += ilen) 2409 { 2410 /* (Re)fill instruction buffer from memory if necessary, but do not 2411 read memory beyond PC to be sure we stay within text section 2412 (this protection only works if a non-zero pc is supplied). */ 2413 2414 if (ia + xtensa_isa_maxlength (isa) > bt) 2415 { 2416 ba = ia; 2417 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; 2418 if (target_read_memory (ba, ibuf, bt - ba) != 0 ) 2419 error (_("Unable to read target memory ...")); 2420 } 2421 2422 /* Decode format information. */ 2423 2424 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); 2425 ifmt = xtensa_format_decode (isa, ins); 2426 if (ifmt == XTENSA_UNDEFINED) 2427 { 2428 fail = 1; 2429 goto done; 2430 } 2431 ilen = xtensa_format_length (isa, ifmt); 2432 if (ilen == XTENSA_UNDEFINED) 2433 { 2434 fail = 1; 2435 goto done; 2436 } 2437 islots = xtensa_format_num_slots (isa, ifmt); 2438 if (islots == XTENSA_UNDEFINED) 2439 { 2440 fail = 1; 2441 goto done; 2442 } 2443 2444 /* Analyze a bundle or a single instruction, using a snapshot of 2445 the register tracking info as input for the entire bundle so that 2446 register changes do not take effect within this bundle. */ 2447 2448 for (j = 0; j < nregs; ++j) 2449 rtmp[j] = cache->c0.c0_rt[j]; 2450 2451 for (is = 0; is < islots; ++is) 2452 { 2453 /* Decode a slot and classify the opcode. */ 2454 2455 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); 2456 if (fail) 2457 goto done; 2458 2459 opc = xtensa_opcode_decode (isa, ifmt, is, slot); 2460 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", 2461 (unsigned)ia, opc); 2462 if (opc == XTENSA_UNDEFINED) 2463 opclass = c0opc_illegal; 2464 else 2465 opclass = call0_classify_opcode (isa, opc); 2466 2467 /* Decide whether to track this opcode, ignore it, or bail out. */ 2468 2469 switch (opclass) 2470 { 2471 case c0opc_illegal: 2472 case c0opc_break: 2473 fail = 1; 2474 goto done; 2475 2476 case c0opc_uninteresting: 2477 continue; 2478 2479 case c0opc_flow: /* Flow control instructions stop analysis. */ 2480 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */ 2481 goto done; 2482 2483 case c0opc_entry: 2484 cache->call0 = 0; 2485 ia += ilen; /* Skip over 'entry' insn. */ 2486 goto done; 2487 2488 default: 2489 cache->call0 = 1; 2490 } 2491 2492 /* Only expected opcodes should get this far. */ 2493 2494 /* Extract and decode the operands. */ 2495 nods = xtensa_opcode_num_operands (isa, opc); 2496 if (nods == XTENSA_UNDEFINED) 2497 { 2498 fail = 1; 2499 goto done; 2500 } 2501 2502 for (j = 0; j < nods && j < C0_MAXOPDS; ++j) 2503 { 2504 fail = xtensa_operand_get_field (isa, opc, j, ifmt, 2505 is, slot, &odv[j]); 2506 if (fail) 2507 goto done; 2508 2509 fail = xtensa_operand_decode (isa, opc, j, &odv[j]); 2510 if (fail) 2511 goto done; 2512 } 2513 2514 /* Check operands to verify use of 'mov' assembler macro. */ 2515 if (opclass == c0opc_mov && nods == 3) 2516 { 2517 if (odv[2] == odv[1]) 2518 { 2519 nods = 2; 2520 if ((odv[0] == 1) && (odv[1] != 1)) 2521 /* OR A1, An, An , where n != 1. 2522 This means we are inside epilogue already. */ 2523 goto done; 2524 } 2525 else 2526 { 2527 opclass = c0opc_uninteresting; 2528 continue; 2529 } 2530 } 2531 2532 /* Track register movement and modification for this operation. */ 2533 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp, 2534 opclass, nods, odv, ia, 1, cache); 2535 if (fail) 2536 goto done; 2537 } 2538 } 2539 done: 2540 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", 2541 (unsigned)ia, fail ? "failed" : "succeeded"); 2542 xtensa_insnbuf_free(isa, slot); 2543 xtensa_insnbuf_free(isa, ins); 2544 return fail ? XTENSA_ISA_BADPC : ia; 2545 } 2546 2547 /* Initialize frame cache for the current frame in CALL0 ABI. */ 2548 2549 static void 2550 call0_frame_cache (struct frame_info *this_frame, 2551 xtensa_frame_cache_t *cache, CORE_ADDR pc) 2552 { 2553 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2554 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2555 CORE_ADDR start_pc; /* The beginning of the function. */ 2556 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ 2557 CORE_ADDR sp, fp, ra; 2558 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk; 2559 2560 sp = get_frame_register_unsigned 2561 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); 2562 fp = sp; /* Assume FP == SP until proven otherwise. */ 2563 2564 /* Find the beginning of the prologue of the function containing the PC 2565 and analyze it up to the PC or the end of the prologue. */ 2566 2567 if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) 2568 { 2569 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache); 2570 2571 if (body_pc == XTENSA_ISA_BADPC) 2572 { 2573 warning_once (); 2574 ra = 0; 2575 goto finish_frame_analysis; 2576 } 2577 } 2578 2579 /* Get the frame information and FP (if used) at the current PC. 2580 If PC is in the prologue, the prologue analysis is more reliable 2581 than DWARF info. We don't not know for sure, if PC is in the prologue, 2582 but we do know no calls have yet taken place, so we can almost 2583 certainly rely on the prologue analysis. */ 2584 2585 if (body_pc <= pc) 2586 { 2587 /* Prologue analysis was successful up to the PC. 2588 It includes the cases when PC == START_PC. */ 2589 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; 2590 /* c0_hasfp == true means there is a frame pointer because 2591 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] 2592 was derived from SP. Otherwise, it would be C0_FP. */ 2593 fp_regnum = c0_hasfp ? C0_FP : C0_SP; 2594 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; 2595 fp_regnum += gdbarch_tdep (gdbarch)->a0_base; 2596 } 2597 else /* No data from the prologue analysis. */ 2598 { 2599 c0_hasfp = 0; 2600 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; 2601 c0_frmsz = 0; 2602 start_pc = pc; 2603 } 2604 2605 if (cache->c0.c0_fpalign) 2606 { 2607 /* This frame has a special prologue with a dynamic stack adjustment 2608 to force an alignment, which is bigger than standard 16 bytes. */ 2609 2610 CORE_ADDR unaligned_sp; 2611 2612 if (cache->c0.c0_old_sp == C0_INEXP) 2613 /* This can't be. Prologue code should be consistent. 2614 Unaligned stack pointer should be saved in a spare register. */ 2615 { 2616 warning_once (); 2617 ra = 0; 2618 goto finish_frame_analysis; 2619 } 2620 2621 if (cache->c0.c0_sp_ofs == C0_NOSTK) 2622 /* Saved unaligned value of SP is kept in a register. */ 2623 unaligned_sp = get_frame_register_unsigned 2624 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp); 2625 else 2626 /* Get the value from stack. */ 2627 unaligned_sp = (CORE_ADDR) 2628 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order); 2629 2630 prev_sp = unaligned_sp + c0_frmsz; 2631 } 2632 else 2633 prev_sp = fp + c0_frmsz; 2634 2635 /* Frame size from debug info or prologue tracking does not account for 2636 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ 2637 if (c0_hasfp) 2638 { 2639 fp = get_frame_register_unsigned (this_frame, fp_regnum); 2640 2641 /* Update the stack frame size. */ 2642 c0_frmsz += fp - sp; 2643 } 2644 2645 /* Get the return address (RA) from the stack if saved, 2646 or try to get it from a register. */ 2647 2648 to_stk = cache->c0.c0_rt[C0_RA].to_stk; 2649 if (to_stk != C0_NOSTK) 2650 ra = (CORE_ADDR) 2651 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 2652 4, byte_order); 2653 2654 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST 2655 && cache->c0.c0_rt[C0_RA].fr_ofs == 0) 2656 { 2657 /* Special case for terminating backtrace at a function that wants to 2658 be seen as the outermost one. Such a function will clear it's RA (A0) 2659 register to 0 in the prologue instead of saving its original value. */ 2660 ra = 0; 2661 } 2662 else 2663 { 2664 /* RA was copied to another register or (before any function call) may 2665 still be in the original RA register. This is not always reliable: 2666 even in a leaf function, register tracking stops after prologue, and 2667 even in prologue, non-prologue instructions (not tracked) may overwrite 2668 RA or any register it was copied to. If likely in prologue or before 2669 any call, use retracking info and hope for the best (compiler should 2670 have saved RA in stack if not in a leaf function). If not in prologue, 2671 too bad. */ 2672 2673 int i; 2674 for (i = 0; 2675 (i < C0_NREGS) 2676 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); 2677 ++i); 2678 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) 2679 i = C0_RA; 2680 if (i < C0_NREGS) 2681 { 2682 ra = get_frame_register_unsigned 2683 (this_frame, 2684 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); 2685 } 2686 else ra = 0; 2687 } 2688 2689 finish_frame_analysis: 2690 cache->pc = start_pc; 2691 cache->ra = ra; 2692 /* RA == 0 marks the outermost frame. Do not go past it. */ 2693 cache->prev_sp = (ra != 0) ? prev_sp : 0; 2694 cache->c0.fp_regnum = fp_regnum; 2695 cache->c0.c0_frmsz = c0_frmsz; 2696 cache->c0.c0_hasfp = c0_hasfp; 2697 cache->c0.c0_fp = fp; 2698 } 2699 2700 static CORE_ADDR a0_saved; 2701 static CORE_ADDR a7_saved; 2702 static CORE_ADDR a11_saved; 2703 static int a0_was_saved; 2704 static int a7_was_saved; 2705 static int a11_was_saved; 2706 2707 /* Simulate L32E instruction: AT <-- ref (AS + offset). */ 2708 static void 2709 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) 2710 { 2711 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); 2712 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); 2713 CORE_ADDR addr = xtensa_read_register (asreg) + offset; 2714 unsigned int spilled_value 2715 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch)); 2716 2717 if ((at == 0) && !a0_was_saved) 2718 { 2719 a0_saved = xtensa_read_register (atreg); 2720 a0_was_saved = 1; 2721 } 2722 else if ((at == 7) && !a7_was_saved) 2723 { 2724 a7_saved = xtensa_read_register (atreg); 2725 a7_was_saved = 1; 2726 } 2727 else if ((at == 11) && !a11_was_saved) 2728 { 2729 a11_saved = xtensa_read_register (atreg); 2730 a11_was_saved = 1; 2731 } 2732 2733 xtensa_write_register (atreg, spilled_value); 2734 } 2735 2736 /* Simulate S32E instruction: AT --> ref (AS + offset). */ 2737 static void 2738 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) 2739 { 2740 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); 2741 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); 2742 CORE_ADDR addr = xtensa_read_register (asreg) + offset; 2743 ULONGEST spilled_value = xtensa_read_register (atreg); 2744 2745 write_memory_unsigned_integer (addr, 4, 2746 gdbarch_byte_order (gdbarch), 2747 spilled_value); 2748 } 2749 2750 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200 2751 2752 typedef enum 2753 { 2754 xtWindowOverflow, 2755 xtWindowUnderflow, 2756 xtNoExceptionHandler 2757 } xtensa_exception_handler_t; 2758 2759 /* Execute instruction stream from current PC until hitting RFWU or RFWO. 2760 Return type of Xtensa Window Interrupt Handler on success. */ 2761 static xtensa_exception_handler_t 2762 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb) 2763 { 2764 xtensa_isa isa; 2765 xtensa_insnbuf ins, slot; 2766 gdb_byte ibuf[XTENSA_ISA_BSZ]; 2767 CORE_ADDR ia, bt, ba; 2768 xtensa_format ifmt; 2769 int ilen, islots, is; 2770 xtensa_opcode opc; 2771 int insn_num = 0; 2772 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR); 2773 2774 uint32_t at, as, offset; 2775 2776 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ 2777 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; 2778 2779 isa = xtensa_default_isa; 2780 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); 2781 ins = xtensa_insnbuf_alloc (isa); 2782 slot = xtensa_insnbuf_alloc (isa); 2783 ba = 0; 2784 ia = current_pc; 2785 bt = ia; 2786 2787 a0_was_saved = 0; 2788 a7_was_saved = 0; 2789 a11_was_saved = 0; 2790 2791 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN) 2792 { 2793 if (ia + xtensa_isa_maxlength (isa) > bt) 2794 { 2795 ba = ia; 2796 bt = (ba + XTENSA_ISA_BSZ); 2797 if (target_read_memory (ba, ibuf, bt - ba) != 0) 2798 return xtNoExceptionHandler; 2799 } 2800 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); 2801 ifmt = xtensa_format_decode (isa, ins); 2802 if (ifmt == XTENSA_UNDEFINED) 2803 return xtNoExceptionHandler; 2804 ilen = xtensa_format_length (isa, ifmt); 2805 if (ilen == XTENSA_UNDEFINED) 2806 return xtNoExceptionHandler; 2807 islots = xtensa_format_num_slots (isa, ifmt); 2808 if (islots == XTENSA_UNDEFINED) 2809 return xtNoExceptionHandler; 2810 for (is = 0; is < islots; ++is) 2811 { 2812 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) 2813 return xtNoExceptionHandler; 2814 opc = xtensa_opcode_decode (isa, ifmt, is, slot); 2815 if (opc == XTENSA_UNDEFINED) 2816 return xtNoExceptionHandler; 2817 switch (call0_classify_opcode (isa, opc)) 2818 { 2819 case c0opc_illegal: 2820 case c0opc_flow: 2821 case c0opc_entry: 2822 case c0opc_break: 2823 /* We expect none of them here. */ 2824 return xtNoExceptionHandler; 2825 case c0opc_l32e: 2826 func = execute_l32e; 2827 break; 2828 case c0opc_s32e: 2829 func = execute_s32e; 2830 break; 2831 case c0opc_rfwo: /* RFWO. */ 2832 /* Here, we return from WindowOverflow handler and, 2833 if we stopped at the very beginning, which means 2834 A0 was saved, we have to restore it now. */ 2835 if (a0_was_saved) 2836 { 2837 int arreg = arreg_number (gdbarch, 2838 gdbarch_tdep (gdbarch)->a0_base, 2839 wb); 2840 xtensa_write_register (arreg, a0_saved); 2841 } 2842 return xtWindowOverflow; 2843 case c0opc_rfwu: /* RFWU. */ 2844 /* Here, we return from WindowUnderflow handler. 2845 Let's see if either A7 or A11 has to be restored. */ 2846 if (WindowUnderflow12) 2847 { 2848 if (a11_was_saved) 2849 { 2850 int arreg = arreg_number (gdbarch, 2851 gdbarch_tdep (gdbarch)->a0_base + 11, 2852 wb); 2853 xtensa_write_register (arreg, a11_saved); 2854 } 2855 } 2856 else if (a7_was_saved) 2857 { 2858 int arreg = arreg_number (gdbarch, 2859 gdbarch_tdep (gdbarch)->a0_base + 7, 2860 wb); 2861 xtensa_write_register (arreg, a7_saved); 2862 } 2863 return xtWindowUnderflow; 2864 default: /* Simply skip this insns. */ 2865 continue; 2866 } 2867 2868 /* Decode arguments for L32E / S32E and simulate their execution. */ 2869 if ( xtensa_opcode_num_operands (isa, opc) != 3 ) 2870 return xtNoExceptionHandler; 2871 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at)) 2872 return xtNoExceptionHandler; 2873 if (xtensa_operand_decode (isa, opc, 0, &at)) 2874 return xtNoExceptionHandler; 2875 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as)) 2876 return xtNoExceptionHandler; 2877 if (xtensa_operand_decode (isa, opc, 1, &as)) 2878 return xtNoExceptionHandler; 2879 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset)) 2880 return xtNoExceptionHandler; 2881 if (xtensa_operand_decode (isa, opc, 2, &offset)) 2882 return xtNoExceptionHandler; 2883 2884 (*func) (gdbarch, at, as, offset, wb); 2885 } 2886 2887 ia += ilen; 2888 } 2889 return xtNoExceptionHandler; 2890 } 2891 2892 /* Handle Window Overflow / Underflow exception frames. */ 2893 2894 static void 2895 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, 2896 xtensa_frame_cache_t *cache, 2897 CORE_ADDR pc) 2898 { 2899 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2900 CORE_ADDR ps, wb, ws, ra; 2901 int epc1_regnum, i, regnum; 2902 xtensa_exception_handler_t eh_type; 2903 2904 /* Read PS, WB, and WS from the hardware. Note that PS register 2905 must be present, if Windowed ABI is supported. */ 2906 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch)); 2907 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum); 2908 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum); 2909 2910 /* Execute all the remaining instructions from Window Interrupt Handler 2911 by simulating them on the remote protocol level. On return, set the 2912 type of Xtensa Window Interrupt Handler, or report an error. */ 2913 eh_type = execute_code (gdbarch, pc, wb); 2914 if (eh_type == xtNoExceptionHandler) 2915 error (_("\ 2916 Unable to decode Xtensa Window Interrupt Handler's code.")); 2917 2918 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */ 2919 cache->call0 = 0; /* It's Windowed ABI. */ 2920 2921 /* All registers for the cached frame will be alive. */ 2922 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) 2923 cache->wd.aregs[i] = -1; 2924 2925 if (eh_type == xtWindowOverflow) 2926 cache->wd.ws = ws ^ (1 << wb); 2927 else /* eh_type == xtWindowUnderflow. */ 2928 cache->wd.ws = ws | (1 << wb); 2929 2930 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */ 2931 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base, 2932 cache->wd.wb); 2933 ra = xtensa_read_register (regnum); 2934 cache->wd.callsize = WINSIZE (ra); 2935 cache->prev_sp = xtensa_read_register (regnum + 1); 2936 /* Set regnum to a frame pointer of the frame being cached. */ 2937 regnum = xtensa_scan_prologue (gdbarch, pc); 2938 regnum = arreg_number (gdbarch, 2939 gdbarch_tdep (gdbarch)->a0_base + regnum, 2940 cache->wd.wb); 2941 cache->base = get_frame_register_unsigned (this_frame, regnum); 2942 2943 /* Read PC of interrupted function from EPC1 register. */ 2944 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1"); 2945 if (epc1_regnum < 0) 2946 error(_("Unable to read Xtensa register EPC1")); 2947 cache->ra = xtensa_read_register (epc1_regnum); 2948 cache->pc = get_frame_func (this_frame); 2949 } 2950 2951 2952 /* Skip function prologue. 2953 2954 Return the pc of the first instruction after prologue. GDB calls this to 2955 find the address of the first line of the function or (if there is no line 2956 number information) to skip the prologue for planting breakpoints on 2957 function entries. Use debug info (if present) or prologue analysis to skip 2958 the prologue to achieve reliable debugging behavior. For windowed ABI, 2959 only the 'entry' instruction is skipped. It is not strictly necessary to 2960 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to 2961 backtrace at any point in the prologue, however certain potential hazards 2962 are avoided and a more "normal" debugging experience is ensured by 2963 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). 2964 For example, if we don't skip the prologue: 2965 - Some args may not yet have been saved to the stack where the debug 2966 info expects to find them (true anyway when only 'entry' is skipped); 2967 - Software breakpoints ('break' instrs) may not have been unplanted 2968 when the prologue analysis is done on initializing the frame cache, 2969 and breaks in the prologue will throw off the analysis. 2970 2971 If we have debug info ( line-number info, in particular ) we simply skip 2972 the code associated with the first function line effectively skipping 2973 the prologue code. It works even in cases like 2974 2975 int main() 2976 { int local_var = 1; 2977 .... 2978 } 2979 2980 because, for this source code, both Xtensa compilers will generate two 2981 separate entries ( with the same line number ) in dwarf line-number 2982 section to make sure there is a boundary between the prologue code and 2983 the rest of the function. 2984 2985 If there is no debug info, we need to analyze the code. */ 2986 2987 /* #define DONT_SKIP_PROLOGUE */ 2988 2989 static CORE_ADDR 2990 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 2991 { 2992 struct symtab_and_line prologue_sal; 2993 CORE_ADDR body_pc; 2994 2995 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); 2996 2997 #if DONT_SKIP_PROLOGUE 2998 return start_pc; 2999 #endif 3000 3001 /* Try to find first body line from debug info. */ 3002 3003 prologue_sal = find_pc_line (start_pc, 0); 3004 if (prologue_sal.line != 0) /* Found debug info. */ 3005 { 3006 /* In Call0, it is possible to have a function with only one instruction 3007 ('ret') resulting from a one-line optimized function that does nothing. 3008 In that case, prologue_sal.end may actually point to the start of the 3009 next function in the text section, causing a breakpoint to be set at 3010 the wrong place. Check, if the end address is within a different 3011 function, and if so return the start PC. We know we have symbol 3012 information. */ 3013 3014 CORE_ADDR end_func; 3015 3016 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) 3017 && call0_ret (start_pc, prologue_sal.end)) 3018 return start_pc; 3019 3020 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); 3021 if (end_func != start_pc) 3022 return start_pc; 3023 3024 return prologue_sal.end; 3025 } 3026 3027 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ 3028 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 3029 xtensa_alloc_frame_cache (0)); 3030 return body_pc != 0 ? body_pc : start_pc; 3031 } 3032 3033 /* Verify the current configuration. */ 3034 static void 3035 xtensa_verify_config (struct gdbarch *gdbarch) 3036 { 3037 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3038 string_file log; 3039 3040 /* Verify that we got a reasonable number of AREGS. */ 3041 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) 3042 log.printf (_("\ 3043 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), 3044 tdep->num_aregs); 3045 3046 /* Verify that certain registers exist. */ 3047 3048 if (tdep->pc_regnum == -1) 3049 log.printf (_("\n\tpc_regnum: No PC register")); 3050 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) 3051 log.printf (_("\n\tps_regnum: No PS register")); 3052 3053 if (tdep->isa_use_windowed_registers) 3054 { 3055 if (tdep->wb_regnum == -1) 3056 log.printf (_("\n\twb_regnum: No WB register")); 3057 if (tdep->ws_regnum == -1) 3058 log.printf (_("\n\tws_regnum: No WS register")); 3059 if (tdep->ar_base == -1) 3060 log.printf (_("\n\tar_base: No AR registers")); 3061 } 3062 3063 if (tdep->a0_base == -1) 3064 log.printf (_("\n\ta0_base: No Ax registers")); 3065 3066 if (!log.empty ()) 3067 internal_error (__FILE__, __LINE__, 3068 _("the following are invalid: %s"), log.c_str ()); 3069 } 3070 3071 3072 /* Derive specific register numbers from the array of registers. */ 3073 3074 static void 3075 xtensa_derive_tdep (struct gdbarch_tdep *tdep) 3076 { 3077 xtensa_register_t* rmap; 3078 int n, max_size = 4; 3079 3080 tdep->num_regs = 0; 3081 tdep->num_nopriv_regs = 0; 3082 3083 /* Special registers 0..255 (core). */ 3084 #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) 3085 /* User registers 0..255. */ 3086 #define XTENSA_DBREGN_UREG(n) (0x0300+(n)) 3087 3088 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) 3089 { 3090 if (rmap->target_number == 0x0020) 3091 tdep->pc_regnum = n; 3092 else if (rmap->target_number == 0x0100) 3093 tdep->ar_base = n; 3094 else if (rmap->target_number == 0x0000) 3095 tdep->a0_base = n; 3096 else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) 3097 tdep->wb_regnum = n; 3098 else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) 3099 tdep->ws_regnum = n; 3100 else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) 3101 tdep->debugcause_regnum = n; 3102 else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) 3103 tdep->exccause_regnum = n; 3104 else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) 3105 tdep->excvaddr_regnum = n; 3106 else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) 3107 tdep->lbeg_regnum = n; 3108 else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) 3109 tdep->lend_regnum = n; 3110 else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) 3111 tdep->lcount_regnum = n; 3112 else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) 3113 tdep->sar_regnum = n; 3114 else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) 3115 tdep->litbase_regnum = n; 3116 else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) 3117 tdep->ps_regnum = n; 3118 else if (rmap->target_number == XTENSA_DBREGN_UREG(231)) 3119 tdep->threadptr_regnum = n; 3120 #if 0 3121 else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) 3122 tdep->interrupt_regnum = n; 3123 else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) 3124 tdep->interrupt2_regnum = n; 3125 else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) 3126 tdep->cpenable_regnum = n; 3127 #endif 3128 3129 if (rmap->byte_size > max_size) 3130 max_size = rmap->byte_size; 3131 if (rmap->mask != 0 && tdep->num_regs == 0) 3132 tdep->num_regs = n; 3133 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 3134 && tdep->num_nopriv_regs == 0) 3135 tdep->num_nopriv_regs = n; 3136 } 3137 if (tdep->num_regs == 0) 3138 tdep->num_regs = tdep->num_nopriv_regs; 3139 3140 /* Number of pseudo registers. */ 3141 tdep->num_pseudo_regs = n - tdep->num_regs; 3142 3143 /* Empirically determined maximum sizes. */ 3144 tdep->max_register_raw_size = max_size; 3145 tdep->max_register_virtual_size = max_size; 3146 } 3147 3148 /* Module "constructor" function. */ 3149 3150 extern struct gdbarch_tdep xtensa_tdep; 3151 3152 static struct gdbarch * 3153 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 3154 { 3155 struct gdbarch_tdep *tdep; 3156 struct gdbarch *gdbarch; 3157 3158 DEBUGTRACE ("gdbarch_init()\n"); 3159 3160 if (!xtensa_default_isa) 3161 xtensa_default_isa = xtensa_isa_init (0, 0); 3162 3163 /* We have to set the byte order before we call gdbarch_alloc. */ 3164 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; 3165 3166 tdep = &xtensa_tdep; 3167 gdbarch = gdbarch_alloc (&info, tdep); 3168 xtensa_derive_tdep (tdep); 3169 3170 /* Verify our configuration. */ 3171 xtensa_verify_config (gdbarch); 3172 xtensa_session_once_reported = 0; 3173 3174 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); 3175 set_gdbarch_wchar_signed (gdbarch, 0); 3176 3177 /* Pseudo-Register read/write. */ 3178 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); 3179 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); 3180 3181 /* Set target information. */ 3182 set_gdbarch_num_regs (gdbarch, tdep->num_regs); 3183 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); 3184 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); 3185 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); 3186 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); 3187 3188 /* Renumber registers for known formats (stabs and dwarf2). */ 3189 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); 3190 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); 3191 3192 /* We provide our own function to get register information. */ 3193 set_gdbarch_register_name (gdbarch, xtensa_register_name); 3194 set_gdbarch_register_type (gdbarch, xtensa_register_type); 3195 3196 /* To call functions from GDB using dummy frame. */ 3197 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); 3198 3199 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 3200 3201 set_gdbarch_return_value (gdbarch, xtensa_return_value); 3202 3203 /* Advance PC across any prologue instructions to reach "real" code. */ 3204 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); 3205 3206 /* Stack grows downward. */ 3207 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 3208 3209 /* Set breakpoints. */ 3210 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 3211 xtensa_breakpoint_kind_from_pc); 3212 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 3213 xtensa_sw_breakpoint_from_kind); 3214 3215 /* After breakpoint instruction or illegal instruction, pc still 3216 points at break instruction, so don't decrement. */ 3217 set_gdbarch_decr_pc_after_break (gdbarch, 0); 3218 3219 /* We don't skip args. */ 3220 set_gdbarch_frame_args_skip (gdbarch, 0); 3221 3222 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); 3223 3224 set_gdbarch_frame_align (gdbarch, xtensa_frame_align); 3225 3226 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); 3227 3228 /* Frame handling. */ 3229 frame_base_set_default (gdbarch, &xtensa_frame_base); 3230 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); 3231 dwarf2_append_unwinders (gdbarch); 3232 3233 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 3234 3235 xtensa_add_reggroups (gdbarch); 3236 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); 3237 3238 set_gdbarch_iterate_over_regset_sections 3239 (gdbarch, xtensa_iterate_over_regset_sections); 3240 3241 set_solib_svr4_fetch_link_map_offsets 3242 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 3243 3244 /* Hook in the ABI-specific overrides, if they have been registered. */ 3245 gdbarch_init_osabi (info, gdbarch); 3246 3247 return gdbarch; 3248 } 3249 3250 static void 3251 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 3252 { 3253 error (_("xtensa_dump_tdep(): not implemented")); 3254 } 3255 3256 void 3257 _initialize_xtensa_tdep (void) 3258 { 3259 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); 3260 xtensa_init_reggroups (); 3261 3262 add_setshow_zuinteger_cmd ("xtensa", 3263 class_maintenance, 3264 &xtensa_debug_level, 3265 _("Set Xtensa debugging."), 3266 _("Show Xtensa debugging."), _("\ 3267 When non-zero, Xtensa-specific debugging is enabled. \ 3268 Can be 1, 2, 3, or 4 indicating the level of debugging."), 3269 NULL, 3270 NULL, 3271 &setdebuglist, &showdebuglist); 3272 } 3273