xref: /netbsd-src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/vsx-regs.exp (revision d536862b7d93d77932ef5de7eebdc48d76921b77) 
1# Copyright (C) 2008-2019 Free Software Foundation, Inc.
2#
3# This program is free software; you can redistribute it and/or modify
4# it under the terms of the GNU General Public License as published by
5# the Free Software Foundation; either version 3 of the License, or
6# (at your option) any later version.
7#
8# This program is distributed in the hope that it will be useful,
9# but WITHOUT ANY WARRANTY; without even the implied warranty of
10# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11# GNU General Public License for more details.
12#
13# You should have received a copy of the GNU General Public License
14# along with this program.  If not, see <http://www.gnu.org/licenses/>.
15#
16
17#
18# Test the use of VSX registers, for Powerpc.
19#
20
21
22if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
23    verbose "Skipping vsx register tests."
24    return
25}
26
27standard_testfile
28
29set compile_flags {debug nowarnings quiet}
30if [get_compiler_info] {
31    warning "get_compiler failed"
32    return -1
33}
34
35if [test_compiler_info gcc*] {
36    set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
37} elseif [test_compiler_info xlc*] {
38    set compile_flags "$compile_flags additional_flags=-qaltivec"
39} else {
40    warning "unknown compiler"
41    return -1
42}
43
44if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
45     untested "failed to compile"
46     return -1
47}
48
49gdb_start
50gdb_reinitialize_dir $srcdir/$subdir
51gdb_load ${binfile}
52
53# Run to `main' where we begin our tests.
54
55if ![runto_main] then {
56    fail "can't run to main"
57    return 0
58}
59
60set endianness [get_endianness]
61
62# Data sets used throughout the test
63
64if {$endianness == "big"} {
65    set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
66
67    set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
68
69    set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
70
71    set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
72
73    set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
74
75    set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
76} else {
77    set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
78
79    set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
80
81    set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
82
83    set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
84
85    set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
86
87    set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
88}
89
90set float_register ".raw 0xdeadbeefdeadbeef."
91
92# First run the F0~F31/VS0~VS31 tests
93
94# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
95for {set i 0} {$i < 32} {incr i 1} {
96    gdb_test_no_output "set \$f$i = 1\.3"
97}
98
99for {set i 0} {$i < 32} {incr i 1} {
100    gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
101}
102
103# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
104for {set i 0} {$i < 32} {incr i 1} {
105        for {set j 0} {$j < 4} {incr j 1} {
106           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
107        }
108}
109
110for {set i 0} {$i < 32} {incr i 1} {
111    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
112}
113
114for {set i 0} {$i < 32} {incr i 1} {
115    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
116}
117
118# Now run the VR0~VR31/VS32~VS63 tests
119
120# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
121for {set i 0} {$i < 32} {incr i 1} {
122        for {set j 0} {$j < 4} {incr j 1} {
123           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
124        }
125}
126
127for {set i 32} {$i < 64} {incr i 1} {
128    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
129}
130# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
131for {set i 32} {$i < 64} {incr i 1} {
132        for {set j 0} {$j < 4} {incr j 1} {
133           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
134        }
135}
136
137for {set i 0} {$i < 32} {incr i 1} {
138    gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
139    gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i"
140}
141
142# Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
143# below because then we'll have more interesting register values to verify
144# later when loading the core file (i.e., different register values for different
145# vector register banks).
146
147set corefile [standard_output_file vsx-core.test]
148set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]
149
150# Now run the F32~F63/VR0~VR31 tests.
151
152# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
153for {set i 32} {$i < 64} {incr i 1} {
154    gdb_test_no_output "set \$f$i = 1\.3"
155}
156
157for {set i 0} {$i < 32} {incr i 1} {
158    gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
159    gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)"
160}
161
162# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
163for {set i 0} {$i < 32} {incr i 1} {
164        for {set j 0} {$j < 4} {incr j 1} {
165           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
166        }
167}
168
169for {set i 32} {$i < 64} {incr i 1} {
170    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
171}
172
173for {set i 0} {$i < 32} {incr i 1} {
174    gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
175    gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)"
176}
177
178# Test reading the core file.
179
180if {!$core_supported} {
181  return -1
182}
183
184gdb_exit
185gdb_start
186gdb_reinitialize_dir $srcdir/$subdir
187gdb_load ${binfile}
188
189set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
190if { $core_loaded == -1 } {
191    # No use proceeding from here.
192    return
193}
194
195for {set i 0} {$i < 32} {incr i 1} {
196    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
197}
198
199for {set i 32} {$i < 64} {incr i 1} {
200    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"
201}
202