1 /* Target-dependent code for SPARC. 2 3 Copyright (C) 2003-2017 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "arch-utils.h" 22 #include "dis-asm.h" 23 #include "dwarf2-frame.h" 24 #include "floatformat.h" 25 #include "frame.h" 26 #include "frame-base.h" 27 #include "frame-unwind.h" 28 #include "gdbcore.h" 29 #include "gdbtypes.h" 30 #include "inferior.h" 31 #include "symtab.h" 32 #include "objfiles.h" 33 #include "osabi.h" 34 #include "regcache.h" 35 #include "target.h" 36 #include "target-descriptions.h" 37 #include "value.h" 38 39 #include "sparc-tdep.h" 40 #include "sparc-ravenscar-thread.h" 41 #include <algorithm> 42 43 struct regset; 44 45 /* This file implements the SPARC 32-bit ABI as defined by the section 46 "Low-Level System Information" of the SPARC Compliance Definition 47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD 48 lists changes with respect to the original 32-bit psABI as defined 49 in the "System V ABI, SPARC Processor Supplement". 50 51 Note that if we talk about SunOS, we mean SunOS 4.x, which was 52 BSD-based, which is sometimes (retroactively?) referred to as 53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and 54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 55 suffering from severe version number inflation). Solaris 2.x is 56 also known as SunOS 5.x, since that's what uname(1) says. Solaris 57 2.x is SVR4-based. */ 58 59 /* Please use the sparc32_-prefix for 32-bit specific code, the 60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for 61 code that can handle both. The 64-bit specific code lives in 62 sparc64-tdep.c; don't add any here. */ 63 64 /* The SPARC Floating-Point Quad-Precision format is similar to 65 big-endian IA-64 Quad-Precision format. */ 66 #define floatformats_sparc_quad floatformats_ia64_quad 67 68 /* The stack pointer is offset from the stack frame by a BIAS of 2047 69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC 70 hosts, so undefine it first. */ 71 #undef BIAS 72 #define BIAS 2047 73 74 /* Macros to extract fields from SPARC instructions. */ 75 #define X_OP(i) (((i) >> 30) & 0x3) 76 #define X_RD(i) (((i) >> 25) & 0x1f) 77 #define X_A(i) (((i) >> 29) & 1) 78 #define X_COND(i) (((i) >> 25) & 0xf) 79 #define X_OP2(i) (((i) >> 22) & 0x7) 80 #define X_IMM22(i) ((i) & 0x3fffff) 81 #define X_OP3(i) (((i) >> 19) & 0x3f) 82 #define X_RS1(i) (((i) >> 14) & 0x1f) 83 #define X_RS2(i) ((i) & 0x1f) 84 #define X_I(i) (((i) >> 13) & 1) 85 /* Sign extension macros. */ 86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) 89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) 90 /* Macros to identify some instructions. */ 91 /* RETURN (RETT in V8) */ 92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) 93 94 /* Fetch the instruction at PC. Instructions are always big-endian 95 even if the processor operates in little-endian mode. */ 96 97 unsigned long 98 sparc_fetch_instruction (CORE_ADDR pc) 99 { 100 gdb_byte buf[4]; 101 unsigned long insn; 102 int i; 103 104 /* If we can't read the instruction at PC, return zero. */ 105 if (target_read_memory (pc, buf, sizeof (buf))) 106 return 0; 107 108 insn = 0; 109 for (i = 0; i < sizeof (buf); i++) 110 insn = (insn << 8) | buf[i]; 111 return insn; 112 } 113 114 115 /* Return non-zero if the instruction corresponding to PC is an "unimp" 116 instruction. */ 117 118 static int 119 sparc_is_unimp_insn (CORE_ADDR pc) 120 { 121 const unsigned long insn = sparc_fetch_instruction (pc); 122 123 return ((insn & 0xc1c00000) == 0); 124 } 125 126 /* Return non-zero if the instruction corresponding to PC is an 127 "annulled" branch, i.e. the annul bit is set. */ 128 129 int 130 sparc_is_annulled_branch_insn (CORE_ADDR pc) 131 { 132 /* The branch instructions featuring an annul bit can be identified 133 by the following bit patterns: 134 135 OP=0 136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). 137 OP2=2: Branch on Integer Condition Codes (Bcc). 138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). 139 OP2=6: Branch on FP Condition Codes (FBcc). 140 OP2=3 && Bit28=0: 141 Branch on Integer Register with Prediction (BPr). 142 143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 144 coprocessor branch instructions (Op2=7). */ 145 146 const unsigned long insn = sparc_fetch_instruction (pc); 147 const unsigned op2 = X_OP2 (insn); 148 149 if ((X_OP (insn) == 0) 150 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) 151 || ((op2 == 3) && ((insn & 0x10000000) == 0)))) 152 return X_A (insn); 153 else 154 return 0; 155 } 156 157 /* OpenBSD/sparc includes StackGhost, which according to the author's 158 website http://stackghost.cerias.purdue.edu "... transparently and 159 automatically protects applications' stack frames; more 160 specifically, it guards the return pointers. The protection 161 mechanisms require no application source or binary modification and 162 imposes only a negligible performance penalty." 163 164 The same website provides the following description of how 165 StackGhost works: 166 167 "StackGhost interfaces with the kernel trap handler that would 168 normally write out registers to the stack and the handler that 169 would read them back in. By XORing a cookie into the 170 return-address saved in the user stack when it is actually written 171 to the stack, and then XOR it out when the return-address is pulled 172 from the stack, StackGhost can cause attacker corrupted return 173 pointers to behave in a manner the attacker cannot predict. 174 StackGhost can also use several unused bits in the return pointer 175 to detect a smashed return pointer and abort the process." 176 177 For GDB this means that whenever we're reading %i7 from a stack 178 frame's window save area, we'll have to XOR the cookie. 179 180 More information on StackGuard can be found on in: 181 182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated 183 Stack Protection." 2001. Published in USENIX Security Symposium 184 '01. */ 185 186 /* Fetch StackGhost Per-Process XOR cookie. */ 187 188 ULONGEST 189 sparc_fetch_wcookie (struct gdbarch *gdbarch) 190 { 191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 192 struct target_ops *ops = ¤t_target; 193 gdb_byte buf[8]; 194 int len; 195 196 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); 197 if (len == -1) 198 return 0; 199 200 /* We should have either an 32-bit or an 64-bit cookie. */ 201 gdb_assert (len == 4 || len == 8); 202 203 return extract_unsigned_integer (buf, len, byte_order); 204 } 205 206 207 /* The functions on this page are intended to be used to classify 208 function arguments. */ 209 210 /* Check whether TYPE is "Integral or Pointer". */ 211 212 static int 213 sparc_integral_or_pointer_p (const struct type *type) 214 { 215 int len = TYPE_LENGTH (type); 216 217 switch (TYPE_CODE (type)) 218 { 219 case TYPE_CODE_INT: 220 case TYPE_CODE_BOOL: 221 case TYPE_CODE_CHAR: 222 case TYPE_CODE_ENUM: 223 case TYPE_CODE_RANGE: 224 /* We have byte, half-word, word and extended-word/doubleword 225 integral types. The doubleword is an extension to the 226 original 32-bit ABI by the SCD 2.4.x. */ 227 return (len == 1 || len == 2 || len == 4 || len == 8); 228 case TYPE_CODE_PTR: 229 case TYPE_CODE_REF: 230 case TYPE_CODE_RVALUE_REF: 231 /* Allow either 32-bit or 64-bit pointers. */ 232 return (len == 4 || len == 8); 233 default: 234 break; 235 } 236 237 return 0; 238 } 239 240 /* Check whether TYPE is "Floating". */ 241 242 static int 243 sparc_floating_p (const struct type *type) 244 { 245 switch (TYPE_CODE (type)) 246 { 247 case TYPE_CODE_FLT: 248 { 249 int len = TYPE_LENGTH (type); 250 return (len == 4 || len == 8 || len == 16); 251 } 252 default: 253 break; 254 } 255 256 return 0; 257 } 258 259 /* Check whether TYPE is "Complex Floating". */ 260 261 static int 262 sparc_complex_floating_p (const struct type *type) 263 { 264 switch (TYPE_CODE (type)) 265 { 266 case TYPE_CODE_COMPLEX: 267 { 268 int len = TYPE_LENGTH (type); 269 return (len == 8 || len == 16 || len == 32); 270 } 271 default: 272 break; 273 } 274 275 return 0; 276 } 277 278 /* Check whether TYPE is "Structure or Union". 279 280 In terms of Ada subprogram calls, arrays are treated the same as 281 struct and union types. So this function also returns non-zero 282 for array types. */ 283 284 static int 285 sparc_structure_or_union_p (const struct type *type) 286 { 287 switch (TYPE_CODE (type)) 288 { 289 case TYPE_CODE_STRUCT: 290 case TYPE_CODE_UNION: 291 case TYPE_CODE_ARRAY: 292 return 1; 293 default: 294 break; 295 } 296 297 return 0; 298 } 299 300 /* Register information. */ 301 #define SPARC32_FPU_REGISTERS \ 302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ 305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 306 #define SPARC32_CP0_REGISTERS \ 307 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" 308 309 static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; 310 static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; 311 static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; 312 313 static const char *sparc32_register_names[] = 314 { 315 SPARC_CORE_REGISTERS, 316 SPARC32_FPU_REGISTERS, 317 SPARC32_CP0_REGISTERS 318 }; 319 320 /* Total number of registers. */ 321 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) 322 323 /* We provide the aliases %d0..%d30 for the floating registers as 324 "psuedo" registers. */ 325 326 static const char *sparc32_pseudo_register_names[] = 327 { 328 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", 329 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" 330 }; 331 332 /* Total number of pseudo registers. */ 333 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) 334 335 /* Return the name of pseudo register REGNUM. */ 336 337 static const char * 338 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 339 { 340 regnum -= gdbarch_num_regs (gdbarch); 341 342 if (regnum < SPARC32_NUM_PSEUDO_REGS) 343 return sparc32_pseudo_register_names[regnum]; 344 345 internal_error (__FILE__, __LINE__, 346 _("sparc32_pseudo_register_name: bad register number %d"), 347 regnum); 348 } 349 350 /* Return the name of register REGNUM. */ 351 352 static const char * 353 sparc32_register_name (struct gdbarch *gdbarch, int regnum) 354 { 355 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 356 return tdesc_register_name (gdbarch, regnum); 357 358 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 359 return sparc32_register_names[regnum]; 360 361 return sparc32_pseudo_register_name (gdbarch, regnum); 362 } 363 364 /* Construct types for ISA-specific registers. */ 365 366 static struct type * 367 sparc_psr_type (struct gdbarch *gdbarch) 368 { 369 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 370 371 if (!tdep->sparc_psr_type) 372 { 373 struct type *type; 374 375 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); 376 append_flags_type_flag (type, 5, "ET"); 377 append_flags_type_flag (type, 6, "PS"); 378 append_flags_type_flag (type, 7, "S"); 379 append_flags_type_flag (type, 12, "EF"); 380 append_flags_type_flag (type, 13, "EC"); 381 382 tdep->sparc_psr_type = type; 383 } 384 385 return tdep->sparc_psr_type; 386 } 387 388 static struct type * 389 sparc_fsr_type (struct gdbarch *gdbarch) 390 { 391 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 392 393 if (!tdep->sparc_fsr_type) 394 { 395 struct type *type; 396 397 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); 398 append_flags_type_flag (type, 0, "NXA"); 399 append_flags_type_flag (type, 1, "DZA"); 400 append_flags_type_flag (type, 2, "UFA"); 401 append_flags_type_flag (type, 3, "OFA"); 402 append_flags_type_flag (type, 4, "NVA"); 403 append_flags_type_flag (type, 5, "NXC"); 404 append_flags_type_flag (type, 6, "DZC"); 405 append_flags_type_flag (type, 7, "UFC"); 406 append_flags_type_flag (type, 8, "OFC"); 407 append_flags_type_flag (type, 9, "NVC"); 408 append_flags_type_flag (type, 22, "NS"); 409 append_flags_type_flag (type, 23, "NXM"); 410 append_flags_type_flag (type, 24, "DZM"); 411 append_flags_type_flag (type, 25, "UFM"); 412 append_flags_type_flag (type, 26, "OFM"); 413 append_flags_type_flag (type, 27, "NVM"); 414 415 tdep->sparc_fsr_type = type; 416 } 417 418 return tdep->sparc_fsr_type; 419 } 420 421 /* Return the GDB type object for the "standard" data type of data in 422 pseudo register REGNUM. */ 423 424 static struct type * 425 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 426 { 427 regnum -= gdbarch_num_regs (gdbarch); 428 429 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) 430 return builtin_type (gdbarch)->builtin_double; 431 432 internal_error (__FILE__, __LINE__, 433 _("sparc32_pseudo_register_type: bad register number %d"), 434 regnum); 435 } 436 437 /* Return the GDB type object for the "standard" data type of data in 438 register REGNUM. */ 439 440 static struct type * 441 sparc32_register_type (struct gdbarch *gdbarch, int regnum) 442 { 443 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 444 return tdesc_register_type (gdbarch, regnum); 445 446 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) 447 return builtin_type (gdbarch)->builtin_float; 448 449 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) 450 return builtin_type (gdbarch)->builtin_data_ptr; 451 452 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 453 return builtin_type (gdbarch)->builtin_func_ptr; 454 455 if (regnum == SPARC32_PSR_REGNUM) 456 return sparc_psr_type (gdbarch); 457 458 if (regnum == SPARC32_FSR_REGNUM) 459 return sparc_fsr_type (gdbarch); 460 461 if (regnum >= gdbarch_num_regs (gdbarch)) 462 return sparc32_pseudo_register_type (gdbarch, regnum); 463 464 return builtin_type (gdbarch)->builtin_int32; 465 } 466 467 static enum register_status 468 sparc32_pseudo_register_read (struct gdbarch *gdbarch, 469 struct regcache *regcache, 470 int regnum, gdb_byte *buf) 471 { 472 enum register_status status; 473 474 regnum -= gdbarch_num_regs (gdbarch); 475 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 476 477 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 478 status = regcache_raw_read (regcache, regnum, buf); 479 if (status == REG_VALID) 480 status = regcache_raw_read (regcache, regnum + 1, buf + 4); 481 return status; 482 } 483 484 static void 485 sparc32_pseudo_register_write (struct gdbarch *gdbarch, 486 struct regcache *regcache, 487 int regnum, const gdb_byte *buf) 488 { 489 regnum -= gdbarch_num_regs (gdbarch); 490 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 491 492 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 493 regcache_raw_write (regcache, regnum, buf); 494 regcache_raw_write (regcache, regnum + 1, buf + 4); 495 } 496 497 /* Implement the stack_frame_destroyed_p gdbarch method. */ 498 499 int 500 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 501 { 502 /* This function must return true if we are one instruction after an 503 instruction that destroyed the stack frame of the current 504 function. The SPARC instructions used to restore the callers 505 stack frame are RESTORE and RETURN/RETT. 506 507 Of these RETURN/RETT is a branch instruction and thus we return 508 true if we are in its delay slot. 509 510 RESTORE is almost always found in the delay slot of a branch 511 instruction that transfers control to the caller, such as JMPL. 512 Thus the next instruction is in the caller frame and we don't 513 need to do anything about it. */ 514 515 unsigned int insn = sparc_fetch_instruction (pc - 4); 516 517 return X_RETTURN (insn); 518 } 519 520 521 static CORE_ADDR 522 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 523 { 524 /* The ABI requires double-word alignment. */ 525 return address & ~0x7; 526 } 527 528 static CORE_ADDR 529 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 530 CORE_ADDR funcaddr, 531 struct value **args, int nargs, 532 struct type *value_type, 533 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 534 struct regcache *regcache) 535 { 536 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 537 538 *bp_addr = sp - 4; 539 *real_pc = funcaddr; 540 541 if (using_struct_return (gdbarch, NULL, value_type)) 542 { 543 gdb_byte buf[4]; 544 545 /* This is an UNIMP instruction. */ 546 store_unsigned_integer (buf, 4, byte_order, 547 TYPE_LENGTH (value_type) & 0x1fff); 548 write_memory (sp - 8, buf, 4); 549 return sp - 8; 550 } 551 552 return sp - 4; 553 } 554 555 static CORE_ADDR 556 sparc32_store_arguments (struct regcache *regcache, int nargs, 557 struct value **args, CORE_ADDR sp, 558 int struct_return, CORE_ADDR struct_addr) 559 { 560 struct gdbarch *gdbarch = get_regcache_arch (regcache); 561 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 562 /* Number of words in the "parameter array". */ 563 int num_elements = 0; 564 int element = 0; 565 int i; 566 567 for (i = 0; i < nargs; i++) 568 { 569 struct type *type = value_type (args[i]); 570 int len = TYPE_LENGTH (type); 571 572 if (sparc_structure_or_union_p (type) 573 || (sparc_floating_p (type) && len == 16) 574 || sparc_complex_floating_p (type)) 575 { 576 /* Structure, Union and Quad-Precision Arguments. */ 577 sp -= len; 578 579 /* Use doubleword alignment for these values. That's always 580 correct, and wasting a few bytes shouldn't be a problem. */ 581 sp &= ~0x7; 582 583 write_memory (sp, value_contents (args[i]), len); 584 args[i] = value_from_pointer (lookup_pointer_type (type), sp); 585 num_elements++; 586 } 587 else if (sparc_floating_p (type)) 588 { 589 /* Floating arguments. */ 590 gdb_assert (len == 4 || len == 8); 591 num_elements += (len / 4); 592 } 593 else 594 { 595 /* Integral and pointer arguments. */ 596 gdb_assert (sparc_integral_or_pointer_p (type)); 597 598 if (len < 4) 599 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, 600 args[i]); 601 num_elements += ((len + 3) / 4); 602 } 603 } 604 605 /* Always allocate at least six words. */ 606 sp -= std::max (6, num_elements) * 4; 607 608 /* The psABI says that "Software convention requires space for the 609 struct/union return value pointer, even if the word is unused." */ 610 sp -= 4; 611 612 /* The psABI says that "Although software convention and the 613 operating system require every stack frame to be doubleword 614 aligned." */ 615 sp &= ~0x7; 616 617 for (i = 0; i < nargs; i++) 618 { 619 const bfd_byte *valbuf = value_contents (args[i]); 620 struct type *type = value_type (args[i]); 621 int len = TYPE_LENGTH (type); 622 623 gdb_assert (len == 4 || len == 8); 624 625 if (element < 6) 626 { 627 int regnum = SPARC_O0_REGNUM + element; 628 629 regcache_cooked_write (regcache, regnum, valbuf); 630 if (len > 4 && element < 5) 631 regcache_cooked_write (regcache, regnum + 1, valbuf + 4); 632 } 633 634 /* Always store the argument in memory. */ 635 write_memory (sp + 4 + element * 4, valbuf, len); 636 element += len / 4; 637 } 638 639 gdb_assert (element == num_elements); 640 641 if (struct_return) 642 { 643 gdb_byte buf[4]; 644 645 store_unsigned_integer (buf, 4, byte_order, struct_addr); 646 write_memory (sp, buf, 4); 647 } 648 649 return sp; 650 } 651 652 static CORE_ADDR 653 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 654 struct regcache *regcache, CORE_ADDR bp_addr, 655 int nargs, struct value **args, CORE_ADDR sp, 656 int struct_return, CORE_ADDR struct_addr) 657 { 658 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); 659 660 /* Set return address. */ 661 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); 662 663 /* Set up function arguments. */ 664 sp = sparc32_store_arguments (regcache, nargs, args, sp, 665 struct_return, struct_addr); 666 667 /* Allocate the 16-word window save area. */ 668 sp -= 16 * 4; 669 670 /* Stack should be doubleword aligned at this point. */ 671 gdb_assert (sp % 8 == 0); 672 673 /* Finally, update the stack pointer. */ 674 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); 675 676 return sp; 677 } 678 679 680 /* Use the program counter to determine the contents and size of a 681 breakpoint instruction. Return a pointer to a string of bytes that 682 encode a breakpoint instruction, store the length of the string in 683 *LEN and optionally adjust *PC to point to the correct memory 684 location for inserting the breakpoint. */ 685 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; 686 687 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; 688 689 690 /* Allocate and initialize a frame cache. */ 691 692 static struct sparc_frame_cache * 693 sparc_alloc_frame_cache (void) 694 { 695 struct sparc_frame_cache *cache; 696 697 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); 698 699 /* Base address. */ 700 cache->base = 0; 701 cache->pc = 0; 702 703 /* Frameless until proven otherwise. */ 704 cache->frameless_p = 1; 705 cache->frame_offset = 0; 706 cache->saved_regs_mask = 0; 707 cache->copied_regs_mask = 0; 708 cache->struct_return_p = 0; 709 710 return cache; 711 } 712 713 /* GCC generates several well-known sequences of instructions at the begining 714 of each function prologue when compiling with -fstack-check. If one of 715 such sequences starts at START_PC, then return the address of the 716 instruction immediately past this sequence. Otherwise, return START_PC. */ 717 718 static CORE_ADDR 719 sparc_skip_stack_check (const CORE_ADDR start_pc) 720 { 721 CORE_ADDR pc = start_pc; 722 unsigned long insn; 723 int probing_loop = 0; 724 725 /* With GCC, all stack checking sequences begin with the same two 726 instructions, plus an optional one in the case of a probing loop: 727 728 sethi <some immediate>, %g1 729 sub %sp, %g1, %g1 730 731 or: 732 733 sethi <some immediate>, %g1 734 sethi <some immediate>, %g4 735 sub %sp, %g1, %g1 736 737 or: 738 739 sethi <some immediate>, %g1 740 sub %sp, %g1, %g1 741 sethi <some immediate>, %g4 742 743 If the optional instruction is found (setting g4), assume that a 744 probing loop will follow. */ 745 746 /* sethi <some immediate>, %g1 */ 747 insn = sparc_fetch_instruction (pc); 748 pc = pc + 4; 749 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) 750 return start_pc; 751 752 /* optional: sethi <some immediate>, %g4 */ 753 insn = sparc_fetch_instruction (pc); 754 pc = pc + 4; 755 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 756 { 757 probing_loop = 1; 758 insn = sparc_fetch_instruction (pc); 759 pc = pc + 4; 760 } 761 762 /* sub %sp, %g1, %g1 */ 763 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 764 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) 765 return start_pc; 766 767 insn = sparc_fetch_instruction (pc); 768 pc = pc + 4; 769 770 /* optional: sethi <some immediate>, %g4 */ 771 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 772 { 773 probing_loop = 1; 774 insn = sparc_fetch_instruction (pc); 775 pc = pc + 4; 776 } 777 778 /* First possible sequence: 779 [first two instructions above] 780 clr [%g1 - some immediate] */ 781 782 /* clr [%g1 - some immediate] */ 783 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 784 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 785 { 786 /* Valid stack-check sequence, return the new PC. */ 787 return pc; 788 } 789 790 /* Second possible sequence: A small number of probes. 791 [first two instructions above] 792 clr [%g1] 793 add %g1, -<some immediate>, %g1 794 clr [%g1] 795 [repeat the two instructions above any (small) number of times] 796 clr [%g1 - some immediate] */ 797 798 /* clr [%g1] */ 799 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 800 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 801 { 802 while (1) 803 { 804 /* add %g1, -<some immediate>, %g1 */ 805 insn = sparc_fetch_instruction (pc); 806 pc = pc + 4; 807 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 808 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 809 break; 810 811 /* clr [%g1] */ 812 insn = sparc_fetch_instruction (pc); 813 pc = pc + 4; 814 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 815 && X_RD (insn) == 0 && X_RS1 (insn) == 1)) 816 return start_pc; 817 } 818 819 /* clr [%g1 - some immediate] */ 820 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 821 && X_RS1 (insn) == 1 && X_RD (insn) == 0)) 822 return start_pc; 823 824 /* We found a valid stack-check sequence, return the new PC. */ 825 return pc; 826 } 827 828 /* Third sequence: A probing loop. 829 [first three instructions above] 830 sub %g1, %g4, %g4 831 cmp %g1, %g4 832 be <disp> 833 add %g1, -<some immediate>, %g1 834 ba <disp> 835 clr [%g1] 836 837 And an optional last probe for the remainder: 838 839 clr [%g4 - some immediate] */ 840 841 if (probing_loop) 842 { 843 /* sub %g1, %g4, %g4 */ 844 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 845 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 846 return start_pc; 847 848 /* cmp %g1, %g4 */ 849 insn = sparc_fetch_instruction (pc); 850 pc = pc + 4; 851 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) 852 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 853 return start_pc; 854 855 /* be <disp> */ 856 insn = sparc_fetch_instruction (pc); 857 pc = pc + 4; 858 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) 859 return start_pc; 860 861 /* add %g1, -<some immediate>, %g1 */ 862 insn = sparc_fetch_instruction (pc); 863 pc = pc + 4; 864 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 865 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 866 return start_pc; 867 868 /* ba <disp> */ 869 insn = sparc_fetch_instruction (pc); 870 pc = pc + 4; 871 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) 872 return start_pc; 873 874 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ 875 insn = sparc_fetch_instruction (pc); 876 pc = pc + 4; 877 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 878 && X_RD (insn) == 0 && X_RS1 (insn) == 1 879 && (!X_I(insn) || X_SIMM13 (insn) == 0))) 880 return start_pc; 881 882 /* We found a valid stack-check sequence, return the new PC. */ 883 884 /* optional: clr [%g4 - some immediate] */ 885 insn = sparc_fetch_instruction (pc); 886 pc = pc + 4; 887 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 888 && X_RS1 (insn) == 4 && X_RD (insn) == 0)) 889 return pc - 4; 890 else 891 return pc; 892 } 893 894 /* No stack check code in our prologue, return the start_pc. */ 895 return start_pc; 896 } 897 898 /* Record the effect of a SAVE instruction on CACHE. */ 899 900 void 901 sparc_record_save_insn (struct sparc_frame_cache *cache) 902 { 903 /* The frame is set up. */ 904 cache->frameless_p = 0; 905 906 /* The frame pointer contains the CFA. */ 907 cache->frame_offset = 0; 908 909 /* The `local' and `in' registers are all saved. */ 910 cache->saved_regs_mask = 0xffff; 911 912 /* The `out' registers are all renamed. */ 913 cache->copied_regs_mask = 0xff; 914 } 915 916 /* Do a full analysis of the prologue at PC and update CACHE accordingly. 917 Bail out early if CURRENT_PC is reached. Return the address where 918 the analysis stopped. 919 920 We handle both the traditional register window model and the single 921 register window (aka flat) model. */ 922 923 CORE_ADDR 924 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, 925 CORE_ADDR current_pc, struct sparc_frame_cache *cache) 926 { 927 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 928 unsigned long insn; 929 int offset = 0; 930 int dest = -1; 931 932 pc = sparc_skip_stack_check (pc); 933 934 if (current_pc <= pc) 935 return current_pc; 936 937 /* We have to handle to "Procedure Linkage Table" (PLT) special. On 938 SPARC the linker usually defines a symbol (typically 939 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. 940 This symbol makes us end up here with PC pointing at the start of 941 the PLT and CURRENT_PC probably pointing at a PLT entry. If we 942 would do our normal prologue analysis, we would probably conclude 943 that we've got a frame when in reality we don't, since the 944 dynamic linker patches up the first PLT with some code that 945 starts with a SAVE instruction. Patch up PC such that it points 946 at the start of our PLT entry. */ 947 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) 948 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); 949 950 insn = sparc_fetch_instruction (pc); 951 952 /* Recognize store insns and record their sources. */ 953 while (X_OP (insn) == 3 954 && (X_OP3 (insn) == 0x4 /* stw */ 955 || X_OP3 (insn) == 0x7 /* std */ 956 || X_OP3 (insn) == 0xe) /* stx */ 957 && X_RS1 (insn) == SPARC_SP_REGNUM) 958 { 959 int regnum = X_RD (insn); 960 961 /* Recognize stores into the corresponding stack slots. */ 962 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 963 && ((X_I (insn) 964 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe 965 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS 966 : (regnum - SPARC_L0_REGNUM) * 4)) 967 || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) 968 { 969 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); 970 if (X_OP3 (insn) == 0x7) 971 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); 972 } 973 974 offset += 4; 975 976 insn = sparc_fetch_instruction (pc + offset); 977 } 978 979 /* Recognize a SETHI insn and record its destination. */ 980 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) 981 { 982 dest = X_RD (insn); 983 offset += 4; 984 985 insn = sparc_fetch_instruction (pc + offset); 986 } 987 988 /* Allow for an arithmetic operation on DEST or %g1. */ 989 if (X_OP (insn) == 2 && X_I (insn) 990 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 991 { 992 offset += 4; 993 994 insn = sparc_fetch_instruction (pc + offset); 995 } 996 997 /* Check for the SAVE instruction that sets up the frame. */ 998 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) 999 { 1000 sparc_record_save_insn (cache); 1001 offset += 4; 1002 return pc + offset; 1003 } 1004 1005 /* Check for an arithmetic operation on %sp. */ 1006 if (X_OP (insn) == 2 1007 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1008 && X_RS1 (insn) == SPARC_SP_REGNUM 1009 && X_RD (insn) == SPARC_SP_REGNUM) 1010 { 1011 if (X_I (insn)) 1012 { 1013 cache->frame_offset = X_SIMM13 (insn); 1014 if (X_OP3 (insn) == 0) 1015 cache->frame_offset = -cache->frame_offset; 1016 } 1017 offset += 4; 1018 1019 insn = sparc_fetch_instruction (pc + offset); 1020 1021 /* Check for an arithmetic operation that sets up the frame. */ 1022 if (X_OP (insn) == 2 1023 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1024 && X_RS1 (insn) == SPARC_SP_REGNUM 1025 && X_RD (insn) == SPARC_FP_REGNUM) 1026 { 1027 cache->frameless_p = 0; 1028 cache->frame_offset = 0; 1029 /* We could check that the amount subtracted to %sp above is the 1030 same as the one added here, but this seems superfluous. */ 1031 cache->copied_regs_mask |= 0x40; 1032 offset += 4; 1033 1034 insn = sparc_fetch_instruction (pc + offset); 1035 } 1036 1037 /* Check for a move (or) operation that copies the return register. */ 1038 if (X_OP (insn) == 2 1039 && X_OP3 (insn) == 0x2 1040 && !X_I (insn) 1041 && X_RS1 (insn) == SPARC_G0_REGNUM 1042 && X_RS2 (insn) == SPARC_O7_REGNUM 1043 && X_RD (insn) == SPARC_I7_REGNUM) 1044 { 1045 cache->copied_regs_mask |= 0x80; 1046 offset += 4; 1047 } 1048 1049 return pc + offset; 1050 } 1051 1052 return pc; 1053 } 1054 1055 static CORE_ADDR 1056 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) 1057 { 1058 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1059 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); 1060 } 1061 1062 /* Return PC of first real instruction of the function starting at 1063 START_PC. */ 1064 1065 static CORE_ADDR 1066 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1067 { 1068 struct symtab_and_line sal; 1069 CORE_ADDR func_start, func_end; 1070 struct sparc_frame_cache cache; 1071 1072 /* This is the preferred method, find the end of the prologue by 1073 using the debugging information. */ 1074 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) 1075 { 1076 sal = find_pc_line (func_start, 0); 1077 1078 if (sal.end < func_end 1079 && start_pc <= sal.end) 1080 return sal.end; 1081 } 1082 1083 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); 1084 1085 /* The psABI says that "Although the first 6 words of arguments 1086 reside in registers, the standard stack frame reserves space for 1087 them.". It also suggests that a function may use that space to 1088 "write incoming arguments 0 to 5" into that space, and that's 1089 indeed what GCC seems to be doing. In that case GCC will 1090 generate debug information that points to the stack slots instead 1091 of the registers, so we should consider the instructions that 1092 write out these incoming arguments onto the stack. */ 1093 1094 while (1) 1095 { 1096 unsigned long insn = sparc_fetch_instruction (start_pc); 1097 1098 /* Recognize instructions that store incoming arguments into the 1099 corresponding stack slots. */ 1100 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 1101 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) 1102 { 1103 int regnum = X_RD (insn); 1104 1105 /* Case of arguments still in %o[0..5]. */ 1106 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM 1107 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) 1108 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) 1109 { 1110 start_pc += 4; 1111 continue; 1112 } 1113 1114 /* Case of arguments copied into %i[0..5]. */ 1115 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM 1116 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) 1117 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) 1118 { 1119 start_pc += 4; 1120 continue; 1121 } 1122 } 1123 1124 break; 1125 } 1126 1127 return start_pc; 1128 } 1129 1130 /* Normal frames. */ 1131 1132 struct sparc_frame_cache * 1133 sparc_frame_cache (struct frame_info *this_frame, void **this_cache) 1134 { 1135 struct sparc_frame_cache *cache; 1136 1137 if (*this_cache) 1138 return (struct sparc_frame_cache *) *this_cache; 1139 1140 cache = sparc_alloc_frame_cache (); 1141 *this_cache = cache; 1142 1143 cache->pc = get_frame_func (this_frame); 1144 if (cache->pc != 0) 1145 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, 1146 get_frame_pc (this_frame), cache); 1147 1148 if (cache->frameless_p) 1149 { 1150 /* This function is frameless, so %fp (%i6) holds the frame 1151 pointer for our calling frame. Use %sp (%o6) as this frame's 1152 base address. */ 1153 cache->base = 1154 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1155 } 1156 else 1157 { 1158 /* For normal frames, %fp (%i6) holds the frame pointer, the 1159 base address for the current stack frame. */ 1160 cache->base = 1161 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); 1162 } 1163 1164 cache->base += cache->frame_offset; 1165 1166 if (cache->base & 1) 1167 cache->base += BIAS; 1168 1169 return cache; 1170 } 1171 1172 static int 1173 sparc32_struct_return_from_sym (struct symbol *sym) 1174 { 1175 struct type *type = check_typedef (SYMBOL_TYPE (sym)); 1176 enum type_code code = TYPE_CODE (type); 1177 1178 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) 1179 { 1180 type = check_typedef (TYPE_TARGET_TYPE (type)); 1181 if (sparc_structure_or_union_p (type) 1182 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1183 return 1; 1184 } 1185 1186 return 0; 1187 } 1188 1189 struct sparc_frame_cache * 1190 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) 1191 { 1192 struct sparc_frame_cache *cache; 1193 struct symbol *sym; 1194 1195 if (*this_cache) 1196 return (struct sparc_frame_cache *) *this_cache; 1197 1198 cache = sparc_frame_cache (this_frame, this_cache); 1199 1200 sym = find_pc_function (cache->pc); 1201 if (sym) 1202 { 1203 cache->struct_return_p = sparc32_struct_return_from_sym (sym); 1204 } 1205 else 1206 { 1207 /* There is no debugging information for this function to 1208 help us determine whether this function returns a struct 1209 or not. So we rely on another heuristic which is to check 1210 the instruction at the return address and see if this is 1211 an "unimp" instruction. If it is, then it is a struct-return 1212 function. */ 1213 CORE_ADDR pc; 1214 int regnum = 1215 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1216 1217 pc = get_frame_register_unsigned (this_frame, regnum) + 8; 1218 if (sparc_is_unimp_insn (pc)) 1219 cache->struct_return_p = 1; 1220 } 1221 1222 return cache; 1223 } 1224 1225 static void 1226 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, 1227 struct frame_id *this_id) 1228 { 1229 struct sparc_frame_cache *cache = 1230 sparc32_frame_cache (this_frame, this_cache); 1231 1232 /* This marks the outermost frame. */ 1233 if (cache->base == 0) 1234 return; 1235 1236 (*this_id) = frame_id_build (cache->base, cache->pc); 1237 } 1238 1239 static struct value * 1240 sparc32_frame_prev_register (struct frame_info *this_frame, 1241 void **this_cache, int regnum) 1242 { 1243 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1244 struct sparc_frame_cache *cache = 1245 sparc32_frame_cache (this_frame, this_cache); 1246 1247 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 1248 { 1249 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; 1250 1251 /* If this functions has a Structure, Union or Quad-Precision 1252 return value, we have to skip the UNIMP instruction that encodes 1253 the size of the structure. */ 1254 if (cache->struct_return_p) 1255 pc += 4; 1256 1257 regnum = 1258 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1259 pc += get_frame_register_unsigned (this_frame, regnum) + 8; 1260 return frame_unwind_got_constant (this_frame, regnum, pc); 1261 } 1262 1263 /* Handle StackGhost. */ 1264 { 1265 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1266 1267 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) 1268 { 1269 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1270 ULONGEST i7; 1271 1272 /* Read the value in from memory. */ 1273 i7 = get_frame_memory_unsigned (this_frame, addr, 4); 1274 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); 1275 } 1276 } 1277 1278 /* The previous frame's `local' and `in' registers may have been saved 1279 in the register save area. */ 1280 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1281 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) 1282 { 1283 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1284 1285 return frame_unwind_got_memory (this_frame, regnum, addr); 1286 } 1287 1288 /* The previous frame's `out' registers may be accessible as the current 1289 frame's `in' registers. */ 1290 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM 1291 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) 1292 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); 1293 1294 return frame_unwind_got_register (this_frame, regnum, regnum); 1295 } 1296 1297 static const struct frame_unwind sparc32_frame_unwind = 1298 { 1299 NORMAL_FRAME, 1300 default_frame_unwind_stop_reason, 1301 sparc32_frame_this_id, 1302 sparc32_frame_prev_register, 1303 NULL, 1304 default_frame_sniffer 1305 }; 1306 1307 1308 static CORE_ADDR 1309 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) 1310 { 1311 struct sparc_frame_cache *cache = 1312 sparc32_frame_cache (this_frame, this_cache); 1313 1314 return cache->base; 1315 } 1316 1317 static const struct frame_base sparc32_frame_base = 1318 { 1319 &sparc32_frame_unwind, 1320 sparc32_frame_base_address, 1321 sparc32_frame_base_address, 1322 sparc32_frame_base_address 1323 }; 1324 1325 static struct frame_id 1326 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1327 { 1328 CORE_ADDR sp; 1329 1330 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1331 if (sp & 1) 1332 sp += BIAS; 1333 return frame_id_build (sp, get_frame_pc (this_frame)); 1334 } 1335 1336 1337 /* Extract a function return value of TYPE from REGCACHE, and copy 1338 that into VALBUF. */ 1339 1340 static void 1341 sparc32_extract_return_value (struct type *type, struct regcache *regcache, 1342 gdb_byte *valbuf) 1343 { 1344 int len = TYPE_LENGTH (type); 1345 gdb_byte buf[32]; 1346 1347 gdb_assert (!sparc_structure_or_union_p (type)); 1348 gdb_assert (!(sparc_floating_p (type) && len == 16)); 1349 1350 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1351 { 1352 /* Floating return values. */ 1353 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); 1354 if (len > 4) 1355 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); 1356 if (len > 8) 1357 { 1358 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); 1359 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); 1360 } 1361 if (len > 16) 1362 { 1363 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); 1364 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); 1365 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); 1366 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); 1367 } 1368 memcpy (valbuf, buf, len); 1369 } 1370 else 1371 { 1372 /* Integral and pointer return values. */ 1373 gdb_assert (sparc_integral_or_pointer_p (type)); 1374 1375 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); 1376 if (len > 4) 1377 { 1378 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); 1379 gdb_assert (len == 8); 1380 memcpy (valbuf, buf, 8); 1381 } 1382 else 1383 { 1384 /* Just stripping off any unused bytes should preserve the 1385 signed-ness just fine. */ 1386 memcpy (valbuf, buf + 4 - len, len); 1387 } 1388 } 1389 } 1390 1391 /* Store the function return value of type TYPE from VALBUF into 1392 REGCACHE. */ 1393 1394 static void 1395 sparc32_store_return_value (struct type *type, struct regcache *regcache, 1396 const gdb_byte *valbuf) 1397 { 1398 int len = TYPE_LENGTH (type); 1399 gdb_byte buf[8]; 1400 1401 gdb_assert (!sparc_structure_or_union_p (type)); 1402 gdb_assert (!(sparc_floating_p (type) && len == 16)); 1403 gdb_assert (len <= 8); 1404 1405 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1406 { 1407 /* Floating return values. */ 1408 memcpy (buf, valbuf, len); 1409 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); 1410 if (len > 4) 1411 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); 1412 if (len > 8) 1413 { 1414 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); 1415 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); 1416 } 1417 if (len > 16) 1418 { 1419 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); 1420 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); 1421 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); 1422 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); 1423 } 1424 } 1425 else 1426 { 1427 /* Integral and pointer return values. */ 1428 gdb_assert (sparc_integral_or_pointer_p (type)); 1429 1430 if (len > 4) 1431 { 1432 gdb_assert (len == 8); 1433 memcpy (buf, valbuf, 8); 1434 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); 1435 } 1436 else 1437 { 1438 /* ??? Do we need to do any sign-extension here? */ 1439 memcpy (buf + 4 - len, valbuf, len); 1440 } 1441 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); 1442 } 1443 } 1444 1445 static enum return_value_convention 1446 sparc32_return_value (struct gdbarch *gdbarch, struct value *function, 1447 struct type *type, struct regcache *regcache, 1448 gdb_byte *readbuf, const gdb_byte *writebuf) 1449 { 1450 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1451 1452 /* The psABI says that "...every stack frame reserves the word at 1453 %fp+64. If a function returns a structure, union, or 1454 quad-precision value, this word should hold the address of the 1455 object into which the return value should be copied." This 1456 guarantees that we can always find the return value, not just 1457 before the function returns. */ 1458 1459 if (sparc_structure_or_union_p (type) 1460 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1461 { 1462 ULONGEST sp; 1463 CORE_ADDR addr; 1464 1465 if (readbuf) 1466 { 1467 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1468 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1469 read_memory (addr, readbuf, TYPE_LENGTH (type)); 1470 } 1471 if (writebuf) 1472 { 1473 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1474 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1475 write_memory (addr, writebuf, TYPE_LENGTH (type)); 1476 } 1477 1478 return RETURN_VALUE_ABI_PRESERVES_ADDRESS; 1479 } 1480 1481 if (readbuf) 1482 sparc32_extract_return_value (type, regcache, readbuf); 1483 if (writebuf) 1484 sparc32_store_return_value (type, regcache, writebuf); 1485 1486 return RETURN_VALUE_REGISTER_CONVENTION; 1487 } 1488 1489 static int 1490 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) 1491 { 1492 return (sparc_structure_or_union_p (type) 1493 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) 1494 || sparc_complex_floating_p (type)); 1495 } 1496 1497 static int 1498 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) 1499 { 1500 CORE_ADDR pc = get_frame_address_in_block (this_frame); 1501 struct symbol *sym = find_pc_function (pc); 1502 1503 if (sym) 1504 return sparc32_struct_return_from_sym (sym); 1505 return 0; 1506 } 1507 1508 static void 1509 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1510 struct dwarf2_frame_state_reg *reg, 1511 struct frame_info *this_frame) 1512 { 1513 int off; 1514 1515 switch (regnum) 1516 { 1517 case SPARC_G0_REGNUM: 1518 /* Since %g0 is always zero, there is no point in saving it, and 1519 people will be inclined omit it from the CFI. Make sure we 1520 don't warn about that. */ 1521 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1522 break; 1523 case SPARC_SP_REGNUM: 1524 reg->how = DWARF2_FRAME_REG_CFA; 1525 break; 1526 case SPARC32_PC_REGNUM: 1527 case SPARC32_NPC_REGNUM: 1528 reg->how = DWARF2_FRAME_REG_RA_OFFSET; 1529 off = 8; 1530 if (sparc32_dwarf2_struct_return_p (this_frame)) 1531 off += 4; 1532 if (regnum == SPARC32_NPC_REGNUM) 1533 off += 4; 1534 reg->loc.offset = off; 1535 break; 1536 } 1537 } 1538 1539 1540 /* The SPARC Architecture doesn't have hardware single-step support, 1541 and most operating systems don't implement it either, so we provide 1542 software single-step mechanism. */ 1543 1544 static CORE_ADDR 1545 sparc_analyze_control_transfer (struct regcache *regcache, 1546 CORE_ADDR pc, CORE_ADDR *npc) 1547 { 1548 unsigned long insn = sparc_fetch_instruction (pc); 1549 int conditional_p = X_COND (insn) & 0x7; 1550 int branch_p = 0, fused_p = 0; 1551 long offset = 0; /* Must be signed for sign-extend. */ 1552 1553 if (X_OP (insn) == 0 && X_OP2 (insn) == 3) 1554 { 1555 if ((insn & 0x10000000) == 0) 1556 { 1557 /* Branch on Integer Register with Prediction (BPr). */ 1558 branch_p = 1; 1559 conditional_p = 1; 1560 } 1561 else 1562 { 1563 /* Compare and Branch */ 1564 branch_p = 1; 1565 fused_p = 1; 1566 offset = 4 * X_DISP10 (insn); 1567 } 1568 } 1569 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) 1570 { 1571 /* Branch on Floating-Point Condition Codes (FBfcc). */ 1572 branch_p = 1; 1573 offset = 4 * X_DISP22 (insn); 1574 } 1575 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) 1576 { 1577 /* Branch on Floating-Point Condition Codes with Prediction 1578 (FBPfcc). */ 1579 branch_p = 1; 1580 offset = 4 * X_DISP19 (insn); 1581 } 1582 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) 1583 { 1584 /* Branch on Integer Condition Codes (Bicc). */ 1585 branch_p = 1; 1586 offset = 4 * X_DISP22 (insn); 1587 } 1588 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) 1589 { 1590 /* Branch on Integer Condition Codes with Prediction (BPcc). */ 1591 branch_p = 1; 1592 offset = 4 * X_DISP19 (insn); 1593 } 1594 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) 1595 { 1596 struct frame_info *frame = get_current_frame (); 1597 1598 /* Trap instruction (TRAP). */ 1599 return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame, 1600 insn); 1601 } 1602 1603 /* FIXME: Handle DONE and RETRY instructions. */ 1604 1605 if (branch_p) 1606 { 1607 if (fused_p) 1608 { 1609 /* Fused compare-and-branch instructions are non-delayed, 1610 and do not have an annuling capability. So we need to 1611 always set a breakpoint on both the NPC and the branch 1612 target address. */ 1613 gdb_assert (offset != 0); 1614 return pc + offset; 1615 } 1616 else if (conditional_p) 1617 { 1618 /* For conditional branches, return nPC + 4 iff the annul 1619 bit is 1. */ 1620 return (X_A (insn) ? *npc + 4 : 0); 1621 } 1622 else 1623 { 1624 /* For unconditional branches, return the target if its 1625 specified condition is "always" and return nPC + 4 if the 1626 condition is "never". If the annul bit is 1, set *NPC to 1627 zero. */ 1628 if (X_COND (insn) == 0x0) 1629 pc = *npc, offset = 4; 1630 if (X_A (insn)) 1631 *npc = 0; 1632 1633 return pc + offset; 1634 } 1635 } 1636 1637 return 0; 1638 } 1639 1640 static CORE_ADDR 1641 sparc_step_trap (struct frame_info *frame, unsigned long insn) 1642 { 1643 return 0; 1644 } 1645 1646 static VEC (CORE_ADDR) * 1647 sparc_software_single_step (struct regcache *regcache) 1648 { 1649 struct gdbarch *arch = get_regcache_arch (regcache); 1650 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1651 CORE_ADDR npc, nnpc; 1652 1653 CORE_ADDR pc, orig_npc; 1654 VEC (CORE_ADDR) *next_pcs = NULL; 1655 1656 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); 1657 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); 1658 1659 /* Analyze the instruction at PC. */ 1660 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); 1661 if (npc != 0) 1662 VEC_safe_push (CORE_ADDR, next_pcs, npc); 1663 1664 if (nnpc != 0) 1665 VEC_safe_push (CORE_ADDR, next_pcs, nnpc); 1666 1667 /* Assert that we have set at least one breakpoint, and that 1668 they're not set at the same spot - unless we're going 1669 from here straight to NULL, i.e. a call or jump to 0. */ 1670 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); 1671 gdb_assert (nnpc != npc || orig_npc == 0); 1672 1673 return next_pcs; 1674 } 1675 1676 static void 1677 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) 1678 { 1679 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); 1680 1681 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); 1682 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); 1683 } 1684 1685 1686 /* Iterate over core file register note sections. */ 1687 1688 static void 1689 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, 1690 iterate_over_regset_sections_cb *cb, 1691 void *cb_data, 1692 const struct regcache *regcache) 1693 { 1694 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1695 1696 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); 1697 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); 1698 } 1699 1700 1701 static int 1702 validate_tdesc_registers (const struct target_desc *tdesc, 1703 struct tdesc_arch_data *tdesc_data, 1704 const char *feature_name, 1705 const char *register_names[], 1706 unsigned int registers_num, 1707 unsigned int reg_start) 1708 { 1709 int valid_p = 1; 1710 const struct tdesc_feature *feature; 1711 1712 feature = tdesc_find_feature (tdesc, feature_name); 1713 if (feature == NULL) 1714 return 0; 1715 1716 for (unsigned int i = 0; i < registers_num; i++) 1717 valid_p &= tdesc_numbered_register (feature, tdesc_data, 1718 reg_start + i, 1719 register_names[i]); 1720 1721 return valid_p; 1722 } 1723 1724 static struct gdbarch * 1725 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1726 { 1727 struct gdbarch_tdep *tdep; 1728 const struct target_desc *tdesc = info.target_desc; 1729 struct gdbarch *gdbarch; 1730 int valid_p = 1; 1731 1732 /* If there is already a candidate, use it. */ 1733 arches = gdbarch_list_lookup_by_info (arches, &info); 1734 if (arches != NULL) 1735 return arches->gdbarch; 1736 1737 /* Allocate space for the new architecture. */ 1738 tdep = XCNEW (struct gdbarch_tdep); 1739 gdbarch = gdbarch_alloc (&info, tdep); 1740 1741 tdep->pc_regnum = SPARC32_PC_REGNUM; 1742 tdep->npc_regnum = SPARC32_NPC_REGNUM; 1743 tdep->step_trap = sparc_step_trap; 1744 tdep->fpu_register_names = sparc32_fpu_register_names; 1745 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); 1746 tdep->cp0_register_names = sparc32_cp0_register_names; 1747 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); 1748 1749 set_gdbarch_long_double_bit (gdbarch, 128); 1750 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); 1751 1752 set_gdbarch_wchar_bit (gdbarch, 16); 1753 set_gdbarch_wchar_signed (gdbarch, 1); 1754 1755 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); 1756 set_gdbarch_register_name (gdbarch, sparc32_register_name); 1757 set_gdbarch_register_type (gdbarch, sparc32_register_type); 1758 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); 1759 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); 1760 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); 1761 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); 1762 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); 1763 1764 /* Register numbers of various important registers. */ 1765 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ 1766 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ 1767 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ 1768 1769 /* Call dummy code. */ 1770 set_gdbarch_frame_align (gdbarch, sparc32_frame_align); 1771 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 1772 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); 1773 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); 1774 1775 set_gdbarch_return_value (gdbarch, sparc32_return_value); 1776 set_gdbarch_stabs_argument_has_addr 1777 (gdbarch, sparc32_stabs_argument_has_addr); 1778 1779 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); 1780 1781 /* Stack grows downward. */ 1782 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1783 1784 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 1785 sparc_breakpoint::kind_from_pc); 1786 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 1787 sparc_breakpoint::bp_from_kind); 1788 1789 set_gdbarch_frame_args_skip (gdbarch, 8); 1790 1791 set_gdbarch_print_insn (gdbarch, print_insn_sparc); 1792 1793 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); 1794 set_gdbarch_write_pc (gdbarch, sparc_write_pc); 1795 1796 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); 1797 1798 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); 1799 1800 frame_base_set_default (gdbarch, &sparc32_frame_base); 1801 1802 /* Hook in the DWARF CFI frame unwinder. */ 1803 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); 1804 /* FIXME: kettenis/20050423: Don't enable the unwinder until the 1805 StackGhost issues have been resolved. */ 1806 1807 /* Hook in ABI-specific overrides, if they have been registered. */ 1808 gdbarch_init_osabi (info, gdbarch); 1809 1810 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); 1811 1812 if (tdesc_has_registers (tdesc)) 1813 { 1814 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); 1815 1816 /* Validate that the descriptor provides the mandatory registers 1817 and allocate their numbers. */ 1818 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1819 "org.gnu.gdb.sparc.cpu", 1820 sparc_core_register_names, 1821 ARRAY_SIZE (sparc_core_register_names), 1822 SPARC_G0_REGNUM); 1823 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1824 "org.gnu.gdb.sparc.fpu", 1825 tdep->fpu_register_names, 1826 tdep->fpu_registers_num, 1827 SPARC_F0_REGNUM); 1828 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1829 "org.gnu.gdb.sparc.cp0", 1830 tdep->cp0_register_names, 1831 tdep->cp0_registers_num, 1832 SPARC_F0_REGNUM 1833 + tdep->fpu_registers_num); 1834 if (!valid_p) 1835 { 1836 tdesc_data_cleanup (tdesc_data); 1837 return NULL; 1838 } 1839 1840 /* Target description may have changed. */ 1841 info.tdep_info = tdesc_data; 1842 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 1843 } 1844 1845 /* If we have register sets, enable the generic core file support. */ 1846 if (tdep->gregset) 1847 set_gdbarch_iterate_over_regset_sections 1848 (gdbarch, sparc_iterate_over_regset_sections); 1849 1850 register_sparc_ravenscar_ops (gdbarch); 1851 1852 return gdbarch; 1853 } 1854 1855 /* Helper functions for dealing with register windows. */ 1856 1857 void 1858 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) 1859 { 1860 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1861 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1862 int offset = 0; 1863 gdb_byte buf[8]; 1864 int i; 1865 1866 if (sp & 1) 1867 { 1868 /* Registers are 64-bit. */ 1869 sp += BIAS; 1870 1871 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1872 { 1873 if (regnum == i || regnum == -1) 1874 { 1875 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1876 1877 /* Handle StackGhost. */ 1878 if (i == SPARC_I7_REGNUM) 1879 { 1880 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1881 ULONGEST i7; 1882 1883 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1884 store_unsigned_integer (buf + offset, 8, byte_order, 1885 i7 ^ wcookie); 1886 } 1887 1888 regcache_raw_supply (regcache, i, buf); 1889 } 1890 } 1891 } 1892 else 1893 { 1894 /* Registers are 32-bit. Toss any sign-extension of the stack 1895 pointer. */ 1896 sp &= 0xffffffffUL; 1897 1898 /* Clear out the top half of the temporary buffer, and put the 1899 register value in the bottom half if we're in 64-bit mode. */ 1900 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1901 { 1902 memset (buf, 0, 4); 1903 offset = 4; 1904 } 1905 1906 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1907 { 1908 if (regnum == i || regnum == -1) 1909 { 1910 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1911 buf + offset, 4); 1912 1913 /* Handle StackGhost. */ 1914 if (i == SPARC_I7_REGNUM) 1915 { 1916 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1917 ULONGEST i7; 1918 1919 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 1920 store_unsigned_integer (buf + offset, 4, byte_order, 1921 i7 ^ wcookie); 1922 } 1923 1924 regcache_raw_supply (regcache, i, buf); 1925 } 1926 } 1927 } 1928 } 1929 1930 void 1931 sparc_collect_rwindow (const struct regcache *regcache, 1932 CORE_ADDR sp, int regnum) 1933 { 1934 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1935 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1936 int offset = 0; 1937 gdb_byte buf[8]; 1938 int i; 1939 1940 if (sp & 1) 1941 { 1942 /* Registers are 64-bit. */ 1943 sp += BIAS; 1944 1945 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1946 { 1947 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 1948 { 1949 regcache_raw_collect (regcache, i, buf); 1950 1951 /* Handle StackGhost. */ 1952 if (i == SPARC_I7_REGNUM) 1953 { 1954 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1955 ULONGEST i7; 1956 1957 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1958 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); 1959 } 1960 1961 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1962 } 1963 } 1964 } 1965 else 1966 { 1967 /* Registers are 32-bit. Toss any sign-extension of the stack 1968 pointer. */ 1969 sp &= 0xffffffffUL; 1970 1971 /* Only use the bottom half if we're in 64-bit mode. */ 1972 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1973 offset = 4; 1974 1975 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1976 { 1977 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 1978 { 1979 regcache_raw_collect (regcache, i, buf); 1980 1981 /* Handle StackGhost. */ 1982 if (i == SPARC_I7_REGNUM) 1983 { 1984 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1985 ULONGEST i7; 1986 1987 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 1988 store_unsigned_integer (buf + offset, 4, byte_order, 1989 i7 ^ wcookie); 1990 } 1991 1992 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1993 buf + offset, 4); 1994 } 1995 } 1996 } 1997 } 1998 1999 /* Helper functions for dealing with register sets. */ 2000 2001 void 2002 sparc32_supply_gregset (const struct sparc_gregmap *gregmap, 2003 struct regcache *regcache, 2004 int regnum, const void *gregs) 2005 { 2006 const gdb_byte *regs = (const gdb_byte *) gregs; 2007 gdb_byte zero[4] = { 0 }; 2008 int i; 2009 2010 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2011 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, 2012 regs + gregmap->r_psr_offset); 2013 2014 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2015 regcache_raw_supply (regcache, SPARC32_PC_REGNUM, 2016 regs + gregmap->r_pc_offset); 2017 2018 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2019 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, 2020 regs + gregmap->r_npc_offset); 2021 2022 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2023 regcache_raw_supply (regcache, SPARC32_Y_REGNUM, 2024 regs + gregmap->r_y_offset); 2025 2026 if (regnum == SPARC_G0_REGNUM || regnum == -1) 2027 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); 2028 2029 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2030 { 2031 int offset = gregmap->r_g1_offset; 2032 2033 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2034 { 2035 if (regnum == i || regnum == -1) 2036 regcache_raw_supply (regcache, i, regs + offset); 2037 offset += 4; 2038 } 2039 } 2040 2041 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2042 { 2043 /* Not all of the register set variants include Locals and 2044 Inputs. For those that don't, we read them off the stack. */ 2045 if (gregmap->r_l0_offset == -1) 2046 { 2047 ULONGEST sp; 2048 2049 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 2050 sparc_supply_rwindow (regcache, sp, regnum); 2051 } 2052 else 2053 { 2054 int offset = gregmap->r_l0_offset; 2055 2056 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2057 { 2058 if (regnum == i || regnum == -1) 2059 regcache_raw_supply (regcache, i, regs + offset); 2060 offset += 4; 2061 } 2062 } 2063 } 2064 } 2065 2066 void 2067 sparc32_collect_gregset (const struct sparc_gregmap *gregmap, 2068 const struct regcache *regcache, 2069 int regnum, void *gregs) 2070 { 2071 gdb_byte *regs = (gdb_byte *) gregs; 2072 int i; 2073 2074 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2075 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, 2076 regs + gregmap->r_psr_offset); 2077 2078 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2079 regcache_raw_collect (regcache, SPARC32_PC_REGNUM, 2080 regs + gregmap->r_pc_offset); 2081 2082 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2083 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, 2084 regs + gregmap->r_npc_offset); 2085 2086 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2087 regcache_raw_collect (regcache, SPARC32_Y_REGNUM, 2088 regs + gregmap->r_y_offset); 2089 2090 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2091 { 2092 int offset = gregmap->r_g1_offset; 2093 2094 /* %g0 is always zero. */ 2095 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2096 { 2097 if (regnum == i || regnum == -1) 2098 regcache_raw_collect (regcache, i, regs + offset); 2099 offset += 4; 2100 } 2101 } 2102 2103 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2104 { 2105 /* Not all of the register set variants include Locals and 2106 Inputs. For those that don't, we read them off the stack. */ 2107 if (gregmap->r_l0_offset != -1) 2108 { 2109 int offset = gregmap->r_l0_offset; 2110 2111 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2112 { 2113 if (regnum == i || regnum == -1) 2114 regcache_raw_collect (regcache, i, regs + offset); 2115 offset += 4; 2116 } 2117 } 2118 } 2119 } 2120 2121 void 2122 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, 2123 struct regcache *regcache, 2124 int regnum, const void *fpregs) 2125 { 2126 const gdb_byte *regs = (const gdb_byte *) fpregs; 2127 int i; 2128 2129 for (i = 0; i < 32; i++) 2130 { 2131 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2132 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, 2133 regs + fpregmap->r_f0_offset + (i * 4)); 2134 } 2135 2136 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2137 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, 2138 regs + fpregmap->r_fsr_offset); 2139 } 2140 2141 void 2142 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, 2143 const struct regcache *regcache, 2144 int regnum, void *fpregs) 2145 { 2146 gdb_byte *regs = (gdb_byte *) fpregs; 2147 int i; 2148 2149 for (i = 0; i < 32; i++) 2150 { 2151 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2152 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, 2153 regs + fpregmap->r_f0_offset + (i * 4)); 2154 } 2155 2156 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2157 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, 2158 regs + fpregmap->r_fsr_offset); 2159 } 2160 2161 2162 /* SunOS 4. */ 2163 2164 /* From <machine/reg.h>. */ 2165 const struct sparc_gregmap sparc32_sunos4_gregmap = 2166 { 2167 0 * 4, /* %psr */ 2168 1 * 4, /* %pc */ 2169 2 * 4, /* %npc */ 2170 3 * 4, /* %y */ 2171 -1, /* %wim */ 2172 -1, /* %tbr */ 2173 4 * 4, /* %g1 */ 2174 -1 /* %l0 */ 2175 }; 2176 2177 const struct sparc_fpregmap sparc32_sunos4_fpregmap = 2178 { 2179 0 * 4, /* %f0 */ 2180 33 * 4, /* %fsr */ 2181 }; 2182 2183 const struct sparc_fpregmap sparc32_bsd_fpregmap = 2184 { 2185 0 * 4, /* %f0 */ 2186 32 * 4, /* %fsr */ 2187 }; 2188 2189 2190 /* Provide a prototype to silence -Wmissing-prototypes. */ 2191 void _initialize_sparc_tdep (void); 2192 2193 void 2194 _initialize_sparc_tdep (void) 2195 { 2196 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); 2197 } 2198