1 /* Target-dependent code for SPARC. 2 3 Copyright (C) 2003-2016 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "arch-utils.h" 22 #include "dis-asm.h" 23 #include "dwarf2-frame.h" 24 #include "floatformat.h" 25 #include "frame.h" 26 #include "frame-base.h" 27 #include "frame-unwind.h" 28 #include "gdbcore.h" 29 #include "gdbtypes.h" 30 #include "inferior.h" 31 #include "symtab.h" 32 #include "objfiles.h" 33 #include "osabi.h" 34 #include "regcache.h" 35 #include "target.h" 36 #include "value.h" 37 38 #include "sparc-tdep.h" 39 #include "sparc-ravenscar-thread.h" 40 41 struct regset; 42 43 /* This file implements the SPARC 32-bit ABI as defined by the section 44 "Low-Level System Information" of the SPARC Compliance Definition 45 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD 46 lists changes with respect to the original 32-bit psABI as defined 47 in the "System V ABI, SPARC Processor Supplement". 48 49 Note that if we talk about SunOS, we mean SunOS 4.x, which was 50 BSD-based, which is sometimes (retroactively?) referred to as 51 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and 52 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 53 suffering from severe version number inflation). Solaris 2.x is 54 also known as SunOS 5.x, since that's what uname(1) says. Solaris 55 2.x is SVR4-based. */ 56 57 /* Please use the sparc32_-prefix for 32-bit specific code, the 58 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for 59 code that can handle both. The 64-bit specific code lives in 60 sparc64-tdep.c; don't add any here. */ 61 62 /* The SPARC Floating-Point Quad-Precision format is similar to 63 big-endian IA-64 Quad-Precision format. */ 64 #define floatformats_sparc_quad floatformats_ia64_quad 65 66 /* The stack pointer is offset from the stack frame by a BIAS of 2047 67 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC 68 hosts, so undefine it first. */ 69 #undef BIAS 70 #define BIAS 2047 71 72 /* Macros to extract fields from SPARC instructions. */ 73 #define X_OP(i) (((i) >> 30) & 0x3) 74 #define X_RD(i) (((i) >> 25) & 0x1f) 75 #define X_A(i) (((i) >> 29) & 1) 76 #define X_COND(i) (((i) >> 25) & 0xf) 77 #define X_OP2(i) (((i) >> 22) & 0x7) 78 #define X_IMM22(i) ((i) & 0x3fffff) 79 #define X_OP3(i) (((i) >> 19) & 0x3f) 80 #define X_RS1(i) (((i) >> 14) & 0x1f) 81 #define X_RS2(i) ((i) & 0x1f) 82 #define X_I(i) (((i) >> 13) & 1) 83 /* Sign extension macros. */ 84 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 85 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 86 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) 87 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) 88 /* Macros to identify some instructions. */ 89 /* RETURN (RETT in V8) */ 90 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) 91 92 /* Fetch the instruction at PC. Instructions are always big-endian 93 even if the processor operates in little-endian mode. */ 94 95 unsigned long 96 sparc_fetch_instruction (CORE_ADDR pc) 97 { 98 gdb_byte buf[4]; 99 unsigned long insn; 100 int i; 101 102 /* If we can't read the instruction at PC, return zero. */ 103 if (target_read_memory (pc, buf, sizeof (buf))) 104 return 0; 105 106 insn = 0; 107 for (i = 0; i < sizeof (buf); i++) 108 insn = (insn << 8) | buf[i]; 109 return insn; 110 } 111 112 113 /* Return non-zero if the instruction corresponding to PC is an "unimp" 114 instruction. */ 115 116 static int 117 sparc_is_unimp_insn (CORE_ADDR pc) 118 { 119 const unsigned long insn = sparc_fetch_instruction (pc); 120 121 return ((insn & 0xc1c00000) == 0); 122 } 123 124 /* Return non-zero if the instruction corresponding to PC is an 125 "annulled" branch, i.e. the annul bit is set. */ 126 127 int 128 sparc_is_annulled_branch_insn (CORE_ADDR pc) 129 { 130 /* The branch instructions featuring an annul bit can be identified 131 by the following bit patterns: 132 133 OP=0 134 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). 135 OP2=2: Branch on Integer Condition Codes (Bcc). 136 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). 137 OP2=6: Branch on FP Condition Codes (FBcc). 138 OP2=3 && Bit28=0: 139 Branch on Integer Register with Prediction (BPr). 140 141 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 142 coprocessor branch instructions (Op2=7). */ 143 144 const unsigned long insn = sparc_fetch_instruction (pc); 145 const unsigned op2 = X_OP2 (insn); 146 147 if ((X_OP (insn) == 0) 148 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) 149 || ((op2 == 3) && ((insn & 0x10000000) == 0)))) 150 return X_A (insn); 151 else 152 return 0; 153 } 154 155 /* OpenBSD/sparc includes StackGhost, which according to the author's 156 website http://stackghost.cerias.purdue.edu "... transparently and 157 automatically protects applications' stack frames; more 158 specifically, it guards the return pointers. The protection 159 mechanisms require no application source or binary modification and 160 imposes only a negligible performance penalty." 161 162 The same website provides the following description of how 163 StackGhost works: 164 165 "StackGhost interfaces with the kernel trap handler that would 166 normally write out registers to the stack and the handler that 167 would read them back in. By XORing a cookie into the 168 return-address saved in the user stack when it is actually written 169 to the stack, and then XOR it out when the return-address is pulled 170 from the stack, StackGhost can cause attacker corrupted return 171 pointers to behave in a manner the attacker cannot predict. 172 StackGhost can also use several unused bits in the return pointer 173 to detect a smashed return pointer and abort the process." 174 175 For GDB this means that whenever we're reading %i7 from a stack 176 frame's window save area, we'll have to XOR the cookie. 177 178 More information on StackGuard can be found on in: 179 180 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated 181 Stack Protection." 2001. Published in USENIX Security Symposium 182 '01. */ 183 184 /* Fetch StackGhost Per-Process XOR cookie. */ 185 186 ULONGEST 187 sparc_fetch_wcookie (struct gdbarch *gdbarch) 188 { 189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 190 struct target_ops *ops = ¤t_target; 191 gdb_byte buf[8]; 192 int len; 193 194 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); 195 if (len == -1) 196 return 0; 197 198 /* We should have either an 32-bit or an 64-bit cookie. */ 199 gdb_assert (len == 4 || len == 8); 200 201 return extract_unsigned_integer (buf, len, byte_order); 202 } 203 204 205 /* The functions on this page are intended to be used to classify 206 function arguments. */ 207 208 /* Check whether TYPE is "Integral or Pointer". */ 209 210 static int 211 sparc_integral_or_pointer_p (const struct type *type) 212 { 213 int len = TYPE_LENGTH (type); 214 215 switch (TYPE_CODE (type)) 216 { 217 case TYPE_CODE_INT: 218 case TYPE_CODE_BOOL: 219 case TYPE_CODE_CHAR: 220 case TYPE_CODE_ENUM: 221 case TYPE_CODE_RANGE: 222 /* We have byte, half-word, word and extended-word/doubleword 223 integral types. The doubleword is an extension to the 224 original 32-bit ABI by the SCD 2.4.x. */ 225 return (len == 1 || len == 2 || len == 4 || len == 8); 226 case TYPE_CODE_PTR: 227 case TYPE_CODE_REF: 228 /* Allow either 32-bit or 64-bit pointers. */ 229 return (len == 4 || len == 8); 230 default: 231 break; 232 } 233 234 return 0; 235 } 236 237 /* Check whether TYPE is "Floating". */ 238 239 static int 240 sparc_floating_p (const struct type *type) 241 { 242 switch (TYPE_CODE (type)) 243 { 244 case TYPE_CODE_FLT: 245 { 246 int len = TYPE_LENGTH (type); 247 return (len == 4 || len == 8 || len == 16); 248 } 249 default: 250 break; 251 } 252 253 return 0; 254 } 255 256 /* Check whether TYPE is "Complex Floating". */ 257 258 static int 259 sparc_complex_floating_p (const struct type *type) 260 { 261 switch (TYPE_CODE (type)) 262 { 263 case TYPE_CODE_COMPLEX: 264 { 265 int len = TYPE_LENGTH (type); 266 return (len == 8 || len == 16 || len == 32); 267 } 268 default: 269 break; 270 } 271 272 return 0; 273 } 274 275 /* Check whether TYPE is "Structure or Union". 276 277 In terms of Ada subprogram calls, arrays are treated the same as 278 struct and union types. So this function also returns non-zero 279 for array types. */ 280 281 static int 282 sparc_structure_or_union_p (const struct type *type) 283 { 284 switch (TYPE_CODE (type)) 285 { 286 case TYPE_CODE_STRUCT: 287 case TYPE_CODE_UNION: 288 case TYPE_CODE_ARRAY: 289 return 1; 290 default: 291 break; 292 } 293 294 return 0; 295 } 296 297 /* Register information. */ 298 299 static const char *sparc32_register_names[] = 300 { 301 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 302 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", 303 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 304 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", 305 306 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 307 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 308 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 309 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 310 311 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" 312 }; 313 314 /* Total number of registers. */ 315 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) 316 317 /* We provide the aliases %d0..%d30 for the floating registers as 318 "psuedo" registers. */ 319 320 static const char *sparc32_pseudo_register_names[] = 321 { 322 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", 323 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" 324 }; 325 326 /* Total number of pseudo registers. */ 327 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) 328 329 /* Return the name of register REGNUM. */ 330 331 static const char * 332 sparc32_register_name (struct gdbarch *gdbarch, int regnum) 333 { 334 if (regnum >= 0 && regnum < SPARC32_NUM_REGS) 335 return sparc32_register_names[regnum]; 336 337 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) 338 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; 339 340 return NULL; 341 } 342 343 /* Construct types for ISA-specific registers. */ 344 345 static struct type * 346 sparc_psr_type (struct gdbarch *gdbarch) 347 { 348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 349 350 if (!tdep->sparc_psr_type) 351 { 352 struct type *type; 353 354 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); 355 append_flags_type_flag (type, 5, "ET"); 356 append_flags_type_flag (type, 6, "PS"); 357 append_flags_type_flag (type, 7, "S"); 358 append_flags_type_flag (type, 12, "EF"); 359 append_flags_type_flag (type, 13, "EC"); 360 361 tdep->sparc_psr_type = type; 362 } 363 364 return tdep->sparc_psr_type; 365 } 366 367 static struct type * 368 sparc_fsr_type (struct gdbarch *gdbarch) 369 { 370 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 371 372 if (!tdep->sparc_fsr_type) 373 { 374 struct type *type; 375 376 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); 377 append_flags_type_flag (type, 0, "NXA"); 378 append_flags_type_flag (type, 1, "DZA"); 379 append_flags_type_flag (type, 2, "UFA"); 380 append_flags_type_flag (type, 3, "OFA"); 381 append_flags_type_flag (type, 4, "NVA"); 382 append_flags_type_flag (type, 5, "NXC"); 383 append_flags_type_flag (type, 6, "DZC"); 384 append_flags_type_flag (type, 7, "UFC"); 385 append_flags_type_flag (type, 8, "OFC"); 386 append_flags_type_flag (type, 9, "NVC"); 387 append_flags_type_flag (type, 22, "NS"); 388 append_flags_type_flag (type, 23, "NXM"); 389 append_flags_type_flag (type, 24, "DZM"); 390 append_flags_type_flag (type, 25, "UFM"); 391 append_flags_type_flag (type, 26, "OFM"); 392 append_flags_type_flag (type, 27, "NVM"); 393 394 tdep->sparc_fsr_type = type; 395 } 396 397 return tdep->sparc_fsr_type; 398 } 399 400 /* Return the GDB type object for the "standard" data type of data in 401 register REGNUM. */ 402 403 static struct type * 404 sparc32_register_type (struct gdbarch *gdbarch, int regnum) 405 { 406 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) 407 return builtin_type (gdbarch)->builtin_float; 408 409 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) 410 return builtin_type (gdbarch)->builtin_double; 411 412 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) 413 return builtin_type (gdbarch)->builtin_data_ptr; 414 415 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 416 return builtin_type (gdbarch)->builtin_func_ptr; 417 418 if (regnum == SPARC32_PSR_REGNUM) 419 return sparc_psr_type (gdbarch); 420 421 if (regnum == SPARC32_FSR_REGNUM) 422 return sparc_fsr_type (gdbarch); 423 424 return builtin_type (gdbarch)->builtin_int32; 425 } 426 427 static enum register_status 428 sparc32_pseudo_register_read (struct gdbarch *gdbarch, 429 struct regcache *regcache, 430 int regnum, gdb_byte *buf) 431 { 432 enum register_status status; 433 434 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 435 436 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 437 status = regcache_raw_read (regcache, regnum, buf); 438 if (status == REG_VALID) 439 status = regcache_raw_read (regcache, regnum + 1, buf + 4); 440 return status; 441 } 442 443 static void 444 sparc32_pseudo_register_write (struct gdbarch *gdbarch, 445 struct regcache *regcache, 446 int regnum, const gdb_byte *buf) 447 { 448 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 449 450 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 451 regcache_raw_write (regcache, regnum, buf); 452 regcache_raw_write (regcache, regnum + 1, buf + 4); 453 } 454 455 /* Implement the stack_frame_destroyed_p gdbarch method. */ 456 457 int 458 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 459 { 460 /* This function must return true if we are one instruction after an 461 instruction that destroyed the stack frame of the current 462 function. The SPARC instructions used to restore the callers 463 stack frame are RESTORE and RETURN/RETT. 464 465 Of these RETURN/RETT is a branch instruction and thus we return 466 true if we are in its delay slot. 467 468 RESTORE is almost always found in the delay slot of a branch 469 instruction that transfers control to the caller, such as JMPL. 470 Thus the next instruction is in the caller frame and we don't 471 need to do anything about it. */ 472 473 unsigned int insn = sparc_fetch_instruction (pc - 4); 474 475 return X_RETTURN (insn); 476 } 477 478 479 static CORE_ADDR 480 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 481 { 482 /* The ABI requires double-word alignment. */ 483 return address & ~0x7; 484 } 485 486 static CORE_ADDR 487 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 488 CORE_ADDR funcaddr, 489 struct value **args, int nargs, 490 struct type *value_type, 491 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 492 struct regcache *regcache) 493 { 494 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 495 496 *bp_addr = sp - 4; 497 *real_pc = funcaddr; 498 499 if (using_struct_return (gdbarch, NULL, value_type)) 500 { 501 gdb_byte buf[4]; 502 503 /* This is an UNIMP instruction. */ 504 store_unsigned_integer (buf, 4, byte_order, 505 TYPE_LENGTH (value_type) & 0x1fff); 506 write_memory (sp - 8, buf, 4); 507 return sp - 8; 508 } 509 510 return sp - 4; 511 } 512 513 static CORE_ADDR 514 sparc32_store_arguments (struct regcache *regcache, int nargs, 515 struct value **args, CORE_ADDR sp, 516 int struct_return, CORE_ADDR struct_addr) 517 { 518 struct gdbarch *gdbarch = get_regcache_arch (regcache); 519 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 520 /* Number of words in the "parameter array". */ 521 int num_elements = 0; 522 int element = 0; 523 int i; 524 525 for (i = 0; i < nargs; i++) 526 { 527 struct type *type = value_type (args[i]); 528 int len = TYPE_LENGTH (type); 529 530 if (sparc_structure_or_union_p (type) 531 || (sparc_floating_p (type) && len == 16) 532 || sparc_complex_floating_p (type)) 533 { 534 /* Structure, Union and Quad-Precision Arguments. */ 535 sp -= len; 536 537 /* Use doubleword alignment for these values. That's always 538 correct, and wasting a few bytes shouldn't be a problem. */ 539 sp &= ~0x7; 540 541 write_memory (sp, value_contents (args[i]), len); 542 args[i] = value_from_pointer (lookup_pointer_type (type), sp); 543 num_elements++; 544 } 545 else if (sparc_floating_p (type)) 546 { 547 /* Floating arguments. */ 548 gdb_assert (len == 4 || len == 8); 549 num_elements += (len / 4); 550 } 551 else 552 { 553 /* Integral and pointer arguments. */ 554 gdb_assert (sparc_integral_or_pointer_p (type)); 555 556 if (len < 4) 557 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, 558 args[i]); 559 num_elements += ((len + 3) / 4); 560 } 561 } 562 563 /* Always allocate at least six words. */ 564 sp -= max (6, num_elements) * 4; 565 566 /* The psABI says that "Software convention requires space for the 567 struct/union return value pointer, even if the word is unused." */ 568 sp -= 4; 569 570 /* The psABI says that "Although software convention and the 571 operating system require every stack frame to be doubleword 572 aligned." */ 573 sp &= ~0x7; 574 575 for (i = 0; i < nargs; i++) 576 { 577 const bfd_byte *valbuf = value_contents (args[i]); 578 struct type *type = value_type (args[i]); 579 int len = TYPE_LENGTH (type); 580 581 gdb_assert (len == 4 || len == 8); 582 583 if (element < 6) 584 { 585 int regnum = SPARC_O0_REGNUM + element; 586 587 regcache_cooked_write (regcache, regnum, valbuf); 588 if (len > 4 && element < 5) 589 regcache_cooked_write (regcache, regnum + 1, valbuf + 4); 590 } 591 592 /* Always store the argument in memory. */ 593 write_memory (sp + 4 + element * 4, valbuf, len); 594 element += len / 4; 595 } 596 597 gdb_assert (element == num_elements); 598 599 if (struct_return) 600 { 601 gdb_byte buf[4]; 602 603 store_unsigned_integer (buf, 4, byte_order, struct_addr); 604 write_memory (sp, buf, 4); 605 } 606 607 return sp; 608 } 609 610 static CORE_ADDR 611 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 612 struct regcache *regcache, CORE_ADDR bp_addr, 613 int nargs, struct value **args, CORE_ADDR sp, 614 int struct_return, CORE_ADDR struct_addr) 615 { 616 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); 617 618 /* Set return address. */ 619 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); 620 621 /* Set up function arguments. */ 622 sp = sparc32_store_arguments (regcache, nargs, args, sp, 623 struct_return, struct_addr); 624 625 /* Allocate the 16-word window save area. */ 626 sp -= 16 * 4; 627 628 /* Stack should be doubleword aligned at this point. */ 629 gdb_assert (sp % 8 == 0); 630 631 /* Finally, update the stack pointer. */ 632 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); 633 634 return sp; 635 } 636 637 638 /* Use the program counter to determine the contents and size of a 639 breakpoint instruction. Return a pointer to a string of bytes that 640 encode a breakpoint instruction, store the length of the string in 641 *LEN and optionally adjust *PC to point to the correct memory 642 location for inserting the breakpoint. */ 643 644 static const gdb_byte * 645 sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 646 { 647 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; 648 649 *len = sizeof (break_insn); 650 return break_insn; 651 } 652 653 654 /* Allocate and initialize a frame cache. */ 655 656 static struct sparc_frame_cache * 657 sparc_alloc_frame_cache (void) 658 { 659 struct sparc_frame_cache *cache; 660 661 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); 662 663 /* Base address. */ 664 cache->base = 0; 665 cache->pc = 0; 666 667 /* Frameless until proven otherwise. */ 668 cache->frameless_p = 1; 669 cache->frame_offset = 0; 670 cache->saved_regs_mask = 0; 671 cache->copied_regs_mask = 0; 672 cache->struct_return_p = 0; 673 674 return cache; 675 } 676 677 /* GCC generates several well-known sequences of instructions at the begining 678 of each function prologue when compiling with -fstack-check. If one of 679 such sequences starts at START_PC, then return the address of the 680 instruction immediately past this sequence. Otherwise, return START_PC. */ 681 682 static CORE_ADDR 683 sparc_skip_stack_check (const CORE_ADDR start_pc) 684 { 685 CORE_ADDR pc = start_pc; 686 unsigned long insn; 687 int probing_loop = 0; 688 689 /* With GCC, all stack checking sequences begin with the same two 690 instructions, plus an optional one in the case of a probing loop: 691 692 sethi <some immediate>, %g1 693 sub %sp, %g1, %g1 694 695 or: 696 697 sethi <some immediate>, %g1 698 sethi <some immediate>, %g4 699 sub %sp, %g1, %g1 700 701 or: 702 703 sethi <some immediate>, %g1 704 sub %sp, %g1, %g1 705 sethi <some immediate>, %g4 706 707 If the optional instruction is found (setting g4), assume that a 708 probing loop will follow. */ 709 710 /* sethi <some immediate>, %g1 */ 711 insn = sparc_fetch_instruction (pc); 712 pc = pc + 4; 713 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) 714 return start_pc; 715 716 /* optional: sethi <some immediate>, %g4 */ 717 insn = sparc_fetch_instruction (pc); 718 pc = pc + 4; 719 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 720 { 721 probing_loop = 1; 722 insn = sparc_fetch_instruction (pc); 723 pc = pc + 4; 724 } 725 726 /* sub %sp, %g1, %g1 */ 727 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 728 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) 729 return start_pc; 730 731 insn = sparc_fetch_instruction (pc); 732 pc = pc + 4; 733 734 /* optional: sethi <some immediate>, %g4 */ 735 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 736 { 737 probing_loop = 1; 738 insn = sparc_fetch_instruction (pc); 739 pc = pc + 4; 740 } 741 742 /* First possible sequence: 743 [first two instructions above] 744 clr [%g1 - some immediate] */ 745 746 /* clr [%g1 - some immediate] */ 747 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 748 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 749 { 750 /* Valid stack-check sequence, return the new PC. */ 751 return pc; 752 } 753 754 /* Second possible sequence: A small number of probes. 755 [first two instructions above] 756 clr [%g1] 757 add %g1, -<some immediate>, %g1 758 clr [%g1] 759 [repeat the two instructions above any (small) number of times] 760 clr [%g1 - some immediate] */ 761 762 /* clr [%g1] */ 763 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 764 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 765 { 766 while (1) 767 { 768 /* add %g1, -<some immediate>, %g1 */ 769 insn = sparc_fetch_instruction (pc); 770 pc = pc + 4; 771 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 772 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 773 break; 774 775 /* clr [%g1] */ 776 insn = sparc_fetch_instruction (pc); 777 pc = pc + 4; 778 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 779 && X_RD (insn) == 0 && X_RS1 (insn) == 1)) 780 return start_pc; 781 } 782 783 /* clr [%g1 - some immediate] */ 784 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 785 && X_RS1 (insn) == 1 && X_RD (insn) == 0)) 786 return start_pc; 787 788 /* We found a valid stack-check sequence, return the new PC. */ 789 return pc; 790 } 791 792 /* Third sequence: A probing loop. 793 [first three instructions above] 794 sub %g1, %g4, %g4 795 cmp %g1, %g4 796 be <disp> 797 add %g1, -<some immediate>, %g1 798 ba <disp> 799 clr [%g1] 800 801 And an optional last probe for the remainder: 802 803 clr [%g4 - some immediate] */ 804 805 if (probing_loop) 806 { 807 /* sub %g1, %g4, %g4 */ 808 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 809 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 810 return start_pc; 811 812 /* cmp %g1, %g4 */ 813 insn = sparc_fetch_instruction (pc); 814 pc = pc + 4; 815 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) 816 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 817 return start_pc; 818 819 /* be <disp> */ 820 insn = sparc_fetch_instruction (pc); 821 pc = pc + 4; 822 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) 823 return start_pc; 824 825 /* add %g1, -<some immediate>, %g1 */ 826 insn = sparc_fetch_instruction (pc); 827 pc = pc + 4; 828 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 829 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 830 return start_pc; 831 832 /* ba <disp> */ 833 insn = sparc_fetch_instruction (pc); 834 pc = pc + 4; 835 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) 836 return start_pc; 837 838 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ 839 insn = sparc_fetch_instruction (pc); 840 pc = pc + 4; 841 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 842 && X_RD (insn) == 0 && X_RS1 (insn) == 1 843 && (!X_I(insn) || X_SIMM13 (insn) == 0))) 844 return start_pc; 845 846 /* We found a valid stack-check sequence, return the new PC. */ 847 848 /* optional: clr [%g4 - some immediate] */ 849 insn = sparc_fetch_instruction (pc); 850 pc = pc + 4; 851 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 852 && X_RS1 (insn) == 4 && X_RD (insn) == 0)) 853 return pc - 4; 854 else 855 return pc; 856 } 857 858 /* No stack check code in our prologue, return the start_pc. */ 859 return start_pc; 860 } 861 862 /* Record the effect of a SAVE instruction on CACHE. */ 863 864 void 865 sparc_record_save_insn (struct sparc_frame_cache *cache) 866 { 867 /* The frame is set up. */ 868 cache->frameless_p = 0; 869 870 /* The frame pointer contains the CFA. */ 871 cache->frame_offset = 0; 872 873 /* The `local' and `in' registers are all saved. */ 874 cache->saved_regs_mask = 0xffff; 875 876 /* The `out' registers are all renamed. */ 877 cache->copied_regs_mask = 0xff; 878 } 879 880 /* Do a full analysis of the prologue at PC and update CACHE accordingly. 881 Bail out early if CURRENT_PC is reached. Return the address where 882 the analysis stopped. 883 884 We handle both the traditional register window model and the single 885 register window (aka flat) model. */ 886 887 CORE_ADDR 888 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, 889 CORE_ADDR current_pc, struct sparc_frame_cache *cache) 890 { 891 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 892 unsigned long insn; 893 int offset = 0; 894 int dest = -1; 895 896 pc = sparc_skip_stack_check (pc); 897 898 if (current_pc <= pc) 899 return current_pc; 900 901 /* We have to handle to "Procedure Linkage Table" (PLT) special. On 902 SPARC the linker usually defines a symbol (typically 903 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. 904 This symbol makes us end up here with PC pointing at the start of 905 the PLT and CURRENT_PC probably pointing at a PLT entry. If we 906 would do our normal prologue analysis, we would probably conclude 907 that we've got a frame when in reality we don't, since the 908 dynamic linker patches up the first PLT with some code that 909 starts with a SAVE instruction. Patch up PC such that it points 910 at the start of our PLT entry. */ 911 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) 912 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); 913 914 insn = sparc_fetch_instruction (pc); 915 916 /* Recognize store insns and record their sources. */ 917 while (X_OP (insn) == 3 918 && (X_OP3 (insn) == 0x4 /* stw */ 919 || X_OP3 (insn) == 0x7 /* std */ 920 || X_OP3 (insn) == 0xe) /* stx */ 921 && X_RS1 (insn) == SPARC_SP_REGNUM) 922 { 923 int regnum = X_RD (insn); 924 925 /* Recognize stores into the corresponding stack slots. */ 926 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 927 && ((X_I (insn) 928 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe 929 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS 930 : (regnum - SPARC_L0_REGNUM) * 4)) 931 || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) 932 { 933 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); 934 if (X_OP3 (insn) == 0x7) 935 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); 936 } 937 938 offset += 4; 939 940 insn = sparc_fetch_instruction (pc + offset); 941 } 942 943 /* Recognize a SETHI insn and record its destination. */ 944 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) 945 { 946 dest = X_RD (insn); 947 offset += 4; 948 949 insn = sparc_fetch_instruction (pc + offset); 950 } 951 952 /* Allow for an arithmetic operation on DEST or %g1. */ 953 if (X_OP (insn) == 2 && X_I (insn) 954 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 955 { 956 offset += 4; 957 958 insn = sparc_fetch_instruction (pc + offset); 959 } 960 961 /* Check for the SAVE instruction that sets up the frame. */ 962 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) 963 { 964 sparc_record_save_insn (cache); 965 offset += 4; 966 return pc + offset; 967 } 968 969 /* Check for an arithmetic operation on %sp. */ 970 if (X_OP (insn) == 2 971 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 972 && X_RS1 (insn) == SPARC_SP_REGNUM 973 && X_RD (insn) == SPARC_SP_REGNUM) 974 { 975 if (X_I (insn)) 976 { 977 cache->frame_offset = X_SIMM13 (insn); 978 if (X_OP3 (insn) == 0) 979 cache->frame_offset = -cache->frame_offset; 980 } 981 offset += 4; 982 983 insn = sparc_fetch_instruction (pc + offset); 984 985 /* Check for an arithmetic operation that sets up the frame. */ 986 if (X_OP (insn) == 2 987 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 988 && X_RS1 (insn) == SPARC_SP_REGNUM 989 && X_RD (insn) == SPARC_FP_REGNUM) 990 { 991 cache->frameless_p = 0; 992 cache->frame_offset = 0; 993 /* We could check that the amount subtracted to %sp above is the 994 same as the one added here, but this seems superfluous. */ 995 cache->copied_regs_mask |= 0x40; 996 offset += 4; 997 998 insn = sparc_fetch_instruction (pc + offset); 999 } 1000 1001 /* Check for a move (or) operation that copies the return register. */ 1002 if (X_OP (insn) == 2 1003 && X_OP3 (insn) == 0x2 1004 && !X_I (insn) 1005 && X_RS1 (insn) == SPARC_G0_REGNUM 1006 && X_RS2 (insn) == SPARC_O7_REGNUM 1007 && X_RD (insn) == SPARC_I7_REGNUM) 1008 { 1009 cache->copied_regs_mask |= 0x80; 1010 offset += 4; 1011 } 1012 1013 return pc + offset; 1014 } 1015 1016 return pc; 1017 } 1018 1019 static CORE_ADDR 1020 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) 1021 { 1022 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1023 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); 1024 } 1025 1026 /* Return PC of first real instruction of the function starting at 1027 START_PC. */ 1028 1029 static CORE_ADDR 1030 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1031 { 1032 struct symtab_and_line sal; 1033 CORE_ADDR func_start, func_end; 1034 struct sparc_frame_cache cache; 1035 1036 /* This is the preferred method, find the end of the prologue by 1037 using the debugging information. */ 1038 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) 1039 { 1040 sal = find_pc_line (func_start, 0); 1041 1042 if (sal.end < func_end 1043 && start_pc <= sal.end) 1044 return sal.end; 1045 } 1046 1047 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); 1048 1049 /* The psABI says that "Although the first 6 words of arguments 1050 reside in registers, the standard stack frame reserves space for 1051 them.". It also suggests that a function may use that space to 1052 "write incoming arguments 0 to 5" into that space, and that's 1053 indeed what GCC seems to be doing. In that case GCC will 1054 generate debug information that points to the stack slots instead 1055 of the registers, so we should consider the instructions that 1056 write out these incoming arguments onto the stack. */ 1057 1058 while (1) 1059 { 1060 unsigned long insn = sparc_fetch_instruction (start_pc); 1061 1062 /* Recognize instructions that store incoming arguments into the 1063 corresponding stack slots. */ 1064 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 1065 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) 1066 { 1067 int regnum = X_RD (insn); 1068 1069 /* Case of arguments still in %o[0..5]. */ 1070 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM 1071 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) 1072 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) 1073 { 1074 start_pc += 4; 1075 continue; 1076 } 1077 1078 /* Case of arguments copied into %i[0..5]. */ 1079 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM 1080 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) 1081 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) 1082 { 1083 start_pc += 4; 1084 continue; 1085 } 1086 } 1087 1088 break; 1089 } 1090 1091 return start_pc; 1092 } 1093 1094 /* Normal frames. */ 1095 1096 struct sparc_frame_cache * 1097 sparc_frame_cache (struct frame_info *this_frame, void **this_cache) 1098 { 1099 struct sparc_frame_cache *cache; 1100 1101 if (*this_cache) 1102 return (struct sparc_frame_cache *) *this_cache; 1103 1104 cache = sparc_alloc_frame_cache (); 1105 *this_cache = cache; 1106 1107 cache->pc = get_frame_func (this_frame); 1108 if (cache->pc != 0) 1109 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, 1110 get_frame_pc (this_frame), cache); 1111 1112 if (cache->frameless_p) 1113 { 1114 /* This function is frameless, so %fp (%i6) holds the frame 1115 pointer for our calling frame. Use %sp (%o6) as this frame's 1116 base address. */ 1117 cache->base = 1118 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1119 } 1120 else 1121 { 1122 /* For normal frames, %fp (%i6) holds the frame pointer, the 1123 base address for the current stack frame. */ 1124 cache->base = 1125 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); 1126 } 1127 1128 cache->base += cache->frame_offset; 1129 1130 if (cache->base & 1) 1131 cache->base += BIAS; 1132 1133 return cache; 1134 } 1135 1136 static int 1137 sparc32_struct_return_from_sym (struct symbol *sym) 1138 { 1139 struct type *type = check_typedef (SYMBOL_TYPE (sym)); 1140 enum type_code code = TYPE_CODE (type); 1141 1142 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) 1143 { 1144 type = check_typedef (TYPE_TARGET_TYPE (type)); 1145 if (sparc_structure_or_union_p (type) 1146 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1147 return 1; 1148 } 1149 1150 return 0; 1151 } 1152 1153 struct sparc_frame_cache * 1154 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) 1155 { 1156 struct sparc_frame_cache *cache; 1157 struct symbol *sym; 1158 1159 if (*this_cache) 1160 return (struct sparc_frame_cache *) *this_cache; 1161 1162 cache = sparc_frame_cache (this_frame, this_cache); 1163 1164 sym = find_pc_function (cache->pc); 1165 if (sym) 1166 { 1167 cache->struct_return_p = sparc32_struct_return_from_sym (sym); 1168 } 1169 else 1170 { 1171 /* There is no debugging information for this function to 1172 help us determine whether this function returns a struct 1173 or not. So we rely on another heuristic which is to check 1174 the instruction at the return address and see if this is 1175 an "unimp" instruction. If it is, then it is a struct-return 1176 function. */ 1177 CORE_ADDR pc; 1178 int regnum = 1179 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1180 1181 pc = get_frame_register_unsigned (this_frame, regnum) + 8; 1182 if (sparc_is_unimp_insn (pc)) 1183 cache->struct_return_p = 1; 1184 } 1185 1186 return cache; 1187 } 1188 1189 static void 1190 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, 1191 struct frame_id *this_id) 1192 { 1193 struct sparc_frame_cache *cache = 1194 sparc32_frame_cache (this_frame, this_cache); 1195 1196 /* This marks the outermost frame. */ 1197 if (cache->base == 0) 1198 return; 1199 1200 (*this_id) = frame_id_build (cache->base, cache->pc); 1201 } 1202 1203 static struct value * 1204 sparc32_frame_prev_register (struct frame_info *this_frame, 1205 void **this_cache, int regnum) 1206 { 1207 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1208 struct sparc_frame_cache *cache = 1209 sparc32_frame_cache (this_frame, this_cache); 1210 1211 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 1212 { 1213 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; 1214 1215 /* If this functions has a Structure, Union or Quad-Precision 1216 return value, we have to skip the UNIMP instruction that encodes 1217 the size of the structure. */ 1218 if (cache->struct_return_p) 1219 pc += 4; 1220 1221 regnum = 1222 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1223 pc += get_frame_register_unsigned (this_frame, regnum) + 8; 1224 return frame_unwind_got_constant (this_frame, regnum, pc); 1225 } 1226 1227 /* Handle StackGhost. */ 1228 { 1229 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1230 1231 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) 1232 { 1233 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1234 ULONGEST i7; 1235 1236 /* Read the value in from memory. */ 1237 i7 = get_frame_memory_unsigned (this_frame, addr, 4); 1238 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); 1239 } 1240 } 1241 1242 /* The previous frame's `local' and `in' registers may have been saved 1243 in the register save area. */ 1244 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1245 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) 1246 { 1247 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1248 1249 return frame_unwind_got_memory (this_frame, regnum, addr); 1250 } 1251 1252 /* The previous frame's `out' registers may be accessible as the current 1253 frame's `in' registers. */ 1254 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM 1255 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) 1256 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); 1257 1258 return frame_unwind_got_register (this_frame, regnum, regnum); 1259 } 1260 1261 static const struct frame_unwind sparc32_frame_unwind = 1262 { 1263 NORMAL_FRAME, 1264 default_frame_unwind_stop_reason, 1265 sparc32_frame_this_id, 1266 sparc32_frame_prev_register, 1267 NULL, 1268 default_frame_sniffer 1269 }; 1270 1271 1272 static CORE_ADDR 1273 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) 1274 { 1275 struct sparc_frame_cache *cache = 1276 sparc32_frame_cache (this_frame, this_cache); 1277 1278 return cache->base; 1279 } 1280 1281 static const struct frame_base sparc32_frame_base = 1282 { 1283 &sparc32_frame_unwind, 1284 sparc32_frame_base_address, 1285 sparc32_frame_base_address, 1286 sparc32_frame_base_address 1287 }; 1288 1289 static struct frame_id 1290 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1291 { 1292 CORE_ADDR sp; 1293 1294 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1295 if (sp & 1) 1296 sp += BIAS; 1297 return frame_id_build (sp, get_frame_pc (this_frame)); 1298 } 1299 1300 1301 /* Extract a function return value of TYPE from REGCACHE, and copy 1302 that into VALBUF. */ 1303 1304 static void 1305 sparc32_extract_return_value (struct type *type, struct regcache *regcache, 1306 gdb_byte *valbuf) 1307 { 1308 int len = TYPE_LENGTH (type); 1309 gdb_byte buf[32]; 1310 1311 gdb_assert (!sparc_structure_or_union_p (type)); 1312 gdb_assert (!(sparc_floating_p (type) && len == 16)); 1313 1314 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1315 { 1316 /* Floating return values. */ 1317 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); 1318 if (len > 4) 1319 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); 1320 if (len > 8) 1321 { 1322 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); 1323 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); 1324 } 1325 if (len > 16) 1326 { 1327 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); 1328 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); 1329 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); 1330 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); 1331 } 1332 memcpy (valbuf, buf, len); 1333 } 1334 else 1335 { 1336 /* Integral and pointer return values. */ 1337 gdb_assert (sparc_integral_or_pointer_p (type)); 1338 1339 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); 1340 if (len > 4) 1341 { 1342 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); 1343 gdb_assert (len == 8); 1344 memcpy (valbuf, buf, 8); 1345 } 1346 else 1347 { 1348 /* Just stripping off any unused bytes should preserve the 1349 signed-ness just fine. */ 1350 memcpy (valbuf, buf + 4 - len, len); 1351 } 1352 } 1353 } 1354 1355 /* Store the function return value of type TYPE from VALBUF into 1356 REGCACHE. */ 1357 1358 static void 1359 sparc32_store_return_value (struct type *type, struct regcache *regcache, 1360 const gdb_byte *valbuf) 1361 { 1362 int len = TYPE_LENGTH (type); 1363 gdb_byte buf[8]; 1364 1365 gdb_assert (!sparc_structure_or_union_p (type)); 1366 gdb_assert (!(sparc_floating_p (type) && len == 16)); 1367 gdb_assert (len <= 8); 1368 1369 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1370 { 1371 /* Floating return values. */ 1372 memcpy (buf, valbuf, len); 1373 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); 1374 if (len > 4) 1375 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); 1376 if (len > 8) 1377 { 1378 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); 1379 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); 1380 } 1381 if (len > 16) 1382 { 1383 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); 1384 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); 1385 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); 1386 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); 1387 } 1388 } 1389 else 1390 { 1391 /* Integral and pointer return values. */ 1392 gdb_assert (sparc_integral_or_pointer_p (type)); 1393 1394 if (len > 4) 1395 { 1396 gdb_assert (len == 8); 1397 memcpy (buf, valbuf, 8); 1398 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); 1399 } 1400 else 1401 { 1402 /* ??? Do we need to do any sign-extension here? */ 1403 memcpy (buf + 4 - len, valbuf, len); 1404 } 1405 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); 1406 } 1407 } 1408 1409 static enum return_value_convention 1410 sparc32_return_value (struct gdbarch *gdbarch, struct value *function, 1411 struct type *type, struct regcache *regcache, 1412 gdb_byte *readbuf, const gdb_byte *writebuf) 1413 { 1414 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1415 1416 /* The psABI says that "...every stack frame reserves the word at 1417 %fp+64. If a function returns a structure, union, or 1418 quad-precision value, this word should hold the address of the 1419 object into which the return value should be copied." This 1420 guarantees that we can always find the return value, not just 1421 before the function returns. */ 1422 1423 if (sparc_structure_or_union_p (type) 1424 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1425 { 1426 ULONGEST sp; 1427 CORE_ADDR addr; 1428 1429 if (readbuf) 1430 { 1431 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1432 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1433 read_memory (addr, readbuf, TYPE_LENGTH (type)); 1434 } 1435 if (writebuf) 1436 { 1437 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1438 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1439 write_memory (addr, writebuf, TYPE_LENGTH (type)); 1440 } 1441 1442 return RETURN_VALUE_ABI_PRESERVES_ADDRESS; 1443 } 1444 1445 if (readbuf) 1446 sparc32_extract_return_value (type, regcache, readbuf); 1447 if (writebuf) 1448 sparc32_store_return_value (type, regcache, writebuf); 1449 1450 return RETURN_VALUE_REGISTER_CONVENTION; 1451 } 1452 1453 static int 1454 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) 1455 { 1456 return (sparc_structure_or_union_p (type) 1457 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) 1458 || sparc_complex_floating_p (type)); 1459 } 1460 1461 static int 1462 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) 1463 { 1464 CORE_ADDR pc = get_frame_address_in_block (this_frame); 1465 struct symbol *sym = find_pc_function (pc); 1466 1467 if (sym) 1468 return sparc32_struct_return_from_sym (sym); 1469 return 0; 1470 } 1471 1472 static void 1473 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1474 struct dwarf2_frame_state_reg *reg, 1475 struct frame_info *this_frame) 1476 { 1477 int off; 1478 1479 switch (regnum) 1480 { 1481 case SPARC_G0_REGNUM: 1482 /* Since %g0 is always zero, there is no point in saving it, and 1483 people will be inclined omit it from the CFI. Make sure we 1484 don't warn about that. */ 1485 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1486 break; 1487 case SPARC_SP_REGNUM: 1488 reg->how = DWARF2_FRAME_REG_CFA; 1489 break; 1490 case SPARC32_PC_REGNUM: 1491 case SPARC32_NPC_REGNUM: 1492 reg->how = DWARF2_FRAME_REG_RA_OFFSET; 1493 off = 8; 1494 if (sparc32_dwarf2_struct_return_p (this_frame)) 1495 off += 4; 1496 if (regnum == SPARC32_NPC_REGNUM) 1497 off += 4; 1498 reg->loc.offset = off; 1499 break; 1500 } 1501 } 1502 1503 1504 /* The SPARC Architecture doesn't have hardware single-step support, 1505 and most operating systems don't implement it either, so we provide 1506 software single-step mechanism. */ 1507 1508 static CORE_ADDR 1509 sparc_analyze_control_transfer (struct frame_info *frame, 1510 CORE_ADDR pc, CORE_ADDR *npc) 1511 { 1512 unsigned long insn = sparc_fetch_instruction (pc); 1513 int conditional_p = X_COND (insn) & 0x7; 1514 int branch_p = 0, fused_p = 0; 1515 long offset = 0; /* Must be signed for sign-extend. */ 1516 1517 if (X_OP (insn) == 0 && X_OP2 (insn) == 3) 1518 { 1519 if ((insn & 0x10000000) == 0) 1520 { 1521 /* Branch on Integer Register with Prediction (BPr). */ 1522 branch_p = 1; 1523 conditional_p = 1; 1524 } 1525 else 1526 { 1527 /* Compare and Branch */ 1528 branch_p = 1; 1529 fused_p = 1; 1530 offset = 4 * X_DISP10 (insn); 1531 } 1532 } 1533 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) 1534 { 1535 /* Branch on Floating-Point Condition Codes (FBfcc). */ 1536 branch_p = 1; 1537 offset = 4 * X_DISP22 (insn); 1538 } 1539 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) 1540 { 1541 /* Branch on Floating-Point Condition Codes with Prediction 1542 (FBPfcc). */ 1543 branch_p = 1; 1544 offset = 4 * X_DISP19 (insn); 1545 } 1546 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) 1547 { 1548 /* Branch on Integer Condition Codes (Bicc). */ 1549 branch_p = 1; 1550 offset = 4 * X_DISP22 (insn); 1551 } 1552 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) 1553 { 1554 /* Branch on Integer Condition Codes with Prediction (BPcc). */ 1555 branch_p = 1; 1556 offset = 4 * X_DISP19 (insn); 1557 } 1558 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) 1559 { 1560 /* Trap instruction (TRAP). */ 1561 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); 1562 } 1563 1564 /* FIXME: Handle DONE and RETRY instructions. */ 1565 1566 if (branch_p) 1567 { 1568 if (fused_p) 1569 { 1570 /* Fused compare-and-branch instructions are non-delayed, 1571 and do not have an annuling capability. So we need to 1572 always set a breakpoint on both the NPC and the branch 1573 target address. */ 1574 gdb_assert (offset != 0); 1575 return pc + offset; 1576 } 1577 else if (conditional_p) 1578 { 1579 /* For conditional branches, return nPC + 4 iff the annul 1580 bit is 1. */ 1581 return (X_A (insn) ? *npc + 4 : 0); 1582 } 1583 else 1584 { 1585 /* For unconditional branches, return the target if its 1586 specified condition is "always" and return nPC + 4 if the 1587 condition is "never". If the annul bit is 1, set *NPC to 1588 zero. */ 1589 if (X_COND (insn) == 0x0) 1590 pc = *npc, offset = 4; 1591 if (X_A (insn)) 1592 *npc = 0; 1593 1594 return pc + offset; 1595 } 1596 } 1597 1598 return 0; 1599 } 1600 1601 static CORE_ADDR 1602 sparc_step_trap (struct frame_info *frame, unsigned long insn) 1603 { 1604 return 0; 1605 } 1606 1607 static int 1608 sparc_software_single_step (struct frame_info *frame) 1609 { 1610 struct gdbarch *arch = get_frame_arch (frame); 1611 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1612 struct address_space *aspace = get_frame_address_space (frame); 1613 CORE_ADDR npc, nnpc; 1614 1615 CORE_ADDR pc, orig_npc; 1616 1617 pc = get_frame_register_unsigned (frame, tdep->pc_regnum); 1618 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); 1619 1620 /* Analyze the instruction at PC. */ 1621 nnpc = sparc_analyze_control_transfer (frame, pc, &npc); 1622 if (npc != 0) 1623 insert_single_step_breakpoint (arch, aspace, npc); 1624 1625 if (nnpc != 0) 1626 insert_single_step_breakpoint (arch, aspace, nnpc); 1627 1628 /* Assert that we have set at least one breakpoint, and that 1629 they're not set at the same spot - unless we're going 1630 from here straight to NULL, i.e. a call or jump to 0. */ 1631 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); 1632 gdb_assert (nnpc != npc || orig_npc == 0); 1633 1634 return 1; 1635 } 1636 1637 static void 1638 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) 1639 { 1640 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); 1641 1642 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); 1643 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); 1644 } 1645 1646 1647 /* Iterate over core file register note sections. */ 1648 1649 static void 1650 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, 1651 iterate_over_regset_sections_cb *cb, 1652 void *cb_data, 1653 const struct regcache *regcache) 1654 { 1655 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1656 1657 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); 1658 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); 1659 } 1660 1661 1662 static struct gdbarch * 1663 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1664 { 1665 struct gdbarch_tdep *tdep; 1666 struct gdbarch *gdbarch; 1667 1668 /* If there is already a candidate, use it. */ 1669 arches = gdbarch_list_lookup_by_info (arches, &info); 1670 if (arches != NULL) 1671 return arches->gdbarch; 1672 1673 /* Allocate space for the new architecture. */ 1674 tdep = XCNEW (struct gdbarch_tdep); 1675 gdbarch = gdbarch_alloc (&info, tdep); 1676 1677 tdep->pc_regnum = SPARC32_PC_REGNUM; 1678 tdep->npc_regnum = SPARC32_NPC_REGNUM; 1679 tdep->step_trap = sparc_step_trap; 1680 1681 set_gdbarch_long_double_bit (gdbarch, 128); 1682 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); 1683 1684 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); 1685 set_gdbarch_register_name (gdbarch, sparc32_register_name); 1686 set_gdbarch_register_type (gdbarch, sparc32_register_type); 1687 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); 1688 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); 1689 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); 1690 1691 /* Register numbers of various important registers. */ 1692 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ 1693 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ 1694 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ 1695 1696 /* Call dummy code. */ 1697 set_gdbarch_frame_align (gdbarch, sparc32_frame_align); 1698 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 1699 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); 1700 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); 1701 1702 set_gdbarch_return_value (gdbarch, sparc32_return_value); 1703 set_gdbarch_stabs_argument_has_addr 1704 (gdbarch, sparc32_stabs_argument_has_addr); 1705 1706 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); 1707 1708 /* Stack grows downward. */ 1709 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1710 1711 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); 1712 1713 set_gdbarch_frame_args_skip (gdbarch, 8); 1714 1715 set_gdbarch_print_insn (gdbarch, print_insn_sparc); 1716 1717 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); 1718 set_gdbarch_write_pc (gdbarch, sparc_write_pc); 1719 1720 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); 1721 1722 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); 1723 1724 frame_base_set_default (gdbarch, &sparc32_frame_base); 1725 1726 /* Hook in the DWARF CFI frame unwinder. */ 1727 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); 1728 /* FIXME: kettenis/20050423: Don't enable the unwinder until the 1729 StackGhost issues have been resolved. */ 1730 1731 /* Hook in ABI-specific overrides, if they have been registered. */ 1732 gdbarch_init_osabi (info, gdbarch); 1733 1734 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); 1735 1736 /* If we have register sets, enable the generic core file support. */ 1737 if (tdep->gregset) 1738 set_gdbarch_iterate_over_regset_sections 1739 (gdbarch, sparc_iterate_over_regset_sections); 1740 1741 register_sparc_ravenscar_ops (gdbarch); 1742 1743 return gdbarch; 1744 } 1745 1746 /* Helper functions for dealing with register windows. */ 1747 1748 void 1749 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) 1750 { 1751 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1752 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1753 int offset = 0; 1754 gdb_byte buf[8]; 1755 int i; 1756 1757 if (sp & 1) 1758 { 1759 /* Registers are 64-bit. */ 1760 sp += BIAS; 1761 1762 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1763 { 1764 if (regnum == i || regnum == -1) 1765 { 1766 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1767 1768 /* Handle StackGhost. */ 1769 if (i == SPARC_I7_REGNUM) 1770 { 1771 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1772 ULONGEST i7; 1773 1774 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1775 store_unsigned_integer (buf + offset, 8, byte_order, 1776 i7 ^ wcookie); 1777 } 1778 1779 regcache_raw_supply (regcache, i, buf); 1780 } 1781 } 1782 } 1783 else 1784 { 1785 /* Registers are 32-bit. Toss any sign-extension of the stack 1786 pointer. */ 1787 sp &= 0xffffffffUL; 1788 1789 /* Clear out the top half of the temporary buffer, and put the 1790 register value in the bottom half if we're in 64-bit mode. */ 1791 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1792 { 1793 memset (buf, 0, 4); 1794 offset = 4; 1795 } 1796 1797 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1798 { 1799 if (regnum == i || regnum == -1) 1800 { 1801 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1802 buf + offset, 4); 1803 1804 /* Handle StackGhost. */ 1805 if (i == SPARC_I7_REGNUM) 1806 { 1807 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1808 ULONGEST i7; 1809 1810 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 1811 store_unsigned_integer (buf + offset, 4, byte_order, 1812 i7 ^ wcookie); 1813 } 1814 1815 regcache_raw_supply (regcache, i, buf); 1816 } 1817 } 1818 } 1819 } 1820 1821 void 1822 sparc_collect_rwindow (const struct regcache *regcache, 1823 CORE_ADDR sp, int regnum) 1824 { 1825 struct gdbarch *gdbarch = get_regcache_arch (regcache); 1826 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1827 int offset = 0; 1828 gdb_byte buf[8]; 1829 int i; 1830 1831 if (sp & 1) 1832 { 1833 /* Registers are 64-bit. */ 1834 sp += BIAS; 1835 1836 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1837 { 1838 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 1839 { 1840 regcache_raw_collect (regcache, i, buf); 1841 1842 /* Handle StackGhost. */ 1843 if (i == SPARC_I7_REGNUM) 1844 { 1845 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1846 ULONGEST i7; 1847 1848 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1849 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); 1850 } 1851 1852 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1853 } 1854 } 1855 } 1856 else 1857 { 1858 /* Registers are 32-bit. Toss any sign-extension of the stack 1859 pointer. */ 1860 sp &= 0xffffffffUL; 1861 1862 /* Only use the bottom half if we're in 64-bit mode. */ 1863 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1864 offset = 4; 1865 1866 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1867 { 1868 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 1869 { 1870 regcache_raw_collect (regcache, i, buf); 1871 1872 /* Handle StackGhost. */ 1873 if (i == SPARC_I7_REGNUM) 1874 { 1875 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1876 ULONGEST i7; 1877 1878 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 1879 store_unsigned_integer (buf + offset, 4, byte_order, 1880 i7 ^ wcookie); 1881 } 1882 1883 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1884 buf + offset, 4); 1885 } 1886 } 1887 } 1888 } 1889 1890 /* Helper functions for dealing with register sets. */ 1891 1892 void 1893 sparc32_supply_gregset (const struct sparc_gregmap *gregmap, 1894 struct regcache *regcache, 1895 int regnum, const void *gregs) 1896 { 1897 const gdb_byte *regs = (const gdb_byte *) gregs; 1898 gdb_byte zero[4] = { 0 }; 1899 int i; 1900 1901 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 1902 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, 1903 regs + gregmap->r_psr_offset); 1904 1905 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 1906 regcache_raw_supply (regcache, SPARC32_PC_REGNUM, 1907 regs + gregmap->r_pc_offset); 1908 1909 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 1910 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, 1911 regs + gregmap->r_npc_offset); 1912 1913 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 1914 regcache_raw_supply (regcache, SPARC32_Y_REGNUM, 1915 regs + gregmap->r_y_offset); 1916 1917 if (regnum == SPARC_G0_REGNUM || regnum == -1) 1918 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); 1919 1920 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 1921 { 1922 int offset = gregmap->r_g1_offset; 1923 1924 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 1925 { 1926 if (regnum == i || regnum == -1) 1927 regcache_raw_supply (regcache, i, regs + offset); 1928 offset += 4; 1929 } 1930 } 1931 1932 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 1933 { 1934 /* Not all of the register set variants include Locals and 1935 Inputs. For those that don't, we read them off the stack. */ 1936 if (gregmap->r_l0_offset == -1) 1937 { 1938 ULONGEST sp; 1939 1940 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1941 sparc_supply_rwindow (regcache, sp, regnum); 1942 } 1943 else 1944 { 1945 int offset = gregmap->r_l0_offset; 1946 1947 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1948 { 1949 if (regnum == i || regnum == -1) 1950 regcache_raw_supply (regcache, i, regs + offset); 1951 offset += 4; 1952 } 1953 } 1954 } 1955 } 1956 1957 void 1958 sparc32_collect_gregset (const struct sparc_gregmap *gregmap, 1959 const struct regcache *regcache, 1960 int regnum, void *gregs) 1961 { 1962 gdb_byte *regs = (gdb_byte *) gregs; 1963 int i; 1964 1965 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 1966 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, 1967 regs + gregmap->r_psr_offset); 1968 1969 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 1970 regcache_raw_collect (regcache, SPARC32_PC_REGNUM, 1971 regs + gregmap->r_pc_offset); 1972 1973 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 1974 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, 1975 regs + gregmap->r_npc_offset); 1976 1977 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 1978 regcache_raw_collect (regcache, SPARC32_Y_REGNUM, 1979 regs + gregmap->r_y_offset); 1980 1981 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 1982 { 1983 int offset = gregmap->r_g1_offset; 1984 1985 /* %g0 is always zero. */ 1986 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 1987 { 1988 if (regnum == i || regnum == -1) 1989 regcache_raw_collect (regcache, i, regs + offset); 1990 offset += 4; 1991 } 1992 } 1993 1994 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 1995 { 1996 /* Not all of the register set variants include Locals and 1997 Inputs. For those that don't, we read them off the stack. */ 1998 if (gregmap->r_l0_offset != -1) 1999 { 2000 int offset = gregmap->r_l0_offset; 2001 2002 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2003 { 2004 if (regnum == i || regnum == -1) 2005 regcache_raw_collect (regcache, i, regs + offset); 2006 offset += 4; 2007 } 2008 } 2009 } 2010 } 2011 2012 void 2013 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, 2014 struct regcache *regcache, 2015 int regnum, const void *fpregs) 2016 { 2017 const gdb_byte *regs = (const gdb_byte *) fpregs; 2018 int i; 2019 2020 for (i = 0; i < 32; i++) 2021 { 2022 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2023 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, 2024 regs + fpregmap->r_f0_offset + (i * 4)); 2025 } 2026 2027 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2028 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, 2029 regs + fpregmap->r_fsr_offset); 2030 } 2031 2032 void 2033 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, 2034 const struct regcache *regcache, 2035 int regnum, void *fpregs) 2036 { 2037 gdb_byte *regs = (gdb_byte *) fpregs; 2038 int i; 2039 2040 for (i = 0; i < 32; i++) 2041 { 2042 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2043 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, 2044 regs + fpregmap->r_f0_offset + (i * 4)); 2045 } 2046 2047 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2048 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, 2049 regs + fpregmap->r_fsr_offset); 2050 } 2051 2052 2053 /* SunOS 4. */ 2054 2055 /* From <machine/reg.h>. */ 2056 const struct sparc_gregmap sparc32_sunos4_gregmap = 2057 { 2058 0 * 4, /* %psr */ 2059 1 * 4, /* %pc */ 2060 2 * 4, /* %npc */ 2061 3 * 4, /* %y */ 2062 -1, /* %wim */ 2063 -1, /* %tbr */ 2064 4 * 4, /* %g1 */ 2065 -1 /* %l0 */ 2066 }; 2067 2068 const struct sparc_fpregmap sparc32_sunos4_fpregmap = 2069 { 2070 0 * 4, /* %f0 */ 2071 33 * 4, /* %fsr */ 2072 }; 2073 2074 const struct sparc_fpregmap sparc32_bsd_fpregmap = 2075 { 2076 0 * 4, /* %f0 */ 2077 32 * 4, /* %fsr */ 2078 }; 2079 2080 2081 /* Provide a prototype to silence -Wmissing-prototypes. */ 2082 void _initialize_sparc_tdep (void); 2083 2084 void 2085 _initialize_sparc_tdep (void) 2086 { 2087 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); 2088 } 2089