1 /* Target-dependent code for SPARC. 2 3 Copyright (C) 2003-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "arch-utils.h" 22 #include "dis-asm.h" 23 #include "dwarf2.h" 24 #include "dwarf2-frame.h" 25 #include "frame.h" 26 #include "frame-base.h" 27 #include "frame-unwind.h" 28 #include "gdbcore.h" 29 #include "gdbtypes.h" 30 #include "inferior.h" 31 #include "symtab.h" 32 #include "objfiles.h" 33 #include "osabi.h" 34 #include "regcache.h" 35 #include "target.h" 36 #include "target-descriptions.h" 37 #include "value.h" 38 39 #include "sparc-tdep.h" 40 #include "sparc-ravenscar-thread.h" 41 #include <algorithm> 42 43 struct regset; 44 45 /* This file implements the SPARC 32-bit ABI as defined by the section 46 "Low-Level System Information" of the SPARC Compliance Definition 47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD 48 lists changes with respect to the original 32-bit psABI as defined 49 in the "System V ABI, SPARC Processor Supplement". 50 51 Note that if we talk about SunOS, we mean SunOS 4.x, which was 52 BSD-based, which is sometimes (retroactively?) referred to as 53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and 54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 55 suffering from severe version number inflation). Solaris 2.x is 56 also known as SunOS 5.x, since that's what uname(1) says. Solaris 57 2.x is SVR4-based. */ 58 59 /* Please use the sparc32_-prefix for 32-bit specific code, the 60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for 61 code that can handle both. The 64-bit specific code lives in 62 sparc64-tdep.c; don't add any here. */ 63 64 /* The SPARC Floating-Point Quad-Precision format is similar to 65 big-endian IA-64 Quad-Precision format. */ 66 #define floatformats_sparc_quad floatformats_ia64_quad 67 68 /* The stack pointer is offset from the stack frame by a BIAS of 2047 69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC 70 hosts, so undefine it first. */ 71 #undef BIAS 72 #define BIAS 2047 73 74 /* Macros to extract fields from SPARC instructions. */ 75 #define X_OP(i) (((i) >> 30) & 0x3) 76 #define X_RD(i) (((i) >> 25) & 0x1f) 77 #define X_A(i) (((i) >> 29) & 1) 78 #define X_COND(i) (((i) >> 25) & 0xf) 79 #define X_OP2(i) (((i) >> 22) & 0x7) 80 #define X_IMM22(i) ((i) & 0x3fffff) 81 #define X_OP3(i) (((i) >> 19) & 0x3f) 82 #define X_RS1(i) (((i) >> 14) & 0x1f) 83 #define X_RS2(i) ((i) & 0x1f) 84 #define X_I(i) (((i) >> 13) & 1) 85 /* Sign extension macros. */ 86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) 89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) 90 /* Macros to identify some instructions. */ 91 /* RETURN (RETT in V8) */ 92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) 93 94 /* Fetch the instruction at PC. Instructions are always big-endian 95 even if the processor operates in little-endian mode. */ 96 97 unsigned long 98 sparc_fetch_instruction (CORE_ADDR pc) 99 { 100 gdb_byte buf[4]; 101 unsigned long insn; 102 int i; 103 104 /* If we can't read the instruction at PC, return zero. */ 105 if (target_read_memory (pc, buf, sizeof (buf))) 106 return 0; 107 108 insn = 0; 109 for (i = 0; i < sizeof (buf); i++) 110 insn = (insn << 8) | buf[i]; 111 return insn; 112 } 113 114 115 /* Return non-zero if the instruction corresponding to PC is an "unimp" 116 instruction. */ 117 118 static int 119 sparc_is_unimp_insn (CORE_ADDR pc) 120 { 121 const unsigned long insn = sparc_fetch_instruction (pc); 122 123 return ((insn & 0xc1c00000) == 0); 124 } 125 126 /* Return non-zero if the instruction corresponding to PC is an 127 "annulled" branch, i.e. the annul bit is set. */ 128 129 int 130 sparc_is_annulled_branch_insn (CORE_ADDR pc) 131 { 132 /* The branch instructions featuring an annul bit can be identified 133 by the following bit patterns: 134 135 OP=0 136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). 137 OP2=2: Branch on Integer Condition Codes (Bcc). 138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). 139 OP2=6: Branch on FP Condition Codes (FBcc). 140 OP2=3 && Bit28=0: 141 Branch on Integer Register with Prediction (BPr). 142 143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 144 coprocessor branch instructions (Op2=7). */ 145 146 const unsigned long insn = sparc_fetch_instruction (pc); 147 const unsigned op2 = X_OP2 (insn); 148 149 if ((X_OP (insn) == 0) 150 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) 151 || ((op2 == 3) && ((insn & 0x10000000) == 0)))) 152 return X_A (insn); 153 else 154 return 0; 155 } 156 157 /* OpenBSD/sparc includes StackGhost, which according to the author's 158 website http://stackghost.cerias.purdue.edu "... transparently and 159 automatically protects applications' stack frames; more 160 specifically, it guards the return pointers. The protection 161 mechanisms require no application source or binary modification and 162 imposes only a negligible performance penalty." 163 164 The same website provides the following description of how 165 StackGhost works: 166 167 "StackGhost interfaces with the kernel trap handler that would 168 normally write out registers to the stack and the handler that 169 would read them back in. By XORing a cookie into the 170 return-address saved in the user stack when it is actually written 171 to the stack, and then XOR it out when the return-address is pulled 172 from the stack, StackGhost can cause attacker corrupted return 173 pointers to behave in a manner the attacker cannot predict. 174 StackGhost can also use several unused bits in the return pointer 175 to detect a smashed return pointer and abort the process." 176 177 For GDB this means that whenever we're reading %i7 from a stack 178 frame's window save area, we'll have to XOR the cookie. 179 180 More information on StackGuard can be found on in: 181 182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated 183 Stack Protection." 2001. Published in USENIX Security Symposium 184 '01. */ 185 186 /* Fetch StackGhost Per-Process XOR cookie. */ 187 188 ULONGEST 189 sparc_fetch_wcookie (struct gdbarch *gdbarch) 190 { 191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 192 struct target_ops *ops = current_top_target (); 193 gdb_byte buf[8]; 194 int len; 195 196 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); 197 if (len == -1) 198 return 0; 199 200 /* We should have either an 32-bit or an 64-bit cookie. */ 201 gdb_assert (len == 4 || len == 8); 202 203 return extract_unsigned_integer (buf, len, byte_order); 204 } 205 206 207 /* The functions on this page are intended to be used to classify 208 function arguments. */ 209 210 /* Check whether TYPE is "Integral or Pointer". */ 211 212 static int 213 sparc_integral_or_pointer_p (const struct type *type) 214 { 215 int len = TYPE_LENGTH (type); 216 217 switch (TYPE_CODE (type)) 218 { 219 case TYPE_CODE_INT: 220 case TYPE_CODE_BOOL: 221 case TYPE_CODE_CHAR: 222 case TYPE_CODE_ENUM: 223 case TYPE_CODE_RANGE: 224 /* We have byte, half-word, word and extended-word/doubleword 225 integral types. The doubleword is an extension to the 226 original 32-bit ABI by the SCD 2.4.x. */ 227 return (len == 1 || len == 2 || len == 4 || len == 8); 228 case TYPE_CODE_PTR: 229 case TYPE_CODE_REF: 230 case TYPE_CODE_RVALUE_REF: 231 /* Allow either 32-bit or 64-bit pointers. */ 232 return (len == 4 || len == 8); 233 default: 234 break; 235 } 236 237 return 0; 238 } 239 240 /* Check whether TYPE is "Floating". */ 241 242 static int 243 sparc_floating_p (const struct type *type) 244 { 245 switch (TYPE_CODE (type)) 246 { 247 case TYPE_CODE_FLT: 248 { 249 int len = TYPE_LENGTH (type); 250 return (len == 4 || len == 8 || len == 16); 251 } 252 default: 253 break; 254 } 255 256 return 0; 257 } 258 259 /* Check whether TYPE is "Complex Floating". */ 260 261 static int 262 sparc_complex_floating_p (const struct type *type) 263 { 264 switch (TYPE_CODE (type)) 265 { 266 case TYPE_CODE_COMPLEX: 267 { 268 int len = TYPE_LENGTH (type); 269 return (len == 8 || len == 16 || len == 32); 270 } 271 default: 272 break; 273 } 274 275 return 0; 276 } 277 278 /* Check whether TYPE is "Structure or Union". 279 280 In terms of Ada subprogram calls, arrays are treated the same as 281 struct and union types. So this function also returns non-zero 282 for array types. */ 283 284 static int 285 sparc_structure_or_union_p (const struct type *type) 286 { 287 switch (TYPE_CODE (type)) 288 { 289 case TYPE_CODE_STRUCT: 290 case TYPE_CODE_UNION: 291 case TYPE_CODE_ARRAY: 292 return 1; 293 default: 294 break; 295 } 296 297 return 0; 298 } 299 300 /* Return true if TYPE is returned by memory, false if returned by 301 register. */ 302 303 static bool 304 sparc_structure_return_p (const struct type *type) 305 { 306 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) 307 { 308 /* Float vectors are always returned by memory. */ 309 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) 310 return true; 311 /* Integer vectors are returned by memory if the vector size 312 is greater than 8 bytes long. */ 313 return (TYPE_LENGTH (type) > 8); 314 } 315 316 if (sparc_floating_p (type)) 317 { 318 /* Floating point types are passed by register for size 4 and 319 8 bytes, and by memory for size 16 bytes. */ 320 return (TYPE_LENGTH (type) == 16); 321 } 322 323 /* Other than that, only aggregates of all sizes get returned by 324 memory. */ 325 return sparc_structure_or_union_p (type); 326 } 327 328 /* Return true if arguments of the given TYPE are passed by 329 memory; false if returned by register. */ 330 331 static bool 332 sparc_arg_by_memory_p (const struct type *type) 333 { 334 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) 335 { 336 /* Float vectors are always passed by memory. */ 337 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) 338 return true; 339 /* Integer vectors are passed by memory if the vector size 340 is greater than 8 bytes long. */ 341 return (TYPE_LENGTH (type) > 8); 342 } 343 344 /* Floats are passed by register for size 4 and 8 bytes, and by memory 345 for size 16 bytes. */ 346 if (sparc_floating_p (type)) 347 return (TYPE_LENGTH (type) == 16); 348 349 /* Complex floats and aggregates of all sizes are passed by memory. */ 350 if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) 351 return true; 352 353 /* Everything else gets passed by register. */ 354 return false; 355 } 356 357 /* Register information. */ 358 #define SPARC32_FPU_REGISTERS \ 359 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 360 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 361 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ 362 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 363 #define SPARC32_CP0_REGISTERS \ 364 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" 365 366 static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; 367 static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; 368 static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; 369 370 static const char *sparc32_register_names[] = 371 { 372 SPARC_CORE_REGISTERS, 373 SPARC32_FPU_REGISTERS, 374 SPARC32_CP0_REGISTERS 375 }; 376 377 /* Total number of registers. */ 378 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) 379 380 /* We provide the aliases %d0..%d30 for the floating registers as 381 "psuedo" registers. */ 382 383 static const char *sparc32_pseudo_register_names[] = 384 { 385 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", 386 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" 387 }; 388 389 /* Total number of pseudo registers. */ 390 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) 391 392 /* Return the name of pseudo register REGNUM. */ 393 394 static const char * 395 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 396 { 397 regnum -= gdbarch_num_regs (gdbarch); 398 399 if (regnum < SPARC32_NUM_PSEUDO_REGS) 400 return sparc32_pseudo_register_names[regnum]; 401 402 internal_error (__FILE__, __LINE__, 403 _("sparc32_pseudo_register_name: bad register number %d"), 404 regnum); 405 } 406 407 /* Return the name of register REGNUM. */ 408 409 static const char * 410 sparc32_register_name (struct gdbarch *gdbarch, int regnum) 411 { 412 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 413 return tdesc_register_name (gdbarch, regnum); 414 415 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 416 return sparc32_register_names[regnum]; 417 418 return sparc32_pseudo_register_name (gdbarch, regnum); 419 } 420 421 /* Construct types for ISA-specific registers. */ 422 423 static struct type * 424 sparc_psr_type (struct gdbarch *gdbarch) 425 { 426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 427 428 if (!tdep->sparc_psr_type) 429 { 430 struct type *type; 431 432 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); 433 append_flags_type_flag (type, 5, "ET"); 434 append_flags_type_flag (type, 6, "PS"); 435 append_flags_type_flag (type, 7, "S"); 436 append_flags_type_flag (type, 12, "EF"); 437 append_flags_type_flag (type, 13, "EC"); 438 439 tdep->sparc_psr_type = type; 440 } 441 442 return tdep->sparc_psr_type; 443 } 444 445 static struct type * 446 sparc_fsr_type (struct gdbarch *gdbarch) 447 { 448 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 449 450 if (!tdep->sparc_fsr_type) 451 { 452 struct type *type; 453 454 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); 455 append_flags_type_flag (type, 0, "NXA"); 456 append_flags_type_flag (type, 1, "DZA"); 457 append_flags_type_flag (type, 2, "UFA"); 458 append_flags_type_flag (type, 3, "OFA"); 459 append_flags_type_flag (type, 4, "NVA"); 460 append_flags_type_flag (type, 5, "NXC"); 461 append_flags_type_flag (type, 6, "DZC"); 462 append_flags_type_flag (type, 7, "UFC"); 463 append_flags_type_flag (type, 8, "OFC"); 464 append_flags_type_flag (type, 9, "NVC"); 465 append_flags_type_flag (type, 22, "NS"); 466 append_flags_type_flag (type, 23, "NXM"); 467 append_flags_type_flag (type, 24, "DZM"); 468 append_flags_type_flag (type, 25, "UFM"); 469 append_flags_type_flag (type, 26, "OFM"); 470 append_flags_type_flag (type, 27, "NVM"); 471 472 tdep->sparc_fsr_type = type; 473 } 474 475 return tdep->sparc_fsr_type; 476 } 477 478 /* Return the GDB type object for the "standard" data type of data in 479 pseudo register REGNUM. */ 480 481 static struct type * 482 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 483 { 484 regnum -= gdbarch_num_regs (gdbarch); 485 486 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) 487 return builtin_type (gdbarch)->builtin_double; 488 489 internal_error (__FILE__, __LINE__, 490 _("sparc32_pseudo_register_type: bad register number %d"), 491 regnum); 492 } 493 494 /* Return the GDB type object for the "standard" data type of data in 495 register REGNUM. */ 496 497 static struct type * 498 sparc32_register_type (struct gdbarch *gdbarch, int regnum) 499 { 500 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 501 return tdesc_register_type (gdbarch, regnum); 502 503 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) 504 return builtin_type (gdbarch)->builtin_float; 505 506 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) 507 return builtin_type (gdbarch)->builtin_data_ptr; 508 509 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 510 return builtin_type (gdbarch)->builtin_func_ptr; 511 512 if (regnum == SPARC32_PSR_REGNUM) 513 return sparc_psr_type (gdbarch); 514 515 if (regnum == SPARC32_FSR_REGNUM) 516 return sparc_fsr_type (gdbarch); 517 518 if (regnum >= gdbarch_num_regs (gdbarch)) 519 return sparc32_pseudo_register_type (gdbarch, regnum); 520 521 return builtin_type (gdbarch)->builtin_int32; 522 } 523 524 static enum register_status 525 sparc32_pseudo_register_read (struct gdbarch *gdbarch, 526 readable_regcache *regcache, 527 int regnum, gdb_byte *buf) 528 { 529 enum register_status status; 530 531 regnum -= gdbarch_num_regs (gdbarch); 532 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 533 534 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 535 status = regcache->raw_read (regnum, buf); 536 if (status == REG_VALID) 537 status = regcache->raw_read (regnum + 1, buf + 4); 538 return status; 539 } 540 541 static void 542 sparc32_pseudo_register_write (struct gdbarch *gdbarch, 543 struct regcache *regcache, 544 int regnum, const gdb_byte *buf) 545 { 546 regnum -= gdbarch_num_regs (gdbarch); 547 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 548 549 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 550 regcache->raw_write (regnum, buf); 551 regcache->raw_write (regnum + 1, buf + 4); 552 } 553 554 /* Implement the stack_frame_destroyed_p gdbarch method. */ 555 556 int 557 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 558 { 559 /* This function must return true if we are one instruction after an 560 instruction that destroyed the stack frame of the current 561 function. The SPARC instructions used to restore the callers 562 stack frame are RESTORE and RETURN/RETT. 563 564 Of these RETURN/RETT is a branch instruction and thus we return 565 true if we are in its delay slot. 566 567 RESTORE is almost always found in the delay slot of a branch 568 instruction that transfers control to the caller, such as JMPL. 569 Thus the next instruction is in the caller frame and we don't 570 need to do anything about it. */ 571 572 unsigned int insn = sparc_fetch_instruction (pc - 4); 573 574 return X_RETTURN (insn); 575 } 576 577 578 static CORE_ADDR 579 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 580 { 581 /* The ABI requires double-word alignment. */ 582 return address & ~0x7; 583 } 584 585 static CORE_ADDR 586 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 587 CORE_ADDR funcaddr, 588 struct value **args, int nargs, 589 struct type *value_type, 590 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 591 struct regcache *regcache) 592 { 593 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 594 595 *bp_addr = sp - 4; 596 *real_pc = funcaddr; 597 598 if (using_struct_return (gdbarch, NULL, value_type)) 599 { 600 gdb_byte buf[4]; 601 602 /* This is an UNIMP instruction. */ 603 store_unsigned_integer (buf, 4, byte_order, 604 TYPE_LENGTH (value_type) & 0x1fff); 605 write_memory (sp - 8, buf, 4); 606 return sp - 8; 607 } 608 609 return sp - 4; 610 } 611 612 static CORE_ADDR 613 sparc32_store_arguments (struct regcache *regcache, int nargs, 614 struct value **args, CORE_ADDR sp, 615 function_call_return_method return_method, 616 CORE_ADDR struct_addr) 617 { 618 struct gdbarch *gdbarch = regcache->arch (); 619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 620 /* Number of words in the "parameter array". */ 621 int num_elements = 0; 622 int element = 0; 623 int i; 624 625 for (i = 0; i < nargs; i++) 626 { 627 struct type *type = value_type (args[i]); 628 int len = TYPE_LENGTH (type); 629 630 if (sparc_arg_by_memory_p (type)) 631 { 632 /* Structure, Union and Quad-Precision Arguments. */ 633 sp -= len; 634 635 /* Use doubleword alignment for these values. That's always 636 correct, and wasting a few bytes shouldn't be a problem. */ 637 sp &= ~0x7; 638 639 write_memory (sp, value_contents (args[i]), len); 640 args[i] = value_from_pointer (lookup_pointer_type (type), sp); 641 num_elements++; 642 } 643 else if (sparc_floating_p (type)) 644 { 645 /* Floating arguments. */ 646 gdb_assert (len == 4 || len == 8); 647 num_elements += (len / 4); 648 } 649 else 650 { 651 /* Arguments passed via the General Purpose Registers. */ 652 num_elements += ((len + 3) / 4); 653 } 654 } 655 656 /* Always allocate at least six words. */ 657 sp -= std::max (6, num_elements) * 4; 658 659 /* The psABI says that "Software convention requires space for the 660 struct/union return value pointer, even if the word is unused." */ 661 sp -= 4; 662 663 /* The psABI says that "Although software convention and the 664 operating system require every stack frame to be doubleword 665 aligned." */ 666 sp &= ~0x7; 667 668 for (i = 0; i < nargs; i++) 669 { 670 const bfd_byte *valbuf = value_contents (args[i]); 671 struct type *type = value_type (args[i]); 672 int len = TYPE_LENGTH (type); 673 gdb_byte buf[4]; 674 675 if (len < 4) 676 { 677 memset (buf, 0, 4 - len); 678 memcpy (buf + 4 - len, valbuf, len); 679 valbuf = buf; 680 len = 4; 681 } 682 683 gdb_assert (len == 4 || len == 8); 684 685 if (element < 6) 686 { 687 int regnum = SPARC_O0_REGNUM + element; 688 689 regcache->cooked_write (regnum, valbuf); 690 if (len > 4 && element < 5) 691 regcache->cooked_write (regnum + 1, valbuf + 4); 692 } 693 694 /* Always store the argument in memory. */ 695 write_memory (sp + 4 + element * 4, valbuf, len); 696 element += len / 4; 697 } 698 699 gdb_assert (element == num_elements); 700 701 if (return_method == return_method_struct) 702 { 703 gdb_byte buf[4]; 704 705 store_unsigned_integer (buf, 4, byte_order, struct_addr); 706 write_memory (sp, buf, 4); 707 } 708 709 return sp; 710 } 711 712 static CORE_ADDR 713 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 714 struct regcache *regcache, CORE_ADDR bp_addr, 715 int nargs, struct value **args, CORE_ADDR sp, 716 function_call_return_method return_method, 717 CORE_ADDR struct_addr) 718 { 719 CORE_ADDR call_pc = (return_method == return_method_struct 720 ? (bp_addr - 12) : (bp_addr - 8)); 721 722 /* Set return address. */ 723 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); 724 725 /* Set up function arguments. */ 726 sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, 727 struct_addr); 728 729 /* Allocate the 16-word window save area. */ 730 sp -= 16 * 4; 731 732 /* Stack should be doubleword aligned at this point. */ 733 gdb_assert (sp % 8 == 0); 734 735 /* Finally, update the stack pointer. */ 736 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); 737 738 return sp; 739 } 740 741 742 /* Use the program counter to determine the contents and size of a 743 breakpoint instruction. Return a pointer to a string of bytes that 744 encode a breakpoint instruction, store the length of the string in 745 *LEN and optionally adjust *PC to point to the correct memory 746 location for inserting the breakpoint. */ 747 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; 748 749 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; 750 751 752 /* Allocate and initialize a frame cache. */ 753 754 static struct sparc_frame_cache * 755 sparc_alloc_frame_cache (void) 756 { 757 struct sparc_frame_cache *cache; 758 759 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); 760 761 /* Base address. */ 762 cache->base = 0; 763 cache->pc = 0; 764 765 /* Frameless until proven otherwise. */ 766 cache->frameless_p = 1; 767 cache->frame_offset = 0; 768 cache->saved_regs_mask = 0; 769 cache->copied_regs_mask = 0; 770 cache->struct_return_p = 0; 771 772 return cache; 773 } 774 775 /* GCC generates several well-known sequences of instructions at the begining 776 of each function prologue when compiling with -fstack-check. If one of 777 such sequences starts at START_PC, then return the address of the 778 instruction immediately past this sequence. Otherwise, return START_PC. */ 779 780 static CORE_ADDR 781 sparc_skip_stack_check (const CORE_ADDR start_pc) 782 { 783 CORE_ADDR pc = start_pc; 784 unsigned long insn; 785 int probing_loop = 0; 786 787 /* With GCC, all stack checking sequences begin with the same two 788 instructions, plus an optional one in the case of a probing loop: 789 790 sethi <some immediate>, %g1 791 sub %sp, %g1, %g1 792 793 or: 794 795 sethi <some immediate>, %g1 796 sethi <some immediate>, %g4 797 sub %sp, %g1, %g1 798 799 or: 800 801 sethi <some immediate>, %g1 802 sub %sp, %g1, %g1 803 sethi <some immediate>, %g4 804 805 If the optional instruction is found (setting g4), assume that a 806 probing loop will follow. */ 807 808 /* sethi <some immediate>, %g1 */ 809 insn = sparc_fetch_instruction (pc); 810 pc = pc + 4; 811 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) 812 return start_pc; 813 814 /* optional: sethi <some immediate>, %g4 */ 815 insn = sparc_fetch_instruction (pc); 816 pc = pc + 4; 817 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 818 { 819 probing_loop = 1; 820 insn = sparc_fetch_instruction (pc); 821 pc = pc + 4; 822 } 823 824 /* sub %sp, %g1, %g1 */ 825 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 826 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) 827 return start_pc; 828 829 insn = sparc_fetch_instruction (pc); 830 pc = pc + 4; 831 832 /* optional: sethi <some immediate>, %g4 */ 833 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 834 { 835 probing_loop = 1; 836 insn = sparc_fetch_instruction (pc); 837 pc = pc + 4; 838 } 839 840 /* First possible sequence: 841 [first two instructions above] 842 clr [%g1 - some immediate] */ 843 844 /* clr [%g1 - some immediate] */ 845 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 846 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 847 { 848 /* Valid stack-check sequence, return the new PC. */ 849 return pc; 850 } 851 852 /* Second possible sequence: A small number of probes. 853 [first two instructions above] 854 clr [%g1] 855 add %g1, -<some immediate>, %g1 856 clr [%g1] 857 [repeat the two instructions above any (small) number of times] 858 clr [%g1 - some immediate] */ 859 860 /* clr [%g1] */ 861 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 862 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 863 { 864 while (1) 865 { 866 /* add %g1, -<some immediate>, %g1 */ 867 insn = sparc_fetch_instruction (pc); 868 pc = pc + 4; 869 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 870 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 871 break; 872 873 /* clr [%g1] */ 874 insn = sparc_fetch_instruction (pc); 875 pc = pc + 4; 876 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 877 && X_RD (insn) == 0 && X_RS1 (insn) == 1)) 878 return start_pc; 879 } 880 881 /* clr [%g1 - some immediate] */ 882 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 883 && X_RS1 (insn) == 1 && X_RD (insn) == 0)) 884 return start_pc; 885 886 /* We found a valid stack-check sequence, return the new PC. */ 887 return pc; 888 } 889 890 /* Third sequence: A probing loop. 891 [first three instructions above] 892 sub %g1, %g4, %g4 893 cmp %g1, %g4 894 be <disp> 895 add %g1, -<some immediate>, %g1 896 ba <disp> 897 clr [%g1] 898 899 And an optional last probe for the remainder: 900 901 clr [%g4 - some immediate] */ 902 903 if (probing_loop) 904 { 905 /* sub %g1, %g4, %g4 */ 906 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 907 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 908 return start_pc; 909 910 /* cmp %g1, %g4 */ 911 insn = sparc_fetch_instruction (pc); 912 pc = pc + 4; 913 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) 914 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 915 return start_pc; 916 917 /* be <disp> */ 918 insn = sparc_fetch_instruction (pc); 919 pc = pc + 4; 920 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) 921 return start_pc; 922 923 /* add %g1, -<some immediate>, %g1 */ 924 insn = sparc_fetch_instruction (pc); 925 pc = pc + 4; 926 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 927 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 928 return start_pc; 929 930 /* ba <disp> */ 931 insn = sparc_fetch_instruction (pc); 932 pc = pc + 4; 933 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) 934 return start_pc; 935 936 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ 937 insn = sparc_fetch_instruction (pc); 938 pc = pc + 4; 939 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 940 && X_RD (insn) == 0 && X_RS1 (insn) == 1 941 && (!X_I(insn) || X_SIMM13 (insn) == 0))) 942 return start_pc; 943 944 /* We found a valid stack-check sequence, return the new PC. */ 945 946 /* optional: clr [%g4 - some immediate] */ 947 insn = sparc_fetch_instruction (pc); 948 pc = pc + 4; 949 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 950 && X_RS1 (insn) == 4 && X_RD (insn) == 0)) 951 return pc - 4; 952 else 953 return pc; 954 } 955 956 /* No stack check code in our prologue, return the start_pc. */ 957 return start_pc; 958 } 959 960 /* Record the effect of a SAVE instruction on CACHE. */ 961 962 void 963 sparc_record_save_insn (struct sparc_frame_cache *cache) 964 { 965 /* The frame is set up. */ 966 cache->frameless_p = 0; 967 968 /* The frame pointer contains the CFA. */ 969 cache->frame_offset = 0; 970 971 /* The `local' and `in' registers are all saved. */ 972 cache->saved_regs_mask = 0xffff; 973 974 /* The `out' registers are all renamed. */ 975 cache->copied_regs_mask = 0xff; 976 } 977 978 /* Do a full analysis of the prologue at PC and update CACHE accordingly. 979 Bail out early if CURRENT_PC is reached. Return the address where 980 the analysis stopped. 981 982 We handle both the traditional register window model and the single 983 register window (aka flat) model. */ 984 985 CORE_ADDR 986 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, 987 CORE_ADDR current_pc, struct sparc_frame_cache *cache) 988 { 989 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 990 unsigned long insn; 991 int offset = 0; 992 int dest = -1; 993 994 pc = sparc_skip_stack_check (pc); 995 996 if (current_pc <= pc) 997 return current_pc; 998 999 /* We have to handle to "Procedure Linkage Table" (PLT) special. On 1000 SPARC the linker usually defines a symbol (typically 1001 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. 1002 This symbol makes us end up here with PC pointing at the start of 1003 the PLT and CURRENT_PC probably pointing at a PLT entry. If we 1004 would do our normal prologue analysis, we would probably conclude 1005 that we've got a frame when in reality we don't, since the 1006 dynamic linker patches up the first PLT with some code that 1007 starts with a SAVE instruction. Patch up PC such that it points 1008 at the start of our PLT entry. */ 1009 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) 1010 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); 1011 1012 insn = sparc_fetch_instruction (pc); 1013 1014 /* Recognize store insns and record their sources. */ 1015 while (X_OP (insn) == 3 1016 && (X_OP3 (insn) == 0x4 /* stw */ 1017 || X_OP3 (insn) == 0x7 /* std */ 1018 || X_OP3 (insn) == 0xe) /* stx */ 1019 && X_RS1 (insn) == SPARC_SP_REGNUM) 1020 { 1021 int regnum = X_RD (insn); 1022 1023 /* Recognize stores into the corresponding stack slots. */ 1024 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1025 && ((X_I (insn) 1026 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe 1027 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS 1028 : (regnum - SPARC_L0_REGNUM) * 4)) 1029 || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) 1030 { 1031 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); 1032 if (X_OP3 (insn) == 0x7) 1033 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); 1034 } 1035 1036 offset += 4; 1037 1038 insn = sparc_fetch_instruction (pc + offset); 1039 } 1040 1041 /* Recognize a SETHI insn and record its destination. */ 1042 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) 1043 { 1044 dest = X_RD (insn); 1045 offset += 4; 1046 1047 insn = sparc_fetch_instruction (pc + offset); 1048 } 1049 1050 /* Allow for an arithmetic operation on DEST or %g1. */ 1051 if (X_OP (insn) == 2 && X_I (insn) 1052 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 1053 { 1054 offset += 4; 1055 1056 insn = sparc_fetch_instruction (pc + offset); 1057 } 1058 1059 /* Check for the SAVE instruction that sets up the frame. */ 1060 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) 1061 { 1062 sparc_record_save_insn (cache); 1063 offset += 4; 1064 return pc + offset; 1065 } 1066 1067 /* Check for an arithmetic operation on %sp. */ 1068 if (X_OP (insn) == 2 1069 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1070 && X_RS1 (insn) == SPARC_SP_REGNUM 1071 && X_RD (insn) == SPARC_SP_REGNUM) 1072 { 1073 if (X_I (insn)) 1074 { 1075 cache->frame_offset = X_SIMM13 (insn); 1076 if (X_OP3 (insn) == 0) 1077 cache->frame_offset = -cache->frame_offset; 1078 } 1079 offset += 4; 1080 1081 insn = sparc_fetch_instruction (pc + offset); 1082 1083 /* Check for an arithmetic operation that sets up the frame. */ 1084 if (X_OP (insn) == 2 1085 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1086 && X_RS1 (insn) == SPARC_SP_REGNUM 1087 && X_RD (insn) == SPARC_FP_REGNUM) 1088 { 1089 cache->frameless_p = 0; 1090 cache->frame_offset = 0; 1091 /* We could check that the amount subtracted to %sp above is the 1092 same as the one added here, but this seems superfluous. */ 1093 cache->copied_regs_mask |= 0x40; 1094 offset += 4; 1095 1096 insn = sparc_fetch_instruction (pc + offset); 1097 } 1098 1099 /* Check for a move (or) operation that copies the return register. */ 1100 if (X_OP (insn) == 2 1101 && X_OP3 (insn) == 0x2 1102 && !X_I (insn) 1103 && X_RS1 (insn) == SPARC_G0_REGNUM 1104 && X_RS2 (insn) == SPARC_O7_REGNUM 1105 && X_RD (insn) == SPARC_I7_REGNUM) 1106 { 1107 cache->copied_regs_mask |= 0x80; 1108 offset += 4; 1109 } 1110 1111 return pc + offset; 1112 } 1113 1114 return pc; 1115 } 1116 1117 static CORE_ADDR 1118 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) 1119 { 1120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1121 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); 1122 } 1123 1124 /* Return PC of first real instruction of the function starting at 1125 START_PC. */ 1126 1127 static CORE_ADDR 1128 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1129 { 1130 struct symtab_and_line sal; 1131 CORE_ADDR func_start, func_end; 1132 struct sparc_frame_cache cache; 1133 1134 /* This is the preferred method, find the end of the prologue by 1135 using the debugging information. */ 1136 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) 1137 { 1138 sal = find_pc_line (func_start, 0); 1139 1140 if (sal.end < func_end 1141 && start_pc <= sal.end) 1142 return sal.end; 1143 } 1144 1145 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); 1146 1147 /* The psABI says that "Although the first 6 words of arguments 1148 reside in registers, the standard stack frame reserves space for 1149 them.". It also suggests that a function may use that space to 1150 "write incoming arguments 0 to 5" into that space, and that's 1151 indeed what GCC seems to be doing. In that case GCC will 1152 generate debug information that points to the stack slots instead 1153 of the registers, so we should consider the instructions that 1154 write out these incoming arguments onto the stack. */ 1155 1156 while (1) 1157 { 1158 unsigned long insn = sparc_fetch_instruction (start_pc); 1159 1160 /* Recognize instructions that store incoming arguments into the 1161 corresponding stack slots. */ 1162 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 1163 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) 1164 { 1165 int regnum = X_RD (insn); 1166 1167 /* Case of arguments still in %o[0..5]. */ 1168 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM 1169 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) 1170 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) 1171 { 1172 start_pc += 4; 1173 continue; 1174 } 1175 1176 /* Case of arguments copied into %i[0..5]. */ 1177 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM 1178 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) 1179 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) 1180 { 1181 start_pc += 4; 1182 continue; 1183 } 1184 } 1185 1186 break; 1187 } 1188 1189 return start_pc; 1190 } 1191 1192 /* Normal frames. */ 1193 1194 struct sparc_frame_cache * 1195 sparc_frame_cache (struct frame_info *this_frame, void **this_cache) 1196 { 1197 struct sparc_frame_cache *cache; 1198 1199 if (*this_cache) 1200 return (struct sparc_frame_cache *) *this_cache; 1201 1202 cache = sparc_alloc_frame_cache (); 1203 *this_cache = cache; 1204 1205 cache->pc = get_frame_func (this_frame); 1206 if (cache->pc != 0) 1207 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, 1208 get_frame_pc (this_frame), cache); 1209 1210 if (cache->frameless_p) 1211 { 1212 /* This function is frameless, so %fp (%i6) holds the frame 1213 pointer for our calling frame. Use %sp (%o6) as this frame's 1214 base address. */ 1215 cache->base = 1216 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1217 } 1218 else 1219 { 1220 /* For normal frames, %fp (%i6) holds the frame pointer, the 1221 base address for the current stack frame. */ 1222 cache->base = 1223 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); 1224 } 1225 1226 cache->base += cache->frame_offset; 1227 1228 if (cache->base & 1) 1229 cache->base += BIAS; 1230 1231 return cache; 1232 } 1233 1234 static int 1235 sparc32_struct_return_from_sym (struct symbol *sym) 1236 { 1237 struct type *type = check_typedef (SYMBOL_TYPE (sym)); 1238 enum type_code code = TYPE_CODE (type); 1239 1240 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) 1241 { 1242 type = check_typedef (TYPE_TARGET_TYPE (type)); 1243 if (sparc_structure_or_union_p (type) 1244 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1245 return 1; 1246 } 1247 1248 return 0; 1249 } 1250 1251 struct sparc_frame_cache * 1252 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) 1253 { 1254 struct sparc_frame_cache *cache; 1255 struct symbol *sym; 1256 1257 if (*this_cache) 1258 return (struct sparc_frame_cache *) *this_cache; 1259 1260 cache = sparc_frame_cache (this_frame, this_cache); 1261 1262 sym = find_pc_function (cache->pc); 1263 if (sym) 1264 { 1265 cache->struct_return_p = sparc32_struct_return_from_sym (sym); 1266 } 1267 else 1268 { 1269 /* There is no debugging information for this function to 1270 help us determine whether this function returns a struct 1271 or not. So we rely on another heuristic which is to check 1272 the instruction at the return address and see if this is 1273 an "unimp" instruction. If it is, then it is a struct-return 1274 function. */ 1275 CORE_ADDR pc; 1276 int regnum = 1277 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1278 1279 pc = get_frame_register_unsigned (this_frame, regnum) + 8; 1280 if (sparc_is_unimp_insn (pc)) 1281 cache->struct_return_p = 1; 1282 } 1283 1284 return cache; 1285 } 1286 1287 static void 1288 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, 1289 struct frame_id *this_id) 1290 { 1291 struct sparc_frame_cache *cache = 1292 sparc32_frame_cache (this_frame, this_cache); 1293 1294 /* This marks the outermost frame. */ 1295 if (cache->base == 0) 1296 return; 1297 1298 (*this_id) = frame_id_build (cache->base, cache->pc); 1299 } 1300 1301 static struct value * 1302 sparc32_frame_prev_register (struct frame_info *this_frame, 1303 void **this_cache, int regnum) 1304 { 1305 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1306 struct sparc_frame_cache *cache = 1307 sparc32_frame_cache (this_frame, this_cache); 1308 1309 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 1310 { 1311 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; 1312 1313 /* If this functions has a Structure, Union or Quad-Precision 1314 return value, we have to skip the UNIMP instruction that encodes 1315 the size of the structure. */ 1316 if (cache->struct_return_p) 1317 pc += 4; 1318 1319 regnum = 1320 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1321 pc += get_frame_register_unsigned (this_frame, regnum) + 8; 1322 return frame_unwind_got_constant (this_frame, regnum, pc); 1323 } 1324 1325 /* Handle StackGhost. */ 1326 { 1327 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1328 1329 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) 1330 { 1331 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1332 ULONGEST i7; 1333 1334 /* Read the value in from memory. */ 1335 i7 = get_frame_memory_unsigned (this_frame, addr, 4); 1336 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); 1337 } 1338 } 1339 1340 /* The previous frame's `local' and `in' registers may have been saved 1341 in the register save area. */ 1342 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1343 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) 1344 { 1345 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1346 1347 return frame_unwind_got_memory (this_frame, regnum, addr); 1348 } 1349 1350 /* The previous frame's `out' registers may be accessible as the current 1351 frame's `in' registers. */ 1352 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM 1353 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) 1354 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); 1355 1356 return frame_unwind_got_register (this_frame, regnum, regnum); 1357 } 1358 1359 static const struct frame_unwind sparc32_frame_unwind = 1360 { 1361 NORMAL_FRAME, 1362 default_frame_unwind_stop_reason, 1363 sparc32_frame_this_id, 1364 sparc32_frame_prev_register, 1365 NULL, 1366 default_frame_sniffer 1367 }; 1368 1369 1370 static CORE_ADDR 1371 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) 1372 { 1373 struct sparc_frame_cache *cache = 1374 sparc32_frame_cache (this_frame, this_cache); 1375 1376 return cache->base; 1377 } 1378 1379 static const struct frame_base sparc32_frame_base = 1380 { 1381 &sparc32_frame_unwind, 1382 sparc32_frame_base_address, 1383 sparc32_frame_base_address, 1384 sparc32_frame_base_address 1385 }; 1386 1387 static struct frame_id 1388 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1389 { 1390 CORE_ADDR sp; 1391 1392 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1393 if (sp & 1) 1394 sp += BIAS; 1395 return frame_id_build (sp, get_frame_pc (this_frame)); 1396 } 1397 1398 1399 /* Extract a function return value of TYPE from REGCACHE, and copy 1400 that into VALBUF. */ 1401 1402 static void 1403 sparc32_extract_return_value (struct type *type, struct regcache *regcache, 1404 gdb_byte *valbuf) 1405 { 1406 int len = TYPE_LENGTH (type); 1407 gdb_byte buf[32]; 1408 1409 gdb_assert (!sparc_structure_return_p (type)); 1410 1411 if (sparc_floating_p (type) || sparc_complex_floating_p (type) 1412 || TYPE_CODE (type) == TYPE_CODE_ARRAY) 1413 { 1414 /* Floating return values. */ 1415 regcache->cooked_read (SPARC_F0_REGNUM, buf); 1416 if (len > 4) 1417 regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); 1418 if (len > 8) 1419 { 1420 regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); 1421 regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); 1422 } 1423 if (len > 16) 1424 { 1425 regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); 1426 regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); 1427 regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); 1428 regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); 1429 } 1430 memcpy (valbuf, buf, len); 1431 } 1432 else 1433 { 1434 /* Integral and pointer return values. */ 1435 gdb_assert (sparc_integral_or_pointer_p (type)); 1436 1437 regcache->cooked_read (SPARC_O0_REGNUM, buf); 1438 if (len > 4) 1439 { 1440 regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); 1441 gdb_assert (len == 8); 1442 memcpy (valbuf, buf, 8); 1443 } 1444 else 1445 { 1446 /* Just stripping off any unused bytes should preserve the 1447 signed-ness just fine. */ 1448 memcpy (valbuf, buf + 4 - len, len); 1449 } 1450 } 1451 } 1452 1453 /* Store the function return value of type TYPE from VALBUF into 1454 REGCACHE. */ 1455 1456 static void 1457 sparc32_store_return_value (struct type *type, struct regcache *regcache, 1458 const gdb_byte *valbuf) 1459 { 1460 int len = TYPE_LENGTH (type); 1461 gdb_byte buf[32]; 1462 1463 gdb_assert (!sparc_structure_return_p (type)); 1464 1465 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1466 { 1467 /* Floating return values. */ 1468 memcpy (buf, valbuf, len); 1469 regcache->cooked_write (SPARC_F0_REGNUM, buf); 1470 if (len > 4) 1471 regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); 1472 if (len > 8) 1473 { 1474 regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); 1475 regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); 1476 } 1477 if (len > 16) 1478 { 1479 regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); 1480 regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); 1481 regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); 1482 regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); 1483 } 1484 } 1485 else 1486 { 1487 /* Integral and pointer return values. */ 1488 gdb_assert (sparc_integral_or_pointer_p (type)); 1489 1490 if (len > 4) 1491 { 1492 gdb_assert (len == 8); 1493 memcpy (buf, valbuf, 8); 1494 regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); 1495 } 1496 else 1497 { 1498 /* ??? Do we need to do any sign-extension here? */ 1499 memcpy (buf + 4 - len, valbuf, len); 1500 } 1501 regcache->cooked_write (SPARC_O0_REGNUM, buf); 1502 } 1503 } 1504 1505 static enum return_value_convention 1506 sparc32_return_value (struct gdbarch *gdbarch, struct value *function, 1507 struct type *type, struct regcache *regcache, 1508 gdb_byte *readbuf, const gdb_byte *writebuf) 1509 { 1510 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1511 1512 /* The psABI says that "...every stack frame reserves the word at 1513 %fp+64. If a function returns a structure, union, or 1514 quad-precision value, this word should hold the address of the 1515 object into which the return value should be copied." This 1516 guarantees that we can always find the return value, not just 1517 before the function returns. */ 1518 1519 if (sparc_structure_return_p (type)) 1520 { 1521 ULONGEST sp; 1522 CORE_ADDR addr; 1523 1524 if (readbuf) 1525 { 1526 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1527 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1528 read_memory (addr, readbuf, TYPE_LENGTH (type)); 1529 } 1530 if (writebuf) 1531 { 1532 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1533 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1534 write_memory (addr, writebuf, TYPE_LENGTH (type)); 1535 } 1536 1537 return RETURN_VALUE_ABI_PRESERVES_ADDRESS; 1538 } 1539 1540 if (readbuf) 1541 sparc32_extract_return_value (type, regcache, readbuf); 1542 if (writebuf) 1543 sparc32_store_return_value (type, regcache, writebuf); 1544 1545 return RETURN_VALUE_REGISTER_CONVENTION; 1546 } 1547 1548 static int 1549 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) 1550 { 1551 return (sparc_structure_or_union_p (type) 1552 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) 1553 || sparc_complex_floating_p (type)); 1554 } 1555 1556 static int 1557 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) 1558 { 1559 CORE_ADDR pc = get_frame_address_in_block (this_frame); 1560 struct symbol *sym = find_pc_function (pc); 1561 1562 if (sym) 1563 return sparc32_struct_return_from_sym (sym); 1564 return 0; 1565 } 1566 1567 static void 1568 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1569 struct dwarf2_frame_state_reg *reg, 1570 struct frame_info *this_frame) 1571 { 1572 int off; 1573 1574 switch (regnum) 1575 { 1576 case SPARC_G0_REGNUM: 1577 /* Since %g0 is always zero, there is no point in saving it, and 1578 people will be inclined omit it from the CFI. Make sure we 1579 don't warn about that. */ 1580 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1581 break; 1582 case SPARC_SP_REGNUM: 1583 reg->how = DWARF2_FRAME_REG_CFA; 1584 break; 1585 case SPARC32_PC_REGNUM: 1586 case SPARC32_NPC_REGNUM: 1587 reg->how = DWARF2_FRAME_REG_RA_OFFSET; 1588 off = 8; 1589 if (sparc32_dwarf2_struct_return_p (this_frame)) 1590 off += 4; 1591 if (regnum == SPARC32_NPC_REGNUM) 1592 off += 4; 1593 reg->loc.offset = off; 1594 break; 1595 } 1596 } 1597 1598 /* Implement the execute_dwarf_cfa_vendor_op method. */ 1599 1600 static bool 1601 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, 1602 struct dwarf2_frame_state *fs) 1603 { 1604 /* Only DW_CFA_GNU_window_save is expected on SPARC. */ 1605 if (op != DW_CFA_GNU_window_save) 1606 return false; 1607 1608 uint64_t reg; 1609 int size = register_size (gdbarch, 0); 1610 1611 fs->regs.alloc_regs (32); 1612 for (reg = 8; reg < 16; reg++) 1613 { 1614 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; 1615 fs->regs.reg[reg].loc.reg = reg + 16; 1616 } 1617 for (reg = 16; reg < 32; reg++) 1618 { 1619 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; 1620 fs->regs.reg[reg].loc.offset = (reg - 16) * size; 1621 } 1622 1623 return true; 1624 } 1625 1626 1627 /* The SPARC Architecture doesn't have hardware single-step support, 1628 and most operating systems don't implement it either, so we provide 1629 software single-step mechanism. */ 1630 1631 static CORE_ADDR 1632 sparc_analyze_control_transfer (struct regcache *regcache, 1633 CORE_ADDR pc, CORE_ADDR *npc) 1634 { 1635 unsigned long insn = sparc_fetch_instruction (pc); 1636 int conditional_p = X_COND (insn) & 0x7; 1637 int branch_p = 0, fused_p = 0; 1638 long offset = 0; /* Must be signed for sign-extend. */ 1639 1640 if (X_OP (insn) == 0 && X_OP2 (insn) == 3) 1641 { 1642 if ((insn & 0x10000000) == 0) 1643 { 1644 /* Branch on Integer Register with Prediction (BPr). */ 1645 branch_p = 1; 1646 conditional_p = 1; 1647 } 1648 else 1649 { 1650 /* Compare and Branch */ 1651 branch_p = 1; 1652 fused_p = 1; 1653 offset = 4 * X_DISP10 (insn); 1654 } 1655 } 1656 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) 1657 { 1658 /* Branch on Floating-Point Condition Codes (FBfcc). */ 1659 branch_p = 1; 1660 offset = 4 * X_DISP22 (insn); 1661 } 1662 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) 1663 { 1664 /* Branch on Floating-Point Condition Codes with Prediction 1665 (FBPfcc). */ 1666 branch_p = 1; 1667 offset = 4 * X_DISP19 (insn); 1668 } 1669 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) 1670 { 1671 /* Branch on Integer Condition Codes (Bicc). */ 1672 branch_p = 1; 1673 offset = 4 * X_DISP22 (insn); 1674 } 1675 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) 1676 { 1677 /* Branch on Integer Condition Codes with Prediction (BPcc). */ 1678 branch_p = 1; 1679 offset = 4 * X_DISP19 (insn); 1680 } 1681 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) 1682 { 1683 struct frame_info *frame = get_current_frame (); 1684 1685 /* Trap instruction (TRAP). */ 1686 return gdbarch_tdep (regcache->arch ())->step_trap (frame, 1687 insn); 1688 } 1689 1690 /* FIXME: Handle DONE and RETRY instructions. */ 1691 1692 if (branch_p) 1693 { 1694 if (fused_p) 1695 { 1696 /* Fused compare-and-branch instructions are non-delayed, 1697 and do not have an annuling capability. So we need to 1698 always set a breakpoint on both the NPC and the branch 1699 target address. */ 1700 gdb_assert (offset != 0); 1701 return pc + offset; 1702 } 1703 else if (conditional_p) 1704 { 1705 /* For conditional branches, return nPC + 4 iff the annul 1706 bit is 1. */ 1707 return (X_A (insn) ? *npc + 4 : 0); 1708 } 1709 else 1710 { 1711 /* For unconditional branches, return the target if its 1712 specified condition is "always" and return nPC + 4 if the 1713 condition is "never". If the annul bit is 1, set *NPC to 1714 zero. */ 1715 if (X_COND (insn) == 0x0) 1716 pc = *npc, offset = 4; 1717 if (X_A (insn)) 1718 *npc = 0; 1719 1720 return pc + offset; 1721 } 1722 } 1723 1724 return 0; 1725 } 1726 1727 static CORE_ADDR 1728 sparc_step_trap (struct frame_info *frame, unsigned long insn) 1729 { 1730 return 0; 1731 } 1732 1733 static std::vector<CORE_ADDR> 1734 sparc_software_single_step (struct regcache *regcache) 1735 { 1736 struct gdbarch *arch = regcache->arch (); 1737 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1738 CORE_ADDR npc, nnpc; 1739 1740 CORE_ADDR pc, orig_npc; 1741 std::vector<CORE_ADDR> next_pcs; 1742 1743 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); 1744 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); 1745 1746 /* Analyze the instruction at PC. */ 1747 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); 1748 if (npc != 0) 1749 next_pcs.push_back (npc); 1750 1751 if (nnpc != 0) 1752 next_pcs.push_back (nnpc); 1753 1754 /* Assert that we have set at least one breakpoint, and that 1755 they're not set at the same spot - unless we're going 1756 from here straight to NULL, i.e. a call or jump to 0. */ 1757 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); 1758 gdb_assert (nnpc != npc || orig_npc == 0); 1759 1760 return next_pcs; 1761 } 1762 1763 static void 1764 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) 1765 { 1766 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); 1767 1768 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); 1769 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); 1770 } 1771 1772 1773 /* Iterate over core file register note sections. */ 1774 1775 static void 1776 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, 1777 iterate_over_regset_sections_cb *cb, 1778 void *cb_data, 1779 const struct regcache *regcache) 1780 { 1781 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1782 1783 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, 1784 cb_data); 1785 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, 1786 NULL, cb_data); 1787 } 1788 1789 1790 static int 1791 validate_tdesc_registers (const struct target_desc *tdesc, 1792 struct tdesc_arch_data *tdesc_data, 1793 const char *feature_name, 1794 const char *register_names[], 1795 unsigned int registers_num, 1796 unsigned int reg_start) 1797 { 1798 int valid_p = 1; 1799 const struct tdesc_feature *feature; 1800 1801 feature = tdesc_find_feature (tdesc, feature_name); 1802 if (feature == NULL) 1803 return 0; 1804 1805 for (unsigned int i = 0; i < registers_num; i++) 1806 valid_p &= tdesc_numbered_register (feature, tdesc_data, 1807 reg_start + i, 1808 register_names[i]); 1809 1810 return valid_p; 1811 } 1812 1813 static struct gdbarch * 1814 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1815 { 1816 struct gdbarch_tdep *tdep; 1817 const struct target_desc *tdesc = info.target_desc; 1818 struct gdbarch *gdbarch; 1819 int valid_p = 1; 1820 1821 /* If there is already a candidate, use it. */ 1822 arches = gdbarch_list_lookup_by_info (arches, &info); 1823 if (arches != NULL) 1824 return arches->gdbarch; 1825 1826 /* Allocate space for the new architecture. */ 1827 tdep = XCNEW (struct gdbarch_tdep); 1828 gdbarch = gdbarch_alloc (&info, tdep); 1829 1830 tdep->pc_regnum = SPARC32_PC_REGNUM; 1831 tdep->npc_regnum = SPARC32_NPC_REGNUM; 1832 tdep->step_trap = sparc_step_trap; 1833 tdep->fpu_register_names = sparc32_fpu_register_names; 1834 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); 1835 tdep->cp0_register_names = sparc32_cp0_register_names; 1836 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); 1837 1838 set_gdbarch_long_double_bit (gdbarch, 128); 1839 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); 1840 1841 set_gdbarch_wchar_bit (gdbarch, 16); 1842 set_gdbarch_wchar_signed (gdbarch, 1); 1843 1844 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); 1845 set_gdbarch_register_name (gdbarch, sparc32_register_name); 1846 set_gdbarch_register_type (gdbarch, sparc32_register_type); 1847 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); 1848 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); 1849 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); 1850 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); 1851 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); 1852 1853 /* Register numbers of various important registers. */ 1854 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ 1855 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ 1856 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ 1857 1858 /* Call dummy code. */ 1859 set_gdbarch_frame_align (gdbarch, sparc32_frame_align); 1860 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 1861 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); 1862 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); 1863 1864 set_gdbarch_return_value (gdbarch, sparc32_return_value); 1865 set_gdbarch_stabs_argument_has_addr 1866 (gdbarch, sparc32_stabs_argument_has_addr); 1867 1868 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); 1869 1870 /* Stack grows downward. */ 1871 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1872 1873 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 1874 sparc_breakpoint::kind_from_pc); 1875 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 1876 sparc_breakpoint::bp_from_kind); 1877 1878 set_gdbarch_frame_args_skip (gdbarch, 8); 1879 1880 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); 1881 set_gdbarch_write_pc (gdbarch, sparc_write_pc); 1882 1883 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); 1884 1885 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); 1886 1887 frame_base_set_default (gdbarch, &sparc32_frame_base); 1888 1889 /* Hook in the DWARF CFI frame unwinder. */ 1890 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); 1891 /* Register DWARF vendor CFI handler. */ 1892 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, 1893 sparc_execute_dwarf_cfa_vendor_op); 1894 /* FIXME: kettenis/20050423: Don't enable the unwinder until the 1895 StackGhost issues have been resolved. */ 1896 1897 /* Hook in ABI-specific overrides, if they have been registered. */ 1898 gdbarch_init_osabi (info, gdbarch); 1899 1900 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); 1901 1902 if (tdesc_has_registers (tdesc)) 1903 { 1904 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); 1905 1906 /* Validate that the descriptor provides the mandatory registers 1907 and allocate their numbers. */ 1908 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1909 "org.gnu.gdb.sparc.cpu", 1910 sparc_core_register_names, 1911 ARRAY_SIZE (sparc_core_register_names), 1912 SPARC_G0_REGNUM); 1913 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1914 "org.gnu.gdb.sparc.fpu", 1915 tdep->fpu_register_names, 1916 tdep->fpu_registers_num, 1917 SPARC_F0_REGNUM); 1918 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1919 "org.gnu.gdb.sparc.cp0", 1920 tdep->cp0_register_names, 1921 tdep->cp0_registers_num, 1922 SPARC_F0_REGNUM 1923 + tdep->fpu_registers_num); 1924 if (!valid_p) 1925 { 1926 tdesc_data_cleanup (tdesc_data); 1927 return NULL; 1928 } 1929 1930 /* Target description may have changed. */ 1931 info.tdesc_data = tdesc_data; 1932 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 1933 } 1934 1935 /* If we have register sets, enable the generic core file support. */ 1936 if (tdep->gregset) 1937 set_gdbarch_iterate_over_regset_sections 1938 (gdbarch, sparc_iterate_over_regset_sections); 1939 1940 register_sparc_ravenscar_ops (gdbarch); 1941 1942 return gdbarch; 1943 } 1944 1945 /* Helper functions for dealing with register windows. */ 1946 1947 void 1948 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) 1949 { 1950 struct gdbarch *gdbarch = regcache->arch (); 1951 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1952 int offset = 0; 1953 gdb_byte buf[8]; 1954 int i; 1955 1956 if (sp & 1) 1957 { 1958 /* Registers are 64-bit. */ 1959 sp += BIAS; 1960 1961 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1962 { 1963 if (regnum == i || regnum == -1) 1964 { 1965 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1966 1967 /* Handle StackGhost. */ 1968 if (i == SPARC_I7_REGNUM) 1969 { 1970 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1971 ULONGEST i7; 1972 1973 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1974 store_unsigned_integer (buf + offset, 8, byte_order, 1975 i7 ^ wcookie); 1976 } 1977 1978 regcache->raw_supply (i, buf); 1979 } 1980 } 1981 } 1982 else 1983 { 1984 /* Registers are 32-bit. Toss any sign-extension of the stack 1985 pointer. */ 1986 sp &= 0xffffffffUL; 1987 1988 /* Clear out the top half of the temporary buffer, and put the 1989 register value in the bottom half if we're in 64-bit mode. */ 1990 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 1991 { 1992 memset (buf, 0, 4); 1993 offset = 4; 1994 } 1995 1996 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1997 { 1998 if (regnum == i || regnum == -1) 1999 { 2000 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 2001 buf + offset, 4); 2002 2003 /* Handle StackGhost. */ 2004 if (i == SPARC_I7_REGNUM) 2005 { 2006 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2007 ULONGEST i7; 2008 2009 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2010 store_unsigned_integer (buf + offset, 4, byte_order, 2011 i7 ^ wcookie); 2012 } 2013 2014 regcache->raw_supply (i, buf); 2015 } 2016 } 2017 } 2018 } 2019 2020 void 2021 sparc_collect_rwindow (const struct regcache *regcache, 2022 CORE_ADDR sp, int regnum) 2023 { 2024 struct gdbarch *gdbarch = regcache->arch (); 2025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2026 int offset = 0; 2027 gdb_byte buf[8]; 2028 int i; 2029 2030 if (sp & 1) 2031 { 2032 /* Registers are 64-bit. */ 2033 sp += BIAS; 2034 2035 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2036 { 2037 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2038 { 2039 regcache->raw_collect (i, buf); 2040 2041 /* Handle StackGhost. */ 2042 if (i == SPARC_I7_REGNUM) 2043 { 2044 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2045 ULONGEST i7; 2046 2047 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 2048 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); 2049 } 2050 2051 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 2052 } 2053 } 2054 } 2055 else 2056 { 2057 /* Registers are 32-bit. Toss any sign-extension of the stack 2058 pointer. */ 2059 sp &= 0xffffffffUL; 2060 2061 /* Only use the bottom half if we're in 64-bit mode. */ 2062 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 2063 offset = 4; 2064 2065 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2066 { 2067 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2068 { 2069 regcache->raw_collect (i, buf); 2070 2071 /* Handle StackGhost. */ 2072 if (i == SPARC_I7_REGNUM) 2073 { 2074 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2075 ULONGEST i7; 2076 2077 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2078 store_unsigned_integer (buf + offset, 4, byte_order, 2079 i7 ^ wcookie); 2080 } 2081 2082 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 2083 buf + offset, 4); 2084 } 2085 } 2086 } 2087 } 2088 2089 /* Helper functions for dealing with register sets. */ 2090 2091 void 2092 sparc32_supply_gregset (const struct sparc_gregmap *gregmap, 2093 struct regcache *regcache, 2094 int regnum, const void *gregs) 2095 { 2096 const gdb_byte *regs = (const gdb_byte *) gregs; 2097 gdb_byte zero[4] = { 0 }; 2098 int i; 2099 2100 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2101 regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2102 2103 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2104 regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2105 2106 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2107 regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2108 2109 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2110 regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2111 2112 if (regnum == SPARC_G0_REGNUM || regnum == -1) 2113 regcache->raw_supply (SPARC_G0_REGNUM, &zero); 2114 2115 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2116 { 2117 int offset = gregmap->r_g1_offset; 2118 2119 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2120 { 2121 if (regnum == i || regnum == -1) 2122 regcache->raw_supply (i, regs + offset); 2123 offset += 4; 2124 } 2125 } 2126 2127 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2128 { 2129 /* Not all of the register set variants include Locals and 2130 Inputs. For those that don't, we read them off the stack. */ 2131 if (gregmap->r_l0_offset == -1) 2132 { 2133 ULONGEST sp; 2134 2135 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 2136 sparc_supply_rwindow (regcache, sp, regnum); 2137 } 2138 else 2139 { 2140 int offset = gregmap->r_l0_offset; 2141 2142 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2143 { 2144 if (regnum == i || regnum == -1) 2145 regcache->raw_supply (i, regs + offset); 2146 offset += 4; 2147 } 2148 } 2149 } 2150 } 2151 2152 void 2153 sparc32_collect_gregset (const struct sparc_gregmap *gregmap, 2154 const struct regcache *regcache, 2155 int regnum, void *gregs) 2156 { 2157 gdb_byte *regs = (gdb_byte *) gregs; 2158 int i; 2159 2160 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2161 regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2162 2163 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2164 regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2165 2166 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2167 regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2168 2169 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2170 regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2171 2172 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2173 { 2174 int offset = gregmap->r_g1_offset; 2175 2176 /* %g0 is always zero. */ 2177 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2178 { 2179 if (regnum == i || regnum == -1) 2180 regcache->raw_collect (i, regs + offset); 2181 offset += 4; 2182 } 2183 } 2184 2185 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2186 { 2187 /* Not all of the register set variants include Locals and 2188 Inputs. For those that don't, we read them off the stack. */ 2189 if (gregmap->r_l0_offset != -1) 2190 { 2191 int offset = gregmap->r_l0_offset; 2192 2193 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2194 { 2195 if (regnum == i || regnum == -1) 2196 regcache->raw_collect (i, regs + offset); 2197 offset += 4; 2198 } 2199 } 2200 } 2201 } 2202 2203 void 2204 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, 2205 struct regcache *regcache, 2206 int regnum, const void *fpregs) 2207 { 2208 const gdb_byte *regs = (const gdb_byte *) fpregs; 2209 int i; 2210 2211 for (i = 0; i < 32; i++) 2212 { 2213 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2214 regcache->raw_supply (SPARC_F0_REGNUM + i, 2215 regs + fpregmap->r_f0_offset + (i * 4)); 2216 } 2217 2218 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2219 regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); 2220 } 2221 2222 void 2223 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, 2224 const struct regcache *regcache, 2225 int regnum, void *fpregs) 2226 { 2227 gdb_byte *regs = (gdb_byte *) fpregs; 2228 int i; 2229 2230 for (i = 0; i < 32; i++) 2231 { 2232 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2233 regcache->raw_collect (SPARC_F0_REGNUM + i, 2234 regs + fpregmap->r_f0_offset + (i * 4)); 2235 } 2236 2237 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2238 regcache->raw_collect (SPARC32_FSR_REGNUM, 2239 regs + fpregmap->r_fsr_offset); 2240 } 2241 2242 2243 /* SunOS 4. */ 2244 2245 /* From <machine/reg.h>. */ 2246 const struct sparc_gregmap sparc32_sunos4_gregmap = 2247 { 2248 0 * 4, /* %psr */ 2249 1 * 4, /* %pc */ 2250 2 * 4, /* %npc */ 2251 3 * 4, /* %y */ 2252 -1, /* %wim */ 2253 -1, /* %tbr */ 2254 4 * 4, /* %g1 */ 2255 -1 /* %l0 */ 2256 }; 2257 2258 const struct sparc_fpregmap sparc32_sunos4_fpregmap = 2259 { 2260 0 * 4, /* %f0 */ 2261 33 * 4, /* %fsr */ 2262 }; 2263 2264 const struct sparc_fpregmap sparc32_bsd_fpregmap = 2265 { 2266 0 * 4, /* %f0 */ 2267 32 * 4, /* %fsr */ 2268 }; 2269 2270 void 2271 _initialize_sparc_tdep (void) 2272 { 2273 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); 2274 } 2275