1 /* Target-dependent code for Renesas Super-H, for GDB. 2 3 Copyright (C) 1993-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* Contributed by Steve Chamberlain 21 sac@cygnus.com. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "frame-base.h" 26 #include "frame-unwind.h" 27 #include "dwarf2-frame.h" 28 #include "symtab.h" 29 #include "gdbtypes.h" 30 #include "gdbcmd.h" 31 #include "gdbcore.h" 32 #include "value.h" 33 #include "dis-asm.h" 34 #include "inferior.h" 35 #include "arch-utils.h" 36 #include "regcache.h" 37 #include "target-float.h" 38 #include "osabi.h" 39 #include "reggroups.h" 40 #include "regset.h" 41 #include "objfiles.h" 42 43 #include "sh-tdep.h" 44 45 #include "elf-bfd.h" 46 #include "solib-svr4.h" 47 48 /* sh flags */ 49 #include "elf/sh.h" 50 #include "dwarf2.h" 51 /* registers numbers shared with the simulator. */ 52 #include "gdb/sim-sh.h" 53 #include <algorithm> 54 55 /* List of "set sh ..." and "show sh ..." commands. */ 56 static struct cmd_list_element *setshcmdlist = NULL; 57 static struct cmd_list_element *showshcmdlist = NULL; 58 59 static const char sh_cc_gcc[] = "gcc"; 60 static const char sh_cc_renesas[] = "renesas"; 61 static const char *const sh_cc_enum[] = { 62 sh_cc_gcc, 63 sh_cc_renesas, 64 NULL 65 }; 66 67 static const char *sh_active_calling_convention = sh_cc_gcc; 68 69 #define SH_NUM_REGS 67 70 71 struct sh_frame_cache 72 { 73 /* Base address. */ 74 CORE_ADDR base; 75 LONGEST sp_offset; 76 CORE_ADDR pc; 77 78 /* Flag showing that a frame has been created in the prologue code. */ 79 int uses_fp; 80 81 /* Saved registers. */ 82 CORE_ADDR saved_regs[SH_NUM_REGS]; 83 CORE_ADDR saved_sp; 84 }; 85 86 static int 87 sh_is_renesas_calling_convention (struct type *func_type) 88 { 89 int val = 0; 90 91 if (func_type) 92 { 93 func_type = check_typedef (func_type); 94 95 if (TYPE_CODE (func_type) == TYPE_CODE_PTR) 96 func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); 97 98 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC 99 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) 100 val = 1; 101 } 102 103 if (sh_active_calling_convention == sh_cc_renesas) 104 val = 1; 105 106 return val; 107 } 108 109 static const char * 110 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) 111 { 112 static const char *register_names[] = { 113 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 114 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 115 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 116 "", "", 117 "", "", "", "", "", "", "", "", 118 "", "", "", "", "", "", "", "", 119 "", "", 120 "", "", "", "", "", "", "", "", 121 "", "", "", "", "", "", "", "", 122 "", "", "", "", "", "", "", "", 123 }; 124 if (reg_nr < 0) 125 return NULL; 126 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 127 return NULL; 128 return register_names[reg_nr]; 129 } 130 131 static const char * 132 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) 133 { 134 static const char *register_names[] = { 135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 137 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 138 "", "", 139 "", "", "", "", "", "", "", "", 140 "", "", "", "", "", "", "", "", 141 "ssr", "spc", 142 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 143 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" 144 "", "", "", "", "", "", "", "", 145 }; 146 if (reg_nr < 0) 147 return NULL; 148 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 149 return NULL; 150 return register_names[reg_nr]; 151 } 152 153 static const char * 154 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) 155 { 156 static const char *register_names[] = { 157 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 158 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 159 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 160 "fpul", "fpscr", 161 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 162 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 163 "ssr", "spc", 164 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 165 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 166 "", "", "", "", "", "", "", "", 167 }; 168 if (reg_nr < 0) 169 return NULL; 170 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 171 return NULL; 172 return register_names[reg_nr]; 173 } 174 175 static const char * 176 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) 177 { 178 static const char *register_names[] = { 179 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 180 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 181 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 182 "fpul", "fpscr", 183 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 184 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 185 "", "", 186 "", "", "", "", "", "", "", "", 187 "", "", "", "", "", "", "", "", 188 "", "", "", "", "", "", "", "", 189 }; 190 if (reg_nr < 0) 191 return NULL; 192 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 193 return NULL; 194 return register_names[reg_nr]; 195 } 196 197 static const char * 198 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) 199 { 200 static const char *register_names[] = { 201 /* general registers 0-15 */ 202 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 203 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 204 /* 16 - 22 */ 205 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 206 /* 23, 24 */ 207 "fpul", "fpscr", 208 /* floating point registers 25 - 40 */ 209 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 210 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 211 /* 41, 42 */ 212 "", "", 213 /* 43 - 62. Banked registers. The bank number used is determined by 214 the bank register (63). */ 215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 216 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 217 "machb", "ivnb", "prb", "gbrb", "maclb", 218 /* 63: register bank number, not a real register but used to 219 communicate the register bank currently get/set. This register 220 is hidden to the user, who manipulates it using the pseudo 221 register called "bank" (67). See below. */ 222 "", 223 /* 64 - 66 */ 224 "ibcr", "ibnr", "tbr", 225 /* 67: register bank number, the user visible pseudo register. */ 226 "bank", 227 /* double precision (pseudo) 68 - 75 */ 228 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 229 }; 230 if (reg_nr < 0) 231 return NULL; 232 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 233 return NULL; 234 return register_names[reg_nr]; 235 } 236 237 static const char * 238 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 239 { 240 static const char *register_names[] = { 241 /* general registers 0-15 */ 242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 244 /* 16 - 22 */ 245 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 246 /* 23, 24 */ 247 "", "", 248 /* floating point registers 25 - 40 */ 249 "", "", "", "", "", "", "", "", 250 "", "", "", "", "", "", "", "", 251 /* 41, 42 */ 252 "", "", 253 /* 43 - 62. Banked registers. The bank number used is determined by 254 the bank register (63). */ 255 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 256 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 257 "machb", "ivnb", "prb", "gbrb", "maclb", 258 /* 63: register bank number, not a real register but used to 259 communicate the register bank currently get/set. This register 260 is hidden to the user, who manipulates it using the pseudo 261 register called "bank" (67). See below. */ 262 "", 263 /* 64 - 66 */ 264 "ibcr", "ibnr", "tbr", 265 /* 67: register bank number, the user visible pseudo register. */ 266 "bank", 267 /* double precision (pseudo) 68 - 75 */ 268 "", "", "", "", "", "", "", "", 269 }; 270 if (reg_nr < 0) 271 return NULL; 272 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 273 return NULL; 274 return register_names[reg_nr]; 275 } 276 277 static const char * 278 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 279 { 280 static const char *register_names[] = { 281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 283 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 284 "", "dsr", 285 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 286 "y0", "y1", "", "", "", "", "", "mod", 287 "", "", 288 "rs", "re", "", "", "", "", "", "", 289 "", "", "", "", "", "", "", "", 290 "", "", "", "", "", "", "", "", 291 }; 292 if (reg_nr < 0) 293 return NULL; 294 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 295 return NULL; 296 return register_names[reg_nr]; 297 } 298 299 static const char * 300 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 301 { 302 static const char *register_names[] = { 303 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 304 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 305 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 306 "", "dsr", 307 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 308 "y0", "y1", "", "", "", "", "", "mod", 309 "ssr", "spc", 310 "rs", "re", "", "", "", "", "", "", 311 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 312 "", "", "", "", "", "", "", "", 313 "", "", "", "", "", "", "", "", 314 }; 315 if (reg_nr < 0) 316 return NULL; 317 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 318 return NULL; 319 return register_names[reg_nr]; 320 } 321 322 static const char * 323 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) 324 { 325 static const char *register_names[] = { 326 /* general registers 0-15 */ 327 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 328 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 329 /* 16 - 22 */ 330 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 331 /* 23, 24 */ 332 "fpul", "fpscr", 333 /* floating point registers 25 - 40 */ 334 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 335 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 336 /* 41, 42 */ 337 "ssr", "spc", 338 /* bank 0 43 - 50 */ 339 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 340 /* bank 1 51 - 58 */ 341 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 342 /* 59 - 66 */ 343 "", "", "", "", "", "", "", "", 344 /* pseudo bank register. */ 345 "", 346 /* double precision (pseudo) 68 - 75 */ 347 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 348 /* vectors (pseudo) 76 - 79 */ 349 "fv0", "fv4", "fv8", "fv12", 350 /* FIXME: missing XF */ 351 /* FIXME: missing XD */ 352 }; 353 if (reg_nr < 0) 354 return NULL; 355 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 356 return NULL; 357 return register_names[reg_nr]; 358 } 359 360 static const char * 361 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 362 { 363 static const char *register_names[] = { 364 /* general registers 0-15 */ 365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 367 /* 16 - 22 */ 368 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 369 /* 23, 24 */ 370 "", "", 371 /* floating point registers 25 - 40 -- not for nofpu target */ 372 "", "", "", "", "", "", "", "", 373 "", "", "", "", "", "", "", "", 374 /* 41, 42 */ 375 "ssr", "spc", 376 /* bank 0 43 - 50 */ 377 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 378 /* bank 1 51 - 58 */ 379 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 380 /* 59 - 66 */ 381 "", "", "", "", "", "", "", "", 382 /* pseudo bank register. */ 383 "", 384 /* double precision (pseudo) 68 - 75 -- not for nofpu target */ 385 "", "", "", "", "", "", "", "", 386 /* vectors (pseudo) 76 - 79 -- not for nofpu target */ 387 "", "", "", "", 388 }; 389 if (reg_nr < 0) 390 return NULL; 391 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 392 return NULL; 393 return register_names[reg_nr]; 394 } 395 396 static const char * 397 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 398 { 399 static const char *register_names[] = { 400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 402 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 403 "", "dsr", 404 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 405 "y0", "y1", "", "", "", "", "", "mod", 406 "ssr", "spc", 407 "rs", "re", "", "", "", "", "", "", 408 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 409 "", "", "", "", "", "", "", "", 410 "", "", "", "", "", "", "", "", 411 }; 412 if (reg_nr < 0) 413 return NULL; 414 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 415 return NULL; 416 return register_names[reg_nr]; 417 } 418 419 /* Implement the breakpoint_kind_from_pc gdbarch method. */ 420 421 static int 422 sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 423 { 424 return 2; 425 } 426 427 /* Implement the sw_breakpoint_from_kind gdbarch method. */ 428 429 static const gdb_byte * 430 sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 431 { 432 *size = kind; 433 434 /* For remote stub targets, trapa #20 is used. */ 435 if (strcmp (target_shortname, "remote") == 0) 436 { 437 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; 438 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; 439 440 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 441 return big_remote_breakpoint; 442 else 443 return little_remote_breakpoint; 444 } 445 else 446 { 447 /* 0xc3c3 is trapa #c3, and it works in big and little endian 448 modes. */ 449 static unsigned char breakpoint[] = { 0xc3, 0xc3 }; 450 451 return breakpoint; 452 } 453 } 454 455 /* Prologue looks like 456 mov.l r14,@-r15 457 sts.l pr,@-r15 458 mov.l <regs>,@-r15 459 sub <room_for_loca_vars>,r15 460 mov r15,r14 461 462 Actually it can be more complicated than this but that's it, basically. */ 463 464 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) 465 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) 466 467 /* JSR @Rm 0100mmmm00001011 */ 468 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) 469 470 /* STS.L PR,@-r15 0100111100100010 471 r15-4-->r15, PR-->(r15) */ 472 #define IS_STS(x) ((x) == 0x4f22) 473 474 /* STS.L MACL,@-r15 0100111100010010 475 r15-4-->r15, MACL-->(r15) */ 476 #define IS_MACL_STS(x) ((x) == 0x4f12) 477 478 /* MOV.L Rm,@-r15 00101111mmmm0110 479 r15-4-->r15, Rm-->(R15) */ 480 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) 481 482 /* MOV r15,r14 0110111011110011 483 r15-->r14 */ 484 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) 485 486 /* ADD #imm,r15 01111111iiiiiiii 487 r15+imm-->r15 */ 488 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) 489 490 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) 491 #define IS_SHLL_R3(x) ((x) == 0x4300) 492 493 /* ADD r3,r15 0011111100111100 494 r15+r3-->r15 */ 495 #define IS_ADD_R3SP(x) ((x) == 0x3f3c) 496 497 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 498 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 499 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ 500 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to 501 make this entirely clear. */ 502 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ 503 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) 504 505 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ 506 #define IS_MOV_ARG_TO_REG(x) \ 507 (((x) & 0xf00f) == 0x6003 && \ 508 ((x) & 0x00f0) >= 0x0040 && \ 509 ((x) & 0x00f0) <= 0x0070) 510 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ 511 #define IS_MOV_ARG_TO_IND_R14(x) \ 512 (((x) & 0xff0f) == 0x2e02 && \ 513 ((x) & 0x00f0) >= 0x0040 && \ 514 ((x) & 0x00f0) <= 0x0070) 515 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ 516 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ 517 (((x) & 0xff00) == 0x1e00 && \ 518 ((x) & 0x00f0) >= 0x0040 && \ 519 ((x) & 0x00f0) <= 0x0070) 520 521 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ 522 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) 523 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ 524 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) 525 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ 526 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) 527 /* SUB Rn,R15 00111111nnnn1000 */ 528 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) 529 530 #define FPSCR_SZ (1 << 20) 531 532 /* The following instructions are used for epilogue testing. */ 533 #define IS_RESTORE_FP(x) ((x) == 0x6ef6) 534 #define IS_RTS(x) ((x) == 0x000b) 535 #define IS_LDS(x) ((x) == 0x4f26) 536 #define IS_MACL_LDS(x) ((x) == 0x4f16) 537 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) 538 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) 539 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) 540 541 static CORE_ADDR 542 sh_analyze_prologue (struct gdbarch *gdbarch, 543 CORE_ADDR pc, CORE_ADDR limit_pc, 544 struct sh_frame_cache *cache, ULONGEST fpscr) 545 { 546 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 547 ULONGEST inst; 548 int offset; 549 int sav_offset = 0; 550 int r3_val = 0; 551 int reg, sav_reg = -1; 552 553 cache->uses_fp = 0; 554 for (; pc < limit_pc; pc += 2) 555 { 556 inst = read_memory_unsigned_integer (pc, 2, byte_order); 557 /* See where the registers will be saved to. */ 558 if (IS_PUSH (inst)) 559 { 560 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; 561 cache->sp_offset += 4; 562 } 563 else if (IS_STS (inst)) 564 { 565 cache->saved_regs[PR_REGNUM] = cache->sp_offset; 566 cache->sp_offset += 4; 567 } 568 else if (IS_MACL_STS (inst)) 569 { 570 cache->saved_regs[MACL_REGNUM] = cache->sp_offset; 571 cache->sp_offset += 4; 572 } 573 else if (IS_MOV_R3 (inst)) 574 { 575 r3_val = ((inst & 0xff) ^ 0x80) - 0x80; 576 } 577 else if (IS_SHLL_R3 (inst)) 578 { 579 r3_val <<= 1; 580 } 581 else if (IS_ADD_R3SP (inst)) 582 { 583 cache->sp_offset += -r3_val; 584 } 585 else if (IS_ADD_IMM_SP (inst)) 586 { 587 offset = ((inst & 0xff) ^ 0x80) - 0x80; 588 cache->sp_offset -= offset; 589 } 590 else if (IS_MOVW_PCREL_TO_REG (inst)) 591 { 592 if (sav_reg < 0) 593 { 594 reg = GET_TARGET_REG (inst); 595 if (reg < 14) 596 { 597 sav_reg = reg; 598 offset = (inst & 0xff) << 1; 599 sav_offset = 600 read_memory_integer ((pc + 4) + offset, 2, byte_order); 601 } 602 } 603 } 604 else if (IS_MOVL_PCREL_TO_REG (inst)) 605 { 606 if (sav_reg < 0) 607 { 608 reg = GET_TARGET_REG (inst); 609 if (reg < 14) 610 { 611 sav_reg = reg; 612 offset = (inst & 0xff) << 2; 613 sav_offset = 614 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 615 4, byte_order); 616 } 617 } 618 } 619 else if (IS_MOVI20 (inst) 620 && (pc + 2 < limit_pc)) 621 { 622 if (sav_reg < 0) 623 { 624 reg = GET_TARGET_REG (inst); 625 if (reg < 14) 626 { 627 sav_reg = reg; 628 sav_offset = GET_SOURCE_REG (inst) << 16; 629 /* MOVI20 is a 32 bit instruction! */ 630 pc += 2; 631 sav_offset 632 |= read_memory_unsigned_integer (pc, 2, byte_order); 633 /* Now sav_offset contains an unsigned 20 bit value. 634 It must still get sign extended. */ 635 if (sav_offset & 0x00080000) 636 sav_offset |= 0xfff00000; 637 } 638 } 639 } 640 else if (IS_SUB_REG_FROM_SP (inst)) 641 { 642 reg = GET_SOURCE_REG (inst); 643 if (sav_reg > 0 && reg == sav_reg) 644 { 645 sav_reg = -1; 646 } 647 cache->sp_offset += sav_offset; 648 } 649 else if (IS_FPUSH (inst)) 650 { 651 if (fpscr & FPSCR_SZ) 652 { 653 cache->sp_offset += 8; 654 } 655 else 656 { 657 cache->sp_offset += 4; 658 } 659 } 660 else if (IS_MOV_SP_FP (inst)) 661 { 662 pc += 2; 663 /* Don't go any further than six more instructions. */ 664 limit_pc = std::min (limit_pc, pc + (2 * 6)); 665 666 cache->uses_fp = 1; 667 /* At this point, only allow argument register moves to other 668 registers or argument register moves to @(X,fp) which are 669 moving the register arguments onto the stack area allocated 670 by a former add somenumber to SP call. Don't allow moving 671 to an fp indirect address above fp + cache->sp_offset. */ 672 for (; pc < limit_pc; pc += 2) 673 { 674 inst = read_memory_integer (pc, 2, byte_order); 675 if (IS_MOV_ARG_TO_IND_R14 (inst)) 676 { 677 reg = GET_SOURCE_REG (inst); 678 if (cache->sp_offset > 0) 679 cache->saved_regs[reg] = cache->sp_offset; 680 } 681 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) 682 { 683 reg = GET_SOURCE_REG (inst); 684 offset = (inst & 0xf) * 4; 685 if (cache->sp_offset > offset) 686 cache->saved_regs[reg] = cache->sp_offset - offset; 687 } 688 else if (IS_MOV_ARG_TO_REG (inst)) 689 continue; 690 else 691 break; 692 } 693 break; 694 } 695 else if (IS_JSR (inst)) 696 { 697 /* We have found a jsr that has been scheduled into the prologue. 698 If we continue the scan and return a pc someplace after this, 699 then setting a breakpoint on this function will cause it to 700 appear to be called after the function it is calling via the 701 jsr, which will be very confusing. Most likely the next 702 instruction is going to be IS_MOV_SP_FP in the delay slot. If 703 so, note that before returning the current pc. */ 704 if (pc + 2 < limit_pc) 705 { 706 inst = read_memory_integer (pc + 2, 2, byte_order); 707 if (IS_MOV_SP_FP (inst)) 708 cache->uses_fp = 1; 709 } 710 break; 711 } 712 #if 0 /* This used to just stop when it found an instruction 713 that was not considered part of the prologue. Now, 714 we just keep going looking for likely 715 instructions. */ 716 else 717 break; 718 #endif 719 } 720 721 return pc; 722 } 723 724 /* Skip any prologue before the guts of a function. */ 725 static CORE_ADDR 726 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 727 { 728 CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; 729 struct sh_frame_cache cache; 730 731 /* See if we can determine the end of the prologue via the symbol table. 732 If so, then return either PC, or the PC after the prologue, whichever 733 is greater. */ 734 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) 735 { 736 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); 737 if (post_prologue_pc != 0) 738 return std::max (pc, post_prologue_pc); 739 } 740 741 /* Can't determine prologue from the symbol table, need to examine 742 instructions. */ 743 744 /* Find an upper limit on the function prologue using the debug 745 information. If the debug information could not be used to provide 746 that bound, then use an arbitrary large number as the upper bound. */ 747 limit_pc = skip_prologue_using_sal (gdbarch, pc); 748 if (limit_pc == 0) 749 /* Don't go any further than 28 instructions. */ 750 limit_pc = pc + (2 * 28); 751 752 /* Do not allow limit_pc to be past the function end, if we know 753 where that end is... */ 754 if (func_end_addr != 0) 755 limit_pc = std::min (limit_pc, func_end_addr); 756 757 cache.sp_offset = -4; 758 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); 759 if (cache.uses_fp) 760 pc = post_prologue_pc; 761 762 return pc; 763 } 764 765 /* The ABI says: 766 767 Aggregate types not bigger than 8 bytes that have the same size and 768 alignment as one of the integer scalar types are returned in the 769 same registers as the integer type they match. 770 771 For example, a 2-byte aligned structure with size 2 bytes has the 772 same size and alignment as a short int, and will be returned in R0. 773 A 4-byte aligned structure with size 8 bytes has the same size and 774 alignment as a long long int, and will be returned in R0 and R1. 775 776 When an aggregate type is returned in R0 and R1, R0 contains the 777 first four bytes of the aggregate, and R1 contains the 778 remainder. If the size of the aggregate type is not a multiple of 4 779 bytes, the aggregate is tail-padded up to a multiple of 4 780 bytes. The value of the padding is undefined. For little-endian 781 targets the padding will appear at the most significant end of the 782 last element, for big-endian targets the padding appears at the 783 least significant end of the last element. 784 785 All other aggregate types are returned by address. The caller 786 function passes the address of an area large enough to hold the 787 aggregate value in R2. The called function stores the result in 788 this location. 789 790 To reiterate, structs smaller than 8 bytes could also be returned 791 in memory, if they don't pass the "same size and alignment as an 792 integer type" rule. 793 794 For example, in 795 796 struct s { char c[3]; } wibble; 797 struct s foo(void) { return wibble; } 798 799 the return value from foo() will be in memory, not 800 in R0, because there is no 3-byte integer type. 801 802 Similarly, in 803 804 struct s { char c[2]; } wibble; 805 struct s foo(void) { return wibble; } 806 807 because a struct containing two chars has alignment 1, that matches 808 type char, but size 2, that matches type short. There's no integer 809 type that has alignment 1 and size 2, so the struct is returned in 810 memory. */ 811 812 static int 813 sh_use_struct_convention (int renesas_abi, struct type *type) 814 { 815 int len = TYPE_LENGTH (type); 816 int nelem = TYPE_NFIELDS (type); 817 818 /* The Renesas ABI returns aggregate types always on stack. */ 819 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT 820 || TYPE_CODE (type) == TYPE_CODE_UNION)) 821 return 1; 822 823 /* Non-power of 2 length types and types bigger than 8 bytes (which don't 824 fit in two registers anyway) use struct convention. */ 825 if (len != 1 && len != 2 && len != 4 && len != 8) 826 return 1; 827 828 /* Scalar types and aggregate types with exactly one field are aligned 829 by definition. They are returned in registers. */ 830 if (nelem <= 1) 831 return 0; 832 833 /* If the first field in the aggregate has the same length as the entire 834 aggregate type, the type is returned in registers. */ 835 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) 836 return 0; 837 838 /* If the size of the aggregate is 8 bytes and the first field is 839 of size 4 bytes its alignment is equal to long long's alignment, 840 so it's returned in registers. */ 841 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) 842 return 0; 843 844 /* Otherwise use struct convention. */ 845 return 1; 846 } 847 848 static int 849 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) 850 { 851 /* The Renesas ABI returns long longs/doubles etc. always on stack. */ 852 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) 853 return 1; 854 return sh_use_struct_convention (renesas_abi, type); 855 } 856 857 static CORE_ADDR 858 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) 859 { 860 return sp & ~3; 861 } 862 863 /* Function: push_dummy_call (formerly push_arguments) 864 Setup the function arguments for calling a function in the inferior. 865 866 On the Renesas SH architecture, there are four registers (R4 to R7) 867 which are dedicated for passing function arguments. Up to the first 868 four arguments (depending on size) may go into these registers. 869 The rest go on the stack. 870 871 MVS: Except on SH variants that have floating point registers. 872 In that case, float and double arguments are passed in the same 873 manner, but using FP registers instead of GP registers. 874 875 Arguments that are smaller than 4 bytes will still take up a whole 876 register or a whole 32-bit word on the stack, and will be 877 right-justified in the register or the stack word. This includes 878 chars, shorts, and small aggregate types. 879 880 Arguments that are larger than 4 bytes may be split between two or 881 more registers. If there are not enough registers free, an argument 882 may be passed partly in a register (or registers), and partly on the 883 stack. This includes doubles, long longs, and larger aggregates. 884 As far as I know, there is no upper limit to the size of aggregates 885 that will be passed in this way; in other words, the convention of 886 passing a pointer to a large aggregate instead of a copy is not used. 887 888 MVS: The above appears to be true for the SH variants that do not 889 have an FPU, however those that have an FPU appear to copy the 890 aggregate argument onto the stack (and not place it in registers) 891 if it is larger than 16 bytes (four GP registers). 892 893 An exceptional case exists for struct arguments (and possibly other 894 aggregates such as arrays) if the size is larger than 4 bytes but 895 not a multiple of 4 bytes. In this case the argument is never split 896 between the registers and the stack, but instead is copied in its 897 entirety onto the stack, AND also copied into as many registers as 898 there is room for. In other words, space in registers permitting, 899 two copies of the same argument are passed in. As far as I can tell, 900 only the one on the stack is used, although that may be a function 901 of the level of compiler optimization. I suspect this is a compiler 902 bug. Arguments of these odd sizes are left-justified within the 903 word (as opposed to arguments smaller than 4 bytes, which are 904 right-justified). 905 906 If the function is to return an aggregate type such as a struct, it 907 is either returned in the normal return value register R0 (if its 908 size is no greater than one byte), or else the caller must allocate 909 space into which the callee will copy the return value (if the size 910 is greater than one byte). In this case, a pointer to the return 911 value location is passed into the callee in register R2, which does 912 not displace any of the other arguments passed in via registers R4 913 to R7. */ 914 915 /* Helper function to justify value in register according to endianess. */ 916 static const gdb_byte * 917 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) 918 { 919 static gdb_byte valbuf[4]; 920 921 memset (valbuf, 0, sizeof (valbuf)); 922 if (len < 4) 923 { 924 /* value gets right-justified in the register or stack word. */ 925 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 926 memcpy (valbuf + (4 - len), value_contents (val), len); 927 else 928 memcpy (valbuf, value_contents (val), len); 929 return valbuf; 930 } 931 return value_contents (val); 932 } 933 934 /* Helper function to eval number of bytes to allocate on stack. */ 935 static CORE_ADDR 936 sh_stack_allocsize (int nargs, struct value **args) 937 { 938 int stack_alloc = 0; 939 while (nargs-- > 0) 940 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); 941 return stack_alloc; 942 } 943 944 /* Helper functions for getting the float arguments right. Registers usage 945 depends on the ABI and the endianess. The comments should enlighten how 946 it's intended to work. */ 947 948 /* This array stores which of the float arg registers are already in use. */ 949 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; 950 951 /* This function just resets the above array to "no reg used so far". */ 952 static void 953 sh_init_flt_argreg (void) 954 { 955 memset (flt_argreg_array, 0, sizeof flt_argreg_array); 956 } 957 958 /* This function returns the next register to use for float arg passing. 959 It returns either a valid value between FLOAT_ARG0_REGNUM and 960 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns 961 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. 962 963 Note that register number 0 in flt_argreg_array corresponds with the 964 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is 965 29) the parity of the register number is preserved, which is important 966 for the double register passing test (see the "argreg & 1" test below). */ 967 static int 968 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) 969 { 970 int argreg; 971 972 /* First search for the next free register. */ 973 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; 974 ++argreg) 975 if (!flt_argreg_array[argreg]) 976 break; 977 978 /* No register left? */ 979 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 980 return FLOAT_ARGLAST_REGNUM + 1; 981 982 if (len == 8) 983 { 984 /* Doubles are always starting in a even register number. */ 985 if (argreg & 1) 986 { 987 /* In gcc ABI, the skipped register is lost for further argument 988 passing now. Not so in Renesas ABI. */ 989 if (!sh_is_renesas_calling_convention (func_type)) 990 flt_argreg_array[argreg] = 1; 991 992 ++argreg; 993 994 /* No register left? */ 995 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 996 return FLOAT_ARGLAST_REGNUM + 1; 997 } 998 /* Also mark the next register as used. */ 999 flt_argreg_array[argreg + 1] = 1; 1000 } 1001 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 1002 && !sh_is_renesas_calling_convention (func_type)) 1003 { 1004 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ 1005 if (!flt_argreg_array[argreg + 1]) 1006 ++argreg; 1007 } 1008 flt_argreg_array[argreg] = 1; 1009 return FLOAT_ARG0_REGNUM + argreg; 1010 } 1011 1012 /* Helper function which figures out, if a type is treated like a float type. 1013 1014 The FPU ABIs have a special way how to treat types as float types. 1015 Structures with exactly one member, which is of type float or double, are 1016 treated exactly as the base types float or double: 1017 1018 struct sf { 1019 float f; 1020 }; 1021 1022 struct sd { 1023 double d; 1024 }; 1025 1026 are handled the same way as just 1027 1028 float f; 1029 1030 double d; 1031 1032 As a result, arguments of these struct types are pushed into floating point 1033 registers exactly as floats or doubles, using the same decision algorithm. 1034 1035 The same is valid if these types are used as function return types. The 1036 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 1037 or even using struct convention as it is for other structs. */ 1038 1039 static int 1040 sh_treat_as_flt_p (struct type *type) 1041 { 1042 /* Ordinary float types are obviously treated as float. */ 1043 if (TYPE_CODE (type) == TYPE_CODE_FLT) 1044 return 1; 1045 /* Otherwise non-struct types are not treated as float. */ 1046 if (TYPE_CODE (type) != TYPE_CODE_STRUCT) 1047 return 0; 1048 /* Otherwise structs with more than one memeber are not treated as float. */ 1049 if (TYPE_NFIELDS (type) != 1) 1050 return 0; 1051 /* Otherwise if the type of that member is float, the whole type is 1052 treated as float. */ 1053 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) 1054 return 1; 1055 /* Otherwise it's not treated as float. */ 1056 return 0; 1057 } 1058 1059 static CORE_ADDR 1060 sh_push_dummy_call_fpu (struct gdbarch *gdbarch, 1061 struct value *function, 1062 struct regcache *regcache, 1063 CORE_ADDR bp_addr, int nargs, 1064 struct value **args, 1065 CORE_ADDR sp, function_call_return_method return_method, 1066 CORE_ADDR struct_addr) 1067 { 1068 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1069 int stack_offset = 0; 1070 int argreg = ARG0_REGNUM; 1071 int flt_argreg = 0; 1072 int argnum; 1073 struct type *func_type = value_type (function); 1074 struct type *type; 1075 CORE_ADDR regval; 1076 const gdb_byte *val; 1077 int len, reg_size = 0; 1078 int pass_on_stack = 0; 1079 int treat_as_flt; 1080 int last_reg_arg = INT_MAX; 1081 1082 /* The Renesas ABI expects all varargs arguments, plus the last 1083 non-vararg argument to be on the stack, no matter how many 1084 registers have been used so far. */ 1085 if (sh_is_renesas_calling_convention (func_type) 1086 && TYPE_VARARGS (func_type)) 1087 last_reg_arg = TYPE_NFIELDS (func_type) - 2; 1088 1089 /* First force sp to a 4-byte alignment. */ 1090 sp = sh_frame_align (gdbarch, sp); 1091 1092 /* Make room on stack for args. */ 1093 sp -= sh_stack_allocsize (nargs, args); 1094 1095 /* Initialize float argument mechanism. */ 1096 sh_init_flt_argreg (); 1097 1098 /* Now load as many as possible of the first arguments into 1099 registers, and push the rest onto the stack. There are 16 bytes 1100 in four registers available. Loop thru args from first to last. */ 1101 for (argnum = 0; argnum < nargs; argnum++) 1102 { 1103 type = value_type (args[argnum]); 1104 len = TYPE_LENGTH (type); 1105 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1106 1107 /* Some decisions have to be made how various types are handled. 1108 This also differs in different ABIs. */ 1109 pass_on_stack = 0; 1110 1111 /* Find out the next register to use for a floating point value. */ 1112 treat_as_flt = sh_treat_as_flt_p (type); 1113 if (treat_as_flt) 1114 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); 1115 /* In Renesas ABI, long longs and aggregate types are always passed 1116 on stack. */ 1117 else if (sh_is_renesas_calling_convention (func_type) 1118 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) 1119 || TYPE_CODE (type) == TYPE_CODE_STRUCT 1120 || TYPE_CODE (type) == TYPE_CODE_UNION)) 1121 pass_on_stack = 1; 1122 /* In contrast to non-FPU CPUs, arguments are never split between 1123 registers and stack. If an argument doesn't fit in the remaining 1124 registers it's always pushed entirely on the stack. */ 1125 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) 1126 pass_on_stack = 1; 1127 1128 while (len > 0) 1129 { 1130 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) 1131 || (!treat_as_flt && (argreg > ARGLAST_REGNUM 1132 || pass_on_stack)) 1133 || argnum > last_reg_arg) 1134 { 1135 /* The data goes entirely on the stack, 4-byte aligned. */ 1136 reg_size = (len + 3) & ~3; 1137 write_memory (sp + stack_offset, val, reg_size); 1138 stack_offset += reg_size; 1139 } 1140 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) 1141 { 1142 /* Argument goes in a float argument register. */ 1143 reg_size = register_size (gdbarch, flt_argreg); 1144 regval = extract_unsigned_integer (val, reg_size, byte_order); 1145 /* In little endian mode, float types taking two registers 1146 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must 1147 be stored swapped in the argument registers. The below 1148 code first writes the first 32 bits in the next but one 1149 register, increments the val and len values accordingly 1150 and then proceeds as normal by writing the second 32 bits 1151 into the next register. */ 1152 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 1153 && TYPE_LENGTH (type) == 2 * reg_size) 1154 { 1155 regcache_cooked_write_unsigned (regcache, flt_argreg + 1, 1156 regval); 1157 val += reg_size; 1158 len -= reg_size; 1159 regval = extract_unsigned_integer (val, reg_size, 1160 byte_order); 1161 } 1162 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); 1163 } 1164 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) 1165 { 1166 /* there's room in a register */ 1167 reg_size = register_size (gdbarch, argreg); 1168 regval = extract_unsigned_integer (val, reg_size, byte_order); 1169 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1170 } 1171 /* Store the value one register at a time or in one step on 1172 stack. */ 1173 len -= reg_size; 1174 val += reg_size; 1175 } 1176 } 1177 1178 if (return_method == return_method_struct) 1179 { 1180 if (sh_is_renesas_calling_convention (func_type)) 1181 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1182 the stack and store the struct return address there. */ 1183 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1184 else 1185 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1186 its own dedicated register. */ 1187 regcache_cooked_write_unsigned (regcache, 1188 STRUCT_RETURN_REGNUM, struct_addr); 1189 } 1190 1191 /* Store return address. */ 1192 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1193 1194 /* Update stack pointer. */ 1195 regcache_cooked_write_unsigned (regcache, 1196 gdbarch_sp_regnum (gdbarch), sp); 1197 1198 return sp; 1199 } 1200 1201 static CORE_ADDR 1202 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, 1203 struct value *function, 1204 struct regcache *regcache, 1205 CORE_ADDR bp_addr, 1206 int nargs, struct value **args, 1207 CORE_ADDR sp, 1208 function_call_return_method return_method, 1209 CORE_ADDR struct_addr) 1210 { 1211 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1212 int stack_offset = 0; 1213 int argreg = ARG0_REGNUM; 1214 int argnum; 1215 struct type *func_type = value_type (function); 1216 struct type *type; 1217 CORE_ADDR regval; 1218 const gdb_byte *val; 1219 int len, reg_size = 0; 1220 int pass_on_stack = 0; 1221 int last_reg_arg = INT_MAX; 1222 1223 /* The Renesas ABI expects all varargs arguments, plus the last 1224 non-vararg argument to be on the stack, no matter how many 1225 registers have been used so far. */ 1226 if (sh_is_renesas_calling_convention (func_type) 1227 && TYPE_VARARGS (func_type)) 1228 last_reg_arg = TYPE_NFIELDS (func_type) - 2; 1229 1230 /* First force sp to a 4-byte alignment. */ 1231 sp = sh_frame_align (gdbarch, sp); 1232 1233 /* Make room on stack for args. */ 1234 sp -= sh_stack_allocsize (nargs, args); 1235 1236 /* Now load as many as possible of the first arguments into 1237 registers, and push the rest onto the stack. There are 16 bytes 1238 in four registers available. Loop thru args from first to last. */ 1239 for (argnum = 0; argnum < nargs; argnum++) 1240 { 1241 type = value_type (args[argnum]); 1242 len = TYPE_LENGTH (type); 1243 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1244 1245 /* Some decisions have to be made how various types are handled. 1246 This also differs in different ABIs. */ 1247 pass_on_stack = 0; 1248 /* Renesas ABI pushes doubles and long longs entirely on stack. 1249 Same goes for aggregate types. */ 1250 if (sh_is_renesas_calling_convention (func_type) 1251 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) 1252 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) 1253 || TYPE_CODE (type) == TYPE_CODE_STRUCT 1254 || TYPE_CODE (type) == TYPE_CODE_UNION)) 1255 pass_on_stack = 1; 1256 while (len > 0) 1257 { 1258 if (argreg > ARGLAST_REGNUM || pass_on_stack 1259 || argnum > last_reg_arg) 1260 { 1261 /* The remainder of the data goes entirely on the stack, 1262 4-byte aligned. */ 1263 reg_size = (len + 3) & ~3; 1264 write_memory (sp + stack_offset, val, reg_size); 1265 stack_offset += reg_size; 1266 } 1267 else if (argreg <= ARGLAST_REGNUM) 1268 { 1269 /* There's room in a register. */ 1270 reg_size = register_size (gdbarch, argreg); 1271 regval = extract_unsigned_integer (val, reg_size, byte_order); 1272 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1273 } 1274 /* Store the value reg_size bytes at a time. This means that things 1275 larger than reg_size bytes may go partly in registers and partly 1276 on the stack. */ 1277 len -= reg_size; 1278 val += reg_size; 1279 } 1280 } 1281 1282 if (return_method == return_method_struct) 1283 { 1284 if (sh_is_renesas_calling_convention (func_type)) 1285 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1286 the stack and store the struct return address there. */ 1287 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1288 else 1289 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1290 its own dedicated register. */ 1291 regcache_cooked_write_unsigned (regcache, 1292 STRUCT_RETURN_REGNUM, struct_addr); 1293 } 1294 1295 /* Store return address. */ 1296 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1297 1298 /* Update stack pointer. */ 1299 regcache_cooked_write_unsigned (regcache, 1300 gdbarch_sp_regnum (gdbarch), sp); 1301 1302 return sp; 1303 } 1304 1305 /* Find a function's return value in the appropriate registers (in 1306 regbuf), and copy it into valbuf. Extract from an array REGBUF 1307 containing the (raw) register state a function return value of type 1308 TYPE, and copy that, in virtual format, into VALBUF. */ 1309 static void 1310 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, 1311 gdb_byte *valbuf) 1312 { 1313 struct gdbarch *gdbarch = regcache->arch (); 1314 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1315 int len = TYPE_LENGTH (type); 1316 1317 if (len <= 4) 1318 { 1319 ULONGEST c; 1320 1321 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); 1322 store_unsigned_integer (valbuf, len, byte_order, c); 1323 } 1324 else if (len == 8) 1325 { 1326 int i, regnum = R0_REGNUM; 1327 for (i = 0; i < len; i += 4) 1328 regcache->raw_read (regnum++, valbuf + i); 1329 } 1330 else 1331 error (_("bad size for return value")); 1332 } 1333 1334 static void 1335 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, 1336 gdb_byte *valbuf) 1337 { 1338 struct gdbarch *gdbarch = regcache->arch (); 1339 if (sh_treat_as_flt_p (type)) 1340 { 1341 int len = TYPE_LENGTH (type); 1342 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1343 for (i = 0; i < len; i += 4) 1344 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1345 regcache->raw_read (regnum++, 1346 valbuf + len - 4 - i); 1347 else 1348 regcache->raw_read (regnum++, valbuf + i); 1349 } 1350 else 1351 sh_extract_return_value_nofpu (type, regcache, valbuf); 1352 } 1353 1354 /* Write into appropriate registers a function return value 1355 of type TYPE, given in virtual format. 1356 If the architecture is sh4 or sh3e, store a function's return value 1357 in the R0 general register or in the FP0 floating point register, 1358 depending on the type of the return value. In all the other cases 1359 the result is stored in r0, left-justified. */ 1360 static void 1361 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, 1362 const gdb_byte *valbuf) 1363 { 1364 struct gdbarch *gdbarch = regcache->arch (); 1365 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1366 ULONGEST val; 1367 int len = TYPE_LENGTH (type); 1368 1369 if (len <= 4) 1370 { 1371 val = extract_unsigned_integer (valbuf, len, byte_order); 1372 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); 1373 } 1374 else 1375 { 1376 int i, regnum = R0_REGNUM; 1377 for (i = 0; i < len; i += 4) 1378 regcache->raw_write (regnum++, valbuf + i); 1379 } 1380 } 1381 1382 static void 1383 sh_store_return_value_fpu (struct type *type, struct regcache *regcache, 1384 const gdb_byte *valbuf) 1385 { 1386 struct gdbarch *gdbarch = regcache->arch (); 1387 if (sh_treat_as_flt_p (type)) 1388 { 1389 int len = TYPE_LENGTH (type); 1390 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1391 for (i = 0; i < len; i += 4) 1392 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1393 regcache->raw_write (regnum++, 1394 valbuf + len - 4 - i); 1395 else 1396 regcache->raw_write (regnum++, valbuf + i); 1397 } 1398 else 1399 sh_store_return_value_nofpu (type, regcache, valbuf); 1400 } 1401 1402 static enum return_value_convention 1403 sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, 1404 struct type *type, struct regcache *regcache, 1405 gdb_byte *readbuf, const gdb_byte *writebuf) 1406 { 1407 struct type *func_type = function ? value_type (function) : NULL; 1408 1409 if (sh_use_struct_convention_nofpu ( 1410 sh_is_renesas_calling_convention (func_type), type)) 1411 return RETURN_VALUE_STRUCT_CONVENTION; 1412 if (writebuf) 1413 sh_store_return_value_nofpu (type, regcache, writebuf); 1414 else if (readbuf) 1415 sh_extract_return_value_nofpu (type, regcache, readbuf); 1416 return RETURN_VALUE_REGISTER_CONVENTION; 1417 } 1418 1419 static enum return_value_convention 1420 sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, 1421 struct type *type, struct regcache *regcache, 1422 gdb_byte *readbuf, const gdb_byte *writebuf) 1423 { 1424 struct type *func_type = function ? value_type (function) : NULL; 1425 1426 if (sh_use_struct_convention ( 1427 sh_is_renesas_calling_convention (func_type), type)) 1428 return RETURN_VALUE_STRUCT_CONVENTION; 1429 if (writebuf) 1430 sh_store_return_value_fpu (type, regcache, writebuf); 1431 else if (readbuf) 1432 sh_extract_return_value_fpu (type, regcache, readbuf); 1433 return RETURN_VALUE_REGISTER_CONVENTION; 1434 } 1435 1436 static struct type * 1437 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) 1438 { 1439 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1440 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1441 return builtin_type (gdbarch)->builtin_float; 1442 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1443 return builtin_type (gdbarch)->builtin_double; 1444 else 1445 return builtin_type (gdbarch)->builtin_int; 1446 } 1447 1448 /* Return the GDB type object for the "standard" data type 1449 of data in register N. */ 1450 static struct type * 1451 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) 1452 { 1453 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1454 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1455 return builtin_type (gdbarch)->builtin_float; 1456 else 1457 return builtin_type (gdbarch)->builtin_int; 1458 } 1459 1460 static struct type * 1461 sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) 1462 { 1463 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, 1464 0, high); 1465 } 1466 1467 static struct type * 1468 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) 1469 { 1470 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1471 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1472 return builtin_type (gdbarch)->builtin_float; 1473 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1474 return builtin_type (gdbarch)->builtin_double; 1475 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1476 return sh_sh4_build_float_register_type (gdbarch, 3); 1477 else 1478 return builtin_type (gdbarch)->builtin_int; 1479 } 1480 1481 static struct type * 1482 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) 1483 { 1484 return builtin_type (gdbarch)->builtin_int; 1485 } 1486 1487 /* Is a register in a reggroup? 1488 The default code in reggroup.c doesn't identify system registers, some 1489 float registers or any of the vector registers. 1490 TODO: sh2a and dsp registers. */ 1491 static int 1492 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 1493 struct reggroup *reggroup) 1494 { 1495 if (gdbarch_register_name (gdbarch, regnum) == NULL 1496 || *gdbarch_register_name (gdbarch, regnum) == '\0') 1497 return 0; 1498 1499 if (reggroup == float_reggroup 1500 && (regnum == FPUL_REGNUM 1501 || regnum == FPSCR_REGNUM)) 1502 return 1; 1503 1504 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) 1505 { 1506 if (reggroup == vector_reggroup || reggroup == float_reggroup) 1507 return 1; 1508 if (reggroup == general_reggroup) 1509 return 0; 1510 } 1511 1512 if (regnum == VBR_REGNUM 1513 || regnum == SR_REGNUM 1514 || regnum == FPSCR_REGNUM 1515 || regnum == SSR_REGNUM 1516 || regnum == SPC_REGNUM) 1517 { 1518 if (reggroup == system_reggroup) 1519 return 1; 1520 if (reggroup == general_reggroup) 1521 return 0; 1522 } 1523 1524 /* The default code can cope with any other registers. */ 1525 return default_register_reggroup_p (gdbarch, regnum, reggroup); 1526 } 1527 1528 /* On the sh4, the DRi pseudo registers are problematic if the target 1529 is little endian. When the user writes one of those registers, for 1530 instance with 'set var $dr0=1', we want the double to be stored 1531 like this: 1532 fr0 = 0x00 0x00 0xf0 0x3f 1533 fr1 = 0x00 0x00 0x00 0x00 1534 1535 This corresponds to little endian byte order & big endian word 1536 order. However if we let gdb write the register w/o conversion, it 1537 will write fr0 and fr1 this way: 1538 fr0 = 0x00 0x00 0x00 0x00 1539 fr1 = 0x00 0x00 0xf0 0x3f 1540 because it will consider fr0 and fr1 as a single LE stretch of memory. 1541 1542 To achieve what we want we must force gdb to store things in 1543 floatformat_ieee_double_littlebyte_bigword (which is defined in 1544 include/floatformat.h and libiberty/floatformat.c. 1545 1546 In case the target is big endian, there is no problem, the 1547 raw bytes will look like: 1548 fr0 = 0x3f 0xf0 0x00 0x00 1549 fr1 = 0x00 0x00 0x00 0x00 1550 1551 The other pseudo registers (the FVs) also don't pose a problem 1552 because they are stored as 4 individual FP elements. */ 1553 1554 static struct type * 1555 sh_littlebyte_bigword_type (struct gdbarch *gdbarch) 1556 { 1557 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1558 1559 if (tdep->sh_littlebyte_bigword_type == NULL) 1560 tdep->sh_littlebyte_bigword_type 1561 = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", 1562 floatformats_ieee_double_littlebyte_bigword); 1563 1564 return tdep->sh_littlebyte_bigword_type; 1565 } 1566 1567 static void 1568 sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, 1569 struct type *type, gdb_byte *from, gdb_byte *to) 1570 { 1571 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) 1572 { 1573 /* It is a no-op. */ 1574 memcpy (to, from, register_size (gdbarch, regnum)); 1575 return; 1576 } 1577 1578 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1579 target_float_convert (from, sh_littlebyte_bigword_type (gdbarch), 1580 to, type); 1581 else 1582 error 1583 ("sh_register_convert_to_virtual called with non DR register number"); 1584 } 1585 1586 static void 1587 sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, 1588 int regnum, const gdb_byte *from, gdb_byte *to) 1589 { 1590 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) 1591 { 1592 /* It is a no-op. */ 1593 memcpy (to, from, register_size (gdbarch, regnum)); 1594 return; 1595 } 1596 1597 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1598 target_float_convert (from, type, 1599 to, sh_littlebyte_bigword_type (gdbarch)); 1600 else 1601 error (_("sh_register_convert_to_raw called with non DR register number")); 1602 } 1603 1604 /* For vectors of 4 floating point registers. */ 1605 static int 1606 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) 1607 { 1608 int fp_regnum; 1609 1610 fp_regnum = gdbarch_fp0_regnum (gdbarch) 1611 + (fv_regnum - FV0_REGNUM) * 4; 1612 return fp_regnum; 1613 } 1614 1615 /* For double precision floating point registers, i.e 2 fp regs. */ 1616 static int 1617 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) 1618 { 1619 int fp_regnum; 1620 1621 fp_regnum = gdbarch_fp0_regnum (gdbarch) 1622 + (dr_regnum - DR0_REGNUM) * 2; 1623 return fp_regnum; 1624 } 1625 1626 /* Concatenate PORTIONS contiguous raw registers starting at 1627 BASE_REGNUM into BUFFER. */ 1628 1629 static enum register_status 1630 pseudo_register_read_portions (struct gdbarch *gdbarch, 1631 readable_regcache *regcache, 1632 int portions, 1633 int base_regnum, gdb_byte *buffer) 1634 { 1635 int portion; 1636 1637 for (portion = 0; portion < portions; portion++) 1638 { 1639 enum register_status status; 1640 gdb_byte *b; 1641 1642 b = buffer + register_size (gdbarch, base_regnum) * portion; 1643 status = regcache->raw_read (base_regnum + portion, b); 1644 if (status != REG_VALID) 1645 return status; 1646 } 1647 1648 return REG_VALID; 1649 } 1650 1651 static enum register_status 1652 sh_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 1653 int reg_nr, gdb_byte *buffer) 1654 { 1655 int base_regnum; 1656 enum register_status status; 1657 1658 if (reg_nr == PSEUDO_BANK_REGNUM) 1659 return regcache->raw_read (BANK_REGNUM, buffer); 1660 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1661 { 1662 /* Enough space for two float registers. */ 1663 gdb_byte temp_buffer[4 * 2]; 1664 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 1665 1666 /* Build the value in the provided buffer. */ 1667 /* Read the real regs for which this one is an alias. */ 1668 status = pseudo_register_read_portions (gdbarch, regcache, 1669 2, base_regnum, temp_buffer); 1670 if (status == REG_VALID) 1671 { 1672 /* We must pay attention to the endiannes. */ 1673 sh_register_convert_to_virtual (gdbarch, reg_nr, 1674 register_type (gdbarch, reg_nr), 1675 temp_buffer, buffer); 1676 } 1677 return status; 1678 } 1679 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1680 { 1681 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 1682 1683 /* Read the real regs for which this one is an alias. */ 1684 return pseudo_register_read_portions (gdbarch, regcache, 1685 4, base_regnum, buffer); 1686 } 1687 else 1688 gdb_assert_not_reached ("invalid pseudo register number"); 1689 } 1690 1691 static void 1692 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1693 int reg_nr, const gdb_byte *buffer) 1694 { 1695 int base_regnum, portion; 1696 1697 if (reg_nr == PSEUDO_BANK_REGNUM) 1698 { 1699 /* When the bank register is written to, the whole register bank 1700 is switched and all values in the bank registers must be read 1701 from the target/sim again. We're just invalidating the regcache 1702 so that a re-read happens next time it's necessary. */ 1703 int bregnum; 1704 1705 regcache->raw_write (BANK_REGNUM, buffer); 1706 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) 1707 regcache->invalidate (bregnum); 1708 } 1709 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1710 { 1711 /* Enough space for two float registers. */ 1712 gdb_byte temp_buffer[4 * 2]; 1713 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 1714 1715 /* We must pay attention to the endiannes. */ 1716 sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), 1717 reg_nr, buffer, temp_buffer); 1718 1719 /* Write the real regs for which this one is an alias. */ 1720 for (portion = 0; portion < 2; portion++) 1721 regcache->raw_write (base_regnum + portion, 1722 (temp_buffer 1723 + register_size (gdbarch, 1724 base_regnum) * portion)); 1725 } 1726 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1727 { 1728 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 1729 1730 /* Write the real regs for which this one is an alias. */ 1731 for (portion = 0; portion < 4; portion++) 1732 regcache->raw_write (base_regnum + portion, 1733 (buffer 1734 + register_size (gdbarch, 1735 base_regnum) * portion)); 1736 } 1737 } 1738 1739 static int 1740 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) 1741 { 1742 if (legacy_register_sim_regno (gdbarch, nr) < 0) 1743 return legacy_register_sim_regno (gdbarch, nr); 1744 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) 1745 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; 1746 if (nr == MOD_REGNUM) 1747 return SIM_SH_MOD_REGNUM; 1748 if (nr == RS_REGNUM) 1749 return SIM_SH_RS_REGNUM; 1750 if (nr == RE_REGNUM) 1751 return SIM_SH_RE_REGNUM; 1752 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) 1753 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; 1754 return nr; 1755 } 1756 1757 static int 1758 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) 1759 { 1760 switch (nr) 1761 { 1762 case TBR_REGNUM: 1763 return SIM_SH_TBR_REGNUM; 1764 case IBNR_REGNUM: 1765 return SIM_SH_IBNR_REGNUM; 1766 case IBCR_REGNUM: 1767 return SIM_SH_IBCR_REGNUM; 1768 case BANK_REGNUM: 1769 return SIM_SH_BANK_REGNUM; 1770 case MACLB_REGNUM: 1771 return SIM_SH_BANK_MACL_REGNUM; 1772 case GBRB_REGNUM: 1773 return SIM_SH_BANK_GBR_REGNUM; 1774 case PRB_REGNUM: 1775 return SIM_SH_BANK_PR_REGNUM; 1776 case IVNB_REGNUM: 1777 return SIM_SH_BANK_IVN_REGNUM; 1778 case MACHB_REGNUM: 1779 return SIM_SH_BANK_MACH_REGNUM; 1780 default: 1781 break; 1782 } 1783 return legacy_register_sim_regno (gdbarch, nr); 1784 } 1785 1786 /* Set up the register unwinding such that call-clobbered registers are 1787 not displayed in frames >0 because the true value is not certain. 1788 The 'undefined' registers will show up as 'not available' unless the 1789 CFI says otherwise. 1790 1791 This function is currently set up for SH4 and compatible only. */ 1792 1793 static void 1794 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1795 struct dwarf2_frame_state_reg *reg, 1796 struct frame_info *this_frame) 1797 { 1798 /* Mark the PC as the destination for the return address. */ 1799 if (regnum == gdbarch_pc_regnum (gdbarch)) 1800 reg->how = DWARF2_FRAME_REG_RA; 1801 1802 /* Mark the stack pointer as the call frame address. */ 1803 else if (regnum == gdbarch_sp_regnum (gdbarch)) 1804 reg->how = DWARF2_FRAME_REG_CFA; 1805 1806 /* The above was taken from the default init_reg in dwarf2-frame.c 1807 while the below is SH specific. */ 1808 1809 /* Caller save registers. */ 1810 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) 1811 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) 1812 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) 1813 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) 1814 || (regnum == MACH_REGNUM) 1815 || (regnum == MACL_REGNUM) 1816 || (regnum == FPUL_REGNUM) 1817 || (regnum == SR_REGNUM)) 1818 reg->how = DWARF2_FRAME_REG_UNDEFINED; 1819 1820 /* Callee save registers. */ 1821 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) 1822 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) 1823 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) 1824 || (regnum == FV0_REGNUM+3)) 1825 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1826 1827 /* Other registers. These are not in the ABI and may or may not 1828 mean anything in frames >0 so don't show them. */ 1829 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) 1830 || (regnum == GBR_REGNUM) 1831 || (regnum == VBR_REGNUM) 1832 || (regnum == FPSCR_REGNUM) 1833 || (regnum == SSR_REGNUM) 1834 || (regnum == SPC_REGNUM)) 1835 reg->how = DWARF2_FRAME_REG_UNDEFINED; 1836 } 1837 1838 static struct sh_frame_cache * 1839 sh_alloc_frame_cache (void) 1840 { 1841 struct sh_frame_cache *cache; 1842 int i; 1843 1844 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); 1845 1846 /* Base address. */ 1847 cache->base = 0; 1848 cache->saved_sp = 0; 1849 cache->sp_offset = 0; 1850 cache->pc = 0; 1851 1852 /* Frameless until proven otherwise. */ 1853 cache->uses_fp = 0; 1854 1855 /* Saved registers. We initialize these to -1 since zero is a valid 1856 offset (that's where fp is supposed to be stored). */ 1857 for (i = 0; i < SH_NUM_REGS; i++) 1858 { 1859 cache->saved_regs[i] = -1; 1860 } 1861 1862 return cache; 1863 } 1864 1865 static struct sh_frame_cache * 1866 sh_frame_cache (struct frame_info *this_frame, void **this_cache) 1867 { 1868 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1869 struct sh_frame_cache *cache; 1870 CORE_ADDR current_pc; 1871 int i; 1872 1873 if (*this_cache) 1874 return (struct sh_frame_cache *) *this_cache; 1875 1876 cache = sh_alloc_frame_cache (); 1877 *this_cache = cache; 1878 1879 /* In principle, for normal frames, fp holds the frame pointer, 1880 which holds the base address for the current stack frame. 1881 However, for functions that don't need it, the frame pointer is 1882 optional. For these "frameless" functions the frame pointer is 1883 actually the frame pointer of the calling frame. */ 1884 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); 1885 if (cache->base == 0) 1886 return cache; 1887 1888 cache->pc = get_frame_func (this_frame); 1889 current_pc = get_frame_pc (this_frame); 1890 if (cache->pc != 0) 1891 { 1892 ULONGEST fpscr; 1893 1894 /* Check for the existence of the FPSCR register. If it exists, 1895 fetch its value for use in prologue analysis. Passing a zero 1896 value is the best choice for architecture variants upon which 1897 there's no FPSCR register. */ 1898 if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) 1899 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); 1900 else 1901 fpscr = 0; 1902 1903 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); 1904 } 1905 1906 if (!cache->uses_fp) 1907 { 1908 /* We didn't find a valid frame, which means that CACHE->base 1909 currently holds the frame pointer for our calling frame. If 1910 we're at the start of a function, or somewhere half-way its 1911 prologue, the function's frame probably hasn't been fully 1912 setup yet. Try to reconstruct the base address for the stack 1913 frame by looking at the stack pointer. For truly "frameless" 1914 functions this might work too. */ 1915 cache->base = get_frame_register_unsigned 1916 (this_frame, gdbarch_sp_regnum (gdbarch)); 1917 } 1918 1919 /* Now that we have the base address for the stack frame we can 1920 calculate the value of sp in the calling frame. */ 1921 cache->saved_sp = cache->base + cache->sp_offset; 1922 1923 /* Adjust all the saved registers such that they contain addresses 1924 instead of offsets. */ 1925 for (i = 0; i < SH_NUM_REGS; i++) 1926 if (cache->saved_regs[i] != -1) 1927 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; 1928 1929 return cache; 1930 } 1931 1932 static struct value * 1933 sh_frame_prev_register (struct frame_info *this_frame, 1934 void **this_cache, int regnum) 1935 { 1936 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1937 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 1938 1939 gdb_assert (regnum >= 0); 1940 1941 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 1942 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 1943 1944 /* The PC of the previous frame is stored in the PR register of 1945 the current frame. Frob regnum so that we pull the value from 1946 the correct place. */ 1947 if (regnum == gdbarch_pc_regnum (gdbarch)) 1948 regnum = PR_REGNUM; 1949 1950 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) 1951 return frame_unwind_got_memory (this_frame, regnum, 1952 cache->saved_regs[regnum]); 1953 1954 return frame_unwind_got_register (this_frame, regnum, regnum); 1955 } 1956 1957 static void 1958 sh_frame_this_id (struct frame_info *this_frame, void **this_cache, 1959 struct frame_id *this_id) 1960 { 1961 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 1962 1963 /* This marks the outermost frame. */ 1964 if (cache->base == 0) 1965 return; 1966 1967 *this_id = frame_id_build (cache->saved_sp, cache->pc); 1968 } 1969 1970 static const struct frame_unwind sh_frame_unwind = { 1971 NORMAL_FRAME, 1972 default_frame_unwind_stop_reason, 1973 sh_frame_this_id, 1974 sh_frame_prev_register, 1975 NULL, 1976 default_frame_sniffer 1977 }; 1978 1979 static CORE_ADDR 1980 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1981 { 1982 return frame_unwind_register_unsigned (next_frame, 1983 gdbarch_sp_regnum (gdbarch)); 1984 } 1985 1986 static CORE_ADDR 1987 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1988 { 1989 return frame_unwind_register_unsigned (next_frame, 1990 gdbarch_pc_regnum (gdbarch)); 1991 } 1992 1993 static struct frame_id 1994 sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1995 { 1996 CORE_ADDR sp = get_frame_register_unsigned (this_frame, 1997 gdbarch_sp_regnum (gdbarch)); 1998 return frame_id_build (sp, get_frame_pc (this_frame)); 1999 } 2000 2001 static CORE_ADDR 2002 sh_frame_base_address (struct frame_info *this_frame, void **this_cache) 2003 { 2004 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 2005 2006 return cache->base; 2007 } 2008 2009 static const struct frame_base sh_frame_base = { 2010 &sh_frame_unwind, 2011 sh_frame_base_address, 2012 sh_frame_base_address, 2013 sh_frame_base_address 2014 }; 2015 2016 static struct sh_frame_cache * 2017 sh_make_stub_cache (struct frame_info *this_frame) 2018 { 2019 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2020 struct sh_frame_cache *cache; 2021 2022 cache = sh_alloc_frame_cache (); 2023 2024 cache->saved_sp 2025 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 2026 2027 return cache; 2028 } 2029 2030 static void 2031 sh_stub_this_id (struct frame_info *this_frame, void **this_cache, 2032 struct frame_id *this_id) 2033 { 2034 struct sh_frame_cache *cache; 2035 2036 if (*this_cache == NULL) 2037 *this_cache = sh_make_stub_cache (this_frame); 2038 cache = (struct sh_frame_cache *) *this_cache; 2039 2040 *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); 2041 } 2042 2043 static int 2044 sh_stub_unwind_sniffer (const struct frame_unwind *self, 2045 struct frame_info *this_frame, 2046 void **this_prologue_cache) 2047 { 2048 CORE_ADDR addr_in_block; 2049 2050 addr_in_block = get_frame_address_in_block (this_frame); 2051 if (in_plt_section (addr_in_block)) 2052 return 1; 2053 2054 return 0; 2055 } 2056 2057 static const struct frame_unwind sh_stub_unwind = 2058 { 2059 NORMAL_FRAME, 2060 default_frame_unwind_stop_reason, 2061 sh_stub_this_id, 2062 sh_frame_prev_register, 2063 NULL, 2064 sh_stub_unwind_sniffer 2065 }; 2066 2067 /* Implement the stack_frame_destroyed_p gdbarch method. 2068 2069 The epilogue is defined here as the area at the end of a function, 2070 either on the `ret' instruction itself or after an instruction which 2071 destroys the function's stack frame. */ 2072 2073 static int 2074 sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2075 { 2076 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2077 CORE_ADDR func_addr = 0, func_end = 0; 2078 2079 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 2080 { 2081 ULONGEST inst; 2082 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes 2083 for a nop and some fixed data (e.g. big offsets) which are 2084 unfortunately also treated as part of the function (which 2085 means, they are below func_end. */ 2086 CORE_ADDR addr = func_end - 28; 2087 if (addr < func_addr + 4) 2088 addr = func_addr + 4; 2089 if (pc < addr) 2090 return 0; 2091 2092 /* First search forward until hitting an rts. */ 2093 while (addr < func_end 2094 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) 2095 addr += 2; 2096 if (addr >= func_end) 2097 return 0; 2098 2099 /* At this point we should find a mov.l @r15+,r14 instruction, 2100 either before or after the rts. If not, then the function has 2101 probably no "normal" epilogue and we bail out here. */ 2102 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2103 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, 2104 byte_order))) 2105 addr -= 2; 2106 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, 2107 byte_order))) 2108 return 0; 2109 2110 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2111 2112 /* Step over possible lds.l @r15+,macl. */ 2113 if (IS_MACL_LDS (inst)) 2114 { 2115 addr -= 2; 2116 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2117 } 2118 2119 /* Step over possible lds.l @r15+,pr. */ 2120 if (IS_LDS (inst)) 2121 { 2122 addr -= 2; 2123 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2124 } 2125 2126 /* Step over possible mov r14,r15. */ 2127 if (IS_MOV_FP_SP (inst)) 2128 { 2129 addr -= 2; 2130 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2131 } 2132 2133 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 2134 instructions. */ 2135 while (addr > func_addr + 4 2136 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) 2137 { 2138 addr -= 2; 2139 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2140 } 2141 2142 /* On SH2a check if the previous instruction was perhaps a MOVI20. 2143 That's allowed for the epilogue. */ 2144 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a 2145 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) 2146 && addr > func_addr + 6 2147 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, 2148 byte_order))) 2149 addr -= 4; 2150 2151 if (pc >= addr) 2152 return 1; 2153 } 2154 return 0; 2155 } 2156 2157 2158 /* Supply register REGNUM from the buffer specified by REGS and LEN 2159 in the register set REGSET to register cache REGCACHE. 2160 REGTABLE specifies where each register can be found in REGS. 2161 If REGNUM is -1, do this for all registers in REGSET. */ 2162 2163 void 2164 sh_corefile_supply_regset (const struct regset *regset, 2165 struct regcache *regcache, 2166 int regnum, const void *regs, size_t len) 2167 { 2168 struct gdbarch *gdbarch = regcache->arch (); 2169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2170 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2171 ? tdep->core_gregmap 2172 : tdep->core_fpregmap); 2173 int i; 2174 2175 for (i = 0; regmap[i].regnum != -1; i++) 2176 { 2177 if ((regnum == -1 || regnum == regmap[i].regnum) 2178 && regmap[i].offset + 4 <= len) 2179 regcache->raw_supply 2180 (regmap[i].regnum, (char *) regs + regmap[i].offset); 2181 } 2182 } 2183 2184 /* Collect register REGNUM in the register set REGSET from register cache 2185 REGCACHE into the buffer specified by REGS and LEN. 2186 REGTABLE specifies where each register can be found in REGS. 2187 If REGNUM is -1, do this for all registers in REGSET. */ 2188 2189 void 2190 sh_corefile_collect_regset (const struct regset *regset, 2191 const struct regcache *regcache, 2192 int regnum, void *regs, size_t len) 2193 { 2194 struct gdbarch *gdbarch = regcache->arch (); 2195 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2196 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2197 ? tdep->core_gregmap 2198 : tdep->core_fpregmap); 2199 int i; 2200 2201 for (i = 0; regmap[i].regnum != -1; i++) 2202 { 2203 if ((regnum == -1 || regnum == regmap[i].regnum) 2204 && regmap[i].offset + 4 <= len) 2205 regcache->raw_collect (regmap[i].regnum, 2206 (char *)regs + regmap[i].offset); 2207 } 2208 } 2209 2210 /* The following two regsets have the same contents, so it is tempting to 2211 unify them, but they are distiguished by their address, so don't. */ 2212 2213 const struct regset sh_corefile_gregset = 2214 { 2215 NULL, 2216 sh_corefile_supply_regset, 2217 sh_corefile_collect_regset 2218 }; 2219 2220 static const struct regset sh_corefile_fpregset = 2221 { 2222 NULL, 2223 sh_corefile_supply_regset, 2224 sh_corefile_collect_regset 2225 }; 2226 2227 static void 2228 sh_iterate_over_regset_sections (struct gdbarch *gdbarch, 2229 iterate_over_regset_sections_cb *cb, 2230 void *cb_data, 2231 const struct regcache *regcache) 2232 { 2233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2234 2235 if (tdep->core_gregmap != NULL) 2236 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, 2237 &sh_corefile_gregset, NULL, cb_data); 2238 2239 if (tdep->core_fpregmap != NULL) 2240 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, 2241 &sh_corefile_fpregset, NULL, cb_data); 2242 } 2243 2244 /* This is the implementation of gdbarch method 2245 return_in_first_hidden_param_p. */ 2246 2247 static int 2248 sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, 2249 struct type *type) 2250 { 2251 return 0; 2252 } 2253 2254 2255 2256 static struct gdbarch * 2257 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2258 { 2259 struct gdbarch *gdbarch; 2260 struct gdbarch_tdep *tdep; 2261 2262 /* If there is already a candidate, use it. */ 2263 arches = gdbarch_list_lookup_by_info (arches, &info); 2264 if (arches != NULL) 2265 return arches->gdbarch; 2266 2267 /* None found, create a new architecture from the information 2268 provided. */ 2269 tdep = XCNEW (struct gdbarch_tdep); 2270 gdbarch = gdbarch_alloc (&info, tdep); 2271 2272 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2273 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2274 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2275 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2276 2277 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2278 set_gdbarch_wchar_signed (gdbarch, 0); 2279 2280 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2281 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2282 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2283 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2284 2285 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); 2286 set_gdbarch_sp_regnum (gdbarch, 15); 2287 set_gdbarch_pc_regnum (gdbarch, 16); 2288 set_gdbarch_fp0_regnum (gdbarch, -1); 2289 set_gdbarch_num_pseudo_regs (gdbarch, 0); 2290 2291 set_gdbarch_register_type (gdbarch, sh_default_register_type); 2292 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); 2293 2294 set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc); 2295 set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind); 2296 2297 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); 2298 2299 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); 2300 2301 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); 2302 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2303 2304 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); 2305 set_gdbarch_return_in_first_hidden_param_p (gdbarch, 2306 sh_return_in_first_hidden_param_p); 2307 2308 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2309 2310 set_gdbarch_frame_align (gdbarch, sh_frame_align); 2311 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); 2312 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); 2313 set_gdbarch_dummy_id (gdbarch, sh_dummy_id); 2314 frame_base_set_default (gdbarch, &sh_frame_base); 2315 2316 set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p); 2317 2318 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); 2319 2320 set_gdbarch_iterate_over_regset_sections 2321 (gdbarch, sh_iterate_over_regset_sections); 2322 2323 switch (info.bfd_arch_info->mach) 2324 { 2325 case bfd_mach_sh: 2326 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2327 break; 2328 2329 case bfd_mach_sh2: 2330 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2331 break; 2332 2333 case bfd_mach_sh2e: 2334 /* doubles on sh2e and sh3e are actually 4 byte. */ 2335 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2336 set_gdbarch_double_format (gdbarch, floatformats_ieee_single); 2337 2338 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); 2339 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2340 set_gdbarch_fp0_regnum (gdbarch, 25); 2341 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2342 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2343 break; 2344 2345 case bfd_mach_sh2a: 2346 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); 2347 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); 2348 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2349 2350 set_gdbarch_fp0_regnum (gdbarch, 25); 2351 set_gdbarch_num_pseudo_regs (gdbarch, 9); 2352 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2353 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2354 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2355 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2356 break; 2357 2358 case bfd_mach_sh2a_nofpu: 2359 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); 2360 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2361 2362 set_gdbarch_num_pseudo_regs (gdbarch, 1); 2363 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2364 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2365 break; 2366 2367 case bfd_mach_sh_dsp: 2368 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); 2369 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2370 break; 2371 2372 case bfd_mach_sh3: 2373 case bfd_mach_sh3_nommu: 2374 case bfd_mach_sh2a_nofpu_or_sh3_nommu: 2375 set_gdbarch_register_name (gdbarch, sh_sh3_register_name); 2376 break; 2377 2378 case bfd_mach_sh3e: 2379 case bfd_mach_sh2a_or_sh3e: 2380 /* doubles on sh2e and sh3e are actually 4 byte. */ 2381 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2382 set_gdbarch_double_format (gdbarch, floatformats_ieee_single); 2383 2384 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); 2385 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2386 set_gdbarch_fp0_regnum (gdbarch, 25); 2387 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2388 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2389 break; 2390 2391 case bfd_mach_sh3_dsp: 2392 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); 2393 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2394 break; 2395 2396 case bfd_mach_sh4: 2397 case bfd_mach_sh4a: 2398 case bfd_mach_sh2a_or_sh4: 2399 set_gdbarch_register_name (gdbarch, sh_sh4_register_name); 2400 set_gdbarch_register_type (gdbarch, sh_sh4_register_type); 2401 set_gdbarch_fp0_regnum (gdbarch, 25); 2402 set_gdbarch_num_pseudo_regs (gdbarch, 13); 2403 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2404 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2405 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2406 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2407 break; 2408 2409 case bfd_mach_sh4_nofpu: 2410 case bfd_mach_sh4a_nofpu: 2411 case bfd_mach_sh4_nommu_nofpu: 2412 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: 2413 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); 2414 break; 2415 2416 case bfd_mach_sh4al_dsp: 2417 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); 2418 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2419 break; 2420 2421 default: 2422 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2423 break; 2424 } 2425 2426 /* Hook in ABI-specific overrides, if they have been registered. */ 2427 gdbarch_init_osabi (info, gdbarch); 2428 2429 dwarf2_append_unwinders (gdbarch); 2430 frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); 2431 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); 2432 2433 return gdbarch; 2434 } 2435 2436 static void 2437 show_sh_command (const char *args, int from_tty) 2438 { 2439 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); 2440 } 2441 2442 static void 2443 set_sh_command (const char *args, int from_tty) 2444 { 2445 printf_unfiltered 2446 ("\"set sh\" must be followed by an appropriate subcommand.\n"); 2447 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); 2448 } 2449 2450 void 2451 _initialize_sh_tdep (void) 2452 { 2453 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); 2454 2455 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", 2456 &setshcmdlist, "set sh ", 0, &setlist); 2457 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", 2458 &showshcmdlist, "show sh ", 0, &showlist); 2459 2460 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, 2461 &sh_active_calling_convention, 2462 _("Set calling convention used when calling target " 2463 "functions from GDB."), 2464 _("Show calling convention used when calling target " 2465 "functions from GDB."), 2466 _("gcc - Use GCC calling convention (default).\n" 2467 "renesas - Enforce Renesas calling convention."), 2468 NULL, NULL, 2469 &setshcmdlist, &showshcmdlist); 2470 } 2471