1 /* Target-dependent code for the S12Z, for the GDB. 2 Copyright (C) 2018-2020 Free Software Foundation, Inc. 3 4 This file is part of GDB. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19 /* Much of this file is shamelessly copied from or1k-tdep.c and others. */ 20 21 #include "defs.h" 22 23 #include "arch-utils.h" 24 #include "dwarf2/frame.h" 25 #include "gdbsupport/errors.h" 26 #include "frame-unwind.h" 27 #include "gdbcore.h" 28 #include "gdbcmd.h" 29 #include "inferior.h" 30 #include "opcode/s12z.h" 31 #include "trad-frame.h" 32 #include "remote.h" 33 #include "opcodes/s12z-opc.h" 34 35 /* Two of the registers included in S12Z_N_REGISTERS are 36 the CCH and CCL "registers" which are just views into 37 the CCW register. */ 38 #define N_PHYSICAL_REGISTERS (S12Z_N_REGISTERS - 2) 39 40 41 /* A permutation of all the physical registers. Indexing this array 42 with an integer from gdb's internal representation will return the 43 register enum. */ 44 static const int reg_perm[N_PHYSICAL_REGISTERS] = 45 { 46 REG_D0, 47 REG_D1, 48 REG_D2, 49 REG_D3, 50 REG_D4, 51 REG_D5, 52 REG_D6, 53 REG_D7, 54 REG_X, 55 REG_Y, 56 REG_S, 57 REG_P, 58 REG_CCW 59 }; 60 61 /* The inverse of the above permutation. Indexing this 62 array with a register enum (e.g. REG_D2) will return the register 63 number in gdb's internal representation. */ 64 static const int inv_reg_perm[N_PHYSICAL_REGISTERS] = 65 { 66 2, 3, 4, 5, /* d2, d3, d4, d5 */ 67 0, 1, /* d0, d1 */ 68 6, 7, /* d6, d7 */ 69 8, 9, 10, 11, 12 /* x, y, s, p, ccw */ 70 }; 71 72 /* Return the name of the register REGNUM. */ 73 static const char * 74 s12z_register_name (struct gdbarch *gdbarch, int regnum) 75 { 76 /* Registers is declared in opcodes/s12z.h. */ 77 return registers[reg_perm[regnum]].name; 78 } 79 80 static CORE_ADDR 81 s12z_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 82 { 83 CORE_ADDR start_pc = 0; 84 85 if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) 86 { 87 CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc); 88 89 if (prologue_end != 0) 90 return prologue_end; 91 } 92 93 warning (_("%s Failed to find end of prologue PC = %08x"), 94 __FUNCTION__, (unsigned int) pc); 95 96 return pc; 97 } 98 99 static struct type * 100 s12z_register_type (struct gdbarch *gdbarch, int reg_nr) 101 { 102 switch (registers[reg_perm[reg_nr]].bytes) 103 { 104 case 1: 105 return builtin_type (gdbarch)->builtin_uint8; 106 case 2: 107 return builtin_type (gdbarch)->builtin_uint16; 108 case 3: 109 return builtin_type (gdbarch)->builtin_uint24; 110 case 4: 111 return builtin_type (gdbarch)->builtin_uint32; 112 default: 113 return builtin_type (gdbarch)->builtin_uint32; 114 } 115 return builtin_type (gdbarch)->builtin_int0; 116 } 117 118 119 static int 120 s12z_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int num) 121 { 122 switch (num) 123 { 124 case 15: return REG_S; 125 case 7: return REG_X; 126 case 8: return REG_Y; 127 case 42: return REG_D0; 128 case 43: return REG_D1; 129 case 44: return REG_D2; 130 case 45: return REG_D3; 131 case 46: return REG_D4; 132 case 47: return REG_D5; 133 case 48: return REG_D6; 134 case 49: return REG_D7; 135 } 136 return -1; 137 } 138 139 140 /* Support functions for frame handling. */ 141 142 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */ 143 144 static int ATTRIBUTE_PRINTF (2, 3) 145 s12z_fprintf_disasm (void *stream, const char *format, ...) 146 { 147 return 0; 148 } 149 150 static struct disassemble_info 151 s12z_disassemble_info (struct gdbarch *gdbarch) 152 { 153 struct disassemble_info di; 154 init_disassemble_info (&di, &null_stream, s12z_fprintf_disasm); 155 di.arch = gdbarch_bfd_arch_info (gdbarch)->arch; 156 di.mach = gdbarch_bfd_arch_info (gdbarch)->mach; 157 di.endian = gdbarch_byte_order (gdbarch); 158 di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr, 159 unsigned int len, struct disassemble_info *info) 160 { 161 return target_read_code (memaddr, myaddr, len); 162 }; 163 return di; 164 } 165 166 167 /* A struct (based on mem_read_abstraction_base) to read memory 168 through the disassemble_info API. */ 169 struct mem_read_abstraction 170 { 171 struct mem_read_abstraction_base base; /* The parent struct. */ 172 bfd_vma memaddr; /* Where to read from. */ 173 struct disassemble_info* info; /* The disassembler to use for reading. */ 174 }; 175 176 /* Advance the reader by one byte. */ 177 static void 178 advance (struct mem_read_abstraction_base *b) 179 { 180 struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; 181 mra->memaddr++; 182 } 183 184 /* Return the current position of the reader. */ 185 static bfd_vma 186 posn (struct mem_read_abstraction_base *b) 187 { 188 struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; 189 return mra->memaddr; 190 } 191 192 /* Read the N bytes at OFFSET using B. The bytes read are stored in BYTES. 193 It is the caller's responsibility to ensure that this is of at least N 194 in size. */ 195 static int 196 abstract_read_memory (struct mem_read_abstraction_base *b, 197 int offset, 198 size_t n, bfd_byte *bytes) 199 { 200 struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b; 201 202 int status = 203 (*mra->info->read_memory_func) (mra->memaddr + offset, 204 bytes, n, mra->info); 205 206 if (status != 0) 207 { 208 (*mra->info->memory_error_func) (status, mra->memaddr, mra->info); 209 return -1; 210 } 211 212 return 0; 213 } 214 215 216 /* Return the stack adjustment caused by a push or pull instruction. */ 217 static int 218 push_pull_get_stack_adjustment (int n_operands, 219 struct operand *const *operands) 220 { 221 int stack_adjustment = 0; 222 gdb_assert (n_operands > 0); 223 if (operands[0]->cl == OPND_CL_REGISTER_ALL) 224 stack_adjustment = 26; /* All the regs are involved. */ 225 else if (operands[0]->cl == OPND_CL_REGISTER_ALL16) 226 stack_adjustment = 4 * 2; /* All four 16 bit regs are involved. */ 227 else 228 for (int i = 0; i < n_operands; ++i) 229 { 230 if (operands[i]->cl != OPND_CL_REGISTER) 231 continue; /* I don't think this can ever happen. */ 232 const struct register_operand *op 233 = (const struct register_operand *) operands[i]; 234 switch (op->reg) 235 { 236 case REG_X: 237 case REG_Y: 238 stack_adjustment += 3; 239 break; 240 case REG_D7: 241 case REG_D6: 242 stack_adjustment += 4; 243 break; 244 case REG_D2: 245 case REG_D3: 246 case REG_D4: 247 case REG_D5: 248 stack_adjustment += 2; 249 break; 250 case REG_D0: 251 case REG_D1: 252 case REG_CCL: 253 case REG_CCH: 254 stack_adjustment += 1; 255 break; 256 default: 257 gdb_assert_not_reached ("Invalid register in push/pull operation."); 258 break; 259 } 260 } 261 return stack_adjustment; 262 } 263 264 /* Initialize a prologue cache. */ 265 266 static struct trad_frame_cache * 267 s12z_frame_cache (struct frame_info *this_frame, void **prologue_cache) 268 { 269 struct trad_frame_cache *info; 270 271 CORE_ADDR this_sp; 272 CORE_ADDR this_sp_for_id; 273 274 CORE_ADDR start_addr; 275 CORE_ADDR end_addr; 276 277 /* Nothing to do if we already have this info. */ 278 if (NULL != *prologue_cache) 279 return (struct trad_frame_cache *) *prologue_cache; 280 281 /* Get a new prologue cache and populate it with default values. */ 282 info = trad_frame_cache_zalloc (this_frame); 283 *prologue_cache = info; 284 285 /* Find the start address of this function (which is a normal frame, even 286 if the next frame is the sentinel frame) and the end of its prologue. */ 287 CORE_ADDR this_pc = get_frame_pc (this_frame); 288 struct gdbarch *gdbarch = get_frame_arch (this_frame); 289 find_pc_partial_function (this_pc, NULL, &start_addr, NULL); 290 291 /* Get the stack pointer if we have one (if there's no process executing 292 yet we won't have a frame. */ 293 this_sp = (NULL == this_frame) ? 0 : 294 get_frame_register_unsigned (this_frame, REG_S); 295 296 /* Return early if GDB couldn't find the function. */ 297 if (start_addr == 0) 298 { 299 warning (_("Couldn't find function including address %s SP is %s"), 300 paddress (gdbarch, this_pc), 301 paddress (gdbarch, this_sp)); 302 303 /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB 304 crashing right at the beginning. Build the frame ID as best we 305 can. */ 306 trad_frame_set_id (info, frame_id_build (this_sp, this_pc)); 307 308 return info; 309 } 310 311 /* The default frame base of this frame (for ID purposes only - frame 312 base is an overloaded term) is its stack pointer. For now we use the 313 value of the SP register in this frame. However if the PC is in the 314 prologue of this frame, before the SP has been set up, then the value 315 will actually be that of the prev frame, and we'll need to adjust it 316 later. */ 317 trad_frame_set_this_base (info, this_sp); 318 this_sp_for_id = this_sp; 319 320 /* We should only examine code that is in the prologue. This is all code 321 up to (but not including) end_addr. We should only populate the cache 322 while the address is up to (but not including) the PC or end_addr, 323 whichever is first. */ 324 end_addr = s12z_skip_prologue (gdbarch, start_addr); 325 326 /* All the following analysis only occurs if we are in the prologue and 327 have executed the code. Check we have a sane prologue size, and if 328 zero we are frameless and can give up here. */ 329 if (end_addr < start_addr) 330 error (_("end addr %s is less than start addr %s"), 331 paddress (gdbarch, end_addr), paddress (gdbarch, start_addr)); 332 333 CORE_ADDR addr = start_addr; /* Where we have got to? */ 334 int frame_size = 0; 335 int saved_frame_size = 0; 336 337 struct disassemble_info di = s12z_disassemble_info (gdbarch); 338 339 340 struct mem_read_abstraction mra; 341 mra.base.read = (int (*)(mem_read_abstraction_base*, 342 int, size_t, bfd_byte*)) abstract_read_memory; 343 mra.base.advance = advance ; 344 mra.base.posn = posn; 345 mra.info = &di; 346 347 while (this_pc > addr) 348 { 349 enum optr optr = OP_INVALID; 350 short osize; 351 int n_operands = 0; 352 struct operand *operands[6]; 353 mra.memaddr = addr; 354 int n_bytes = 355 decode_s12z (&optr, &osize, &n_operands, operands, 356 (mem_read_abstraction_base *) &mra); 357 358 switch (optr) 359 { 360 case OP_tbNE: 361 case OP_tbPL: 362 case OP_tbMI: 363 case OP_tbGT: 364 case OP_tbLE: 365 case OP_dbNE: 366 case OP_dbEQ: 367 case OP_dbPL: 368 case OP_dbMI: 369 case OP_dbGT: 370 case OP_dbLE: 371 /* Conditional Branches. If any of these are encountered, then 372 it is likely that a RTS will terminate it. So we need to save 373 the frame size so it can be restored. */ 374 saved_frame_size = frame_size; 375 break; 376 case OP_rts: 377 /* Restore the frame size from a previously saved value. */ 378 frame_size = saved_frame_size; 379 break; 380 case OP_push: 381 frame_size += push_pull_get_stack_adjustment (n_operands, operands); 382 break; 383 case OP_pull: 384 frame_size -= push_pull_get_stack_adjustment (n_operands, operands); 385 break; 386 case OP_lea: 387 if (operands[0]->cl == OPND_CL_REGISTER) 388 { 389 int reg = ((struct register_operand *) (operands[0]))->reg; 390 if ((reg == REG_S) && (operands[1]->cl == OPND_CL_MEMORY)) 391 { 392 const struct memory_operand *mo 393 = (const struct memory_operand * ) operands[1]; 394 if (mo->n_regs == 1 && !mo->indirect 395 && mo->regs[0] == REG_S 396 && mo->mutation == OPND_RM_NONE) 397 { 398 /* LEA S, (xxx, S) -- Decrement the stack. This is 399 almost certainly the start of a frame. */ 400 int simm = (signed char) mo->base_offset; 401 frame_size -= simm; 402 } 403 } 404 } 405 break; 406 default: 407 break; 408 } 409 addr += n_bytes; 410 for (int o = 0; o < n_operands; ++o) 411 free (operands[o]); 412 } 413 414 /* If the PC has not actually got to this point, then the frame 415 base will be wrong, and we adjust it. */ 416 if (this_pc < addr) 417 { 418 /* Only do if executing. */ 419 if (0 != this_sp) 420 { 421 this_sp_for_id = this_sp - frame_size; 422 trad_frame_set_this_base (info, this_sp_for_id); 423 } 424 trad_frame_set_reg_value (info, REG_S, this_sp + 3); 425 trad_frame_set_reg_addr (info, REG_P, this_sp); 426 } 427 else 428 { 429 gdb_assert (this_sp == this_sp_for_id); 430 /* The stack pointer of the prev frame is frame_size greater 431 than the stack pointer of this frame plus one address 432 size (caused by the JSR or BSR). */ 433 trad_frame_set_reg_value (info, REG_S, 434 this_sp + frame_size + 3); 435 trad_frame_set_reg_addr (info, REG_P, this_sp + frame_size); 436 } 437 438 439 /* Build the frame ID. */ 440 trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr)); 441 442 return info; 443 } 444 445 /* Implement the this_id function for the stub unwinder. */ 446 static void 447 s12z_frame_this_id (struct frame_info *this_frame, 448 void **prologue_cache, struct frame_id *this_id) 449 { 450 struct trad_frame_cache *info = s12z_frame_cache (this_frame, 451 prologue_cache); 452 453 trad_frame_get_id (info, this_id); 454 } 455 456 457 /* Implement the prev_register function for the stub unwinder. */ 458 static struct value * 459 s12z_frame_prev_register (struct frame_info *this_frame, 460 void **prologue_cache, int regnum) 461 { 462 struct trad_frame_cache *info = s12z_frame_cache (this_frame, 463 prologue_cache); 464 465 return trad_frame_get_register (info, this_frame, regnum); 466 } 467 468 /* Data structures for the normal prologue-analysis-based unwinder. */ 469 static const struct frame_unwind s12z_frame_unwind = { 470 NORMAL_FRAME, 471 default_frame_unwind_stop_reason, 472 s12z_frame_this_id, 473 s12z_frame_prev_register, 474 NULL, 475 default_frame_sniffer, 476 NULL, 477 }; 478 479 480 constexpr gdb_byte s12z_break_insn[] = {0x00}; 481 482 typedef BP_MANIPULATION (s12z_break_insn) s12z_breakpoint; 483 484 struct gdbarch_tdep 485 { 486 }; 487 488 /* A vector of human readable characters representing the 489 bits in the CCW register. Unused bits are represented as '-'. 490 Lowest significant bit comes first. */ 491 static const char ccw_bits[] = 492 { 493 'C', /* Carry */ 494 'V', /* Two's Complement Overflow */ 495 'Z', /* Zero */ 496 'N', /* Negative */ 497 'I', /* Interrupt */ 498 '-', 499 'X', /* Non-Maskable Interrupt */ 500 'S', /* STOP Disable */ 501 '0', /* Interrupt priority level */ 502 '0', /* ditto */ 503 '0', /* ditto */ 504 '-', 505 '-', 506 '-', 507 '-', 508 'U' /* User/Supervisor State. */ 509 }; 510 511 /* Print a human readable representation of the CCW register. 512 For example: "u----000SX-Inzvc" corresponds to the value 513 0xD0. */ 514 static void 515 s12z_print_ccw_info (struct gdbarch *gdbarch, 516 struct ui_file *file, 517 struct frame_info *frame, 518 int reg) 519 { 520 struct value *v = value_of_register (reg, frame); 521 const char *name = gdbarch_register_name (gdbarch, reg); 522 uint32_t ccw = value_as_long (v); 523 fputs_filtered (name, file); 524 size_t len = strlen (name); 525 const int stop_1 = 15; 526 const int stop_2 = 17; 527 for (int i = 0; i < stop_1 - len; ++i) 528 fputc_filtered (' ', file); 529 fprintf_filtered (file, "0x%04x", ccw); 530 for (int i = 0; i < stop_2 - len; ++i) 531 fputc_filtered (' ', file); 532 for (int b = 15; b >= 0; --b) 533 { 534 if (ccw & (0x1u << b)) 535 { 536 if (ccw_bits[b] == 0) 537 fputc_filtered ('1', file); 538 else 539 fputc_filtered (ccw_bits[b], file); 540 } 541 else 542 fputc_filtered (tolower (ccw_bits[b]), file); 543 } 544 fputc_filtered ('\n', file); 545 } 546 547 static void 548 s12z_print_registers_info (struct gdbarch *gdbarch, 549 struct ui_file *file, 550 struct frame_info *frame, 551 int regnum, int print_all) 552 { 553 const int numregs = (gdbarch_num_regs (gdbarch) 554 + gdbarch_num_pseudo_regs (gdbarch)); 555 556 if (regnum == -1) 557 { 558 for (int reg = 0; reg < numregs; reg++) 559 { 560 if (REG_CCW == reg_perm[reg]) 561 { 562 s12z_print_ccw_info (gdbarch, file, frame, reg); 563 continue; 564 } 565 default_print_registers_info (gdbarch, file, frame, reg, print_all); 566 } 567 } 568 else if (REG_CCW == reg_perm[regnum]) 569 s12z_print_ccw_info (gdbarch, file, frame, regnum); 570 else 571 default_print_registers_info (gdbarch, file, frame, regnum, print_all); 572 } 573 574 575 576 577 static void 578 s12z_extract_return_value (struct type *type, struct regcache *regcache, 579 void *valbuf) 580 { 581 int reg = -1; 582 583 switch (TYPE_LENGTH (type)) 584 { 585 case 0: /* Nothing to do */ 586 return; 587 588 case 1: 589 reg = REG_D0; 590 break; 591 592 case 2: 593 reg = REG_D2; 594 break; 595 596 case 3: 597 reg = REG_X; 598 break; 599 600 case 4: 601 reg = REG_D6; 602 break; 603 604 default: 605 error (_("bad size for return value")); 606 return; 607 } 608 609 regcache->cooked_read (inv_reg_perm[reg], (gdb_byte *) valbuf); 610 } 611 612 static enum return_value_convention 613 s12z_return_value (struct gdbarch *gdbarch, struct value *function, 614 struct type *type, struct regcache *regcache, 615 gdb_byte *readbuf, const gdb_byte *writebuf) 616 { 617 if (type->code () == TYPE_CODE_STRUCT 618 || type->code () == TYPE_CODE_UNION 619 || type->code () == TYPE_CODE_ARRAY 620 || TYPE_LENGTH (type) > 4) 621 return RETURN_VALUE_STRUCT_CONVENTION; 622 623 if (readbuf) 624 s12z_extract_return_value (type, regcache, readbuf); 625 626 return RETURN_VALUE_REGISTER_CONVENTION; 627 } 628 629 630 static void 631 show_bdccsr_command (const char *args, int from_tty) 632 { 633 struct string_file output; 634 target_rcmd ("bdccsr", &output); 635 636 printf_unfiltered ("The current BDCCSR value is %s\n", output.string().c_str()); 637 } 638 639 static struct gdbarch * 640 s12z_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 641 { 642 struct gdbarch_tdep *tdep = XNEW (struct gdbarch_tdep); 643 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); 644 645 add_cmd ("bdccsr", class_support, show_bdccsr_command, 646 _("Show the current value of the microcontroller's BDCCSR."), 647 &maintenanceinfolist); 648 649 /* Target data types. */ 650 set_gdbarch_short_bit (gdbarch, 16); 651 set_gdbarch_int_bit (gdbarch, 16); 652 set_gdbarch_long_bit (gdbarch, 32); 653 set_gdbarch_long_long_bit (gdbarch, 32); 654 set_gdbarch_ptr_bit (gdbarch, 24); 655 set_gdbarch_addr_bit (gdbarch, 24); 656 set_gdbarch_char_signed (gdbarch, 0); 657 658 set_gdbarch_ps_regnum (gdbarch, REG_CCW); 659 set_gdbarch_pc_regnum (gdbarch, REG_P); 660 set_gdbarch_sp_regnum (gdbarch, REG_S); 661 662 663 set_gdbarch_print_registers_info (gdbarch, s12z_print_registers_info); 664 665 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 666 s12z_breakpoint::kind_from_pc); 667 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 668 s12z_breakpoint::bp_from_kind); 669 670 set_gdbarch_num_regs (gdbarch, N_PHYSICAL_REGISTERS); 671 set_gdbarch_register_name (gdbarch, s12z_register_name); 672 set_gdbarch_skip_prologue (gdbarch, s12z_skip_prologue); 673 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 674 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, s12z_dwarf_reg_to_regnum); 675 676 set_gdbarch_register_type (gdbarch, s12z_register_type); 677 678 frame_unwind_append_unwinder (gdbarch, &s12z_frame_unwind); 679 /* Currently, the only known producer for this architecture, produces buggy 680 dwarf CFI. So don't append a dwarf unwinder until the situation is 681 better understood. */ 682 683 set_gdbarch_return_value (gdbarch, s12z_return_value); 684 685 return gdbarch; 686 } 687 688 void _initialize_s12z_tdep (); 689 void 690 _initialize_s12z_tdep () 691 { 692 gdbarch_register (bfd_arch_s12z, s12z_gdbarch_init, NULL); 693 } 694