1 /* Target-dependent code for FreeBSD on RISC-V processors. 2 Copyright (C) 2018-2020 Free Software Foundation, Inc. 3 4 This file is part of GDB. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19 #include "defs.h" 20 #include "fbsd-tdep.h" 21 #include "osabi.h" 22 #include "riscv-tdep.h" 23 #include "riscv-fbsd-tdep.h" 24 #include "solib-svr4.h" 25 #include "target.h" 26 #include "trad-frame.h" 27 #include "tramp-frame.h" 28 #include "gdbarch.h" 29 #include "inferior.h" 30 31 /* Register maps. */ 32 33 static const struct regcache_map_entry riscv_fbsd_gregmap[] = 34 { 35 { 1, RISCV_RA_REGNUM, 0 }, 36 { 1, RISCV_SP_REGNUM, 0 }, 37 { 1, RISCV_GP_REGNUM, 0 }, 38 { 1, RISCV_TP_REGNUM, 0 }, 39 { 3, 5, 0 }, /* t0 - t2 */ 40 { 4, 28, 0 }, /* t3 - t6 */ 41 { 2, RISCV_FP_REGNUM, 0 }, /* s0 - s1 */ 42 { 10, 18, 0 }, /* s2 - s11 */ 43 { 8, RISCV_A0_REGNUM, 0 }, /* a0 - a7 */ 44 { 1, RISCV_PC_REGNUM, 0 }, 45 { 1, RISCV_CSR_SSTATUS_REGNUM, 0 }, 46 { 0 } 47 }; 48 49 static const struct regcache_map_entry riscv_fbsd_fpregmap[] = 50 { 51 { 32, RISCV_FIRST_FP_REGNUM, 16 }, 52 { 1, RISCV_CSR_FCSR_REGNUM, 8 }, 53 { 0 } 54 }; 55 56 /* Supply the general-purpose registers stored in GREGS to REGCACHE. 57 This function only exists to supply the always-zero x0 in addition 58 to the registers in GREGS. */ 59 60 static void 61 riscv_fbsd_supply_gregset (const struct regset *regset, 62 struct regcache *regcache, int regnum, 63 const void *gregs, size_t len) 64 { 65 regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len); 66 if (regnum == -1 || regnum == RISCV_ZERO_REGNUM) 67 regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM); 68 } 69 70 /* Register set definitions. */ 71 72 const struct regset riscv_fbsd_gregset = 73 { 74 riscv_fbsd_gregmap, 75 riscv_fbsd_supply_gregset, regcache_collect_regset 76 }; 77 78 const struct regset riscv_fbsd_fpregset = 79 { 80 riscv_fbsd_fpregmap, 81 regcache_supply_regset, regcache_collect_regset 82 }; 83 84 /* Implement the "iterate_over_regset_sections" gdbarch method. */ 85 86 static void 87 riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, 88 iterate_over_regset_sections_cb *cb, 89 void *cb_data, 90 const struct regcache *regcache) 91 { 92 cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch), 93 RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch), 94 &riscv_fbsd_gregset, NULL, cb_data); 95 cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET, 96 &riscv_fbsd_fpregset, NULL, cb_data); 97 } 98 99 /* In a signal frame, sp points to a 'struct sigframe' which is 100 defined as: 101 102 struct sigframe { 103 siginfo_t sf_si; 104 ucontext_t sf_uc; 105 }; 106 107 ucontext_t is defined as: 108 109 struct __ucontext { 110 sigset_t uc_sigmask; 111 mcontext_t uc_mcontext; 112 ... 113 }; 114 115 The mcontext_t contains the general purpose register set followed 116 by the floating point register set. The floating point register 117 set is only valid if the _MC_FP_VALID flag is set in mc_flags. */ 118 119 #define RISCV_SIGFRAME_UCONTEXT_OFFSET 80 120 #define RISCV_UCONTEXT_MCONTEXT_OFFSET 16 121 #define RISCV_MCONTEXT_FLAG_FP_VALID 0x1 122 123 /* Implement the "init" method of struct tramp_frame. */ 124 125 static void 126 riscv_fbsd_sigframe_init (const struct tramp_frame *self, 127 struct frame_info *this_frame, 128 struct trad_frame_cache *this_cache, 129 CORE_ADDR func) 130 { 131 struct gdbarch *gdbarch = get_frame_arch (this_frame); 132 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 133 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM); 134 CORE_ADDR mcontext_addr 135 = (sp 136 + RISCV_SIGFRAME_UCONTEXT_OFFSET 137 + RISCV_UCONTEXT_MCONTEXT_OFFSET); 138 gdb_byte buf[4]; 139 140 trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr, 141 RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch)); 142 143 CORE_ADDR fpregs_addr 144 = mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch); 145 CORE_ADDR fp_flags_addr 146 = fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET; 147 if (target_read_memory (fp_flags_addr, buf, 4) == 0 148 && (extract_unsigned_integer (buf, 4, byte_order) 149 & RISCV_MCONTEXT_FLAG_FP_VALID)) 150 trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr, 151 RISCV_FBSD_SIZEOF_FPREGSET); 152 153 trad_frame_set_id (this_cache, frame_id_build (sp, func)); 154 } 155 156 /* RISC-V supports 16-bit instructions ("C") as well as 32-bit 157 instructions. The signal trampoline on FreeBSD uses a mix of 158 these, but tramp_frame assumes a fixed instruction size. To cope, 159 claim that all instructions are 16 bits and use two "slots" for 160 32-bit instructions. */ 161 162 static const struct tramp_frame riscv_fbsd_sigframe = 163 { 164 SIGTRAMP_FRAME, 165 2, 166 { 167 {0x850a, ULONGEST_MAX}, /* mov a0, sp */ 168 {0x0513, ULONGEST_MAX}, /* addi a0, a0, #SF_UC */ 169 {0x0505, ULONGEST_MAX}, 170 {0x0293, ULONGEST_MAX}, /* li t0, #SYS_sigreturn */ 171 {0x1a10, ULONGEST_MAX}, 172 {0x0073, ULONGEST_MAX}, /* ecall */ 173 {0x0000, ULONGEST_MAX}, 174 {TRAMP_SENTINEL_INSN, ULONGEST_MAX} 175 }, 176 riscv_fbsd_sigframe_init 177 }; 178 179 /* Implement the "get_thread_local_address" gdbarch method. */ 180 181 static CORE_ADDR 182 riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid, 183 CORE_ADDR lm_addr, CORE_ADDR offset) 184 { 185 struct regcache *regcache; 186 187 regcache = get_thread_arch_regcache (current_inferior ()->process_target (), 188 ptid, gdbarch); 189 190 target_fetch_registers (regcache, RISCV_TP_REGNUM); 191 192 ULONGEST tp; 193 if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID) 194 error (_("Unable to fetch %%tp")); 195 196 /* %tp points to the end of the TCB which contains two pointers. 197 The first pointer in the TCB points to the DTV array. */ 198 CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2; 199 return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset); 200 } 201 202 /* Implement the 'init_osabi' method of struct gdb_osabi_handler. */ 203 204 static void 205 riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 206 { 207 /* Generic FreeBSD support. */ 208 fbsd_init_abi (info, gdbarch); 209 210 set_gdbarch_software_single_step (gdbarch, riscv_software_single_step); 211 212 set_solib_svr4_fetch_link_map_offsets (gdbarch, 213 (riscv_isa_xlen (gdbarch) == 4 214 ? svr4_ilp32_fetch_link_map_offsets 215 : svr4_lp64_fetch_link_map_offsets)); 216 217 tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe); 218 219 set_gdbarch_iterate_over_regset_sections 220 (gdbarch, riscv_fbsd_iterate_over_regset_sections); 221 222 set_gdbarch_fetch_tls_load_module_address (gdbarch, 223 svr4_fetch_objfile_link_map); 224 set_gdbarch_get_thread_local_address (gdbarch, 225 riscv_fbsd_get_thread_local_address); 226 } 227 228 void _initialize_riscv_fbsd_tdep (); 229 void 230 _initialize_riscv_fbsd_tdep () 231 { 232 gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD, 233 riscv_fbsd_init_abi); 234 } 235