1 /* Target-machine dependent code for Nios II, for GDB. 2 Copyright (C) 2012-2016 Free Software Foundation, Inc. 3 Contributed by Peter Brookes (pbrookes@altera.com) 4 and Andrew Draper (adraper@altera.com). 5 Contributed by Mentor Graphics, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "frame.h" 24 #include "frame-unwind.h" 25 #include "frame-base.h" 26 #include "trad-frame.h" 27 #include "dwarf2-frame.h" 28 #include "symtab.h" 29 #include "inferior.h" 30 #include "gdbtypes.h" 31 #include "gdbcore.h" 32 #include "gdbcmd.h" 33 #include "osabi.h" 34 #include "target.h" 35 #include "dis-asm.h" 36 #include "regcache.h" 37 #include "value.h" 38 #include "symfile.h" 39 #include "arch-utils.h" 40 #include "floatformat.h" 41 #include "infcall.h" 42 #include "regset.h" 43 #include "target-descriptions.h" 44 45 /* To get entry_point_address. */ 46 #include "objfiles.h" 47 48 /* Nios II specific header. */ 49 #include "nios2-tdep.h" 50 51 #include "features/nios2.c" 52 53 /* Control debugging information emitted in this file. */ 54 55 static int nios2_debug = 0; 56 57 /* The following structures are used in the cache for prologue 58 analysis; see the reg_value and reg_saved tables in 59 struct nios2_unwind_cache, respectively. */ 60 61 /* struct reg_value is used to record that a register has the same value 62 as reg at the given offset from the start of a function. */ 63 64 struct reg_value 65 { 66 int reg; 67 unsigned int offset; 68 }; 69 70 /* struct reg_saved is used to record that a register value has been saved at 71 basereg + addr, for basereg >= 0. If basereg < 0, that indicates 72 that the register is not known to have been saved. Note that when 73 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0), 74 addr is an absolute address. */ 75 76 struct reg_saved 77 { 78 int basereg; 79 CORE_ADDR addr; 80 }; 81 82 struct nios2_unwind_cache 83 { 84 /* The frame's base, optionally used by the high-level debug info. */ 85 CORE_ADDR base; 86 87 /* The previous frame's inner most stack address. Used as this 88 frame ID's stack_addr. */ 89 CORE_ADDR cfa; 90 91 /* The address of the first instruction in this function. */ 92 CORE_ADDR pc; 93 94 /* Which register holds the return address for the frame. */ 95 int return_regnum; 96 97 /* Table indicating what changes have been made to each register. */ 98 struct reg_value reg_value[NIOS2_NUM_REGS]; 99 100 /* Table indicating where each register has been saved. */ 101 struct reg_saved reg_saved[NIOS2_NUM_REGS]; 102 }; 103 104 105 /* This array is a mapping from Dwarf-2 register numbering to GDB's. */ 106 107 static int nios2_dwarf2gdb_regno_map[] = 108 { 109 0, 1, 2, 3, 110 4, 5, 6, 7, 111 8, 9, 10, 11, 112 12, 13, 14, 15, 113 16, 17, 18, 19, 114 20, 21, 22, 23, 115 24, 25, 116 NIOS2_GP_REGNUM, /* 26 */ 117 NIOS2_SP_REGNUM, /* 27 */ 118 NIOS2_FP_REGNUM, /* 28 */ 119 NIOS2_EA_REGNUM, /* 29 */ 120 NIOS2_BA_REGNUM, /* 30 */ 121 NIOS2_RA_REGNUM, /* 31 */ 122 NIOS2_PC_REGNUM, /* 32 */ 123 NIOS2_STATUS_REGNUM, /* 33 */ 124 NIOS2_ESTATUS_REGNUM, /* 34 */ 125 NIOS2_BSTATUS_REGNUM, /* 35 */ 126 NIOS2_IENABLE_REGNUM, /* 36 */ 127 NIOS2_IPENDING_REGNUM, /* 37 */ 128 NIOS2_CPUID_REGNUM, /* 38 */ 129 39, /* CTL6 */ /* 39 */ 130 NIOS2_EXCEPTION_REGNUM, /* 40 */ 131 NIOS2_PTEADDR_REGNUM, /* 41 */ 132 NIOS2_TLBACC_REGNUM, /* 42 */ 133 NIOS2_TLBMISC_REGNUM, /* 43 */ 134 NIOS2_ECCINJ_REGNUM, /* 44 */ 135 NIOS2_BADADDR_REGNUM, /* 45 */ 136 NIOS2_CONFIG_REGNUM, /* 46 */ 137 NIOS2_MPUBASE_REGNUM, /* 47 */ 138 NIOS2_MPUACC_REGNUM /* 48 */ 139 }; 140 141 gdb_static_assert (ARRAY_SIZE (nios2_dwarf2gdb_regno_map) == NIOS2_NUM_REGS); 142 143 /* Implement the dwarf2_reg_to_regnum gdbarch method. */ 144 145 static int 146 nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) 147 { 148 if (dw_reg < 0 || dw_reg >= NIOS2_NUM_REGS) 149 return -1; 150 151 return nios2_dwarf2gdb_regno_map[dw_reg]; 152 } 153 154 /* Canonical names for the 49 registers. */ 155 156 static const char *const nios2_reg_names[NIOS2_NUM_REGS] = 157 { 158 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", 159 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 160 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 161 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra", 162 "pc", 163 "status", "estatus", "bstatus", "ienable", 164 "ipending", "cpuid", "ctl6", "exception", 165 "pteaddr", "tlbacc", "tlbmisc", "eccinj", 166 "badaddr", "config", "mpubase", "mpuacc" 167 }; 168 169 /* Implement the register_name gdbarch method. */ 170 171 static const char * 172 nios2_register_name (struct gdbarch *gdbarch, int regno) 173 { 174 /* Use mnemonic aliases for GPRs. */ 175 if (regno >= 0 && regno < NIOS2_NUM_REGS) 176 return nios2_reg_names[regno]; 177 else 178 return tdesc_register_name (gdbarch, regno); 179 } 180 181 /* Implement the register_type gdbarch method. */ 182 183 static struct type * 184 nios2_register_type (struct gdbarch *gdbarch, int regno) 185 { 186 /* If the XML description has register information, use that to 187 determine the register type. */ 188 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 189 return tdesc_register_type (gdbarch, regno); 190 191 if (regno == NIOS2_PC_REGNUM) 192 return builtin_type (gdbarch)->builtin_func_ptr; 193 else if (regno == NIOS2_SP_REGNUM) 194 return builtin_type (gdbarch)->builtin_data_ptr; 195 else 196 return builtin_type (gdbarch)->builtin_uint32; 197 } 198 199 /* Given a return value in REGCACHE with a type VALTYPE, 200 extract and copy its value into VALBUF. */ 201 202 static void 203 nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype, 204 struct regcache *regcache, gdb_byte *valbuf) 205 { 206 int len = TYPE_LENGTH (valtype); 207 208 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 209 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 210 regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); 211 else 212 { 213 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 214 + register_size (gdbarch, NIOS2_R3_REGNUM))); 215 regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); 216 regcache_cooked_read (regcache, NIOS2_R3_REGNUM, valbuf + 4); 217 } 218 } 219 220 /* Write into appropriate registers a function return value 221 of type TYPE, given in virtual format. */ 222 223 static void 224 nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype, 225 struct regcache *regcache, const gdb_byte *valbuf) 226 { 227 int len = TYPE_LENGTH (valtype); 228 229 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 230 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 231 regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); 232 else 233 { 234 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 235 + register_size (gdbarch, NIOS2_R3_REGNUM))); 236 regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); 237 regcache_cooked_write (regcache, NIOS2_R3_REGNUM, valbuf + 4); 238 } 239 } 240 241 242 /* Set up the default values of the registers. */ 243 244 static void 245 nios2_setup_default (struct nios2_unwind_cache *cache) 246 { 247 int i; 248 249 for (i = 0; i < NIOS2_NUM_REGS; i++) 250 { 251 /* All registers start off holding their previous values. */ 252 cache->reg_value[i].reg = i; 253 cache->reg_value[i].offset = 0; 254 255 /* All registers start off not saved. */ 256 cache->reg_saved[i].basereg = -1; 257 cache->reg_saved[i].addr = 0; 258 } 259 } 260 261 /* Initialize the unwind cache. */ 262 263 static void 264 nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc) 265 { 266 cache->base = 0; 267 cache->cfa = 0; 268 cache->pc = pc; 269 cache->return_regnum = NIOS2_RA_REGNUM; 270 nios2_setup_default (cache); 271 } 272 273 /* Read and identify an instruction at PC. If INSNP is non-null, 274 store the instruction word into that location. Return the opcode 275 pointer or NULL if the memory couldn't be read or disassembled. */ 276 277 static const struct nios2_opcode * 278 nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc, 279 unsigned int *insnp) 280 { 281 LONGEST memword; 282 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 283 unsigned int insn; 284 285 if (mach == bfd_mach_nios2r2) 286 { 287 if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 288 BFD_ENDIAN_LITTLE, &memword) 289 && !safe_read_memory_integer (pc, NIOS2_CDX_OPCODE_SIZE, 290 BFD_ENDIAN_LITTLE, &memword)) 291 return NULL; 292 } 293 else if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 294 gdbarch_byte_order (gdbarch), &memword)) 295 return NULL; 296 297 insn = (unsigned int) memword; 298 if (insnp) 299 *insnp = insn; 300 return nios2_find_opcode_hash (insn, mach); 301 } 302 303 304 /* Match and disassemble an ADD-type instruction, with 3 register operands. 305 Returns true on success, and fills in the operand pointers. */ 306 307 static int 308 nios2_match_add (uint32_t insn, const struct nios2_opcode *op, 309 unsigned long mach, int *ra, int *rb, int *rc) 310 { 311 int is_r2 = (mach == bfd_mach_nios2r2); 312 313 if (!is_r2 && (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV)) 314 { 315 *ra = GET_IW_R_A (insn); 316 *rb = GET_IW_R_B (insn); 317 *rc = GET_IW_R_C (insn); 318 return 1; 319 } 320 else if (!is_r2) 321 return 0; 322 else if (op->match == MATCH_R2_ADD || op->match == MATCH_R2_MOV) 323 { 324 *ra = GET_IW_F3X6L5_A (insn); 325 *rb = GET_IW_F3X6L5_B (insn); 326 *rc = GET_IW_F3X6L5_C (insn); 327 return 1; 328 } 329 else if (op->match == MATCH_R2_ADD_N) 330 { 331 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 332 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 333 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 334 return 1; 335 } 336 else if (op->match == MATCH_R2_MOV_N) 337 { 338 *ra = GET_IW_F2_A (insn); 339 *rb = 0; 340 *rc = GET_IW_F2_B (insn); 341 return 1; 342 } 343 return 0; 344 } 345 346 /* Match and disassemble a SUB-type instruction, with 3 register operands. 347 Returns true on success, and fills in the operand pointers. */ 348 349 static int 350 nios2_match_sub (uint32_t insn, const struct nios2_opcode *op, 351 unsigned long mach, int *ra, int *rb, int *rc) 352 { 353 int is_r2 = (mach == bfd_mach_nios2r2); 354 355 if (!is_r2 && op->match == MATCH_R1_SUB) 356 { 357 *ra = GET_IW_R_A (insn); 358 *rb = GET_IW_R_B (insn); 359 *rc = GET_IW_R_C (insn); 360 return 1; 361 } 362 else if (!is_r2) 363 return 0; 364 else if (op->match == MATCH_R2_SUB) 365 { 366 *ra = GET_IW_F3X6L5_A (insn); 367 *rb = GET_IW_F3X6L5_B (insn); 368 *rc = GET_IW_F3X6L5_C (insn); 369 return 1; 370 } 371 else if (op->match == MATCH_R2_SUB_N) 372 { 373 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 374 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 375 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 376 return 1; 377 } 378 return 0; 379 } 380 381 /* Match and disassemble an ADDI-type instruction, with 2 register operands 382 and one immediate operand. 383 Returns true on success, and fills in the operand pointers. */ 384 385 static int 386 nios2_match_addi (uint32_t insn, const struct nios2_opcode *op, 387 unsigned long mach, int *ra, int *rb, int *imm) 388 { 389 int is_r2 = (mach == bfd_mach_nios2r2); 390 391 if (!is_r2 && op->match == MATCH_R1_ADDI) 392 { 393 *ra = GET_IW_I_A (insn); 394 *rb = GET_IW_I_B (insn); 395 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 396 return 1; 397 } 398 else if (!is_r2) 399 return 0; 400 else if (op->match == MATCH_R2_ADDI) 401 { 402 *ra = GET_IW_F2I16_A (insn); 403 *rb = GET_IW_F2I16_B (insn); 404 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 405 return 1; 406 } 407 else if (op->match == MATCH_R2_ADDI_N || op->match == MATCH_R2_SUBI_N) 408 { 409 *ra = nios2_r2_reg3_mappings[GET_IW_T2X1I3_A3 (insn)]; 410 *rb = nios2_r2_reg3_mappings[GET_IW_T2X1I3_B3 (insn)]; 411 *imm = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (insn)]; 412 if (op->match == MATCH_R2_SUBI_N) 413 *imm = - (*imm); 414 return 1; 415 } 416 else if (op->match == MATCH_R2_SPADDI_N) 417 { 418 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 419 *rb = NIOS2_SP_REGNUM; 420 *imm = GET_IW_T1I7_IMM7 (insn) << 2; 421 return 1; 422 } 423 else if (op->match == MATCH_R2_SPINCI_N || op->match == MATCH_R2_SPDECI_N) 424 { 425 *ra = NIOS2_SP_REGNUM; 426 *rb = NIOS2_SP_REGNUM; 427 *imm = GET_IW_X1I7_IMM7 (insn) << 2; 428 if (op->match == MATCH_R2_SPDECI_N) 429 *imm = - (*imm); 430 return 1; 431 } 432 return 0; 433 } 434 435 /* Match and disassemble an ORHI-type instruction, with 2 register operands 436 and one unsigned immediate operand. 437 Returns true on success, and fills in the operand pointers. */ 438 439 static int 440 nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op, 441 unsigned long mach, int *ra, int *rb, unsigned int *uimm) 442 { 443 int is_r2 = (mach == bfd_mach_nios2r2); 444 445 if (!is_r2 && op->match == MATCH_R1_ORHI) 446 { 447 *ra = GET_IW_I_A (insn); 448 *rb = GET_IW_I_B (insn); 449 *uimm = GET_IW_I_IMM16 (insn); 450 return 1; 451 } 452 else if (!is_r2) 453 return 0; 454 else if (op->match == MATCH_R2_ORHI) 455 { 456 *ra = GET_IW_F2I16_A (insn); 457 *rb = GET_IW_F2I16_B (insn); 458 *uimm = GET_IW_F2I16_IMM16 (insn); 459 return 1; 460 } 461 return 0; 462 } 463 464 /* Match and disassemble a STW-type instruction, with 2 register operands 465 and one immediate operand. 466 Returns true on success, and fills in the operand pointers. */ 467 468 static int 469 nios2_match_stw (uint32_t insn, const struct nios2_opcode *op, 470 unsigned long mach, int *ra, int *rb, int *imm) 471 { 472 int is_r2 = (mach == bfd_mach_nios2r2); 473 474 if (!is_r2 && (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO)) 475 { 476 *ra = GET_IW_I_A (insn); 477 *rb = GET_IW_I_B (insn); 478 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 479 return 1; 480 } 481 else if (!is_r2) 482 return 0; 483 else if (op->match == MATCH_R2_STW) 484 { 485 *ra = GET_IW_F2I16_A (insn); 486 *rb = GET_IW_F2I16_B (insn); 487 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 488 return 1; 489 } 490 else if (op->match == MATCH_R2_STWIO) 491 { 492 *ra = GET_IW_F2X4I12_A (insn); 493 *rb = GET_IW_F2X4I12_B (insn); 494 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 495 return 1; 496 } 497 else if (op->match == MATCH_R2_STW_N) 498 { 499 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 500 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 501 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 502 return 1; 503 } 504 else if (op->match == MATCH_R2_STWSP_N) 505 { 506 *ra = NIOS2_SP_REGNUM; 507 *rb = GET_IW_F1I5_B (insn); 508 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 509 return 1; 510 } 511 else if (op->match == MATCH_R2_STWZ_N) 512 { 513 *ra = nios2_r2_reg3_mappings[GET_IW_T1X1I6_A3 (insn)]; 514 *rb = 0; 515 *imm = GET_IW_T1X1I6_IMM6 (insn) << 2; 516 return 1; 517 } 518 return 0; 519 } 520 521 /* Match and disassemble a LDW-type instruction, with 2 register operands 522 and one immediate operand. 523 Returns true on success, and fills in the operand pointers. */ 524 525 static int 526 nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op, 527 unsigned long mach, int *ra, int *rb, int *imm) 528 { 529 int is_r2 = (mach == bfd_mach_nios2r2); 530 531 if (!is_r2 && (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO)) 532 { 533 *ra = GET_IW_I_A (insn); 534 *rb = GET_IW_I_B (insn); 535 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 536 return 1; 537 } 538 else if (!is_r2) 539 return 0; 540 else if (op->match == MATCH_R2_LDW) 541 { 542 *ra = GET_IW_F2I16_A (insn); 543 *rb = GET_IW_F2I16_B (insn); 544 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 545 return 1; 546 } 547 else if (op->match == MATCH_R2_LDWIO) 548 { 549 *ra = GET_IW_F2X4I12_A (insn); 550 *rb = GET_IW_F2X4I12_B (insn); 551 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 552 return 1; 553 } 554 else if (op->match == MATCH_R2_LDW_N) 555 { 556 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 557 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 558 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 559 return 1; 560 } 561 else if (op->match == MATCH_R2_LDWSP_N) 562 { 563 *ra = NIOS2_SP_REGNUM; 564 *rb = GET_IW_F1I5_B (insn); 565 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 566 return 1; 567 } 568 return 0; 569 } 570 571 /* Match and disassemble a RDCTL instruction, with 2 register operands. 572 Returns true on success, and fills in the operand pointers. */ 573 574 static int 575 nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op, 576 unsigned long mach, int *ra, int *rc) 577 { 578 int is_r2 = (mach == bfd_mach_nios2r2); 579 580 if (!is_r2 && (op->match == MATCH_R1_RDCTL)) 581 { 582 *ra = GET_IW_R_IMM5 (insn); 583 *rc = GET_IW_R_C (insn); 584 return 1; 585 } 586 else if (!is_r2) 587 return 0; 588 else if (op->match == MATCH_R2_RDCTL) 589 { 590 *ra = GET_IW_F3X6L5_IMM5 (insn); 591 *rc = GET_IW_F3X6L5_C (insn); 592 return 1; 593 } 594 return 0; 595 } 596 597 /* Match and disassemble a PUSH.N or STWM instruction. 598 Returns true on success, and fills in the operand pointers. */ 599 600 static int 601 nios2_match_stwm (uint32_t insn, const struct nios2_opcode *op, 602 unsigned long mach, unsigned int *reglist, 603 int *ra, int *imm, int *wb, int *id) 604 { 605 int is_r2 = (mach == bfd_mach_nios2r2); 606 607 if (!is_r2) 608 return 0; 609 else if (op->match == MATCH_R2_PUSH_N) 610 { 611 *reglist = 1 << 31; 612 if (GET_IW_L5I4X1_FP (insn)) 613 *reglist |= (1 << 28); 614 if (GET_IW_L5I4X1_CS (insn)) 615 { 616 int val = GET_IW_L5I4X1_REGRANGE (insn); 617 *reglist |= nios2_r2_reg_range_mappings[val]; 618 } 619 *ra = NIOS2_SP_REGNUM; 620 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 621 *wb = 1; 622 *id = 0; 623 return 1; 624 } 625 else if (op->match == MATCH_R2_STWM) 626 { 627 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 628 if (GET_IW_F1X4L17_RS (insn)) 629 { 630 *reglist = ((rawmask << 14) & 0x00ffc000); 631 if (rawmask & (1 << 10)) 632 *reglist |= (1 << 28); 633 if (rawmask & (1 << 11)) 634 *reglist |= (1 << 31); 635 } 636 else 637 *reglist = rawmask << 2; 638 *ra = GET_IW_F1X4L17_A (insn); 639 *imm = 0; 640 *wb = GET_IW_F1X4L17_WB (insn); 641 *id = GET_IW_F1X4L17_ID (insn); 642 return 1; 643 } 644 return 0; 645 } 646 647 /* Match and disassemble a POP.N or LDWM instruction. 648 Returns true on success, and fills in the operand pointers. */ 649 650 static int 651 nios2_match_ldwm (uint32_t insn, const struct nios2_opcode *op, 652 unsigned long mach, unsigned int *reglist, 653 int *ra, int *imm, int *wb, int *id, int *ret) 654 { 655 int is_r2 = (mach == bfd_mach_nios2r2); 656 657 if (!is_r2) 658 return 0; 659 else if (op->match == MATCH_R2_POP_N) 660 { 661 *reglist = 1 << 31; 662 if (GET_IW_L5I4X1_FP (insn)) 663 *reglist |= (1 << 28); 664 if (GET_IW_L5I4X1_CS (insn)) 665 { 666 int val = GET_IW_L5I4X1_REGRANGE (insn); 667 *reglist |= nios2_r2_reg_range_mappings[val]; 668 } 669 *ra = NIOS2_SP_REGNUM; 670 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 671 *wb = 1; 672 *id = 1; 673 *ret = 1; 674 return 1; 675 } 676 else if (op->match == MATCH_R2_LDWM) 677 { 678 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 679 if (GET_IW_F1X4L17_RS (insn)) 680 { 681 *reglist = ((rawmask << 14) & 0x00ffc000); 682 if (rawmask & (1 << 10)) 683 *reglist |= (1 << 28); 684 if (rawmask & (1 << 11)) 685 *reglist |= (1 << 31); 686 } 687 else 688 *reglist = rawmask << 2; 689 *ra = GET_IW_F1X4L17_A (insn); 690 *imm = 0; 691 *wb = GET_IW_F1X4L17_WB (insn); 692 *id = GET_IW_F1X4L17_ID (insn); 693 *ret = GET_IW_F1X4L17_PC (insn); 694 return 1; 695 } 696 return 0; 697 } 698 699 /* Match and disassemble a branch instruction, with (potentially) 700 2 register operands and one immediate operand. 701 Returns true on success, and fills in the operand pointers. */ 702 703 enum branch_condition { 704 branch_none, 705 branch_eq, 706 branch_ne, 707 branch_ge, 708 branch_geu, 709 branch_lt, 710 branch_ltu 711 }; 712 713 static int 714 nios2_match_branch (uint32_t insn, const struct nios2_opcode *op, 715 unsigned long mach, int *ra, int *rb, int *imm, 716 enum branch_condition *cond) 717 { 718 int is_r2 = (mach == bfd_mach_nios2r2); 719 720 if (!is_r2) 721 { 722 switch (op->match) 723 { 724 case MATCH_R1_BR: 725 *cond = branch_none; 726 break; 727 case MATCH_R1_BEQ: 728 *cond = branch_eq; 729 break; 730 case MATCH_R1_BNE: 731 *cond = branch_ne; 732 break; 733 case MATCH_R1_BGE: 734 *cond = branch_ge; 735 break; 736 case MATCH_R1_BGEU: 737 *cond = branch_geu; 738 break; 739 case MATCH_R1_BLT: 740 *cond = branch_lt; 741 break; 742 case MATCH_R1_BLTU: 743 *cond = branch_ltu; 744 break; 745 default: 746 return 0; 747 } 748 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 749 *ra = GET_IW_I_A (insn); 750 *rb = GET_IW_I_B (insn); 751 return 1; 752 } 753 else 754 { 755 switch (op->match) 756 { 757 case MATCH_R2_BR_N: 758 *cond = branch_none; 759 *ra = NIOS2_Z_REGNUM; 760 *rb = NIOS2_Z_REGNUM; 761 *imm = (signed) ((GET_IW_I10_IMM10 (insn) << 1) << 21) >> 21; 762 return 1; 763 case MATCH_R2_BEQZ_N: 764 *cond = branch_eq; 765 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 766 *rb = NIOS2_Z_REGNUM; 767 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 768 return 1; 769 case MATCH_R2_BNEZ_N: 770 *cond = branch_ne; 771 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 772 *rb = NIOS2_Z_REGNUM; 773 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 774 return 1; 775 case MATCH_R2_BR: 776 *cond = branch_none; 777 break; 778 case MATCH_R2_BEQ: 779 *cond = branch_eq; 780 break; 781 case MATCH_R2_BNE: 782 *cond = branch_ne; 783 break; 784 case MATCH_R2_BGE: 785 *cond = branch_ge; 786 break; 787 case MATCH_R2_BGEU: 788 *cond = branch_geu; 789 break; 790 case MATCH_R2_BLT: 791 *cond = branch_lt; 792 break; 793 case MATCH_R2_BLTU: 794 *cond = branch_ltu; 795 break; 796 default: 797 return 0; 798 } 799 *ra = GET_IW_F2I16_A (insn); 800 *rb = GET_IW_F2I16_B (insn); 801 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 802 return 1; 803 } 804 return 0; 805 } 806 807 /* Match and disassemble a direct jump instruction, with an 808 unsigned operand. Returns true on success, and fills in the operand 809 pointer. */ 810 811 static int 812 nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op, 813 unsigned long mach, unsigned int *uimm) 814 { 815 int is_r2 = (mach == bfd_mach_nios2r2); 816 817 if (!is_r2 && op->match == MATCH_R1_JMPI) 818 { 819 *uimm = GET_IW_J_IMM26 (insn) << 2; 820 return 1; 821 } 822 else if (!is_r2) 823 return 0; 824 else if (op->match == MATCH_R2_JMPI) 825 { 826 *uimm = GET_IW_L26_IMM26 (insn) << 2; 827 return 1; 828 } 829 return 0; 830 } 831 832 /* Match and disassemble a direct call instruction, with an 833 unsigned operand. Returns true on success, and fills in the operand 834 pointer. */ 835 836 static int 837 nios2_match_calli (uint32_t insn, const struct nios2_opcode *op, 838 unsigned long mach, unsigned int *uimm) 839 { 840 int is_r2 = (mach == bfd_mach_nios2r2); 841 842 if (!is_r2 && op->match == MATCH_R1_CALL) 843 { 844 *uimm = GET_IW_J_IMM26 (insn) << 2; 845 return 1; 846 } 847 else if (!is_r2) 848 return 0; 849 else if (op->match == MATCH_R2_CALL) 850 { 851 *uimm = GET_IW_L26_IMM26 (insn) << 2; 852 return 1; 853 } 854 return 0; 855 } 856 857 /* Match and disassemble an indirect jump instruction, with a 858 (possibly implicit) register operand. Returns true on success, and fills 859 in the operand pointer. */ 860 861 static int 862 nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op, 863 unsigned long mach, int *ra) 864 { 865 int is_r2 = (mach == bfd_mach_nios2r2); 866 867 if (!is_r2) 868 switch (op->match) 869 { 870 case MATCH_R1_JMP: 871 *ra = GET_IW_I_A (insn); 872 return 1; 873 case MATCH_R1_RET: 874 *ra = NIOS2_RA_REGNUM; 875 return 1; 876 case MATCH_R1_ERET: 877 *ra = NIOS2_EA_REGNUM; 878 return 1; 879 case MATCH_R1_BRET: 880 *ra = NIOS2_BA_REGNUM; 881 return 1; 882 default: 883 return 0; 884 } 885 else 886 switch (op->match) 887 { 888 case MATCH_R2_JMP: 889 *ra = GET_IW_F2I16_A (insn); 890 return 1; 891 case MATCH_R2_JMPR_N: 892 *ra = GET_IW_F1X1_A (insn); 893 return 1; 894 case MATCH_R2_RET: 895 case MATCH_R2_RET_N: 896 *ra = NIOS2_RA_REGNUM; 897 return 1; 898 case MATCH_R2_ERET: 899 *ra = NIOS2_EA_REGNUM; 900 return 1; 901 case MATCH_R2_BRET: 902 *ra = NIOS2_BA_REGNUM; 903 return 1; 904 default: 905 return 0; 906 } 907 return 0; 908 } 909 910 /* Match and disassemble an indirect call instruction, with a register 911 operand. Returns true on success, and fills in the operand pointer. */ 912 913 static int 914 nios2_match_callr (uint32_t insn, const struct nios2_opcode *op, 915 unsigned long mach, int *ra) 916 { 917 int is_r2 = (mach == bfd_mach_nios2r2); 918 919 if (!is_r2 && op->match == MATCH_R1_CALLR) 920 { 921 *ra = GET_IW_I_A (insn); 922 return 1; 923 } 924 else if (!is_r2) 925 return 0; 926 else if (op->match == MATCH_R2_CALLR) 927 { 928 *ra = GET_IW_F2I16_A (insn); 929 return 1; 930 } 931 else if (op->match == MATCH_R2_CALLR_N) 932 { 933 *ra = GET_IW_F1X1_A (insn); 934 return 1; 935 } 936 return 0; 937 } 938 939 /* Match and disassemble a break instruction, with an unsigned operand. 940 Returns true on success, and fills in the operand pointer. */ 941 942 static int 943 nios2_match_break (uint32_t insn, const struct nios2_opcode *op, 944 unsigned long mach, unsigned int *uimm) 945 { 946 int is_r2 = (mach == bfd_mach_nios2r2); 947 948 if (!is_r2 && op->match == MATCH_R1_BREAK) 949 { 950 *uimm = GET_IW_R_IMM5 (insn); 951 return 1; 952 } 953 else if (!is_r2) 954 return 0; 955 else if (op->match == MATCH_R2_BREAK) 956 { 957 *uimm = GET_IW_F3X6L5_IMM5 (insn); 958 return 1; 959 } 960 else if (op->match == MATCH_R2_BREAK_N) 961 { 962 *uimm = GET_IW_X2L5_IMM5 (insn); 963 return 1; 964 } 965 return 0; 966 } 967 968 /* Match and disassemble a trap instruction, with an unsigned operand. 969 Returns true on success, and fills in the operand pointer. */ 970 971 static int 972 nios2_match_trap (uint32_t insn, const struct nios2_opcode *op, 973 unsigned long mach, unsigned int *uimm) 974 { 975 int is_r2 = (mach == bfd_mach_nios2r2); 976 977 if (!is_r2 && op->match == MATCH_R1_TRAP) 978 { 979 *uimm = GET_IW_R_IMM5 (insn); 980 return 1; 981 } 982 else if (!is_r2) 983 return 0; 984 else if (op->match == MATCH_R2_TRAP) 985 { 986 *uimm = GET_IW_F3X6L5_IMM5 (insn); 987 return 1; 988 } 989 else if (op->match == MATCH_R2_TRAP_N) 990 { 991 *uimm = GET_IW_X2L5_IMM5 (insn); 992 return 1; 993 } 994 return 0; 995 } 996 997 /* Helper function to identify when we're in a function epilogue; 998 that is, the part of the function from the point at which the 999 stack adjustments are made, to the return or sibcall. 1000 Note that we may have several stack adjustment instructions, and 1001 this function needs to test whether the stack teardown has already 1002 started before current_pc, not whether it has completed. */ 1003 1004 static int 1005 nios2_in_epilogue_p (struct gdbarch *gdbarch, 1006 CORE_ADDR current_pc, 1007 CORE_ADDR start_pc) 1008 { 1009 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1010 int is_r2 = (mach == bfd_mach_nios2r2); 1011 /* Maximum number of possibly-epilogue instructions to check. 1012 Note that this number should not be too large, else we can 1013 potentially end up iterating through unmapped memory. */ 1014 int ninsns, max_insns = 5; 1015 unsigned int insn; 1016 const struct nios2_opcode *op = NULL; 1017 unsigned int uimm; 1018 int imm; 1019 int wb, id, ret; 1020 int ra, rb, rc; 1021 enum branch_condition cond; 1022 CORE_ADDR pc; 1023 1024 /* There has to be a previous instruction in the function. */ 1025 if (current_pc <= start_pc) 1026 return 0; 1027 1028 /* Find the previous instruction before current_pc. For R2, it might 1029 be either a 16-bit or 32-bit instruction; the only way to know for 1030 sure is to scan through from the beginning of the function, 1031 disassembling as we go. */ 1032 if (is_r2) 1033 for (pc = start_pc; ; ) 1034 { 1035 op = nios2_fetch_insn (gdbarch, pc, &insn); 1036 if (op == NULL) 1037 return 0; 1038 if (pc + op->size < current_pc) 1039 pc += op->size; 1040 else 1041 break; 1042 /* We can skip over insns to a forward branch target. Since 1043 the branch offset is relative to the next instruction, 1044 it's correct to do this after incrementing the pc above. */ 1045 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1046 && imm > 0 1047 && pc + imm < current_pc) 1048 pc += imm; 1049 } 1050 /* Otherwise just go back to the previous 32-bit insn. */ 1051 else 1052 pc = current_pc - NIOS2_OPCODE_SIZE; 1053 1054 /* Beginning with the previous instruction we just located, check whether 1055 we are in a sequence of at least one stack adjustment instruction. 1056 Possible instructions here include: 1057 ADDI sp, sp, n 1058 ADD sp, sp, rn 1059 LDW sp, n(sp) 1060 SPINCI.N n 1061 LDWSP.N sp, n(sp) 1062 LDWM {reglist}, (sp)++, wb */ 1063 for (ninsns = 0; ninsns < max_insns; ninsns++) 1064 { 1065 int ok = 0; 1066 1067 /* Fetch the insn at pc. */ 1068 op = nios2_fetch_insn (gdbarch, pc, &insn); 1069 if (op == NULL) 1070 return 0; 1071 pc += op->size; 1072 1073 /* Was it a stack adjustment? */ 1074 if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1075 ok = (rb == NIOS2_SP_REGNUM); 1076 else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1077 ok = (rc == NIOS2_SP_REGNUM); 1078 else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm)) 1079 ok = (rb == NIOS2_SP_REGNUM); 1080 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, 1081 &imm, &wb, &ret, &id)) 1082 ok = (ra == NIOS2_SP_REGNUM && wb && id); 1083 if (!ok) 1084 break; 1085 } 1086 1087 /* No stack adjustments found. */ 1088 if (ninsns == 0) 1089 return 0; 1090 1091 /* We found more stack adjustments than we expect GCC to be generating. 1092 Since it looks like a stack unwind might be in progress tell GDB to 1093 treat it as such. */ 1094 if (ninsns == max_insns) 1095 return 1; 1096 1097 /* The next instruction following the stack adjustments must be a 1098 return, jump, or unconditional branch, or a CDX pop.n or ldwm 1099 that does an implicit return. */ 1100 if (nios2_match_jmpr (insn, op, mach, &ra) 1101 || nios2_match_jmpi (insn, op, mach, &uimm) 1102 || (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 1103 && ret) 1104 || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1105 && cond == branch_none)) 1106 return 1; 1107 1108 return 0; 1109 } 1110 1111 /* Implement the stack_frame_destroyed_p gdbarch method. */ 1112 1113 static int 1114 nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1115 { 1116 CORE_ADDR func_addr; 1117 1118 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 1119 return nios2_in_epilogue_p (gdbarch, pc, func_addr); 1120 1121 return 0; 1122 } 1123 1124 /* Do prologue analysis, returning the PC of the first instruction 1125 after the function prologue. Assumes CACHE has already been 1126 initialized. THIS_FRAME can be null, in which case we are only 1127 interested in skipping the prologue. Otherwise CACHE is filled in 1128 from the frame information. 1129 1130 The prologue may consist of the following parts: 1131 1) Profiling instrumentation. For non-PIC code it looks like: 1132 mov r8, ra 1133 call mcount 1134 mov ra, r8 1135 1136 2) A stack adjustment and save of R4-R7 for varargs functions. 1137 For R2 CDX this is typically handled with a STWM, otherwise 1138 this is typically merged with item 3. 1139 1140 3) A stack adjustment and save of the callee-saved registers. 1141 For R2 CDX these are typically handled with a PUSH.N or STWM, 1142 otherwise as an explicit SP decrement and individual register 1143 saves. 1144 1145 There may also be a stack switch here in an exception handler 1146 in place of a stack adjustment. It looks like: 1147 movhi rx, %hiadj(newstack) 1148 addhi rx, rx, %lo(newstack) 1149 stw sp, constant(rx) 1150 mov sp, rx 1151 1152 4) A frame pointer save, which can be either a MOV or ADDI. 1153 1154 5) A further stack pointer adjustment. This is normally included 1155 adjustment in step 3 unless the total adjustment is too large 1156 to be done in one step. 1157 1158 7) A stack overflow check, which can take either of these forms: 1159 bgeu sp, rx, +8 1160 trap 3 1161 or 1162 bltu sp, rx, .Lstack_overflow 1163 ... 1164 .Lstack_overflow: 1165 trap 3 1166 1167 Older versions of GCC emitted "break 3" instead of "trap 3" here, 1168 so we check for both cases. 1169 1170 Older GCC versions emitted stack overflow checks after the SP 1171 adjustments in both steps 3 and 4. Starting with GCC 6, there is 1172 at most one overflow check, which is placed before the first 1173 stack adjustment for R2 CDX and after the first stack adjustment 1174 otherwise. 1175 1176 The prologue instructions may be combined or interleaved with other 1177 instructions. 1178 1179 To cope with all this variability we decode all the instructions 1180 from the start of the prologue until we hit an instruction that 1181 cannot possibly be a prologue instruction, such as a branch, call, 1182 return, or epilogue instruction. The prologue is considered to end 1183 at the last instruction that can definitely be considered a 1184 prologue instruction. */ 1185 1186 static CORE_ADDR 1187 nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, 1188 const CORE_ADDR current_pc, 1189 struct nios2_unwind_cache *cache, 1190 struct frame_info *this_frame) 1191 { 1192 /* Maximum number of possibly-prologue instructions to check. 1193 Note that this number should not be too large, else we can 1194 potentially end up iterating through unmapped memory. */ 1195 int ninsns, max_insns = 50; 1196 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1197 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1198 1199 /* Does the frame set up the FP register? */ 1200 int base_reg = 0; 1201 1202 struct reg_value *value = cache->reg_value; 1203 struct reg_value temp_value[NIOS2_NUM_REGS]; 1204 1205 int i; 1206 1207 /* Save the starting PC so we can correct the pc after running 1208 through the prolog, using symbol info. */ 1209 CORE_ADDR pc = start_pc; 1210 1211 /* Is this an exception handler? */ 1212 int exception_handler = 0; 1213 1214 /* What was the original value of SP (or fake original value for 1215 functions which switch stacks? */ 1216 CORE_ADDR frame_high; 1217 1218 /* The last definitely-prologue instruction seen. */ 1219 CORE_ADDR prologue_end; 1220 1221 /* Is this the innermost function? */ 1222 int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1); 1223 1224 if (nios2_debug) 1225 fprintf_unfiltered (gdb_stdlog, 1226 "{ nios2_analyze_prologue start=%s, current=%s ", 1227 paddress (gdbarch, start_pc), 1228 paddress (gdbarch, current_pc)); 1229 1230 /* Set up the default values of the registers. */ 1231 nios2_setup_default (cache); 1232 1233 /* Find the prologue instructions. */ 1234 prologue_end = start_pc; 1235 for (ninsns = 0; ninsns < max_insns; ninsns++) 1236 { 1237 /* Present instruction. */ 1238 uint32_t insn; 1239 const struct nios2_opcode *op; 1240 int ra, rb, rc, imm; 1241 unsigned int uimm; 1242 unsigned int reglist; 1243 int wb, id, ret; 1244 enum branch_condition cond; 1245 1246 if (pc == current_pc) 1247 { 1248 /* When we reach the current PC we must save the current 1249 register state (for the backtrace) but keep analysing 1250 because there might be more to find out (eg. is this an 1251 exception handler). */ 1252 memcpy (temp_value, value, sizeof (temp_value)); 1253 value = temp_value; 1254 if (nios2_debug) 1255 fprintf_unfiltered (gdb_stdlog, "*"); 1256 } 1257 1258 op = nios2_fetch_insn (gdbarch, pc, &insn); 1259 1260 /* Unknown opcode? Stop scanning. */ 1261 if (op == NULL) 1262 break; 1263 pc += op->size; 1264 1265 if (nios2_debug) 1266 { 1267 if (op->size == 2) 1268 fprintf_unfiltered (gdb_stdlog, "[%04X]", insn & 0xffff); 1269 else 1270 fprintf_unfiltered (gdb_stdlog, "[%08X]", insn); 1271 } 1272 1273 /* The following instructions can appear in the prologue. */ 1274 1275 if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1276 { 1277 /* ADD rc, ra, rb (also used for MOV) */ 1278 if (rc == NIOS2_SP_REGNUM 1279 && rb == 0 1280 && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg) 1281 { 1282 /* If the previous value of SP is available somewhere 1283 near the new stack pointer value then this is a 1284 stack switch. */ 1285 1286 /* If any registers were saved on the stack before then 1287 we can't backtrace into them now. */ 1288 for (i = 0 ; i < NIOS2_NUM_REGS ; i++) 1289 { 1290 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1291 cache->reg_saved[i].basereg = -1; 1292 if (value[i].reg == NIOS2_SP_REGNUM) 1293 value[i].reg = -1; 1294 } 1295 1296 /* Create a fake "high water mark" 4 bytes above where SP 1297 was stored and fake up the registers to be consistent 1298 with that. */ 1299 value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM; 1300 value[NIOS2_SP_REGNUM].offset 1301 = (value[ra].offset 1302 - cache->reg_saved[NIOS2_SP_REGNUM].addr 1303 - 4); 1304 cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM; 1305 cache->reg_saved[NIOS2_SP_REGNUM].addr = -4; 1306 } 1307 1308 else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1309 /* This is setting SP from FP. This only happens in the 1310 function epilogue. */ 1311 break; 1312 1313 else if (rc != 0) 1314 { 1315 if (value[rb].reg == 0) 1316 value[rc].reg = value[ra].reg; 1317 else if (value[ra].reg == 0) 1318 value[rc].reg = value[rb].reg; 1319 else 1320 value[rc].reg = -1; 1321 value[rc].offset = value[ra].offset + value[rb].offset; 1322 } 1323 1324 /* The add/move is only considered a prologue instruction 1325 if the destination is SP or FP. */ 1326 if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM) 1327 prologue_end = pc; 1328 } 1329 1330 else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc)) 1331 { 1332 /* SUB rc, ra, rb */ 1333 if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM 1334 && value[rc].reg != 0) 1335 /* If we are decrementing the SP by a non-constant amount, 1336 this is alloca, not part of the prologue. */ 1337 break; 1338 else if (rc != 0) 1339 { 1340 if (value[rb].reg == 0) 1341 value[rc].reg = value[ra].reg; 1342 else 1343 value[rc].reg = -1; 1344 value[rc].offset = value[ra].offset - value[rb].offset; 1345 } 1346 } 1347 1348 else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1349 { 1350 /* ADDI rb, ra, imm */ 1351 1352 /* A positive stack adjustment has to be part of the epilogue. */ 1353 if (rb == NIOS2_SP_REGNUM 1354 && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM)) 1355 break; 1356 1357 /* Likewise restoring SP from FP. */ 1358 else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1359 break; 1360 1361 if (rb != 0) 1362 { 1363 value[rb].reg = value[ra].reg; 1364 value[rb].offset = value[ra].offset + imm; 1365 } 1366 1367 /* The add is only considered a prologue instruction 1368 if the destination is SP or FP. */ 1369 if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM) 1370 prologue_end = pc; 1371 } 1372 1373 else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm)) 1374 { 1375 /* ORHI rb, ra, uimm (also used for MOVHI) */ 1376 if (rb != 0) 1377 { 1378 value[rb].reg = (value[ra].reg == 0) ? 0 : -1; 1379 value[rb].offset = value[ra].offset | (uimm << 16); 1380 } 1381 } 1382 1383 else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm)) 1384 { 1385 /* STW rb, imm(ra) */ 1386 1387 /* Are we storing the original value of a register to the stack? 1388 For exception handlers the value of EA-4 (return 1389 address from interrupts etc) is sometimes stored. */ 1390 int orig = value[rb].reg; 1391 if (orig > 0 1392 && (value[rb].offset == 0 1393 || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4)) 1394 && value[ra].reg == NIOS2_SP_REGNUM) 1395 { 1396 if (pc < current_pc) 1397 { 1398 /* Save off callee saved registers. */ 1399 cache->reg_saved[orig].basereg = value[ra].reg; 1400 cache->reg_saved[orig].addr = value[ra].offset + imm; 1401 } 1402 1403 prologue_end = pc; 1404 1405 if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM) 1406 exception_handler = 1; 1407 } 1408 else 1409 /* Non-stack memory writes cannot appear in the prologue. */ 1410 break; 1411 } 1412 1413 else if (nios2_match_stwm (insn, op, mach, 1414 ®list, &ra, &imm, &wb, &id)) 1415 { 1416 /* PUSH.N {reglist}, adjust 1417 or 1418 STWM {reglist}, --(SP)[, writeback] */ 1419 int i; 1420 int off = 0; 1421 1422 if (ra != NIOS2_SP_REGNUM || id != 0) 1423 /* This is a non-stack-push memory write and cannot be 1424 part of the prologue. */ 1425 break; 1426 1427 for (i = 31; i >= 0; i--) 1428 if (reglist & (1 << i)) 1429 { 1430 int orig = value[i].reg; 1431 1432 off += 4; 1433 if (orig > 0 && value[i].offset == 0 && pc < current_pc) 1434 { 1435 cache->reg_saved[orig].basereg 1436 = value[NIOS2_SP_REGNUM].reg; 1437 cache->reg_saved[orig].addr 1438 = value[NIOS2_SP_REGNUM].offset - off; 1439 } 1440 } 1441 1442 if (wb) 1443 value[NIOS2_SP_REGNUM].offset -= off; 1444 value[NIOS2_SP_REGNUM].offset -= imm; 1445 1446 prologue_end = pc; 1447 } 1448 1449 else if (nios2_match_rdctl (insn, op, mach, &ra, &rc)) 1450 { 1451 /* RDCTL rC, ctlN 1452 This can appear in exception handlers in combination with 1453 a subsequent save to the stack frame. */ 1454 if (rc != 0) 1455 { 1456 value[rc].reg = NIOS2_STATUS_REGNUM + ra; 1457 value[rc].offset = 0; 1458 } 1459 } 1460 1461 else if (nios2_match_calli (insn, op, mach, &uimm)) 1462 { 1463 if (value[8].reg == NIOS2_RA_REGNUM 1464 && value[8].offset == 0 1465 && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM 1466 && value[NIOS2_SP_REGNUM].offset == 0) 1467 { 1468 /* A CALL instruction. This is treated as a call to mcount 1469 if ra has been stored into r8 beforehand and if it's 1470 before the stack adjust. 1471 Note mcount corrupts r2-r3, r9-r15 & ra. */ 1472 for (i = 2 ; i <= 3 ; i++) 1473 value[i].reg = -1; 1474 for (i = 9 ; i <= 15 ; i++) 1475 value[i].reg = -1; 1476 value[NIOS2_RA_REGNUM].reg = -1; 1477 1478 prologue_end = pc; 1479 } 1480 1481 /* Other calls are not part of the prologue. */ 1482 else 1483 break; 1484 } 1485 1486 else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 1487 { 1488 /* Branches not involving a stack overflow check aren't part of 1489 the prologue. */ 1490 if (ra != NIOS2_SP_REGNUM) 1491 break; 1492 else if (cond == branch_geu) 1493 { 1494 /* BGEU sp, rx, +8 1495 TRAP 3 (or BREAK 3) 1496 This instruction sequence is used in stack checking; 1497 we can ignore it. */ 1498 unsigned int next_insn; 1499 const struct nios2_opcode *next_op 1500 = nios2_fetch_insn (gdbarch, pc, &next_insn); 1501 if (next_op != NULL 1502 && (nios2_match_trap (next_insn, op, mach, &uimm) 1503 || nios2_match_break (next_insn, op, mach, &uimm))) 1504 pc += next_op->size; 1505 else 1506 break; 1507 } 1508 else if (cond == branch_ltu) 1509 { 1510 /* BLTU sp, rx, .Lstackoverflow 1511 If the location branched to holds a TRAP or BREAK 1512 instruction then this is also stack overflow detection. */ 1513 unsigned int next_insn; 1514 const struct nios2_opcode *next_op 1515 = nios2_fetch_insn (gdbarch, pc + imm, &next_insn); 1516 if (next_op != NULL 1517 && (nios2_match_trap (next_insn, op, mach, &uimm) 1518 || nios2_match_break (next_insn, op, mach, &uimm))) 1519 ; 1520 else 1521 break; 1522 } 1523 else 1524 break; 1525 } 1526 1527 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate 1528 the prologue. */ 1529 else if (nios2_match_callr (insn, op, mach, &ra) 1530 || nios2_match_jmpr (insn, op, mach, &ra) 1531 || nios2_match_jmpi (insn, op, mach, &uimm) 1532 || (nios2_match_ldwm (insn, op, mach, ®list, &ra, 1533 &imm, &wb, &id, &ret) 1534 && ret) 1535 || nios2_match_trap (insn, op, mach, &uimm) 1536 || nios2_match_break (insn, op, mach, &uimm)) 1537 break; 1538 } 1539 1540 /* If THIS_FRAME is NULL, we are being called from skip_prologue 1541 and are only interested in the PROLOGUE_END value, so just 1542 return that now and skip over the cache updates, which depend 1543 on having frame information. */ 1544 if (this_frame == NULL) 1545 return prologue_end; 1546 1547 /* If we are in the function epilogue and have already popped 1548 registers off the stack in preparation for returning, then we 1549 want to go back to the original register values. */ 1550 if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc)) 1551 nios2_setup_default (cache); 1552 1553 /* Exception handlers use a different return address register. */ 1554 if (exception_handler) 1555 cache->return_regnum = NIOS2_EA_REGNUM; 1556 1557 if (nios2_debug) 1558 fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum); 1559 1560 if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM) 1561 /* If the FP now holds an offset from the CFA then this is a 1562 normal frame which uses the frame pointer. */ 1563 base_reg = NIOS2_FP_REGNUM; 1564 else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM) 1565 /* FP doesn't hold an offset from the CFA. If SP still holds an 1566 offset from the CFA then we might be in a function which omits 1567 the frame pointer, or we might be partway through the prologue. 1568 In both cases we can find the CFA using SP. */ 1569 base_reg = NIOS2_SP_REGNUM; 1570 else 1571 { 1572 /* Somehow the stack pointer has been corrupted. 1573 We can't return. */ 1574 if (nios2_debug) 1575 fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n"); 1576 return 0; 1577 } 1578 1579 if (cache->reg_value[base_reg].offset == 0 1580 || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM 1581 || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM) 1582 { 1583 /* If the frame didn't adjust the stack, didn't save RA or 1584 didn't save EA in an exception handler then it must either 1585 be a leaf function (doesn't call any other functions) or it 1586 can't return. If it has called another function then it 1587 can't be a leaf, so set base == 0 to indicate that we can't 1588 backtrace past it. */ 1589 1590 if (!innermost) 1591 { 1592 /* If it isn't the innermost function then it can't be a 1593 leaf, unless it was interrupted. Check whether RA for 1594 this frame is the same as PC. If so then it probably 1595 wasn't interrupted. */ 1596 CORE_ADDR ra 1597 = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM); 1598 1599 if (ra == current_pc) 1600 { 1601 if (nios2_debug) 1602 fprintf_unfiltered 1603 (gdb_stdlog, 1604 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n", 1605 paddress (gdbarch, cache->reg_value[base_reg].offset), 1606 cache->reg_saved[NIOS2_RA_REGNUM].basereg, 1607 cache->return_regnum, 1608 cache->reg_saved[cache->return_regnum].basereg); 1609 return 0; 1610 } 1611 } 1612 } 1613 1614 /* Get the value of whichever register we are using for the 1615 base. */ 1616 cache->base = get_frame_register_unsigned (this_frame, base_reg); 1617 1618 /* What was the value of SP at the start of this function (or just 1619 after the stack switch). */ 1620 frame_high = cache->base - cache->reg_value[base_reg].offset; 1621 1622 /* Adjust all the saved registers such that they contain addresses 1623 instead of offsets. */ 1624 for (i = 0; i < NIOS2_NUM_REGS; i++) 1625 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1626 { 1627 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1628 cache->reg_saved[i].addr += frame_high; 1629 } 1630 1631 for (i = 0; i < NIOS2_NUM_REGS; i++) 1632 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1633 { 1634 CORE_ADDR gp = get_frame_register_unsigned (this_frame, 1635 NIOS2_GP_REGNUM); 1636 1637 for ( ; i < NIOS2_NUM_REGS; i++) 1638 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1639 { 1640 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1641 cache->reg_saved[i].addr += gp; 1642 } 1643 } 1644 1645 /* Work out what the value of SP was on the first instruction of 1646 this function. If we didn't switch stacks then this can be 1647 trivially computed from the base address. */ 1648 if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM) 1649 cache->cfa 1650 = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr, 1651 4, byte_order); 1652 else 1653 cache->cfa = frame_high; 1654 1655 /* Exception handlers restore ESTATUS into STATUS. */ 1656 if (exception_handler) 1657 { 1658 cache->reg_saved[NIOS2_STATUS_REGNUM] 1659 = cache->reg_saved[NIOS2_ESTATUS_REGNUM]; 1660 cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1; 1661 } 1662 1663 if (nios2_debug) 1664 fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n", 1665 paddress (gdbarch, cache->cfa)); 1666 1667 return prologue_end; 1668 } 1669 1670 /* Implement the skip_prologue gdbarch hook. */ 1671 1672 static CORE_ADDR 1673 nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1674 { 1675 CORE_ADDR func_addr; 1676 1677 struct nios2_unwind_cache cache; 1678 1679 /* See if we can determine the end of the prologue via the symbol 1680 table. If so, then return either PC, or the PC after the 1681 prologue, whichever is greater. */ 1682 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1683 { 1684 CORE_ADDR post_prologue_pc 1685 = skip_prologue_using_sal (gdbarch, func_addr); 1686 1687 if (post_prologue_pc != 0) 1688 return max (start_pc, post_prologue_pc); 1689 } 1690 1691 /* Prologue analysis does the rest.... */ 1692 nios2_init_cache (&cache, start_pc); 1693 return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL); 1694 } 1695 1696 /* Implement the breakpoint_from_pc gdbarch hook. 1697 1698 The Nios II ABI for Linux says: "Userspace programs should not use 1699 the break instruction and userspace debuggers should not insert 1700 one." and "Userspace breakpoints are accomplished using the trap 1701 instruction with immediate operand 31 (all ones)." 1702 1703 So, we use "trap 31" consistently as the breakpoint on bare-metal 1704 as well as Linux targets. */ 1705 1706 static const gdb_byte* 1707 nios2_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, 1708 int *bp_size) 1709 { 1710 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); 1711 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1712 1713 if (mach == bfd_mach_nios2r2) 1714 { 1715 /* R2 trap encoding: 1716 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0)) 1717 0xb7fd0020 1718 CDX trap.n encoding: 1719 ((0xd << 12) | (0x1f << 6) | (0x9 << 0)) 1720 0xd7c9 1721 Note that code is always little-endian on R2. */ 1722 static const gdb_byte r2_breakpoint_le[] = {0x20, 0x00, 0xfd, 0xb7}; 1723 static const gdb_byte cdx_breakpoint_le[] = {0xc9, 0xd7}; 1724 unsigned int insn; 1725 const struct nios2_opcode *op 1726 = nios2_fetch_insn (gdbarch, *bp_addr, &insn); 1727 1728 if (op && op->size == NIOS2_CDX_OPCODE_SIZE) 1729 { 1730 *bp_size = NIOS2_CDX_OPCODE_SIZE; 1731 return cdx_breakpoint_le; 1732 } 1733 else 1734 { 1735 *bp_size = NIOS2_OPCODE_SIZE; 1736 return r2_breakpoint_le; 1737 } 1738 } 1739 else 1740 { 1741 /* R1 trap encoding: 1742 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0)) 1743 0x003b6ffa */ 1744 static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0}; 1745 static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa}; 1746 *bp_size = NIOS2_OPCODE_SIZE; 1747 if (byte_order_for_code == BFD_ENDIAN_BIG) 1748 return r1_breakpoint_be; 1749 else 1750 return r1_breakpoint_le; 1751 } 1752 } 1753 1754 /* Implement the print_insn gdbarch method. */ 1755 1756 static int 1757 nios2_print_insn (bfd_vma memaddr, disassemble_info *info) 1758 { 1759 if (info->endian == BFD_ENDIAN_BIG) 1760 return print_insn_big_nios2 (memaddr, info); 1761 else 1762 return print_insn_little_nios2 (memaddr, info); 1763 } 1764 1765 1766 /* Implement the frame_align gdbarch method. */ 1767 1768 static CORE_ADDR 1769 nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1770 { 1771 return align_down (addr, 4); 1772 } 1773 1774 1775 /* Implement the return_value gdbarch method. */ 1776 1777 static enum return_value_convention 1778 nios2_return_value (struct gdbarch *gdbarch, struct value *function, 1779 struct type *type, struct regcache *regcache, 1780 gdb_byte *readbuf, const gdb_byte *writebuf) 1781 { 1782 if (TYPE_LENGTH (type) > 8) 1783 return RETURN_VALUE_STRUCT_CONVENTION; 1784 1785 if (readbuf) 1786 nios2_extract_return_value (gdbarch, type, regcache, readbuf); 1787 if (writebuf) 1788 nios2_store_return_value (gdbarch, type, regcache, writebuf); 1789 1790 return RETURN_VALUE_REGISTER_CONVENTION; 1791 } 1792 1793 /* Implement the dummy_id gdbarch method. */ 1794 1795 static struct frame_id 1796 nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1797 { 1798 return frame_id_build 1799 (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM), 1800 get_frame_pc (this_frame)); 1801 } 1802 1803 /* Implement the push_dummy_call gdbarch method. */ 1804 1805 static CORE_ADDR 1806 nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1807 struct regcache *regcache, CORE_ADDR bp_addr, 1808 int nargs, struct value **args, CORE_ADDR sp, 1809 int struct_return, CORE_ADDR struct_addr) 1810 { 1811 int argreg; 1812 int float_argreg; 1813 int argnum; 1814 int len = 0; 1815 int stack_offset = 0; 1816 CORE_ADDR func_addr = find_function_addr (function, NULL); 1817 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1818 1819 /* Set the return address register to point to the entry point of 1820 the program, where a breakpoint lies in wait. */ 1821 regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr); 1822 1823 /* Now make space on the stack for the args. */ 1824 for (argnum = 0; argnum < nargs; argnum++) 1825 len += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); 1826 sp -= len; 1827 1828 /* Initialize the register pointer. */ 1829 argreg = NIOS2_FIRST_ARGREG; 1830 1831 /* The struct_return pointer occupies the first parameter-passing 1832 register. */ 1833 if (struct_return) 1834 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 1835 1836 /* Now load as many as possible of the first arguments into 1837 registers, and push the rest onto the stack. Loop through args 1838 from first to last. */ 1839 for (argnum = 0; argnum < nargs; argnum++) 1840 { 1841 const gdb_byte *val; 1842 struct value *arg = args[argnum]; 1843 struct type *arg_type = check_typedef (value_type (arg)); 1844 int len = TYPE_LENGTH (arg_type); 1845 1846 val = value_contents (arg); 1847 1848 /* Copy the argument to general registers or the stack in 1849 register-sized pieces. Large arguments are split between 1850 registers and stack. */ 1851 while (len > 0) 1852 { 1853 int partial_len = (len < 4 ? len : 4); 1854 1855 if (argreg <= NIOS2_LAST_ARGREG) 1856 { 1857 /* The argument is being passed in a register. */ 1858 CORE_ADDR regval = extract_unsigned_integer (val, partial_len, 1859 byte_order); 1860 1861 regcache_cooked_write_unsigned (regcache, argreg, regval); 1862 argreg++; 1863 } 1864 else 1865 { 1866 /* The argument is being passed on the stack. */ 1867 CORE_ADDR addr = sp + stack_offset; 1868 1869 write_memory (addr, val, partial_len); 1870 stack_offset += align_up (partial_len, 4); 1871 } 1872 1873 len -= partial_len; 1874 val += partial_len; 1875 } 1876 } 1877 1878 regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp); 1879 1880 /* Return adjusted stack pointer. */ 1881 return sp; 1882 } 1883 1884 /* Implement the unwind_pc gdbarch method. */ 1885 1886 static CORE_ADDR 1887 nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1888 { 1889 gdb_byte buf[4]; 1890 1891 frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf); 1892 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1893 } 1894 1895 /* Implement the unwind_sp gdbarch method. */ 1896 1897 static CORE_ADDR 1898 nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) 1899 { 1900 return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM); 1901 } 1902 1903 /* Use prologue analysis to fill in the register cache 1904 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes 1905 *THIS_PROLOGUE_CACHE first. */ 1906 1907 static struct nios2_unwind_cache * 1908 nios2_frame_unwind_cache (struct frame_info *this_frame, 1909 void **this_prologue_cache) 1910 { 1911 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1912 CORE_ADDR current_pc; 1913 struct nios2_unwind_cache *cache; 1914 1915 if (*this_prologue_cache) 1916 return (struct nios2_unwind_cache *) *this_prologue_cache; 1917 1918 cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache); 1919 *this_prologue_cache = cache; 1920 1921 /* Zero all fields. */ 1922 nios2_init_cache (cache, get_frame_func (this_frame)); 1923 1924 /* Prologue analysis does the rest... */ 1925 current_pc = get_frame_pc (this_frame); 1926 if (cache->pc != 0) 1927 nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); 1928 1929 return cache; 1930 } 1931 1932 /* Implement the this_id function for the normal unwinder. */ 1933 1934 static void 1935 nios2_frame_this_id (struct frame_info *this_frame, void **this_cache, 1936 struct frame_id *this_id) 1937 { 1938 struct nios2_unwind_cache *cache = 1939 nios2_frame_unwind_cache (this_frame, this_cache); 1940 1941 /* This marks the outermost frame. */ 1942 if (cache->base == 0) 1943 return; 1944 1945 *this_id = frame_id_build (cache->cfa, cache->pc); 1946 } 1947 1948 /* Implement the prev_register function for the normal unwinder. */ 1949 1950 static struct value * 1951 nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache, 1952 int regnum) 1953 { 1954 struct nios2_unwind_cache *cache = 1955 nios2_frame_unwind_cache (this_frame, this_cache); 1956 1957 gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS); 1958 1959 /* The PC of the previous frame is stored in the RA register of 1960 the current frame. Frob regnum so that we pull the value from 1961 the correct place. */ 1962 if (regnum == NIOS2_PC_REGNUM) 1963 regnum = cache->return_regnum; 1964 1965 if (regnum == NIOS2_SP_REGNUM && cache->cfa) 1966 return frame_unwind_got_constant (this_frame, regnum, cache->cfa); 1967 1968 /* If we've worked out where a register is stored then load it from 1969 there. */ 1970 if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM) 1971 return frame_unwind_got_memory (this_frame, regnum, 1972 cache->reg_saved[regnum].addr); 1973 1974 return frame_unwind_got_register (this_frame, regnum, regnum); 1975 } 1976 1977 /* Implement the this_base, this_locals, and this_args hooks 1978 for the normal unwinder. */ 1979 1980 static CORE_ADDR 1981 nios2_frame_base_address (struct frame_info *this_frame, void **this_cache) 1982 { 1983 struct nios2_unwind_cache *info 1984 = nios2_frame_unwind_cache (this_frame, this_cache); 1985 1986 return info->base; 1987 } 1988 1989 /* Data structures for the normal prologue-analysis-based 1990 unwinder. */ 1991 1992 static const struct frame_unwind nios2_frame_unwind = 1993 { 1994 NORMAL_FRAME, 1995 default_frame_unwind_stop_reason, 1996 nios2_frame_this_id, 1997 nios2_frame_prev_register, 1998 NULL, 1999 default_frame_sniffer 2000 }; 2001 2002 static const struct frame_base nios2_frame_base = 2003 { 2004 &nios2_frame_unwind, 2005 nios2_frame_base_address, 2006 nios2_frame_base_address, 2007 nios2_frame_base_address 2008 }; 2009 2010 /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use 2011 in the stub unwinder. */ 2012 2013 static struct trad_frame_cache * 2014 nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache) 2015 { 2016 CORE_ADDR pc; 2017 CORE_ADDR start_addr; 2018 CORE_ADDR stack_addr; 2019 struct trad_frame_cache *this_trad_cache; 2020 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2021 2022 if (*this_cache != NULL) 2023 return (struct trad_frame_cache *) *this_cache; 2024 this_trad_cache = trad_frame_cache_zalloc (this_frame); 2025 *this_cache = this_trad_cache; 2026 2027 /* The return address is in the link register. */ 2028 trad_frame_set_reg_realreg (this_trad_cache, 2029 gdbarch_pc_regnum (gdbarch), 2030 NIOS2_RA_REGNUM); 2031 2032 /* Frame ID, since it's a frameless / stackless function, no stack 2033 space is allocated and SP on entry is the current SP. */ 2034 pc = get_frame_pc (this_frame); 2035 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2036 stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM); 2037 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); 2038 /* Assume that the frame's base is the same as the stack pointer. */ 2039 trad_frame_set_this_base (this_trad_cache, stack_addr); 2040 2041 return this_trad_cache; 2042 } 2043 2044 /* Implement the this_id function for the stub unwinder. */ 2045 2046 static void 2047 nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, 2048 struct frame_id *this_id) 2049 { 2050 struct trad_frame_cache *this_trad_cache 2051 = nios2_stub_frame_cache (this_frame, this_cache); 2052 2053 trad_frame_get_id (this_trad_cache, this_id); 2054 } 2055 2056 /* Implement the prev_register function for the stub unwinder. */ 2057 2058 static struct value * 2059 nios2_stub_frame_prev_register (struct frame_info *this_frame, 2060 void **this_cache, int regnum) 2061 { 2062 struct trad_frame_cache *this_trad_cache 2063 = nios2_stub_frame_cache (this_frame, this_cache); 2064 2065 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 2066 } 2067 2068 /* Implement the sniffer function for the stub unwinder. 2069 This unwinder is used for cases where the normal 2070 prologue-analysis-based unwinder can't work, 2071 such as PLT stubs. */ 2072 2073 static int 2074 nios2_stub_frame_sniffer (const struct frame_unwind *self, 2075 struct frame_info *this_frame, void **cache) 2076 { 2077 gdb_byte dummy[4]; 2078 CORE_ADDR pc = get_frame_address_in_block (this_frame); 2079 2080 /* Use the stub unwinder for unreadable code. */ 2081 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 2082 return 1; 2083 2084 if (in_plt_section (pc)) 2085 return 1; 2086 2087 return 0; 2088 } 2089 2090 /* Define the data structures for the stub unwinder. */ 2091 2092 static const struct frame_unwind nios2_stub_frame_unwind = 2093 { 2094 NORMAL_FRAME, 2095 default_frame_unwind_stop_reason, 2096 nios2_stub_frame_this_id, 2097 nios2_stub_frame_prev_register, 2098 NULL, 2099 nios2_stub_frame_sniffer 2100 }; 2101 2102 2103 2104 /* Determine where to set a single step breakpoint while considering 2105 branch prediction. */ 2106 2107 static CORE_ADDR 2108 nios2_get_next_pc (struct frame_info *frame, CORE_ADDR pc) 2109 { 2110 struct gdbarch *gdbarch = get_frame_arch (frame); 2111 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2112 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 2113 unsigned int insn; 2114 const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn); 2115 int ra; 2116 int rb; 2117 int imm; 2118 unsigned int uimm; 2119 int wb, id, ret; 2120 enum branch_condition cond; 2121 2122 /* Do something stupid if we can't disassemble the insn at pc. */ 2123 if (op == NULL) 2124 return pc + NIOS2_OPCODE_SIZE; 2125 2126 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 2127 { 2128 int ras = get_frame_register_signed (frame, ra); 2129 int rbs = get_frame_register_signed (frame, rb); 2130 unsigned int rau = get_frame_register_unsigned (frame, ra); 2131 unsigned int rbu = get_frame_register_unsigned (frame, rb); 2132 2133 pc += op->size; 2134 switch (cond) 2135 { 2136 case branch_none: 2137 pc += imm; 2138 break; 2139 case branch_eq: 2140 if (ras == rbs) 2141 pc += imm; 2142 break; 2143 case branch_ne: 2144 if (ras != rbs) 2145 pc += imm; 2146 break; 2147 case branch_ge: 2148 if (ras >= rbs) 2149 pc += imm; 2150 break; 2151 case branch_geu: 2152 if (rau >= rbu) 2153 pc += imm; 2154 break; 2155 case branch_lt: 2156 if (ras < rbs) 2157 pc += imm; 2158 break; 2159 case branch_ltu: 2160 if (rau < rbu) 2161 pc += imm; 2162 break; 2163 default: 2164 break; 2165 } 2166 } 2167 2168 else if (nios2_match_jmpi (insn, op, mach, &uimm) 2169 || nios2_match_calli (insn, op, mach, &uimm)) 2170 pc = (pc & 0xf0000000) | uimm; 2171 2172 else if (nios2_match_jmpr (insn, op, mach, &ra) 2173 || nios2_match_callr (insn, op, mach, &ra)) 2174 pc = get_frame_register_unsigned (frame, ra); 2175 2176 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 2177 && ret) 2178 { 2179 /* If ra is in the reglist, we have to use the value saved in the 2180 stack frame rather than the current value. */ 2181 if (uimm & (1 << NIOS2_RA_REGNUM)) 2182 pc = nios2_unwind_pc (gdbarch, frame); 2183 else 2184 pc = get_frame_register_unsigned (frame, NIOS2_RA_REGNUM); 2185 } 2186 2187 else if (nios2_match_trap (insn, op, mach, &uimm) && uimm == 0) 2188 { 2189 if (tdep->syscall_next_pc != NULL) 2190 return tdep->syscall_next_pc (frame, op); 2191 } 2192 2193 else 2194 pc += op->size; 2195 2196 return pc; 2197 } 2198 2199 /* Implement the software_single_step gdbarch method. */ 2200 2201 static int 2202 nios2_software_single_step (struct frame_info *frame) 2203 { 2204 struct gdbarch *gdbarch = get_frame_arch (frame); 2205 struct address_space *aspace = get_frame_address_space (frame); 2206 CORE_ADDR next_pc = nios2_get_next_pc (frame, get_frame_pc (frame)); 2207 2208 insert_single_step_breakpoint (gdbarch, aspace, next_pc); 2209 2210 return 1; 2211 } 2212 2213 /* Implement the get_longjump_target gdbarch method. */ 2214 2215 static int 2216 nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2217 { 2218 struct gdbarch *gdbarch = get_frame_arch (frame); 2219 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2220 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2221 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM); 2222 gdb_byte buf[4]; 2223 2224 if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4)) 2225 return 0; 2226 2227 *pc = extract_unsigned_integer (buf, 4, byte_order); 2228 return 1; 2229 } 2230 2231 /* Initialize the Nios II gdbarch. */ 2232 2233 static struct gdbarch * 2234 nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2235 { 2236 struct gdbarch *gdbarch; 2237 struct gdbarch_tdep *tdep; 2238 int i; 2239 struct tdesc_arch_data *tdesc_data = NULL; 2240 const struct target_desc *tdesc = info.target_desc; 2241 2242 if (!tdesc_has_registers (tdesc)) 2243 /* Pick a default target description. */ 2244 tdesc = tdesc_nios2; 2245 2246 /* Check any target description for validity. */ 2247 if (tdesc_has_registers (tdesc)) 2248 { 2249 const struct tdesc_feature *feature; 2250 int valid_p; 2251 2252 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu"); 2253 if (feature == NULL) 2254 return NULL; 2255 2256 tdesc_data = tdesc_data_alloc (); 2257 2258 valid_p = 1; 2259 2260 for (i = 0; i < NIOS2_NUM_REGS; i++) 2261 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 2262 nios2_reg_names[i]); 2263 2264 if (!valid_p) 2265 { 2266 tdesc_data_cleanup (tdesc_data); 2267 return NULL; 2268 } 2269 } 2270 2271 /* Find a candidate among the list of pre-declared architectures. */ 2272 arches = gdbarch_list_lookup_by_info (arches, &info); 2273 if (arches != NULL) 2274 return arches->gdbarch; 2275 2276 /* None found, create a new architecture from the information 2277 provided. */ 2278 tdep = XCNEW (struct gdbarch_tdep); 2279 gdbarch = gdbarch_alloc (&info, tdep); 2280 2281 /* longjmp support not enabled by default. */ 2282 tdep->jb_pc = -1; 2283 2284 /* Data type sizes. */ 2285 set_gdbarch_ptr_bit (gdbarch, 32); 2286 set_gdbarch_addr_bit (gdbarch, 32); 2287 set_gdbarch_short_bit (gdbarch, 16); 2288 set_gdbarch_int_bit (gdbarch, 32); 2289 set_gdbarch_long_bit (gdbarch, 32); 2290 set_gdbarch_long_long_bit (gdbarch, 64); 2291 set_gdbarch_float_bit (gdbarch, 32); 2292 set_gdbarch_double_bit (gdbarch, 64); 2293 2294 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 2295 set_gdbarch_double_format (gdbarch, floatformats_ieee_double); 2296 2297 /* The register set. */ 2298 set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS); 2299 set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM); 2300 set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */ 2301 2302 set_gdbarch_register_name (gdbarch, nios2_register_name); 2303 set_gdbarch_register_type (gdbarch, nios2_register_type); 2304 2305 /* Provide register mappings for stabs and dwarf2. */ 2306 set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2307 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2308 2309 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2310 2311 /* Call dummy code. */ 2312 set_gdbarch_frame_align (gdbarch, nios2_frame_align); 2313 2314 set_gdbarch_return_value (gdbarch, nios2_return_value); 2315 2316 set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue); 2317 set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p); 2318 set_gdbarch_breakpoint_from_pc (gdbarch, nios2_breakpoint_from_pc); 2319 2320 set_gdbarch_dummy_id (gdbarch, nios2_dummy_id); 2321 set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc); 2322 set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp); 2323 2324 /* The dwarf2 unwinder will normally produce the best results if 2325 the debug information is available, so register it first. */ 2326 dwarf2_append_unwinders (gdbarch); 2327 frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind); 2328 frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind); 2329 2330 /* Single stepping. */ 2331 set_gdbarch_software_single_step (gdbarch, nios2_software_single_step); 2332 2333 /* Hook in ABI-specific overrides, if they have been registered. */ 2334 gdbarch_init_osabi (info, gdbarch); 2335 2336 if (tdep->jb_pc >= 0) 2337 set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target); 2338 2339 frame_base_set_default (gdbarch, &nios2_frame_base); 2340 2341 set_gdbarch_print_insn (gdbarch, nios2_print_insn); 2342 2343 /* Enable inferior call support. */ 2344 set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call); 2345 2346 if (tdesc_data) 2347 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 2348 2349 return gdbarch; 2350 } 2351 2352 extern initialize_file_ftype _initialize_nios2_tdep; /* -Wmissing-prototypes */ 2353 2354 void 2355 _initialize_nios2_tdep (void) 2356 { 2357 gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL); 2358 initialize_tdesc_nios2 (); 2359 2360 /* Allow debugging this file's internals. */ 2361 add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug, 2362 _("Set Nios II debugging."), 2363 _("Show Nios II debugging."), 2364 _("When on, Nios II specific debugging is enabled."), 2365 NULL, 2366 NULL, 2367 &setdebuglist, &showdebuglist); 2368 } 2369