1 /* Target-dependent code for GNU/Linux on MIPS processors. 2 3 Copyright (C) 2001-2020 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "gdbcore.h" 22 #include "target.h" 23 #include "solib-svr4.h" 24 #include "osabi.h" 25 #include "mips-tdep.h" 26 #include "frame.h" 27 #include "regcache.h" 28 #include "trad-frame.h" 29 #include "tramp-frame.h" 30 #include "gdbtypes.h" 31 #include "objfiles.h" 32 #include "solib.h" 33 #include "solist.h" 34 #include "symtab.h" 35 #include "target-descriptions.h" 36 #include "regset.h" 37 #include "mips-linux-tdep.h" 38 #include "glibc-tdep.h" 39 #include "linux-tdep.h" 40 #include "xml-syscall.h" 41 #include "gdbsupport/gdb_signals.h" 42 43 #include "features/mips-linux.c" 44 #include "features/mips-dsp-linux.c" 45 #include "features/mips64-linux.c" 46 #include "features/mips64-dsp-linux.c" 47 48 static struct target_so_ops mips_svr4_so_ops; 49 50 /* This enum represents the signals' numbers on the MIPS 51 architecture. It just contains the signal definitions which are 52 different from the generic implementation. 53 54 It is derived from the file <arch/mips/include/uapi/asm/signal.h>, 55 from the Linux kernel tree. */ 56 57 enum 58 { 59 MIPS_LINUX_SIGEMT = 7, 60 MIPS_LINUX_SIGBUS = 10, 61 MIPS_LINUX_SIGSYS = 12, 62 MIPS_LINUX_SIGUSR1 = 16, 63 MIPS_LINUX_SIGUSR2 = 17, 64 MIPS_LINUX_SIGCHLD = 18, 65 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, 66 MIPS_LINUX_SIGPWR = 19, 67 MIPS_LINUX_SIGWINCH = 20, 68 MIPS_LINUX_SIGURG = 21, 69 MIPS_LINUX_SIGIO = 22, 70 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, 71 MIPS_LINUX_SIGSTOP = 23, 72 MIPS_LINUX_SIGTSTP = 24, 73 MIPS_LINUX_SIGCONT = 25, 74 MIPS_LINUX_SIGTTIN = 26, 75 MIPS_LINUX_SIGTTOU = 27, 76 MIPS_LINUX_SIGVTALRM = 28, 77 MIPS_LINUX_SIGPROF = 29, 78 MIPS_LINUX_SIGXCPU = 30, 79 MIPS_LINUX_SIGXFSZ = 31, 80 81 MIPS_LINUX_SIGRTMIN = 32, 82 MIPS_LINUX_SIGRT64 = 64, 83 MIPS_LINUX_SIGRTMAX = 127, 84 }; 85 86 /* Figure out where the longjmp will land. 87 We expect the first arg to be a pointer to the jmp_buf structure 88 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 89 at. The pc is copied into PC. This routine returns 1 on 90 success. */ 91 92 #define MIPS_LINUX_JB_ELEMENT_SIZE 4 93 #define MIPS_LINUX_JB_PC 0 94 95 static int 96 mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 97 { 98 CORE_ADDR jb_addr; 99 struct gdbarch *gdbarch = get_frame_arch (frame); 100 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 101 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; 102 103 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 104 105 if (target_read_memory ((jb_addr 106 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), 107 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) 108 return 0; 109 110 *pc = extract_unsigned_integer (buf, 111 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, 112 byte_order); 113 114 return 1; 115 } 116 117 /* Transform the bits comprising a 32-bit register to the right size 118 for regcache_raw_supply(). This is needed when mips_isa_regsize() 119 is 8. */ 120 121 static void 122 supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) 123 { 124 regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true); 125 } 126 127 /* Unpack an elf_gregset_t into GDB's register cache. */ 128 129 void 130 mips_supply_gregset (struct regcache *regcache, 131 const mips_elf_gregset_t *gregsetp) 132 { 133 int regi; 134 const mips_elf_greg_t *regp = *gregsetp; 135 struct gdbarch *gdbarch = regcache->arch (); 136 137 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) 138 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); 139 140 if (mips_linux_restart_reg_p (gdbarch)) 141 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); 142 143 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); 144 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); 145 146 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, 147 regp + EF_CP0_EPC); 148 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, 149 regp + EF_CP0_BADVADDR); 150 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); 151 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, 152 regp + EF_CP0_CAUSE); 153 154 /* Fill the inaccessible zero register with zero. */ 155 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); 156 } 157 158 static void 159 mips_supply_gregset_wrapper (const struct regset *regset, 160 struct regcache *regcache, 161 int regnum, const void *gregs, size_t len) 162 { 163 gdb_assert (len >= sizeof (mips_elf_gregset_t)); 164 165 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); 166 } 167 168 /* Pack our registers (or one register) into an elf_gregset_t. */ 169 170 void 171 mips_fill_gregset (const struct regcache *regcache, 172 mips_elf_gregset_t *gregsetp, int regno) 173 { 174 struct gdbarch *gdbarch = regcache->arch (); 175 int regaddr, regi; 176 mips_elf_greg_t *regp = *gregsetp; 177 void *dst; 178 179 if (regno == -1) 180 { 181 memset (regp, 0, sizeof (mips_elf_gregset_t)); 182 for (regi = 1; regi < 32; regi++) 183 mips_fill_gregset (regcache, gregsetp, regi); 184 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); 185 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); 186 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); 187 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); 188 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 189 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); 190 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 191 return; 192 } 193 194 if (regno > 0 && regno < 32) 195 { 196 dst = regp + regno + EF_REG0; 197 regcache->raw_collect (regno, dst); 198 return; 199 } 200 201 if (regno == mips_regnum (gdbarch)->lo) 202 regaddr = EF_LO; 203 else if (regno == mips_regnum (gdbarch)->hi) 204 regaddr = EF_HI; 205 else if (regno == mips_regnum (gdbarch)->pc) 206 regaddr = EF_CP0_EPC; 207 else if (regno == mips_regnum (gdbarch)->badvaddr) 208 regaddr = EF_CP0_BADVADDR; 209 else if (regno == MIPS_PS_REGNUM) 210 regaddr = EF_CP0_STATUS; 211 else if (regno == mips_regnum (gdbarch)->cause) 212 regaddr = EF_CP0_CAUSE; 213 else if (mips_linux_restart_reg_p (gdbarch) 214 && regno == MIPS_RESTART_REGNUM) 215 regaddr = EF_REG0; 216 else 217 regaddr = -1; 218 219 if (regaddr != -1) 220 { 221 dst = regp + regaddr; 222 regcache->raw_collect (regno, dst); 223 } 224 } 225 226 static void 227 mips_fill_gregset_wrapper (const struct regset *regset, 228 const struct regcache *regcache, 229 int regnum, void *gregs, size_t len) 230 { 231 gdb_assert (len >= sizeof (mips_elf_gregset_t)); 232 233 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); 234 } 235 236 /* Support for 64-bit ABIs. */ 237 238 /* Figure out where the longjmp will land. 239 We expect the first arg to be a pointer to the jmp_buf structure 240 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 241 at. The pc is copied into PC. This routine returns 1 on 242 success. */ 243 244 /* Details about jmp_buf. */ 245 246 #define MIPS64_LINUX_JB_PC 0 247 248 static int 249 mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 250 { 251 CORE_ADDR jb_addr; 252 struct gdbarch *gdbarch = get_frame_arch (frame); 253 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 254 gdb_byte *buf 255 = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); 256 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; 257 258 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 259 260 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, 261 buf, 262 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) 263 return 0; 264 265 *pc = extract_unsigned_integer (buf, 266 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, 267 byte_order); 268 269 return 1; 270 } 271 272 /* Register set support functions. These operate on standard 64-bit 273 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit 274 target will still use the 64-bit format for PTRACE_GETREGS. */ 275 276 /* Supply a 64-bit register. */ 277 278 static void 279 supply_64bit_reg (struct regcache *regcache, int regnum, 280 const gdb_byte *buf) 281 { 282 struct gdbarch *gdbarch = regcache->arch (); 283 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 284 && register_size (gdbarch, regnum) == 4) 285 regcache->raw_supply (regnum, buf + 4); 286 else 287 regcache->raw_supply (regnum, buf); 288 } 289 290 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ 291 292 void 293 mips64_supply_gregset (struct regcache *regcache, 294 const mips64_elf_gregset_t *gregsetp) 295 { 296 int regi; 297 const mips64_elf_greg_t *regp = *gregsetp; 298 struct gdbarch *gdbarch = regcache->arch (); 299 300 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) 301 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, 302 (const gdb_byte *) (regp + regi)); 303 304 if (mips_linux_restart_reg_p (gdbarch)) 305 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, 306 (const gdb_byte *) (regp + MIPS64_EF_REG0)); 307 308 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, 309 (const gdb_byte *) (regp + MIPS64_EF_LO)); 310 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, 311 (const gdb_byte *) (regp + MIPS64_EF_HI)); 312 313 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, 314 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); 315 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, 316 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); 317 supply_64bit_reg (regcache, MIPS_PS_REGNUM, 318 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); 319 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, 320 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); 321 322 /* Fill the inaccessible zero register with zero. */ 323 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); 324 } 325 326 static void 327 mips64_supply_gregset_wrapper (const struct regset *regset, 328 struct regcache *regcache, 329 int regnum, const void *gregs, size_t len) 330 { 331 gdb_assert (len >= sizeof (mips64_elf_gregset_t)); 332 333 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); 334 } 335 336 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ 337 338 void 339 mips64_fill_gregset (const struct regcache *regcache, 340 mips64_elf_gregset_t *gregsetp, int regno) 341 { 342 struct gdbarch *gdbarch = regcache->arch (); 343 int regaddr, regi; 344 mips64_elf_greg_t *regp = *gregsetp; 345 void *dst; 346 347 if (regno == -1) 348 { 349 memset (regp, 0, sizeof (mips64_elf_gregset_t)); 350 for (regi = 1; regi < 32; regi++) 351 mips64_fill_gregset (regcache, gregsetp, regi); 352 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); 353 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); 354 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); 355 mips64_fill_gregset (regcache, gregsetp, 356 mips_regnum (gdbarch)->badvaddr); 357 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 358 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); 359 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 360 return; 361 } 362 363 if (regno > 0 && regno < 32) 364 regaddr = regno + MIPS64_EF_REG0; 365 else if (regno == mips_regnum (gdbarch)->lo) 366 regaddr = MIPS64_EF_LO; 367 else if (regno == mips_regnum (gdbarch)->hi) 368 regaddr = MIPS64_EF_HI; 369 else if (regno == mips_regnum (gdbarch)->pc) 370 regaddr = MIPS64_EF_CP0_EPC; 371 else if (regno == mips_regnum (gdbarch)->badvaddr) 372 regaddr = MIPS64_EF_CP0_BADVADDR; 373 else if (regno == MIPS_PS_REGNUM) 374 regaddr = MIPS64_EF_CP0_STATUS; 375 else if (regno == mips_regnum (gdbarch)->cause) 376 regaddr = MIPS64_EF_CP0_CAUSE; 377 else if (mips_linux_restart_reg_p (gdbarch) 378 && regno == MIPS_RESTART_REGNUM) 379 regaddr = MIPS64_EF_REG0; 380 else 381 regaddr = -1; 382 383 if (regaddr != -1) 384 { 385 dst = regp + regaddr; 386 regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true); 387 } 388 } 389 390 static void 391 mips64_fill_gregset_wrapper (const struct regset *regset, 392 const struct regcache *regcache, 393 int regnum, void *gregs, size_t len) 394 { 395 gdb_assert (len >= sizeof (mips64_elf_gregset_t)); 396 397 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); 398 } 399 400 /* Likewise, unpack an elf_fpregset_t. Linux only uses even-numbered 401 FPR slots in the Status.FR=0 mode, storing even-odd FPR pairs as the 402 SDC1 instruction would. When run on MIPS I architecture processors 403 all FPR slots used to be used, unusually, holding the respective FPRs 404 in the first 4 bytes, but that was corrected for consistency, with 405 `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator 406 changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU 407 ptrace() handling fixes."), and then broken and fixed over and over 408 again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct 409 MIPS I FP context layout"). */ 410 411 void 412 mips64_supply_fpregset (struct regcache *regcache, 413 const mips64_elf_fpregset_t *fpregsetp) 414 { 415 struct gdbarch *gdbarch = regcache->arch (); 416 int regi; 417 418 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) 419 for (regi = 0; regi < 32; regi++) 420 { 421 const gdb_byte *reg_ptr 422 = (const gdb_byte *) (*fpregsetp + (regi & ~1)); 423 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) 424 reg_ptr += 4; 425 regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, reg_ptr); 426 } 427 else 428 for (regi = 0; regi < 32; regi++) 429 regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, 430 (const char *) (*fpregsetp + regi)); 431 432 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, 433 (const gdb_byte *) (*fpregsetp + 32)); 434 435 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't 436 include it - but the result of PTRACE_GETFPREGS does. The best we 437 can do is to assume that its value is present. */ 438 supply_32bit_reg (regcache, 439 mips_regnum (gdbarch)->fp_implementation_revision, 440 (const gdb_byte *) (*fpregsetp + 32) + 4); 441 } 442 443 static void 444 mips64_supply_fpregset_wrapper (const struct regset *regset, 445 struct regcache *regcache, 446 int regnum, const void *gregs, size_t len) 447 { 448 gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); 449 450 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); 451 } 452 453 /* Likewise, pack one or all floating point registers into an 454 elf_fpregset_t. See `mips_supply_fpregset' for an explanation 455 of the layout. */ 456 457 void 458 mips64_fill_fpregset (const struct regcache *regcache, 459 mips64_elf_fpregset_t *fpregsetp, int regno) 460 { 461 struct gdbarch *gdbarch = regcache->arch (); 462 gdb_byte *to; 463 464 if ((regno >= gdbarch_fp0_regnum (gdbarch)) 465 && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) 466 { 467 if (register_size (gdbarch, regno) == 4) 468 { 469 int regi = regno - gdbarch_fp0_regnum (gdbarch); 470 471 to = (gdb_byte *) (*fpregsetp + (regi & ~1)); 472 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) 473 to += 4; 474 regcache->raw_collect (regno, to); 475 } 476 else 477 { 478 to = (gdb_byte *) (*fpregsetp + regno 479 - gdbarch_fp0_regnum (gdbarch)); 480 regcache->raw_collect (regno, to); 481 } 482 } 483 else if (regno == mips_regnum (gdbarch)->fp_control_status) 484 { 485 to = (gdb_byte *) (*fpregsetp + 32); 486 regcache->raw_collect_integer (regno, to, 4, true); 487 } 488 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 489 { 490 to = (gdb_byte *) (*fpregsetp + 32) + 4; 491 regcache->raw_collect_integer (regno, to, 4, true); 492 } 493 else if (regno == -1) 494 { 495 int regi; 496 497 for (regi = 0; regi < 32; regi++) 498 mips64_fill_fpregset (regcache, fpregsetp, 499 gdbarch_fp0_regnum (gdbarch) + regi); 500 mips64_fill_fpregset (regcache, fpregsetp, 501 mips_regnum (gdbarch)->fp_control_status); 502 mips64_fill_fpregset (regcache, fpregsetp, 503 mips_regnum (gdbarch)->fp_implementation_revision); 504 } 505 } 506 507 static void 508 mips64_fill_fpregset_wrapper (const struct regset *regset, 509 const struct regcache *regcache, 510 int regnum, void *gregs, size_t len) 511 { 512 gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); 513 514 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); 515 } 516 517 static const struct regset mips_linux_gregset = 518 { 519 NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper 520 }; 521 522 static const struct regset mips64_linux_gregset = 523 { 524 NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper 525 }; 526 527 static const struct regset mips64_linux_fpregset = 528 { 529 NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper 530 }; 531 532 static void 533 mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, 534 iterate_over_regset_sections_cb *cb, 535 void *cb_data, 536 const struct regcache *regcache) 537 { 538 if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4) 539 { 540 cb (".reg", sizeof (mips_elf_gregset_t), sizeof (mips_elf_gregset_t), 541 &mips_linux_gregset, NULL, cb_data); 542 cb (".reg2", sizeof (mips64_elf_fpregset_t), 543 sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, 544 NULL, cb_data); 545 } 546 else 547 { 548 cb (".reg", sizeof (mips64_elf_gregset_t), sizeof (mips64_elf_gregset_t), 549 &mips64_linux_gregset, NULL, cb_data); 550 cb (".reg2", sizeof (mips64_elf_fpregset_t), 551 sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, 552 NULL, cb_data); 553 } 554 } 555 556 static const struct target_desc * 557 mips_linux_core_read_description (struct gdbarch *gdbarch, 558 struct target_ops *target, 559 bfd *abfd) 560 { 561 asection *section = bfd_get_section_by_name (abfd, ".reg"); 562 if (! section) 563 return NULL; 564 565 switch (bfd_section_size (section)) 566 { 567 case sizeof (mips_elf_gregset_t): 568 return mips_tdesc_gp32; 569 570 case sizeof (mips64_elf_gregset_t): 571 return mips_tdesc_gp64; 572 573 default: 574 return NULL; 575 } 576 } 577 578 579 /* Check the code at PC for a dynamic linker lazy resolution stub. 580 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" 581 section uniformly since version 2.15. If the pc is in that section, 582 then we are in such a stub. Before that ".stub" was used in 32-bit 583 ELF binaries, however we do not bother checking for that since we 584 have never had and that case should be extremely rare these days. 585 Instead we pattern-match on the code generated by GNU ld. They look 586 like this: 587 588 lw t9,0x8010(gp) 589 addu t7,ra 590 jalr t9,ra 591 addiu t8,zero,INDEX 592 593 (with the appropriate doubleword instructions for N64). As any lazy 594 resolution stubs in microMIPS binaries will always be in a 595 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ 596 597 static int 598 mips_linux_in_dynsym_stub (CORE_ADDR pc) 599 { 600 gdb_byte buf[28], *p; 601 ULONGEST insn, insn1; 602 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); 603 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 604 605 if (in_mips_stubs_section (pc)) 606 return 1; 607 608 read_memory (pc - 12, buf, 28); 609 610 if (n64) 611 { 612 /* ld t9,0x8010(gp) */ 613 insn1 = 0xdf998010; 614 } 615 else 616 { 617 /* lw t9,0x8010(gp) */ 618 insn1 = 0x8f998010; 619 } 620 621 p = buf + 12; 622 while (p >= buf) 623 { 624 insn = extract_unsigned_integer (p, 4, byte_order); 625 if (insn == insn1) 626 break; 627 p -= 4; 628 } 629 if (p < buf) 630 return 0; 631 632 insn = extract_unsigned_integer (p + 4, 4, byte_order); 633 if (n64) 634 { 635 /* 'daddu t7,ra' or 'or t7, ra, zero'*/ 636 if (insn != 0x03e0782d && insn != 0x03e07825) 637 return 0; 638 } 639 else 640 { 641 /* 'addu t7,ra' or 'or t7, ra, zero'*/ 642 if (insn != 0x03e07821 && insn != 0x03e07825) 643 return 0; 644 } 645 646 insn = extract_unsigned_integer (p + 8, 4, byte_order); 647 /* jalr t9,ra */ 648 if (insn != 0x0320f809) 649 return 0; 650 651 insn = extract_unsigned_integer (p + 12, 4, byte_order); 652 if (n64) 653 { 654 /* daddiu t8,zero,0 */ 655 if ((insn & 0xffff0000) != 0x64180000) 656 return 0; 657 } 658 else 659 { 660 /* addiu t8,zero,0 */ 661 if ((insn & 0xffff0000) != 0x24180000) 662 return 0; 663 } 664 665 return 1; 666 } 667 668 /* Return non-zero iff PC belongs to the dynamic linker resolution 669 code, a PLT entry, or a lazy binding stub. */ 670 671 static int 672 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) 673 { 674 /* Check whether PC is in the dynamic linker. This also checks 675 whether it is in the .plt section, used by non-PIC executables. */ 676 if (svr4_in_dynsym_resolve_code (pc)) 677 return 1; 678 679 /* Likewise for the stubs. They live in the .MIPS.stubs section these 680 days, so we check if the PC is within, than fall back to a pattern 681 match. */ 682 if (mips_linux_in_dynsym_stub (pc)) 683 return 1; 684 685 return 0; 686 } 687 688 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, 689 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc 690 implementation of this triggers at "fixup" from the same objfile as 691 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at 692 "__dl_runtime_resolve" directly. An unresolved lazy binding 693 stub will point to _dl_runtime_resolve, which will first call 694 __dl_runtime_resolve, and then pass control to the resolved 695 function. */ 696 697 static CORE_ADDR 698 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) 699 { 700 struct bound_minimal_symbol resolver; 701 702 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); 703 704 if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc) 705 return frame_unwind_caller_pc (get_current_frame ()); 706 707 return glibc_skip_solib_resolver (gdbarch, pc); 708 } 709 710 /* Signal trampoline support. There are four supported layouts for a 711 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and 712 n64 rt_sigframe. We handle them all independently; not the most 713 efficient way, but simplest. First, declare all the unwinders. */ 714 715 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, 716 struct frame_info *this_frame, 717 struct trad_frame_cache *this_cache, 718 CORE_ADDR func); 719 720 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 721 struct frame_info *this_frame, 722 struct trad_frame_cache *this_cache, 723 CORE_ADDR func); 724 725 static int mips_linux_sigframe_validate (const struct tramp_frame *self, 726 struct frame_info *this_frame, 727 CORE_ADDR *pc); 728 729 static int micromips_linux_sigframe_validate (const struct tramp_frame *self, 730 struct frame_info *this_frame, 731 CORE_ADDR *pc); 732 733 #define MIPS_NR_LINUX 4000 734 #define MIPS_NR_N64_LINUX 5000 735 #define MIPS_NR_N32_LINUX 6000 736 737 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 738 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 739 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 740 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 741 742 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn 743 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn 744 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn 745 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn 746 #define MIPS_INST_SYSCALL 0x0000000c 747 748 #define MICROMIPS_INST_LI_V0 0x3040 749 #define MICROMIPS_INST_POOL32A 0x0000 750 #define MICROMIPS_INST_SYSCALL 0x8b7c 751 752 static const struct tramp_frame mips_linux_o32_sigframe = { 753 SIGTRAMP_FRAME, 754 4, 755 { 756 { MIPS_INST_LI_V0_SIGRETURN, ULONGEST_MAX }, 757 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 758 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 759 }, 760 mips_linux_o32_sigframe_init, 761 mips_linux_sigframe_validate 762 }; 763 764 static const struct tramp_frame mips_linux_o32_rt_sigframe = { 765 SIGTRAMP_FRAME, 766 4, 767 { 768 { MIPS_INST_LI_V0_RT_SIGRETURN, ULONGEST_MAX }, 769 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 770 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } }, 771 mips_linux_o32_sigframe_init, 772 mips_linux_sigframe_validate 773 }; 774 775 static const struct tramp_frame mips_linux_n32_rt_sigframe = { 776 SIGTRAMP_FRAME, 777 4, 778 { 779 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, ULONGEST_MAX }, 780 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 781 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 782 }, 783 mips_linux_n32n64_sigframe_init, 784 mips_linux_sigframe_validate 785 }; 786 787 static const struct tramp_frame mips_linux_n64_rt_sigframe = { 788 SIGTRAMP_FRAME, 789 4, 790 { 791 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, ULONGEST_MAX }, 792 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 793 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 794 }, 795 mips_linux_n32n64_sigframe_init, 796 mips_linux_sigframe_validate 797 }; 798 799 static const struct tramp_frame micromips_linux_o32_sigframe = { 800 SIGTRAMP_FRAME, 801 2, 802 { 803 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 804 { MIPS_NR_sigreturn, ULONGEST_MAX }, 805 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 806 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 807 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 808 }, 809 mips_linux_o32_sigframe_init, 810 micromips_linux_sigframe_validate 811 }; 812 813 static const struct tramp_frame micromips_linux_o32_rt_sigframe = { 814 SIGTRAMP_FRAME, 815 2, 816 { 817 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 818 { MIPS_NR_rt_sigreturn, ULONGEST_MAX }, 819 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 820 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 821 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 822 }, 823 mips_linux_o32_sigframe_init, 824 micromips_linux_sigframe_validate 825 }; 826 827 static const struct tramp_frame micromips_linux_n32_rt_sigframe = { 828 SIGTRAMP_FRAME, 829 2, 830 { 831 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 832 { MIPS_NR_N32_rt_sigreturn, ULONGEST_MAX }, 833 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 834 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 835 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 836 }, 837 mips_linux_n32n64_sigframe_init, 838 micromips_linux_sigframe_validate 839 }; 840 841 static const struct tramp_frame micromips_linux_n64_rt_sigframe = { 842 SIGTRAMP_FRAME, 843 2, 844 { 845 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 846 { MIPS_NR_N64_rt_sigreturn, ULONGEST_MAX }, 847 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 848 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 849 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 850 }, 851 mips_linux_n32n64_sigframe_init, 852 micromips_linux_sigframe_validate 853 }; 854 855 /* *INDENT-OFF* */ 856 /* The unwinder for o32 signal frames. The legacy structures look 857 like this: 858 859 struct sigframe { 860 u32 sf_ass[4]; [argument save space for o32] 861 u32 sf_code[2]; [signal trampoline or fill] 862 struct sigcontext sf_sc; 863 sigset_t sf_mask; 864 }; 865 866 Pre-2.6.12 sigcontext: 867 868 struct sigcontext { 869 unsigned int sc_regmask; [Unused] 870 unsigned int sc_status; 871 unsigned long long sc_pc; 872 unsigned long long sc_regs[32]; 873 unsigned long long sc_fpregs[32]; 874 unsigned int sc_ownedfp; 875 unsigned int sc_fpc_csr; 876 unsigned int sc_fpc_eir; [Unused] 877 unsigned int sc_used_math; 878 unsigned int sc_ssflags; [Unused] 879 [Alignment hole of four bytes] 880 unsigned long long sc_mdhi; 881 unsigned long long sc_mdlo; 882 883 unsigned int sc_cause; [Unused] 884 unsigned int sc_badvaddr; [Unused] 885 886 unsigned long sc_sigset[4]; [kernel's sigset_t] 887 }; 888 889 Post-2.6.12 sigcontext (SmartMIPS/DSP support added): 890 891 struct sigcontext { 892 unsigned int sc_regmask; [Unused] 893 unsigned int sc_status; [Unused] 894 unsigned long long sc_pc; 895 unsigned long long sc_regs[32]; 896 unsigned long long sc_fpregs[32]; 897 unsigned int sc_acx; 898 unsigned int sc_fpc_csr; 899 unsigned int sc_fpc_eir; [Unused] 900 unsigned int sc_used_math; 901 unsigned int sc_dsp; 902 [Alignment hole of four bytes] 903 unsigned long long sc_mdhi; 904 unsigned long long sc_mdlo; 905 unsigned long sc_hi1; 906 unsigned long sc_lo1; 907 unsigned long sc_hi2; 908 unsigned long sc_lo2; 909 unsigned long sc_hi3; 910 unsigned long sc_lo3; 911 }; 912 913 The RT signal frames look like this: 914 915 struct rt_sigframe { 916 u32 rs_ass[4]; [argument save space for o32] 917 u32 rs_code[2] [signal trampoline or fill] 918 struct siginfo rs_info; 919 struct ucontext rs_uc; 920 }; 921 922 struct ucontext { 923 unsigned long uc_flags; 924 struct ucontext *uc_link; 925 stack_t uc_stack; 926 [Alignment hole of four bytes] 927 struct sigcontext uc_mcontext; 928 sigset_t uc_sigmask; 929 }; */ 930 /* *INDENT-ON* */ 931 932 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) 933 934 #define RTSIGFRAME_SIGINFO_SIZE 128 935 #define STACK_T_SIZE (3 * 4) 936 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) 937 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 938 + RTSIGFRAME_SIGINFO_SIZE \ 939 + UCONTEXT_SIGCONTEXT_OFFSET) 940 941 #define SIGCONTEXT_PC (1 * 8) 942 #define SIGCONTEXT_REGS (2 * 8) 943 #define SIGCONTEXT_FPREGS (34 * 8) 944 #define SIGCONTEXT_FPCSR (66 * 8 + 4) 945 #define SIGCONTEXT_DSPCTL (68 * 8 + 0) 946 #define SIGCONTEXT_HI (69 * 8) 947 #define SIGCONTEXT_LO (70 * 8) 948 #define SIGCONTEXT_CAUSE (71 * 8 + 0) 949 #define SIGCONTEXT_BADVADDR (71 * 8 + 4) 950 #define SIGCONTEXT_HI1 (71 * 8 + 0) 951 #define SIGCONTEXT_LO1 (71 * 8 + 4) 952 #define SIGCONTEXT_HI2 (72 * 8 + 0) 953 #define SIGCONTEXT_LO2 (72 * 8 + 4) 954 #define SIGCONTEXT_HI3 (73 * 8 + 0) 955 #define SIGCONTEXT_LO3 (73 * 8 + 4) 956 957 #define SIGCONTEXT_REG_SIZE 8 958 959 static void 960 mips_linux_o32_sigframe_init (const struct tramp_frame *self, 961 struct frame_info *this_frame, 962 struct trad_frame_cache *this_cache, 963 CORE_ADDR func) 964 { 965 struct gdbarch *gdbarch = get_frame_arch (this_frame); 966 int ireg; 967 CORE_ADDR frame_sp = get_frame_sp (this_frame); 968 CORE_ADDR sigcontext_base; 969 const struct mips_regnum *regs = mips_regnum (gdbarch); 970 CORE_ADDR regs_base; 971 972 if (self == &mips_linux_o32_sigframe 973 || self == µmips_linux_o32_sigframe) 974 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; 975 else 976 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; 977 978 /* I'm not proud of this hack. Eventually we will have the 979 infrastructure to indicate the size of saved registers on a 980 per-frame basis, but right now we don't; the kernel saves eight 981 bytes but we only want four. Use regs_base to access any 982 64-bit fields. */ 983 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 984 regs_base = sigcontext_base + 4; 985 else 986 regs_base = sigcontext_base; 987 988 if (mips_linux_restart_reg_p (gdbarch)) 989 trad_frame_set_reg_addr (this_cache, 990 (MIPS_RESTART_REGNUM 991 + gdbarch_num_regs (gdbarch)), 992 regs_base + SIGCONTEXT_REGS); 993 994 for (ireg = 1; ireg < 32; ireg++) 995 trad_frame_set_reg_addr (this_cache, 996 (ireg + MIPS_ZERO_REGNUM 997 + gdbarch_num_regs (gdbarch)), 998 (regs_base + SIGCONTEXT_REGS 999 + ireg * SIGCONTEXT_REG_SIZE)); 1000 1001 for (ireg = 0; ireg < 32; ireg++) 1002 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) 1003 trad_frame_set_reg_addr (this_cache, 1004 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1005 (sigcontext_base + SIGCONTEXT_FPREGS + 4 1006 + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); 1007 else 1008 trad_frame_set_reg_addr (this_cache, 1009 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1010 (sigcontext_base + SIGCONTEXT_FPREGS 1011 + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); 1012 1013 trad_frame_set_reg_addr (this_cache, 1014 regs->pc + gdbarch_num_regs (gdbarch), 1015 regs_base + SIGCONTEXT_PC); 1016 1017 trad_frame_set_reg_addr (this_cache, 1018 (regs->fp_control_status 1019 + gdbarch_num_regs (gdbarch)), 1020 sigcontext_base + SIGCONTEXT_FPCSR); 1021 1022 if (regs->dspctl != -1) 1023 trad_frame_set_reg_addr (this_cache, 1024 regs->dspctl + gdbarch_num_regs (gdbarch), 1025 sigcontext_base + SIGCONTEXT_DSPCTL); 1026 1027 trad_frame_set_reg_addr (this_cache, 1028 regs->hi + gdbarch_num_regs (gdbarch), 1029 regs_base + SIGCONTEXT_HI); 1030 trad_frame_set_reg_addr (this_cache, 1031 regs->lo + gdbarch_num_regs (gdbarch), 1032 regs_base + SIGCONTEXT_LO); 1033 1034 if (regs->dspacc != -1) 1035 { 1036 trad_frame_set_reg_addr (this_cache, 1037 regs->dspacc + 0 + gdbarch_num_regs (gdbarch), 1038 sigcontext_base + SIGCONTEXT_HI1); 1039 trad_frame_set_reg_addr (this_cache, 1040 regs->dspacc + 1 + gdbarch_num_regs (gdbarch), 1041 sigcontext_base + SIGCONTEXT_LO1); 1042 trad_frame_set_reg_addr (this_cache, 1043 regs->dspacc + 2 + gdbarch_num_regs (gdbarch), 1044 sigcontext_base + SIGCONTEXT_HI2); 1045 trad_frame_set_reg_addr (this_cache, 1046 regs->dspacc + 3 + gdbarch_num_regs (gdbarch), 1047 sigcontext_base + SIGCONTEXT_LO2); 1048 trad_frame_set_reg_addr (this_cache, 1049 regs->dspacc + 4 + gdbarch_num_regs (gdbarch), 1050 sigcontext_base + SIGCONTEXT_HI3); 1051 trad_frame_set_reg_addr (this_cache, 1052 regs->dspacc + 5 + gdbarch_num_regs (gdbarch), 1053 sigcontext_base + SIGCONTEXT_LO3); 1054 } 1055 else 1056 { 1057 trad_frame_set_reg_addr (this_cache, 1058 regs->cause + gdbarch_num_regs (gdbarch), 1059 sigcontext_base + SIGCONTEXT_CAUSE); 1060 trad_frame_set_reg_addr (this_cache, 1061 regs->badvaddr + gdbarch_num_regs (gdbarch), 1062 sigcontext_base + SIGCONTEXT_BADVADDR); 1063 } 1064 1065 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 1066 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); 1067 } 1068 1069 /* *INDENT-OFF* */ 1070 /* For N32/N64 things look different. There is no non-rt signal frame. 1071 1072 struct rt_sigframe_n32 { 1073 u32 rs_ass[4]; [ argument save space for o32 ] 1074 u32 rs_code[2]; [ signal trampoline or fill ] 1075 struct siginfo rs_info; 1076 struct ucontextn32 rs_uc; 1077 }; 1078 1079 struct ucontextn32 { 1080 u32 uc_flags; 1081 s32 uc_link; 1082 stack32_t uc_stack; 1083 struct sigcontext uc_mcontext; 1084 sigset_t uc_sigmask; [ mask last for extensibility ] 1085 }; 1086 1087 struct rt_sigframe { 1088 u32 rs_ass[4]; [ argument save space for o32 ] 1089 u32 rs_code[2]; [ signal trampoline ] 1090 struct siginfo rs_info; 1091 struct ucontext rs_uc; 1092 }; 1093 1094 struct ucontext { 1095 unsigned long uc_flags; 1096 struct ucontext *uc_link; 1097 stack_t uc_stack; 1098 struct sigcontext uc_mcontext; 1099 sigset_t uc_sigmask; [ mask last for extensibility ] 1100 }; 1101 1102 And the sigcontext is different (this is for both n32 and n64): 1103 1104 struct sigcontext { 1105 unsigned long long sc_regs[32]; 1106 unsigned long long sc_fpregs[32]; 1107 unsigned long long sc_mdhi; 1108 unsigned long long sc_hi1; 1109 unsigned long long sc_hi2; 1110 unsigned long long sc_hi3; 1111 unsigned long long sc_mdlo; 1112 unsigned long long sc_lo1; 1113 unsigned long long sc_lo2; 1114 unsigned long long sc_lo3; 1115 unsigned long long sc_pc; 1116 unsigned int sc_fpc_csr; 1117 unsigned int sc_used_math; 1118 unsigned int sc_dsp; 1119 unsigned int sc_reserved; 1120 }; 1121 1122 That is the post-2.6.12 definition of the 64-bit sigcontext; before 1123 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were 1124 included too. */ 1125 /* *INDENT-ON* */ 1126 1127 #define N32_STACK_T_SIZE STACK_T_SIZE 1128 #define N64_STACK_T_SIZE (2 * 8 + 4) 1129 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) 1130 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) 1131 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 1132 + RTSIGFRAME_SIGINFO_SIZE \ 1133 + N32_UCONTEXT_SIGCONTEXT_OFFSET) 1134 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 1135 + RTSIGFRAME_SIGINFO_SIZE \ 1136 + N64_UCONTEXT_SIGCONTEXT_OFFSET) 1137 1138 #define N64_SIGCONTEXT_REGS (0 * 8) 1139 #define N64_SIGCONTEXT_FPREGS (32 * 8) 1140 #define N64_SIGCONTEXT_HI (64 * 8) 1141 #define N64_SIGCONTEXT_HI1 (65 * 8) 1142 #define N64_SIGCONTEXT_HI2 (66 * 8) 1143 #define N64_SIGCONTEXT_HI3 (67 * 8) 1144 #define N64_SIGCONTEXT_LO (68 * 8) 1145 #define N64_SIGCONTEXT_LO1 (69 * 8) 1146 #define N64_SIGCONTEXT_LO2 (70 * 8) 1147 #define N64_SIGCONTEXT_LO3 (71 * 8) 1148 #define N64_SIGCONTEXT_PC (72 * 8) 1149 #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) 1150 #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) 1151 1152 #define N64_SIGCONTEXT_REG_SIZE 8 1153 1154 static void 1155 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 1156 struct frame_info *this_frame, 1157 struct trad_frame_cache *this_cache, 1158 CORE_ADDR func) 1159 { 1160 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1161 int ireg; 1162 CORE_ADDR frame_sp = get_frame_sp (this_frame); 1163 CORE_ADDR sigcontext_base; 1164 const struct mips_regnum *regs = mips_regnum (gdbarch); 1165 1166 if (self == &mips_linux_n32_rt_sigframe 1167 || self == µmips_linux_n32_rt_sigframe) 1168 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; 1169 else 1170 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; 1171 1172 if (mips_linux_restart_reg_p (gdbarch)) 1173 trad_frame_set_reg_addr (this_cache, 1174 (MIPS_RESTART_REGNUM 1175 + gdbarch_num_regs (gdbarch)), 1176 sigcontext_base + N64_SIGCONTEXT_REGS); 1177 1178 for (ireg = 1; ireg < 32; ireg++) 1179 trad_frame_set_reg_addr (this_cache, 1180 (ireg + MIPS_ZERO_REGNUM 1181 + gdbarch_num_regs (gdbarch)), 1182 (sigcontext_base + N64_SIGCONTEXT_REGS 1183 + ireg * N64_SIGCONTEXT_REG_SIZE)); 1184 1185 for (ireg = 0; ireg < 32; ireg++) 1186 trad_frame_set_reg_addr (this_cache, 1187 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1188 (sigcontext_base + N64_SIGCONTEXT_FPREGS 1189 + ireg * N64_SIGCONTEXT_REG_SIZE)); 1190 1191 trad_frame_set_reg_addr (this_cache, 1192 regs->pc + gdbarch_num_regs (gdbarch), 1193 sigcontext_base + N64_SIGCONTEXT_PC); 1194 1195 trad_frame_set_reg_addr (this_cache, 1196 (regs->fp_control_status 1197 + gdbarch_num_regs (gdbarch)), 1198 sigcontext_base + N64_SIGCONTEXT_FPCSR); 1199 1200 trad_frame_set_reg_addr (this_cache, 1201 regs->hi + gdbarch_num_regs (gdbarch), 1202 sigcontext_base + N64_SIGCONTEXT_HI); 1203 trad_frame_set_reg_addr (this_cache, 1204 regs->lo + gdbarch_num_regs (gdbarch), 1205 sigcontext_base + N64_SIGCONTEXT_LO); 1206 1207 if (regs->dspacc != -1) 1208 { 1209 trad_frame_set_reg_addr (this_cache, 1210 regs->dspacc + 0 + gdbarch_num_regs (gdbarch), 1211 sigcontext_base + N64_SIGCONTEXT_HI1); 1212 trad_frame_set_reg_addr (this_cache, 1213 regs->dspacc + 1 + gdbarch_num_regs (gdbarch), 1214 sigcontext_base + N64_SIGCONTEXT_LO1); 1215 trad_frame_set_reg_addr (this_cache, 1216 regs->dspacc + 2 + gdbarch_num_regs (gdbarch), 1217 sigcontext_base + N64_SIGCONTEXT_HI2); 1218 trad_frame_set_reg_addr (this_cache, 1219 regs->dspacc + 3 + gdbarch_num_regs (gdbarch), 1220 sigcontext_base + N64_SIGCONTEXT_LO2); 1221 trad_frame_set_reg_addr (this_cache, 1222 regs->dspacc + 4 + gdbarch_num_regs (gdbarch), 1223 sigcontext_base + N64_SIGCONTEXT_HI3); 1224 trad_frame_set_reg_addr (this_cache, 1225 regs->dspacc + 5 + gdbarch_num_regs (gdbarch), 1226 sigcontext_base + N64_SIGCONTEXT_LO3); 1227 } 1228 if (regs->dspctl != -1) 1229 trad_frame_set_reg_addr (this_cache, 1230 regs->dspctl + gdbarch_num_regs (gdbarch), 1231 sigcontext_base + N64_SIGCONTEXT_DSPCTL); 1232 1233 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 1234 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); 1235 } 1236 1237 /* Implement struct tramp_frame's "validate" method for standard MIPS code. */ 1238 1239 static int 1240 mips_linux_sigframe_validate (const struct tramp_frame *self, 1241 struct frame_info *this_frame, 1242 CORE_ADDR *pc) 1243 { 1244 return mips_pc_is_mips (*pc); 1245 } 1246 1247 /* Implement struct tramp_frame's "validate" method for microMIPS code. */ 1248 1249 static int 1250 micromips_linux_sigframe_validate (const struct tramp_frame *self, 1251 struct frame_info *this_frame, 1252 CORE_ADDR *pc) 1253 { 1254 if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc)) 1255 { 1256 *pc = mips_unmake_compact_addr (*pc); 1257 return 1; 1258 } 1259 else 1260 return 0; 1261 } 1262 1263 /* Implement the "write_pc" gdbarch method. */ 1264 1265 static void 1266 mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) 1267 { 1268 struct gdbarch *gdbarch = regcache->arch (); 1269 1270 mips_write_pc (regcache, pc); 1271 1272 /* Clear the syscall restart flag. */ 1273 if (mips_linux_restart_reg_p (gdbarch)) 1274 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); 1275 } 1276 1277 /* Return 1 if MIPS_RESTART_REGNUM is usable. */ 1278 1279 int 1280 mips_linux_restart_reg_p (struct gdbarch *gdbarch) 1281 { 1282 /* If we do not have a target description with registers, then 1283 MIPS_RESTART_REGNUM will not be included in the register set. */ 1284 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) 1285 return 0; 1286 1287 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will 1288 either be GPR-sized or missing. */ 1289 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; 1290 } 1291 1292 /* When FRAME is at a syscall instruction, return the PC of the next 1293 instruction to be executed. */ 1294 1295 static CORE_ADDR 1296 mips_linux_syscall_next_pc (struct frame_info *frame) 1297 { 1298 CORE_ADDR pc = get_frame_pc (frame); 1299 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); 1300 1301 /* If we are about to make a sigreturn syscall, use the unwinder to 1302 decode the signal frame. */ 1303 if (v0 == MIPS_NR_sigreturn 1304 || v0 == MIPS_NR_rt_sigreturn 1305 || v0 == MIPS_NR_N64_rt_sigreturn 1306 || v0 == MIPS_NR_N32_rt_sigreturn) 1307 return frame_unwind_caller_pc (get_current_frame ()); 1308 1309 return pc + 4; 1310 } 1311 1312 /* Return the current system call's number present in the 1313 v0 register. When the function fails, it returns -1. */ 1314 1315 static LONGEST 1316 mips_linux_get_syscall_number (struct gdbarch *gdbarch, 1317 thread_info *thread) 1318 { 1319 struct regcache *regcache = get_thread_regcache (thread); 1320 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1321 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1322 int regsize = register_size (gdbarch, MIPS_V0_REGNUM); 1323 /* The content of a register */ 1324 gdb_byte buf[8]; 1325 /* The result */ 1326 LONGEST ret; 1327 1328 /* Make sure we're in a known ABI */ 1329 gdb_assert (tdep->mips_abi == MIPS_ABI_O32 1330 || tdep->mips_abi == MIPS_ABI_N32 1331 || tdep->mips_abi == MIPS_ABI_N64); 1332 1333 gdb_assert (regsize <= sizeof (buf)); 1334 1335 /* Getting the system call number from the register. 1336 syscall number is in v0 or $2. */ 1337 regcache->cooked_read (MIPS_V0_REGNUM, buf); 1338 1339 ret = extract_signed_integer (buf, regsize, byte_order); 1340 1341 return ret; 1342 } 1343 1344 /* Implementation of `gdbarch_gdb_signal_to_target', as defined in 1345 gdbarch.h. */ 1346 1347 static int 1348 mips_gdb_signal_to_target (struct gdbarch *gdbarch, 1349 enum gdb_signal signal) 1350 { 1351 switch (signal) 1352 { 1353 case GDB_SIGNAL_EMT: 1354 return MIPS_LINUX_SIGEMT; 1355 1356 case GDB_SIGNAL_BUS: 1357 return MIPS_LINUX_SIGBUS; 1358 1359 case GDB_SIGNAL_SYS: 1360 return MIPS_LINUX_SIGSYS; 1361 1362 case GDB_SIGNAL_USR1: 1363 return MIPS_LINUX_SIGUSR1; 1364 1365 case GDB_SIGNAL_USR2: 1366 return MIPS_LINUX_SIGUSR2; 1367 1368 case GDB_SIGNAL_CHLD: 1369 return MIPS_LINUX_SIGCHLD; 1370 1371 case GDB_SIGNAL_PWR: 1372 return MIPS_LINUX_SIGPWR; 1373 1374 case GDB_SIGNAL_WINCH: 1375 return MIPS_LINUX_SIGWINCH; 1376 1377 case GDB_SIGNAL_URG: 1378 return MIPS_LINUX_SIGURG; 1379 1380 case GDB_SIGNAL_IO: 1381 return MIPS_LINUX_SIGIO; 1382 1383 case GDB_SIGNAL_POLL: 1384 return MIPS_LINUX_SIGPOLL; 1385 1386 case GDB_SIGNAL_STOP: 1387 return MIPS_LINUX_SIGSTOP; 1388 1389 case GDB_SIGNAL_TSTP: 1390 return MIPS_LINUX_SIGTSTP; 1391 1392 case GDB_SIGNAL_CONT: 1393 return MIPS_LINUX_SIGCONT; 1394 1395 case GDB_SIGNAL_TTIN: 1396 return MIPS_LINUX_SIGTTIN; 1397 1398 case GDB_SIGNAL_TTOU: 1399 return MIPS_LINUX_SIGTTOU; 1400 1401 case GDB_SIGNAL_VTALRM: 1402 return MIPS_LINUX_SIGVTALRM; 1403 1404 case GDB_SIGNAL_PROF: 1405 return MIPS_LINUX_SIGPROF; 1406 1407 case GDB_SIGNAL_XCPU: 1408 return MIPS_LINUX_SIGXCPU; 1409 1410 case GDB_SIGNAL_XFSZ: 1411 return MIPS_LINUX_SIGXFSZ; 1412 1413 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, 1414 therefore we have to handle it here. */ 1415 case GDB_SIGNAL_REALTIME_32: 1416 return MIPS_LINUX_SIGRTMIN; 1417 } 1418 1419 if (signal >= GDB_SIGNAL_REALTIME_33 1420 && signal <= GDB_SIGNAL_REALTIME_63) 1421 { 1422 int offset = signal - GDB_SIGNAL_REALTIME_33; 1423 1424 return MIPS_LINUX_SIGRTMIN + 1 + offset; 1425 } 1426 else if (signal >= GDB_SIGNAL_REALTIME_64 1427 && signal <= GDB_SIGNAL_REALTIME_127) 1428 { 1429 int offset = signal - GDB_SIGNAL_REALTIME_64; 1430 1431 return MIPS_LINUX_SIGRT64 + offset; 1432 } 1433 1434 return linux_gdb_signal_to_target (gdbarch, signal); 1435 } 1436 1437 /* Translate signals based on MIPS signal values. 1438 Adapted from gdb/gdbsupport/signals.c. */ 1439 1440 static enum gdb_signal 1441 mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) 1442 { 1443 switch (signal) 1444 { 1445 case MIPS_LINUX_SIGEMT: 1446 return GDB_SIGNAL_EMT; 1447 1448 case MIPS_LINUX_SIGBUS: 1449 return GDB_SIGNAL_BUS; 1450 1451 case MIPS_LINUX_SIGSYS: 1452 return GDB_SIGNAL_SYS; 1453 1454 case MIPS_LINUX_SIGUSR1: 1455 return GDB_SIGNAL_USR1; 1456 1457 case MIPS_LINUX_SIGUSR2: 1458 return GDB_SIGNAL_USR2; 1459 1460 case MIPS_LINUX_SIGCHLD: 1461 return GDB_SIGNAL_CHLD; 1462 1463 case MIPS_LINUX_SIGPWR: 1464 return GDB_SIGNAL_PWR; 1465 1466 case MIPS_LINUX_SIGWINCH: 1467 return GDB_SIGNAL_WINCH; 1468 1469 case MIPS_LINUX_SIGURG: 1470 return GDB_SIGNAL_URG; 1471 1472 /* No way to differentiate between SIGIO and SIGPOLL. 1473 Therefore, we just handle the first one. */ 1474 case MIPS_LINUX_SIGIO: 1475 return GDB_SIGNAL_IO; 1476 1477 case MIPS_LINUX_SIGSTOP: 1478 return GDB_SIGNAL_STOP; 1479 1480 case MIPS_LINUX_SIGTSTP: 1481 return GDB_SIGNAL_TSTP; 1482 1483 case MIPS_LINUX_SIGCONT: 1484 return GDB_SIGNAL_CONT; 1485 1486 case MIPS_LINUX_SIGTTIN: 1487 return GDB_SIGNAL_TTIN; 1488 1489 case MIPS_LINUX_SIGTTOU: 1490 return GDB_SIGNAL_TTOU; 1491 1492 case MIPS_LINUX_SIGVTALRM: 1493 return GDB_SIGNAL_VTALRM; 1494 1495 case MIPS_LINUX_SIGPROF: 1496 return GDB_SIGNAL_PROF; 1497 1498 case MIPS_LINUX_SIGXCPU: 1499 return GDB_SIGNAL_XCPU; 1500 1501 case MIPS_LINUX_SIGXFSZ: 1502 return GDB_SIGNAL_XFSZ; 1503 } 1504 1505 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) 1506 { 1507 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of 1508 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ 1509 int offset = signal - MIPS_LINUX_SIGRTMIN; 1510 1511 if (offset == 0) 1512 return GDB_SIGNAL_REALTIME_32; 1513 else if (offset < 32) 1514 return (enum gdb_signal) (offset - 1 1515 + (int) GDB_SIGNAL_REALTIME_33); 1516 else 1517 return (enum gdb_signal) (offset - 32 1518 + (int) GDB_SIGNAL_REALTIME_64); 1519 } 1520 1521 return linux_gdb_signal_from_target (gdbarch, signal); 1522 } 1523 1524 /* Initialize one of the GNU/Linux OS ABIs. */ 1525 1526 static void 1527 mips_linux_init_abi (struct gdbarch_info info, 1528 struct gdbarch *gdbarch) 1529 { 1530 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1531 enum mips_abi abi = mips_abi (gdbarch); 1532 struct tdesc_arch_data *tdesc_data = info.tdesc_data; 1533 1534 linux_init_abi (info, gdbarch); 1535 1536 /* Get the syscall number from the arch's register. */ 1537 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); 1538 1539 switch (abi) 1540 { 1541 case MIPS_ABI_O32: 1542 set_gdbarch_get_longjmp_target (gdbarch, 1543 mips_linux_get_longjmp_target); 1544 set_solib_svr4_fetch_link_map_offsets 1545 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1546 tramp_frame_prepend_unwinder (gdbarch, µmips_linux_o32_sigframe); 1547 tramp_frame_prepend_unwinder (gdbarch, 1548 µmips_linux_o32_rt_sigframe); 1549 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); 1550 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); 1551 set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml"); 1552 break; 1553 case MIPS_ABI_N32: 1554 set_gdbarch_get_longjmp_target (gdbarch, 1555 mips_linux_get_longjmp_target); 1556 set_solib_svr4_fetch_link_map_offsets 1557 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1558 set_gdbarch_long_double_bit (gdbarch, 128); 1559 /* These floatformats should probably be renamed. MIPS uses 1560 the same 128-bit IEEE floating point format that IA-64 uses, 1561 except that the quiet/signalling NaN bit is reversed (GDB 1562 does not distinguish between quiet and signalling NaNs). */ 1563 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1564 tramp_frame_prepend_unwinder (gdbarch, 1565 µmips_linux_n32_rt_sigframe); 1566 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); 1567 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml"); 1568 break; 1569 case MIPS_ABI_N64: 1570 set_gdbarch_get_longjmp_target (gdbarch, 1571 mips64_linux_get_longjmp_target); 1572 set_solib_svr4_fetch_link_map_offsets 1573 (gdbarch, svr4_lp64_fetch_link_map_offsets); 1574 set_gdbarch_long_double_bit (gdbarch, 128); 1575 /* These floatformats should probably be renamed. MIPS uses 1576 the same 128-bit IEEE floating point format that IA-64 uses, 1577 except that the quiet/signalling NaN bit is reversed (GDB 1578 does not distinguish between quiet and signalling NaNs). */ 1579 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1580 tramp_frame_prepend_unwinder (gdbarch, 1581 µmips_linux_n64_rt_sigframe); 1582 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); 1583 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml"); 1584 break; 1585 default: 1586 break; 1587 } 1588 1589 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); 1590 1591 set_gdbarch_software_single_step (gdbarch, mips_software_single_step); 1592 1593 /* Enable TLS support. */ 1594 set_gdbarch_fetch_tls_load_module_address (gdbarch, 1595 svr4_fetch_objfile_link_map); 1596 1597 /* Initialize this lazily, to avoid an initialization order 1598 dependency on solib-svr4.c's _initialize routine. */ 1599 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) 1600 { 1601 mips_svr4_so_ops = svr4_so_ops; 1602 mips_svr4_so_ops.in_dynsym_resolve_code 1603 = mips_linux_in_dynsym_resolve_code; 1604 } 1605 set_solib_ops (gdbarch, &mips_svr4_so_ops); 1606 1607 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); 1608 1609 set_gdbarch_core_read_description (gdbarch, 1610 mips_linux_core_read_description); 1611 1612 set_gdbarch_iterate_over_regset_sections 1613 (gdbarch, mips_linux_iterate_over_regset_sections); 1614 1615 set_gdbarch_gdb_signal_from_target (gdbarch, 1616 mips_gdb_signal_from_target); 1617 1618 set_gdbarch_gdb_signal_to_target (gdbarch, 1619 mips_gdb_signal_to_target); 1620 1621 tdep->syscall_next_pc = mips_linux_syscall_next_pc; 1622 1623 if (tdesc_data) 1624 { 1625 const struct tdesc_feature *feature; 1626 1627 /* If we have target-described registers, then we can safely 1628 reserve a number for MIPS_RESTART_REGNUM (whether it is 1629 described or not). */ 1630 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); 1631 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); 1632 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); 1633 1634 /* If it's present, then assign it to the reserved number. */ 1635 feature = tdesc_find_feature (info.target_desc, 1636 "org.gnu.gdb.mips.linux"); 1637 if (feature != NULL) 1638 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, 1639 "restart"); 1640 } 1641 } 1642 1643 void _initialize_mips_linux_tdep (); 1644 void 1645 _initialize_mips_linux_tdep () 1646 { 1647 const struct bfd_arch_info *arch_info; 1648 1649 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); 1650 arch_info != NULL; 1651 arch_info = arch_info->next) 1652 { 1653 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, 1654 GDB_OSABI_LINUX, 1655 mips_linux_init_abi); 1656 } 1657 1658 /* Initialize the standard target descriptions. */ 1659 initialize_tdesc_mips_linux (); 1660 initialize_tdesc_mips_dsp_linux (); 1661 initialize_tdesc_mips64_linux (); 1662 initialize_tdesc_mips64_dsp_linux (); 1663 } 1664