1 /* Target-dependent code for GNU/Linux on MIPS processors. 2 3 Copyright (C) 2001-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "gdbcore.h" 22 #include "target.h" 23 #include "solib-svr4.h" 24 #include "osabi.h" 25 #include "mips-tdep.h" 26 #include "frame.h" 27 #include "regcache.h" 28 #include "trad-frame.h" 29 #include "tramp-frame.h" 30 #include "gdbtypes.h" 31 #include "objfiles.h" 32 #include "solib.h" 33 #include "solist.h" 34 #include "symtab.h" 35 #include "target-descriptions.h" 36 #include "regset.h" 37 #include "mips-linux-tdep.h" 38 #include "glibc-tdep.h" 39 #include "linux-tdep.h" 40 #include "xml-syscall.h" 41 #include "common/gdb_signals.h" 42 43 #include "features/mips-linux.c" 44 #include "features/mips-dsp-linux.c" 45 #include "features/mips64-linux.c" 46 #include "features/mips64-dsp-linux.c" 47 48 static struct target_so_ops mips_svr4_so_ops; 49 50 /* This enum represents the signals' numbers on the MIPS 51 architecture. It just contains the signal definitions which are 52 different from the generic implementation. 53 54 It is derived from the file <arch/mips/include/uapi/asm/signal.h>, 55 from the Linux kernel tree. */ 56 57 enum 58 { 59 MIPS_LINUX_SIGEMT = 7, 60 MIPS_LINUX_SIGBUS = 10, 61 MIPS_LINUX_SIGSYS = 12, 62 MIPS_LINUX_SIGUSR1 = 16, 63 MIPS_LINUX_SIGUSR2 = 17, 64 MIPS_LINUX_SIGCHLD = 18, 65 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, 66 MIPS_LINUX_SIGPWR = 19, 67 MIPS_LINUX_SIGWINCH = 20, 68 MIPS_LINUX_SIGURG = 21, 69 MIPS_LINUX_SIGIO = 22, 70 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, 71 MIPS_LINUX_SIGSTOP = 23, 72 MIPS_LINUX_SIGTSTP = 24, 73 MIPS_LINUX_SIGCONT = 25, 74 MIPS_LINUX_SIGTTIN = 26, 75 MIPS_LINUX_SIGTTOU = 27, 76 MIPS_LINUX_SIGVTALRM = 28, 77 MIPS_LINUX_SIGPROF = 29, 78 MIPS_LINUX_SIGXCPU = 30, 79 MIPS_LINUX_SIGXFSZ = 31, 80 81 MIPS_LINUX_SIGRTMIN = 32, 82 MIPS_LINUX_SIGRT64 = 64, 83 MIPS_LINUX_SIGRTMAX = 127, 84 }; 85 86 /* Figure out where the longjmp will land. 87 We expect the first arg to be a pointer to the jmp_buf structure 88 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 89 at. The pc is copied into PC. This routine returns 1 on 90 success. */ 91 92 #define MIPS_LINUX_JB_ELEMENT_SIZE 4 93 #define MIPS_LINUX_JB_PC 0 94 95 static int 96 mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 97 { 98 CORE_ADDR jb_addr; 99 struct gdbarch *gdbarch = get_frame_arch (frame); 100 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 101 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; 102 103 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 104 105 if (target_read_memory ((jb_addr 106 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), 107 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) 108 return 0; 109 110 *pc = extract_unsigned_integer (buf, 111 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, 112 byte_order); 113 114 return 1; 115 } 116 117 /* Transform the bits comprising a 32-bit register to the right size 118 for regcache_raw_supply(). This is needed when mips_isa_regsize() 119 is 8. */ 120 121 static void 122 supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) 123 { 124 regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true); 125 } 126 127 /* Unpack an elf_gregset_t into GDB's register cache. */ 128 129 void 130 mips_supply_gregset (struct regcache *regcache, 131 const mips_elf_gregset_t *gregsetp) 132 { 133 int regi; 134 const mips_elf_greg_t *regp = *gregsetp; 135 struct gdbarch *gdbarch = regcache->arch (); 136 137 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) 138 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); 139 140 if (mips_linux_restart_reg_p (gdbarch)) 141 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); 142 143 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); 144 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); 145 146 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, 147 regp + EF_CP0_EPC); 148 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, 149 regp + EF_CP0_BADVADDR); 150 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); 151 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, 152 regp + EF_CP0_CAUSE); 153 154 /* Fill the inaccessible zero register with zero. */ 155 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); 156 } 157 158 static void 159 mips_supply_gregset_wrapper (const struct regset *regset, 160 struct regcache *regcache, 161 int regnum, const void *gregs, size_t len) 162 { 163 gdb_assert (len >= sizeof (mips_elf_gregset_t)); 164 165 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); 166 } 167 168 /* Pack our registers (or one register) into an elf_gregset_t. */ 169 170 void 171 mips_fill_gregset (const struct regcache *regcache, 172 mips_elf_gregset_t *gregsetp, int regno) 173 { 174 struct gdbarch *gdbarch = regcache->arch (); 175 int regaddr, regi; 176 mips_elf_greg_t *regp = *gregsetp; 177 void *dst; 178 179 if (regno == -1) 180 { 181 memset (regp, 0, sizeof (mips_elf_gregset_t)); 182 for (regi = 1; regi < 32; regi++) 183 mips_fill_gregset (regcache, gregsetp, regi); 184 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); 185 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); 186 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); 187 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); 188 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 189 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); 190 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 191 return; 192 } 193 194 if (regno > 0 && regno < 32) 195 { 196 dst = regp + regno + EF_REG0; 197 regcache->raw_collect (regno, dst); 198 return; 199 } 200 201 if (regno == mips_regnum (gdbarch)->lo) 202 regaddr = EF_LO; 203 else if (regno == mips_regnum (gdbarch)->hi) 204 regaddr = EF_HI; 205 else if (regno == mips_regnum (gdbarch)->pc) 206 regaddr = EF_CP0_EPC; 207 else if (regno == mips_regnum (gdbarch)->badvaddr) 208 regaddr = EF_CP0_BADVADDR; 209 else if (regno == MIPS_PS_REGNUM) 210 regaddr = EF_CP0_STATUS; 211 else if (regno == mips_regnum (gdbarch)->cause) 212 regaddr = EF_CP0_CAUSE; 213 else if (mips_linux_restart_reg_p (gdbarch) 214 && regno == MIPS_RESTART_REGNUM) 215 regaddr = EF_REG0; 216 else 217 regaddr = -1; 218 219 if (regaddr != -1) 220 { 221 dst = regp + regaddr; 222 regcache->raw_collect (regno, dst); 223 } 224 } 225 226 static void 227 mips_fill_gregset_wrapper (const struct regset *regset, 228 const struct regcache *regcache, 229 int regnum, void *gregs, size_t len) 230 { 231 gdb_assert (len >= sizeof (mips_elf_gregset_t)); 232 233 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); 234 } 235 236 /* Support for 64-bit ABIs. */ 237 238 /* Figure out where the longjmp will land. 239 We expect the first arg to be a pointer to the jmp_buf structure 240 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land 241 at. The pc is copied into PC. This routine returns 1 on 242 success. */ 243 244 /* Details about jmp_buf. */ 245 246 #define MIPS64_LINUX_JB_PC 0 247 248 static int 249 mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 250 { 251 CORE_ADDR jb_addr; 252 struct gdbarch *gdbarch = get_frame_arch (frame); 253 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 254 gdb_byte *buf 255 = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); 256 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; 257 258 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); 259 260 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, 261 buf, 262 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) 263 return 0; 264 265 *pc = extract_unsigned_integer (buf, 266 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, 267 byte_order); 268 269 return 1; 270 } 271 272 /* Register set support functions. These operate on standard 64-bit 273 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit 274 target will still use the 64-bit format for PTRACE_GETREGS. */ 275 276 /* Supply a 64-bit register. */ 277 278 static void 279 supply_64bit_reg (struct regcache *regcache, int regnum, 280 const gdb_byte *buf) 281 { 282 struct gdbarch *gdbarch = regcache->arch (); 283 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 284 && register_size (gdbarch, regnum) == 4) 285 regcache->raw_supply (regnum, buf + 4); 286 else 287 regcache->raw_supply (regnum, buf); 288 } 289 290 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ 291 292 void 293 mips64_supply_gregset (struct regcache *regcache, 294 const mips64_elf_gregset_t *gregsetp) 295 { 296 int regi; 297 const mips64_elf_greg_t *regp = *gregsetp; 298 struct gdbarch *gdbarch = regcache->arch (); 299 300 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) 301 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, 302 (const gdb_byte *) (regp + regi)); 303 304 if (mips_linux_restart_reg_p (gdbarch)) 305 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, 306 (const gdb_byte *) (regp + MIPS64_EF_REG0)); 307 308 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, 309 (const gdb_byte *) (regp + MIPS64_EF_LO)); 310 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, 311 (const gdb_byte *) (regp + MIPS64_EF_HI)); 312 313 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, 314 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); 315 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, 316 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); 317 supply_64bit_reg (regcache, MIPS_PS_REGNUM, 318 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); 319 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, 320 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); 321 322 /* Fill the inaccessible zero register with zero. */ 323 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); 324 } 325 326 static void 327 mips64_supply_gregset_wrapper (const struct regset *regset, 328 struct regcache *regcache, 329 int regnum, const void *gregs, size_t len) 330 { 331 gdb_assert (len >= sizeof (mips64_elf_gregset_t)); 332 333 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); 334 } 335 336 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ 337 338 void 339 mips64_fill_gregset (const struct regcache *regcache, 340 mips64_elf_gregset_t *gregsetp, int regno) 341 { 342 struct gdbarch *gdbarch = regcache->arch (); 343 int regaddr, regi; 344 mips64_elf_greg_t *regp = *gregsetp; 345 void *dst; 346 347 if (regno == -1) 348 { 349 memset (regp, 0, sizeof (mips64_elf_gregset_t)); 350 for (regi = 1; regi < 32; regi++) 351 mips64_fill_gregset (regcache, gregsetp, regi); 352 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); 353 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); 354 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); 355 mips64_fill_gregset (regcache, gregsetp, 356 mips_regnum (gdbarch)->badvaddr); 357 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); 358 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); 359 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); 360 return; 361 } 362 363 if (regno > 0 && regno < 32) 364 regaddr = regno + MIPS64_EF_REG0; 365 else if (regno == mips_regnum (gdbarch)->lo) 366 regaddr = MIPS64_EF_LO; 367 else if (regno == mips_regnum (gdbarch)->hi) 368 regaddr = MIPS64_EF_HI; 369 else if (regno == mips_regnum (gdbarch)->pc) 370 regaddr = MIPS64_EF_CP0_EPC; 371 else if (regno == mips_regnum (gdbarch)->badvaddr) 372 regaddr = MIPS64_EF_CP0_BADVADDR; 373 else if (regno == MIPS_PS_REGNUM) 374 regaddr = MIPS64_EF_CP0_STATUS; 375 else if (regno == mips_regnum (gdbarch)->cause) 376 regaddr = MIPS64_EF_CP0_CAUSE; 377 else if (mips_linux_restart_reg_p (gdbarch) 378 && regno == MIPS_RESTART_REGNUM) 379 regaddr = MIPS64_EF_REG0; 380 else 381 regaddr = -1; 382 383 if (regaddr != -1) 384 { 385 dst = regp + regaddr; 386 regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true); 387 } 388 } 389 390 static void 391 mips64_fill_gregset_wrapper (const struct regset *regset, 392 const struct regcache *regcache, 393 int regnum, void *gregs, size_t len) 394 { 395 gdb_assert (len >= sizeof (mips64_elf_gregset_t)); 396 397 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); 398 } 399 400 /* Likewise, unpack an elf_fpregset_t. Linux only uses even-numbered 401 FPR slots in the Status.FR=0 mode, storing even-odd FPR pairs as the 402 SDC1 instruction would. When run on MIPS I architecture processors 403 all FPR slots used to be used, unusually, holding the respective FPRs 404 in the first 4 bytes, but that was corrected for consistency, with 405 `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator 406 changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU 407 ptrace() handling fixes."), and then broken and fixed over and over 408 again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct 409 MIPS I FP context layout"). */ 410 411 void 412 mips64_supply_fpregset (struct regcache *regcache, 413 const mips64_elf_fpregset_t *fpregsetp) 414 { 415 struct gdbarch *gdbarch = regcache->arch (); 416 int regi; 417 418 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) 419 for (regi = 0; regi < 32; regi++) 420 { 421 const gdb_byte *reg_ptr 422 = (const gdb_byte *) (*fpregsetp + (regi & ~1)); 423 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) 424 reg_ptr += 4; 425 regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, reg_ptr); 426 } 427 else 428 for (regi = 0; regi < 32; regi++) 429 regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, 430 (const char *) (*fpregsetp + regi)); 431 432 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, 433 (const gdb_byte *) (*fpregsetp + 32)); 434 435 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't 436 include it - but the result of PTRACE_GETFPREGS does. The best we 437 can do is to assume that its value is present. */ 438 supply_32bit_reg (regcache, 439 mips_regnum (gdbarch)->fp_implementation_revision, 440 (const gdb_byte *) (*fpregsetp + 32) + 4); 441 } 442 443 static void 444 mips64_supply_fpregset_wrapper (const struct regset *regset, 445 struct regcache *regcache, 446 int regnum, const void *gregs, size_t len) 447 { 448 gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); 449 450 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); 451 } 452 453 /* Likewise, pack one or all floating point registers into an 454 elf_fpregset_t. See `mips_supply_fpregset' for an explanation 455 of the layout. */ 456 457 void 458 mips64_fill_fpregset (const struct regcache *regcache, 459 mips64_elf_fpregset_t *fpregsetp, int regno) 460 { 461 struct gdbarch *gdbarch = regcache->arch (); 462 gdb_byte *to; 463 464 if ((regno >= gdbarch_fp0_regnum (gdbarch)) 465 && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) 466 { 467 if (register_size (gdbarch, regno) == 4) 468 { 469 int regi = regno - gdbarch_fp0_regnum (gdbarch); 470 471 to = (gdb_byte *) (*fpregsetp + (regi & ~1)); 472 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) 473 to += 4; 474 regcache->raw_collect (regno, to); 475 } 476 else 477 { 478 to = (gdb_byte *) (*fpregsetp + regno 479 - gdbarch_fp0_regnum (gdbarch)); 480 regcache->raw_collect (regno, to); 481 } 482 } 483 else if (regno == mips_regnum (gdbarch)->fp_control_status) 484 { 485 to = (gdb_byte *) (*fpregsetp + 32); 486 regcache->raw_collect_integer (regno, to, 4, true); 487 } 488 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 489 { 490 to = (gdb_byte *) (*fpregsetp + 32) + 4; 491 regcache->raw_collect_integer (regno, to, 4, true); 492 } 493 else if (regno == -1) 494 { 495 int regi; 496 497 for (regi = 0; regi < 32; regi++) 498 mips64_fill_fpregset (regcache, fpregsetp, 499 gdbarch_fp0_regnum (gdbarch) + regi); 500 mips64_fill_fpregset (regcache, fpregsetp, 501 mips_regnum (gdbarch)->fp_control_status); 502 mips64_fill_fpregset (regcache, fpregsetp, 503 mips_regnum (gdbarch)->fp_implementation_revision); 504 } 505 } 506 507 static void 508 mips64_fill_fpregset_wrapper (const struct regset *regset, 509 const struct regcache *regcache, 510 int regnum, void *gregs, size_t len) 511 { 512 gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); 513 514 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); 515 } 516 517 static const struct regset mips_linux_gregset = 518 { 519 NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper 520 }; 521 522 static const struct regset mips64_linux_gregset = 523 { 524 NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper 525 }; 526 527 static const struct regset mips64_linux_fpregset = 528 { 529 NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper 530 }; 531 532 static void 533 mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, 534 iterate_over_regset_sections_cb *cb, 535 void *cb_data, 536 const struct regcache *regcache) 537 { 538 if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4) 539 { 540 cb (".reg", sizeof (mips_elf_gregset_t), sizeof (mips_elf_gregset_t), 541 &mips_linux_gregset, NULL, cb_data); 542 cb (".reg2", sizeof (mips64_elf_fpregset_t), 543 sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, 544 NULL, cb_data); 545 } 546 else 547 { 548 cb (".reg", sizeof (mips64_elf_gregset_t), sizeof (mips64_elf_gregset_t), 549 &mips64_linux_gregset, NULL, cb_data); 550 cb (".reg2", sizeof (mips64_elf_fpregset_t), 551 sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, 552 NULL, cb_data); 553 } 554 } 555 556 static const struct target_desc * 557 mips_linux_core_read_description (struct gdbarch *gdbarch, 558 struct target_ops *target, 559 bfd *abfd) 560 { 561 asection *section = bfd_get_section_by_name (abfd, ".reg"); 562 if (! section) 563 return NULL; 564 565 switch (bfd_section_size (abfd, section)) 566 { 567 case sizeof (mips_elf_gregset_t): 568 return mips_tdesc_gp32; 569 570 case sizeof (mips64_elf_gregset_t): 571 return mips_tdesc_gp64; 572 573 default: 574 return NULL; 575 } 576 } 577 578 579 /* Check the code at PC for a dynamic linker lazy resolution stub. 580 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" 581 section uniformly since version 2.15. If the pc is in that section, 582 then we are in such a stub. Before that ".stub" was used in 32-bit 583 ELF binaries, however we do not bother checking for that since we 584 have never had and that case should be extremely rare these days. 585 Instead we pattern-match on the code generated by GNU ld. They look 586 like this: 587 588 lw t9,0x8010(gp) 589 addu t7,ra 590 jalr t9,ra 591 addiu t8,zero,INDEX 592 593 (with the appropriate doubleword instructions for N64). As any lazy 594 resolution stubs in microMIPS binaries will always be in a 595 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ 596 597 static int 598 mips_linux_in_dynsym_stub (CORE_ADDR pc) 599 { 600 gdb_byte buf[28], *p; 601 ULONGEST insn, insn1; 602 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64); 603 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 604 605 if (in_mips_stubs_section (pc)) 606 return 1; 607 608 read_memory (pc - 12, buf, 28); 609 610 if (n64) 611 { 612 /* ld t9,0x8010(gp) */ 613 insn1 = 0xdf998010; 614 } 615 else 616 { 617 /* lw t9,0x8010(gp) */ 618 insn1 = 0x8f998010; 619 } 620 621 p = buf + 12; 622 while (p >= buf) 623 { 624 insn = extract_unsigned_integer (p, 4, byte_order); 625 if (insn == insn1) 626 break; 627 p -= 4; 628 } 629 if (p < buf) 630 return 0; 631 632 insn = extract_unsigned_integer (p + 4, 4, byte_order); 633 if (n64) 634 { 635 /* 'daddu t7,ra' or 'or t7, ra, zero'*/ 636 if (insn != 0x03e0782d || insn != 0x03e07825) 637 return 0; 638 639 } 640 else 641 { 642 /* 'addu t7,ra' or 'or t7, ra, zero'*/ 643 if (insn != 0x03e07821 || insn != 0x03e07825) 644 return 0; 645 646 } 647 648 insn = extract_unsigned_integer (p + 8, 4, byte_order); 649 /* jalr t9,ra */ 650 if (insn != 0x0320f809) 651 return 0; 652 653 insn = extract_unsigned_integer (p + 12, 4, byte_order); 654 if (n64) 655 { 656 /* daddiu t8,zero,0 */ 657 if ((insn & 0xffff0000) != 0x64180000) 658 return 0; 659 } 660 else 661 { 662 /* addiu t8,zero,0 */ 663 if ((insn & 0xffff0000) != 0x24180000) 664 return 0; 665 } 666 667 return 1; 668 } 669 670 /* Return non-zero iff PC belongs to the dynamic linker resolution 671 code, a PLT entry, or a lazy binding stub. */ 672 673 static int 674 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) 675 { 676 /* Check whether PC is in the dynamic linker. This also checks 677 whether it is in the .plt section, used by non-PIC executables. */ 678 if (svr4_in_dynsym_resolve_code (pc)) 679 return 1; 680 681 /* Likewise for the stubs. They live in the .MIPS.stubs section these 682 days, so we check if the PC is within, than fall back to a pattern 683 match. */ 684 if (mips_linux_in_dynsym_stub (pc)) 685 return 1; 686 687 return 0; 688 } 689 690 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, 691 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc 692 implementation of this triggers at "fixup" from the same objfile as 693 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at 694 "__dl_runtime_resolve" directly. An unresolved lazy binding 695 stub will point to _dl_runtime_resolve, which will first call 696 __dl_runtime_resolve, and then pass control to the resolved 697 function. */ 698 699 static CORE_ADDR 700 mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) 701 { 702 struct bound_minimal_symbol resolver; 703 704 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); 705 706 if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc) 707 return frame_unwind_caller_pc (get_current_frame ()); 708 709 return glibc_skip_solib_resolver (gdbarch, pc); 710 } 711 712 /* Signal trampoline support. There are four supported layouts for a 713 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and 714 n64 rt_sigframe. We handle them all independently; not the most 715 efficient way, but simplest. First, declare all the unwinders. */ 716 717 static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, 718 struct frame_info *this_frame, 719 struct trad_frame_cache *this_cache, 720 CORE_ADDR func); 721 722 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 723 struct frame_info *this_frame, 724 struct trad_frame_cache *this_cache, 725 CORE_ADDR func); 726 727 static int mips_linux_sigframe_validate (const struct tramp_frame *self, 728 struct frame_info *this_frame, 729 CORE_ADDR *pc); 730 731 static int micromips_linux_sigframe_validate (const struct tramp_frame *self, 732 struct frame_info *this_frame, 733 CORE_ADDR *pc); 734 735 #define MIPS_NR_LINUX 4000 736 #define MIPS_NR_N64_LINUX 5000 737 #define MIPS_NR_N32_LINUX 6000 738 739 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 740 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 741 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 742 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 743 744 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn 745 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn 746 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn 747 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn 748 #define MIPS_INST_SYSCALL 0x0000000c 749 750 #define MICROMIPS_INST_LI_V0 0x3040 751 #define MICROMIPS_INST_POOL32A 0x0000 752 #define MICROMIPS_INST_SYSCALL 0x8b7c 753 754 static const struct tramp_frame mips_linux_o32_sigframe = { 755 SIGTRAMP_FRAME, 756 4, 757 { 758 { MIPS_INST_LI_V0_SIGRETURN, ULONGEST_MAX }, 759 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 760 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 761 }, 762 mips_linux_o32_sigframe_init, 763 mips_linux_sigframe_validate 764 }; 765 766 static const struct tramp_frame mips_linux_o32_rt_sigframe = { 767 SIGTRAMP_FRAME, 768 4, 769 { 770 { MIPS_INST_LI_V0_RT_SIGRETURN, ULONGEST_MAX }, 771 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 772 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } }, 773 mips_linux_o32_sigframe_init, 774 mips_linux_sigframe_validate 775 }; 776 777 static const struct tramp_frame mips_linux_n32_rt_sigframe = { 778 SIGTRAMP_FRAME, 779 4, 780 { 781 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, ULONGEST_MAX }, 782 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 783 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 784 }, 785 mips_linux_n32n64_sigframe_init, 786 mips_linux_sigframe_validate 787 }; 788 789 static const struct tramp_frame mips_linux_n64_rt_sigframe = { 790 SIGTRAMP_FRAME, 791 4, 792 { 793 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, ULONGEST_MAX }, 794 { MIPS_INST_SYSCALL, ULONGEST_MAX }, 795 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 796 }, 797 mips_linux_n32n64_sigframe_init, 798 mips_linux_sigframe_validate 799 }; 800 801 static const struct tramp_frame micromips_linux_o32_sigframe = { 802 SIGTRAMP_FRAME, 803 2, 804 { 805 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 806 { MIPS_NR_sigreturn, ULONGEST_MAX }, 807 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 808 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 809 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 810 }, 811 mips_linux_o32_sigframe_init, 812 micromips_linux_sigframe_validate 813 }; 814 815 static const struct tramp_frame micromips_linux_o32_rt_sigframe = { 816 SIGTRAMP_FRAME, 817 2, 818 { 819 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 820 { MIPS_NR_rt_sigreturn, ULONGEST_MAX }, 821 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 822 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 823 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 824 }, 825 mips_linux_o32_sigframe_init, 826 micromips_linux_sigframe_validate 827 }; 828 829 static const struct tramp_frame micromips_linux_n32_rt_sigframe = { 830 SIGTRAMP_FRAME, 831 2, 832 { 833 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 834 { MIPS_NR_N32_rt_sigreturn, ULONGEST_MAX }, 835 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 836 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 837 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 838 }, 839 mips_linux_n32n64_sigframe_init, 840 micromips_linux_sigframe_validate 841 }; 842 843 static const struct tramp_frame micromips_linux_n64_rt_sigframe = { 844 SIGTRAMP_FRAME, 845 2, 846 { 847 { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, 848 { MIPS_NR_N64_rt_sigreturn, ULONGEST_MAX }, 849 { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, 850 { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, 851 { TRAMP_SENTINEL_INSN, ULONGEST_MAX } 852 }, 853 mips_linux_n32n64_sigframe_init, 854 micromips_linux_sigframe_validate 855 }; 856 857 /* *INDENT-OFF* */ 858 /* The unwinder for o32 signal frames. The legacy structures look 859 like this: 860 861 struct sigframe { 862 u32 sf_ass[4]; [argument save space for o32] 863 u32 sf_code[2]; [signal trampoline or fill] 864 struct sigcontext sf_sc; 865 sigset_t sf_mask; 866 }; 867 868 Pre-2.6.12 sigcontext: 869 870 struct sigcontext { 871 unsigned int sc_regmask; [Unused] 872 unsigned int sc_status; 873 unsigned long long sc_pc; 874 unsigned long long sc_regs[32]; 875 unsigned long long sc_fpregs[32]; 876 unsigned int sc_ownedfp; 877 unsigned int sc_fpc_csr; 878 unsigned int sc_fpc_eir; [Unused] 879 unsigned int sc_used_math; 880 unsigned int sc_ssflags; [Unused] 881 [Alignment hole of four bytes] 882 unsigned long long sc_mdhi; 883 unsigned long long sc_mdlo; 884 885 unsigned int sc_cause; [Unused] 886 unsigned int sc_badvaddr; [Unused] 887 888 unsigned long sc_sigset[4]; [kernel's sigset_t] 889 }; 890 891 Post-2.6.12 sigcontext (SmartMIPS/DSP support added): 892 893 struct sigcontext { 894 unsigned int sc_regmask; [Unused] 895 unsigned int sc_status; [Unused] 896 unsigned long long sc_pc; 897 unsigned long long sc_regs[32]; 898 unsigned long long sc_fpregs[32]; 899 unsigned int sc_acx; 900 unsigned int sc_fpc_csr; 901 unsigned int sc_fpc_eir; [Unused] 902 unsigned int sc_used_math; 903 unsigned int sc_dsp; 904 [Alignment hole of four bytes] 905 unsigned long long sc_mdhi; 906 unsigned long long sc_mdlo; 907 unsigned long sc_hi1; 908 unsigned long sc_lo1; 909 unsigned long sc_hi2; 910 unsigned long sc_lo2; 911 unsigned long sc_hi3; 912 unsigned long sc_lo3; 913 }; 914 915 The RT signal frames look like this: 916 917 struct rt_sigframe { 918 u32 rs_ass[4]; [argument save space for o32] 919 u32 rs_code[2] [signal trampoline or fill] 920 struct siginfo rs_info; 921 struct ucontext rs_uc; 922 }; 923 924 struct ucontext { 925 unsigned long uc_flags; 926 struct ucontext *uc_link; 927 stack_t uc_stack; 928 [Alignment hole of four bytes] 929 struct sigcontext uc_mcontext; 930 sigset_t uc_sigmask; 931 }; */ 932 /* *INDENT-ON* */ 933 934 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) 935 936 #define RTSIGFRAME_SIGINFO_SIZE 128 937 #define STACK_T_SIZE (3 * 4) 938 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) 939 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 940 + RTSIGFRAME_SIGINFO_SIZE \ 941 + UCONTEXT_SIGCONTEXT_OFFSET) 942 943 #define SIGCONTEXT_PC (1 * 8) 944 #define SIGCONTEXT_REGS (2 * 8) 945 #define SIGCONTEXT_FPREGS (34 * 8) 946 #define SIGCONTEXT_FPCSR (66 * 8 + 4) 947 #define SIGCONTEXT_DSPCTL (68 * 8 + 0) 948 #define SIGCONTEXT_HI (69 * 8) 949 #define SIGCONTEXT_LO (70 * 8) 950 #define SIGCONTEXT_CAUSE (71 * 8 + 0) 951 #define SIGCONTEXT_BADVADDR (71 * 8 + 4) 952 #define SIGCONTEXT_HI1 (71 * 8 + 0) 953 #define SIGCONTEXT_LO1 (71 * 8 + 4) 954 #define SIGCONTEXT_HI2 (72 * 8 + 0) 955 #define SIGCONTEXT_LO2 (72 * 8 + 4) 956 #define SIGCONTEXT_HI3 (73 * 8 + 0) 957 #define SIGCONTEXT_LO3 (73 * 8 + 4) 958 959 #define SIGCONTEXT_REG_SIZE 8 960 961 static void 962 mips_linux_o32_sigframe_init (const struct tramp_frame *self, 963 struct frame_info *this_frame, 964 struct trad_frame_cache *this_cache, 965 CORE_ADDR func) 966 { 967 struct gdbarch *gdbarch = get_frame_arch (this_frame); 968 int ireg; 969 CORE_ADDR frame_sp = get_frame_sp (this_frame); 970 CORE_ADDR sigcontext_base; 971 const struct mips_regnum *regs = mips_regnum (gdbarch); 972 CORE_ADDR regs_base; 973 974 if (self == &mips_linux_o32_sigframe 975 || self == µmips_linux_o32_sigframe) 976 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; 977 else 978 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; 979 980 /* I'm not proud of this hack. Eventually we will have the 981 infrastructure to indicate the size of saved registers on a 982 per-frame basis, but right now we don't; the kernel saves eight 983 bytes but we only want four. Use regs_base to access any 984 64-bit fields. */ 985 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 986 regs_base = sigcontext_base + 4; 987 else 988 regs_base = sigcontext_base; 989 990 if (mips_linux_restart_reg_p (gdbarch)) 991 trad_frame_set_reg_addr (this_cache, 992 (MIPS_RESTART_REGNUM 993 + gdbarch_num_regs (gdbarch)), 994 regs_base + SIGCONTEXT_REGS); 995 996 for (ireg = 1; ireg < 32; ireg++) 997 trad_frame_set_reg_addr (this_cache, 998 (ireg + MIPS_ZERO_REGNUM 999 + gdbarch_num_regs (gdbarch)), 1000 (regs_base + SIGCONTEXT_REGS 1001 + ireg * SIGCONTEXT_REG_SIZE)); 1002 1003 for (ireg = 0; ireg < 32; ireg++) 1004 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) 1005 trad_frame_set_reg_addr (this_cache, 1006 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1007 (sigcontext_base + SIGCONTEXT_FPREGS + 4 1008 + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); 1009 else 1010 trad_frame_set_reg_addr (this_cache, 1011 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1012 (sigcontext_base + SIGCONTEXT_FPREGS 1013 + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); 1014 1015 trad_frame_set_reg_addr (this_cache, 1016 regs->pc + gdbarch_num_regs (gdbarch), 1017 regs_base + SIGCONTEXT_PC); 1018 1019 trad_frame_set_reg_addr (this_cache, 1020 (regs->fp_control_status 1021 + gdbarch_num_regs (gdbarch)), 1022 sigcontext_base + SIGCONTEXT_FPCSR); 1023 1024 if (regs->dspctl != -1) 1025 trad_frame_set_reg_addr (this_cache, 1026 regs->dspctl + gdbarch_num_regs (gdbarch), 1027 sigcontext_base + SIGCONTEXT_DSPCTL); 1028 1029 trad_frame_set_reg_addr (this_cache, 1030 regs->hi + gdbarch_num_regs (gdbarch), 1031 regs_base + SIGCONTEXT_HI); 1032 trad_frame_set_reg_addr (this_cache, 1033 regs->lo + gdbarch_num_regs (gdbarch), 1034 regs_base + SIGCONTEXT_LO); 1035 1036 if (regs->dspacc != -1) 1037 { 1038 trad_frame_set_reg_addr (this_cache, 1039 regs->dspacc + 0 + gdbarch_num_regs (gdbarch), 1040 sigcontext_base + SIGCONTEXT_HI1); 1041 trad_frame_set_reg_addr (this_cache, 1042 regs->dspacc + 1 + gdbarch_num_regs (gdbarch), 1043 sigcontext_base + SIGCONTEXT_LO1); 1044 trad_frame_set_reg_addr (this_cache, 1045 regs->dspacc + 2 + gdbarch_num_regs (gdbarch), 1046 sigcontext_base + SIGCONTEXT_HI2); 1047 trad_frame_set_reg_addr (this_cache, 1048 regs->dspacc + 3 + gdbarch_num_regs (gdbarch), 1049 sigcontext_base + SIGCONTEXT_LO2); 1050 trad_frame_set_reg_addr (this_cache, 1051 regs->dspacc + 4 + gdbarch_num_regs (gdbarch), 1052 sigcontext_base + SIGCONTEXT_HI3); 1053 trad_frame_set_reg_addr (this_cache, 1054 regs->dspacc + 5 + gdbarch_num_regs (gdbarch), 1055 sigcontext_base + SIGCONTEXT_LO3); 1056 } 1057 else 1058 { 1059 trad_frame_set_reg_addr (this_cache, 1060 regs->cause + gdbarch_num_regs (gdbarch), 1061 sigcontext_base + SIGCONTEXT_CAUSE); 1062 trad_frame_set_reg_addr (this_cache, 1063 regs->badvaddr + gdbarch_num_regs (gdbarch), 1064 sigcontext_base + SIGCONTEXT_BADVADDR); 1065 } 1066 1067 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 1068 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); 1069 } 1070 1071 /* *INDENT-OFF* */ 1072 /* For N32/N64 things look different. There is no non-rt signal frame. 1073 1074 struct rt_sigframe_n32 { 1075 u32 rs_ass[4]; [ argument save space for o32 ] 1076 u32 rs_code[2]; [ signal trampoline or fill ] 1077 struct siginfo rs_info; 1078 struct ucontextn32 rs_uc; 1079 }; 1080 1081 struct ucontextn32 { 1082 u32 uc_flags; 1083 s32 uc_link; 1084 stack32_t uc_stack; 1085 struct sigcontext uc_mcontext; 1086 sigset_t uc_sigmask; [ mask last for extensibility ] 1087 }; 1088 1089 struct rt_sigframe { 1090 u32 rs_ass[4]; [ argument save space for o32 ] 1091 u32 rs_code[2]; [ signal trampoline ] 1092 struct siginfo rs_info; 1093 struct ucontext rs_uc; 1094 }; 1095 1096 struct ucontext { 1097 unsigned long uc_flags; 1098 struct ucontext *uc_link; 1099 stack_t uc_stack; 1100 struct sigcontext uc_mcontext; 1101 sigset_t uc_sigmask; [ mask last for extensibility ] 1102 }; 1103 1104 And the sigcontext is different (this is for both n32 and n64): 1105 1106 struct sigcontext { 1107 unsigned long long sc_regs[32]; 1108 unsigned long long sc_fpregs[32]; 1109 unsigned long long sc_mdhi; 1110 unsigned long long sc_hi1; 1111 unsigned long long sc_hi2; 1112 unsigned long long sc_hi3; 1113 unsigned long long sc_mdlo; 1114 unsigned long long sc_lo1; 1115 unsigned long long sc_lo2; 1116 unsigned long long sc_lo3; 1117 unsigned long long sc_pc; 1118 unsigned int sc_fpc_csr; 1119 unsigned int sc_used_math; 1120 unsigned int sc_dsp; 1121 unsigned int sc_reserved; 1122 }; 1123 1124 That is the post-2.6.12 definition of the 64-bit sigcontext; before 1125 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were 1126 included too. */ 1127 /* *INDENT-ON* */ 1128 1129 #define N32_STACK_T_SIZE STACK_T_SIZE 1130 #define N64_STACK_T_SIZE (2 * 8 + 4) 1131 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) 1132 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) 1133 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 1134 + RTSIGFRAME_SIGINFO_SIZE \ 1135 + N32_UCONTEXT_SIGCONTEXT_OFFSET) 1136 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ 1137 + RTSIGFRAME_SIGINFO_SIZE \ 1138 + N64_UCONTEXT_SIGCONTEXT_OFFSET) 1139 1140 #define N64_SIGCONTEXT_REGS (0 * 8) 1141 #define N64_SIGCONTEXT_FPREGS (32 * 8) 1142 #define N64_SIGCONTEXT_HI (64 * 8) 1143 #define N64_SIGCONTEXT_HI1 (65 * 8) 1144 #define N64_SIGCONTEXT_HI2 (66 * 8) 1145 #define N64_SIGCONTEXT_HI3 (67 * 8) 1146 #define N64_SIGCONTEXT_LO (68 * 8) 1147 #define N64_SIGCONTEXT_LO1 (69 * 8) 1148 #define N64_SIGCONTEXT_LO2 (70 * 8) 1149 #define N64_SIGCONTEXT_LO3 (71 * 8) 1150 #define N64_SIGCONTEXT_PC (72 * 8) 1151 #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) 1152 #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) 1153 1154 #define N64_SIGCONTEXT_REG_SIZE 8 1155 1156 static void 1157 mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, 1158 struct frame_info *this_frame, 1159 struct trad_frame_cache *this_cache, 1160 CORE_ADDR func) 1161 { 1162 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1163 int ireg; 1164 CORE_ADDR frame_sp = get_frame_sp (this_frame); 1165 CORE_ADDR sigcontext_base; 1166 const struct mips_regnum *regs = mips_regnum (gdbarch); 1167 1168 if (self == &mips_linux_n32_rt_sigframe 1169 || self == µmips_linux_n32_rt_sigframe) 1170 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; 1171 else 1172 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; 1173 1174 if (mips_linux_restart_reg_p (gdbarch)) 1175 trad_frame_set_reg_addr (this_cache, 1176 (MIPS_RESTART_REGNUM 1177 + gdbarch_num_regs (gdbarch)), 1178 sigcontext_base + N64_SIGCONTEXT_REGS); 1179 1180 for (ireg = 1; ireg < 32; ireg++) 1181 trad_frame_set_reg_addr (this_cache, 1182 (ireg + MIPS_ZERO_REGNUM 1183 + gdbarch_num_regs (gdbarch)), 1184 (sigcontext_base + N64_SIGCONTEXT_REGS 1185 + ireg * N64_SIGCONTEXT_REG_SIZE)); 1186 1187 for (ireg = 0; ireg < 32; ireg++) 1188 trad_frame_set_reg_addr (this_cache, 1189 ireg + regs->fp0 + gdbarch_num_regs (gdbarch), 1190 (sigcontext_base + N64_SIGCONTEXT_FPREGS 1191 + ireg * N64_SIGCONTEXT_REG_SIZE)); 1192 1193 trad_frame_set_reg_addr (this_cache, 1194 regs->pc + gdbarch_num_regs (gdbarch), 1195 sigcontext_base + N64_SIGCONTEXT_PC); 1196 1197 trad_frame_set_reg_addr (this_cache, 1198 (regs->fp_control_status 1199 + gdbarch_num_regs (gdbarch)), 1200 sigcontext_base + N64_SIGCONTEXT_FPCSR); 1201 1202 trad_frame_set_reg_addr (this_cache, 1203 regs->hi + gdbarch_num_regs (gdbarch), 1204 sigcontext_base + N64_SIGCONTEXT_HI); 1205 trad_frame_set_reg_addr (this_cache, 1206 regs->lo + gdbarch_num_regs (gdbarch), 1207 sigcontext_base + N64_SIGCONTEXT_LO); 1208 1209 if (regs->dspacc != -1) 1210 { 1211 trad_frame_set_reg_addr (this_cache, 1212 regs->dspacc + 0 + gdbarch_num_regs (gdbarch), 1213 sigcontext_base + N64_SIGCONTEXT_HI1); 1214 trad_frame_set_reg_addr (this_cache, 1215 regs->dspacc + 1 + gdbarch_num_regs (gdbarch), 1216 sigcontext_base + N64_SIGCONTEXT_LO1); 1217 trad_frame_set_reg_addr (this_cache, 1218 regs->dspacc + 2 + gdbarch_num_regs (gdbarch), 1219 sigcontext_base + N64_SIGCONTEXT_HI2); 1220 trad_frame_set_reg_addr (this_cache, 1221 regs->dspacc + 3 + gdbarch_num_regs (gdbarch), 1222 sigcontext_base + N64_SIGCONTEXT_LO2); 1223 trad_frame_set_reg_addr (this_cache, 1224 regs->dspacc + 4 + gdbarch_num_regs (gdbarch), 1225 sigcontext_base + N64_SIGCONTEXT_HI3); 1226 trad_frame_set_reg_addr (this_cache, 1227 regs->dspacc + 5 + gdbarch_num_regs (gdbarch), 1228 sigcontext_base + N64_SIGCONTEXT_LO3); 1229 } 1230 if (regs->dspctl != -1) 1231 trad_frame_set_reg_addr (this_cache, 1232 regs->dspctl + gdbarch_num_regs (gdbarch), 1233 sigcontext_base + N64_SIGCONTEXT_DSPCTL); 1234 1235 /* Choice of the bottom of the sigframe is somewhat arbitrary. */ 1236 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); 1237 } 1238 1239 /* Implement struct tramp_frame's "validate" method for standard MIPS code. */ 1240 1241 static int 1242 mips_linux_sigframe_validate (const struct tramp_frame *self, 1243 struct frame_info *this_frame, 1244 CORE_ADDR *pc) 1245 { 1246 return mips_pc_is_mips (*pc); 1247 } 1248 1249 /* Implement struct tramp_frame's "validate" method for microMIPS code. */ 1250 1251 static int 1252 micromips_linux_sigframe_validate (const struct tramp_frame *self, 1253 struct frame_info *this_frame, 1254 CORE_ADDR *pc) 1255 { 1256 if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc)) 1257 { 1258 *pc = mips_unmake_compact_addr (*pc); 1259 return 1; 1260 } 1261 else 1262 return 0; 1263 } 1264 1265 /* Implement the "write_pc" gdbarch method. */ 1266 1267 static void 1268 mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) 1269 { 1270 struct gdbarch *gdbarch = regcache->arch (); 1271 1272 mips_write_pc (regcache, pc); 1273 1274 /* Clear the syscall restart flag. */ 1275 if (mips_linux_restart_reg_p (gdbarch)) 1276 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); 1277 } 1278 1279 /* Return 1 if MIPS_RESTART_REGNUM is usable. */ 1280 1281 int 1282 mips_linux_restart_reg_p (struct gdbarch *gdbarch) 1283 { 1284 /* If we do not have a target description with registers, then 1285 MIPS_RESTART_REGNUM will not be included in the register set. */ 1286 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) 1287 return 0; 1288 1289 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will 1290 either be GPR-sized or missing. */ 1291 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; 1292 } 1293 1294 /* When FRAME is at a syscall instruction, return the PC of the next 1295 instruction to be executed. */ 1296 1297 static CORE_ADDR 1298 mips_linux_syscall_next_pc (struct frame_info *frame) 1299 { 1300 CORE_ADDR pc = get_frame_pc (frame); 1301 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); 1302 1303 /* If we are about to make a sigreturn syscall, use the unwinder to 1304 decode the signal frame. */ 1305 if (v0 == MIPS_NR_sigreturn 1306 || v0 == MIPS_NR_rt_sigreturn 1307 || v0 == MIPS_NR_N64_rt_sigreturn 1308 || v0 == MIPS_NR_N32_rt_sigreturn) 1309 return frame_unwind_caller_pc (get_current_frame ()); 1310 1311 return pc + 4; 1312 } 1313 1314 /* Return the current system call's number present in the 1315 v0 register. When the function fails, it returns -1. */ 1316 1317 static LONGEST 1318 mips_linux_get_syscall_number (struct gdbarch *gdbarch, 1319 thread_info *thread) 1320 { 1321 struct regcache *regcache = get_thread_regcache (thread); 1322 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1323 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1324 int regsize = register_size (gdbarch, MIPS_V0_REGNUM); 1325 /* The content of a register */ 1326 gdb_byte buf[8]; 1327 /* The result */ 1328 LONGEST ret; 1329 1330 /* Make sure we're in a known ABI */ 1331 gdb_assert (tdep->mips_abi == MIPS_ABI_O32 1332 || tdep->mips_abi == MIPS_ABI_N32 1333 || tdep->mips_abi == MIPS_ABI_N64); 1334 1335 gdb_assert (regsize <= sizeof (buf)); 1336 1337 /* Getting the system call number from the register. 1338 syscall number is in v0 or $2. */ 1339 regcache->cooked_read (MIPS_V0_REGNUM, buf); 1340 1341 ret = extract_signed_integer (buf, regsize, byte_order); 1342 1343 return ret; 1344 } 1345 1346 /* Implementation of `gdbarch_gdb_signal_to_target', as defined in 1347 gdbarch.h. */ 1348 1349 static int 1350 mips_gdb_signal_to_target (struct gdbarch *gdbarch, 1351 enum gdb_signal signal) 1352 { 1353 switch (signal) 1354 { 1355 case GDB_SIGNAL_EMT: 1356 return MIPS_LINUX_SIGEMT; 1357 1358 case GDB_SIGNAL_BUS: 1359 return MIPS_LINUX_SIGBUS; 1360 1361 case GDB_SIGNAL_SYS: 1362 return MIPS_LINUX_SIGSYS; 1363 1364 case GDB_SIGNAL_USR1: 1365 return MIPS_LINUX_SIGUSR1; 1366 1367 case GDB_SIGNAL_USR2: 1368 return MIPS_LINUX_SIGUSR2; 1369 1370 case GDB_SIGNAL_CHLD: 1371 return MIPS_LINUX_SIGCHLD; 1372 1373 case GDB_SIGNAL_PWR: 1374 return MIPS_LINUX_SIGPWR; 1375 1376 case GDB_SIGNAL_WINCH: 1377 return MIPS_LINUX_SIGWINCH; 1378 1379 case GDB_SIGNAL_URG: 1380 return MIPS_LINUX_SIGURG; 1381 1382 case GDB_SIGNAL_IO: 1383 return MIPS_LINUX_SIGIO; 1384 1385 case GDB_SIGNAL_POLL: 1386 return MIPS_LINUX_SIGPOLL; 1387 1388 case GDB_SIGNAL_STOP: 1389 return MIPS_LINUX_SIGSTOP; 1390 1391 case GDB_SIGNAL_TSTP: 1392 return MIPS_LINUX_SIGTSTP; 1393 1394 case GDB_SIGNAL_CONT: 1395 return MIPS_LINUX_SIGCONT; 1396 1397 case GDB_SIGNAL_TTIN: 1398 return MIPS_LINUX_SIGTTIN; 1399 1400 case GDB_SIGNAL_TTOU: 1401 return MIPS_LINUX_SIGTTOU; 1402 1403 case GDB_SIGNAL_VTALRM: 1404 return MIPS_LINUX_SIGVTALRM; 1405 1406 case GDB_SIGNAL_PROF: 1407 return MIPS_LINUX_SIGPROF; 1408 1409 case GDB_SIGNAL_XCPU: 1410 return MIPS_LINUX_SIGXCPU; 1411 1412 case GDB_SIGNAL_XFSZ: 1413 return MIPS_LINUX_SIGXFSZ; 1414 1415 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, 1416 therefore we have to handle it here. */ 1417 case GDB_SIGNAL_REALTIME_32: 1418 return MIPS_LINUX_SIGRTMIN; 1419 } 1420 1421 if (signal >= GDB_SIGNAL_REALTIME_33 1422 && signal <= GDB_SIGNAL_REALTIME_63) 1423 { 1424 int offset = signal - GDB_SIGNAL_REALTIME_33; 1425 1426 return MIPS_LINUX_SIGRTMIN + 1 + offset; 1427 } 1428 else if (signal >= GDB_SIGNAL_REALTIME_64 1429 && signal <= GDB_SIGNAL_REALTIME_127) 1430 { 1431 int offset = signal - GDB_SIGNAL_REALTIME_64; 1432 1433 return MIPS_LINUX_SIGRT64 + offset; 1434 } 1435 1436 return linux_gdb_signal_to_target (gdbarch, signal); 1437 } 1438 1439 /* Translate signals based on MIPS signal values. 1440 Adapted from gdb/common/signals.c. */ 1441 1442 static enum gdb_signal 1443 mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) 1444 { 1445 switch (signal) 1446 { 1447 case MIPS_LINUX_SIGEMT: 1448 return GDB_SIGNAL_EMT; 1449 1450 case MIPS_LINUX_SIGBUS: 1451 return GDB_SIGNAL_BUS; 1452 1453 case MIPS_LINUX_SIGSYS: 1454 return GDB_SIGNAL_SYS; 1455 1456 case MIPS_LINUX_SIGUSR1: 1457 return GDB_SIGNAL_USR1; 1458 1459 case MIPS_LINUX_SIGUSR2: 1460 return GDB_SIGNAL_USR2; 1461 1462 case MIPS_LINUX_SIGCHLD: 1463 return GDB_SIGNAL_CHLD; 1464 1465 case MIPS_LINUX_SIGPWR: 1466 return GDB_SIGNAL_PWR; 1467 1468 case MIPS_LINUX_SIGWINCH: 1469 return GDB_SIGNAL_WINCH; 1470 1471 case MIPS_LINUX_SIGURG: 1472 return GDB_SIGNAL_URG; 1473 1474 /* No way to differentiate between SIGIO and SIGPOLL. 1475 Therefore, we just handle the first one. */ 1476 case MIPS_LINUX_SIGIO: 1477 return GDB_SIGNAL_IO; 1478 1479 case MIPS_LINUX_SIGSTOP: 1480 return GDB_SIGNAL_STOP; 1481 1482 case MIPS_LINUX_SIGTSTP: 1483 return GDB_SIGNAL_TSTP; 1484 1485 case MIPS_LINUX_SIGCONT: 1486 return GDB_SIGNAL_CONT; 1487 1488 case MIPS_LINUX_SIGTTIN: 1489 return GDB_SIGNAL_TTIN; 1490 1491 case MIPS_LINUX_SIGTTOU: 1492 return GDB_SIGNAL_TTOU; 1493 1494 case MIPS_LINUX_SIGVTALRM: 1495 return GDB_SIGNAL_VTALRM; 1496 1497 case MIPS_LINUX_SIGPROF: 1498 return GDB_SIGNAL_PROF; 1499 1500 case MIPS_LINUX_SIGXCPU: 1501 return GDB_SIGNAL_XCPU; 1502 1503 case MIPS_LINUX_SIGXFSZ: 1504 return GDB_SIGNAL_XFSZ; 1505 } 1506 1507 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) 1508 { 1509 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of 1510 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ 1511 int offset = signal - MIPS_LINUX_SIGRTMIN; 1512 1513 if (offset == 0) 1514 return GDB_SIGNAL_REALTIME_32; 1515 else if (offset < 32) 1516 return (enum gdb_signal) (offset - 1 1517 + (int) GDB_SIGNAL_REALTIME_33); 1518 else 1519 return (enum gdb_signal) (offset - 32 1520 + (int) GDB_SIGNAL_REALTIME_64); 1521 } 1522 1523 return linux_gdb_signal_from_target (gdbarch, signal); 1524 } 1525 1526 /* Initialize one of the GNU/Linux OS ABIs. */ 1527 1528 static void 1529 mips_linux_init_abi (struct gdbarch_info info, 1530 struct gdbarch *gdbarch) 1531 { 1532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1533 enum mips_abi abi = mips_abi (gdbarch); 1534 struct tdesc_arch_data *tdesc_data = info.tdesc_data; 1535 1536 linux_init_abi (info, gdbarch); 1537 1538 /* Get the syscall number from the arch's register. */ 1539 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); 1540 1541 switch (abi) 1542 { 1543 case MIPS_ABI_O32: 1544 set_gdbarch_get_longjmp_target (gdbarch, 1545 mips_linux_get_longjmp_target); 1546 set_solib_svr4_fetch_link_map_offsets 1547 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1548 tramp_frame_prepend_unwinder (gdbarch, µmips_linux_o32_sigframe); 1549 tramp_frame_prepend_unwinder (gdbarch, 1550 µmips_linux_o32_rt_sigframe); 1551 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); 1552 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); 1553 set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml"); 1554 break; 1555 case MIPS_ABI_N32: 1556 set_gdbarch_get_longjmp_target (gdbarch, 1557 mips_linux_get_longjmp_target); 1558 set_solib_svr4_fetch_link_map_offsets 1559 (gdbarch, svr4_ilp32_fetch_link_map_offsets); 1560 set_gdbarch_long_double_bit (gdbarch, 128); 1561 /* These floatformats should probably be renamed. MIPS uses 1562 the same 128-bit IEEE floating point format that IA-64 uses, 1563 except that the quiet/signalling NaN bit is reversed (GDB 1564 does not distinguish between quiet and signalling NaNs). */ 1565 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1566 tramp_frame_prepend_unwinder (gdbarch, 1567 µmips_linux_n32_rt_sigframe); 1568 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); 1569 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml"); 1570 break; 1571 case MIPS_ABI_N64: 1572 set_gdbarch_get_longjmp_target (gdbarch, 1573 mips64_linux_get_longjmp_target); 1574 set_solib_svr4_fetch_link_map_offsets 1575 (gdbarch, svr4_lp64_fetch_link_map_offsets); 1576 set_gdbarch_long_double_bit (gdbarch, 128); 1577 /* These floatformats should probably be renamed. MIPS uses 1578 the same 128-bit IEEE floating point format that IA-64 uses, 1579 except that the quiet/signalling NaN bit is reversed (GDB 1580 does not distinguish between quiet and signalling NaNs). */ 1581 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); 1582 tramp_frame_prepend_unwinder (gdbarch, 1583 µmips_linux_n64_rt_sigframe); 1584 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); 1585 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml"); 1586 break; 1587 default: 1588 break; 1589 } 1590 1591 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); 1592 1593 set_gdbarch_software_single_step (gdbarch, mips_software_single_step); 1594 1595 /* Enable TLS support. */ 1596 set_gdbarch_fetch_tls_load_module_address (gdbarch, 1597 svr4_fetch_objfile_link_map); 1598 1599 /* Initialize this lazily, to avoid an initialization order 1600 dependency on solib-svr4.c's _initialize routine. */ 1601 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) 1602 { 1603 mips_svr4_so_ops = svr4_so_ops; 1604 mips_svr4_so_ops.in_dynsym_resolve_code 1605 = mips_linux_in_dynsym_resolve_code; 1606 } 1607 set_solib_ops (gdbarch, &mips_svr4_so_ops); 1608 1609 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); 1610 1611 set_gdbarch_core_read_description (gdbarch, 1612 mips_linux_core_read_description); 1613 1614 set_gdbarch_iterate_over_regset_sections 1615 (gdbarch, mips_linux_iterate_over_regset_sections); 1616 1617 set_gdbarch_gdb_signal_from_target (gdbarch, 1618 mips_gdb_signal_from_target); 1619 1620 set_gdbarch_gdb_signal_to_target (gdbarch, 1621 mips_gdb_signal_to_target); 1622 1623 tdep->syscall_next_pc = mips_linux_syscall_next_pc; 1624 1625 if (tdesc_data) 1626 { 1627 const struct tdesc_feature *feature; 1628 1629 /* If we have target-described registers, then we can safely 1630 reserve a number for MIPS_RESTART_REGNUM (whether it is 1631 described or not). */ 1632 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); 1633 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); 1634 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); 1635 1636 /* If it's present, then assign it to the reserved number. */ 1637 feature = tdesc_find_feature (info.target_desc, 1638 "org.gnu.gdb.mips.linux"); 1639 if (feature != NULL) 1640 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, 1641 "restart"); 1642 } 1643 } 1644 1645 void 1646 _initialize_mips_linux_tdep (void) 1647 { 1648 const struct bfd_arch_info *arch_info; 1649 1650 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); 1651 arch_info != NULL; 1652 arch_info = arch_info->next) 1653 { 1654 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, 1655 GDB_OSABI_LINUX, 1656 mips_linux_init_abi); 1657 } 1658 1659 /* Initialize the standard target descriptions. */ 1660 initialize_tdesc_mips_linux (); 1661 initialize_tdesc_mips_dsp_linux (); 1662 initialize_tdesc_mips64_linux (); 1663 initialize_tdesc_mips64_dsp_linux (); 1664 } 1665