1 /* Native-dependent code for GNU/Linux on MIPS processors. 2 3 Copyright (C) 2001-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "command.h" 22 #include "gdbcmd.h" 23 #include "inferior.h" 24 #include "mips-tdep.h" 25 #include "target.h" 26 #include "regcache.h" 27 #include "linux-nat-trad.h" 28 #include "mips-linux-tdep.h" 29 #include "target-descriptions.h" 30 31 #include "gdb_proc_service.h" 32 #include "gregset.h" 33 34 #include <sgidefs.h> 35 #include "nat/gdb_ptrace.h" 36 #include <asm/ptrace.h> 37 #include "inf-ptrace.h" 38 39 #include "nat/mips-linux-watch.h" 40 41 #ifndef PTRACE_GET_THREAD_AREA 42 #define PTRACE_GET_THREAD_AREA 25 43 #endif 44 45 class mips_linux_nat_target final : public linux_nat_trad_target 46 { 47 public: 48 /* Add our register access methods. */ 49 void fetch_registers (struct regcache *, int) override; 50 void store_registers (struct regcache *, int) override; 51 52 void close () override; 53 54 int can_use_hw_breakpoint (enum bptype, int, int) override; 55 56 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, 57 struct expression *) override; 58 59 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, 60 struct expression *) override; 61 62 bool stopped_by_watchpoint () override; 63 64 bool stopped_data_address (CORE_ADDR *) override; 65 66 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; 67 68 const struct target_desc *read_description () override; 69 70 protected: 71 /* Override linux_nat_trad_target methods. */ 72 CORE_ADDR register_u_offset (struct gdbarch *gdbarch, 73 int regno, int store_p) override; 74 75 /* Override linux_nat_target low methods. */ 76 void low_new_thread (struct lwp_info *lp) override; 77 78 private: 79 /* Helpers. See definitions. */ 80 void mips64_regsets_store_registers (struct regcache *regcache, 81 int regno); 82 void mips64_regsets_fetch_registers (struct regcache *regcache, 83 int regno); 84 }; 85 86 static mips_linux_nat_target the_mips_linux_nat_target; 87 88 /* Assume that we have PTRACE_GETREGS et al. support. If we do not, 89 we'll clear this and use PTRACE_PEEKUSER instead. */ 90 static int have_ptrace_regsets = 1; 91 92 /* Map gdb internal register number to ptrace ``address''. 93 These ``addresses'' are normally defined in <asm/ptrace.h>. 94 95 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, 96 and there's no point in reading or setting MIPS_ZERO_REGNUM. 97 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ 98 99 static CORE_ADDR 100 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) 101 { 102 CORE_ADDR regaddr; 103 104 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) 105 error (_("Bogon register number %d."), regno); 106 107 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) 108 regaddr = regno; 109 else if ((regno >= mips_regnum (gdbarch)->fp0) 110 && (regno < mips_regnum (gdbarch)->fp0 + 32)) 111 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); 112 else if (regno == mips_regnum (gdbarch)->pc) 113 regaddr = PC; 114 else if (regno == mips_regnum (gdbarch)->cause) 115 regaddr = store? (CORE_ADDR) -1 : CAUSE; 116 else if (regno == mips_regnum (gdbarch)->badvaddr) 117 regaddr = store? (CORE_ADDR) -1 : BADVADDR; 118 else if (regno == mips_regnum (gdbarch)->lo) 119 regaddr = MMLO; 120 else if (regno == mips_regnum (gdbarch)->hi) 121 regaddr = MMHI; 122 else if (regno == mips_regnum (gdbarch)->fp_control_status) 123 regaddr = FPC_CSR; 124 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 125 regaddr = store? (CORE_ADDR) -1 : FPC_EIR; 126 else if (mips_regnum (gdbarch)->dspacc != -1 127 && regno >= mips_regnum (gdbarch)->dspacc 128 && regno < mips_regnum (gdbarch)->dspacc + 6) 129 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); 130 else if (regno == mips_regnum (gdbarch)->dspctl) 131 regaddr = DSP_CONTROL; 132 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) 133 regaddr = 0; 134 else 135 regaddr = (CORE_ADDR) -1; 136 137 return regaddr; 138 } 139 140 static CORE_ADDR 141 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) 142 { 143 CORE_ADDR regaddr; 144 145 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) 146 error (_("Bogon register number %d."), regno); 147 148 /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR 149 or PTRACE_POKEUSR. */ 150 if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET)) 151 return (CORE_ADDR) -1; 152 153 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) 154 regaddr = regno; 155 else if ((regno >= mips_regnum (gdbarch)->fp0) 156 && (regno < mips_regnum (gdbarch)->fp0 + 32)) 157 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); 158 else if (regno == mips_regnum (gdbarch)->pc) 159 regaddr = MIPS64_PC; 160 else if (regno == mips_regnum (gdbarch)->cause) 161 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; 162 else if (regno == mips_regnum (gdbarch)->badvaddr) 163 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; 164 else if (regno == mips_regnum (gdbarch)->lo) 165 regaddr = MIPS64_MMLO; 166 else if (regno == mips_regnum (gdbarch)->hi) 167 regaddr = MIPS64_MMHI; 168 else if (regno == mips_regnum (gdbarch)->fp_control_status) 169 regaddr = MIPS64_FPC_CSR; 170 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 171 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; 172 else if (mips_regnum (gdbarch)->dspacc != -1 173 && regno >= mips_regnum (gdbarch)->dspacc 174 && regno < mips_regnum (gdbarch)->dspacc + 6) 175 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); 176 else if (regno == mips_regnum (gdbarch)->dspctl) 177 regaddr = DSP_CONTROL; 178 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) 179 regaddr = 0; 180 else 181 regaddr = (CORE_ADDR) -1; 182 183 return regaddr; 184 } 185 186 /* Fetch the thread-local storage pointer for libthread_db. */ 187 188 ps_err_e 189 ps_get_thread_area (struct ps_prochandle *ph, 190 lwpid_t lwpid, int idx, void **base) 191 { 192 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) 193 return PS_ERR; 194 195 /* IDX is the bias from the thread pointer to the beginning of the 196 thread descriptor. It has to be subtracted due to implementation 197 quirks in libthread_db. */ 198 *base = (void *) ((char *)*base - idx); 199 200 return PS_OK; 201 } 202 203 /* Wrapper functions. These are only used by libthread_db. */ 204 205 void 206 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) 207 { 208 if (mips_isa_regsize (regcache->arch ()) == 4) 209 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); 210 else 211 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); 212 } 213 214 void 215 fill_gregset (const struct regcache *regcache, 216 gdb_gregset_t *gregsetp, int regno) 217 { 218 if (mips_isa_regsize (regcache->arch ()) == 4) 219 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); 220 else 221 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); 222 } 223 224 void 225 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) 226 { 227 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *) fpregsetp); 228 } 229 230 void 231 fill_fpregset (const struct regcache *regcache, 232 gdb_fpregset_t *fpregsetp, int regno) 233 { 234 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *) fpregsetp, regno); 235 } 236 237 238 /* Fetch REGNO (or all registers if REGNO == -1) from the target 239 using PTRACE_GETREGS et al. */ 240 241 void 242 mips_linux_nat_target::mips64_regsets_fetch_registers 243 (struct regcache *regcache, int regno) 244 { 245 struct gdbarch *gdbarch = regcache->arch (); 246 int is_fp, is_dsp; 247 int have_dsp; 248 int regi; 249 int tid; 250 251 if (regno >= mips_regnum (gdbarch)->fp0 252 && regno <= mips_regnum (gdbarch)->fp0 + 32) 253 is_fp = 1; 254 else if (regno == mips_regnum (gdbarch)->fp_control_status) 255 is_fp = 1; 256 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 257 is_fp = 1; 258 else 259 is_fp = 0; 260 261 /* DSP registers are optional and not a part of any set. */ 262 have_dsp = mips_regnum (gdbarch)->dspctl != -1; 263 if (!have_dsp) 264 is_dsp = 0; 265 else if (regno >= mips_regnum (gdbarch)->dspacc 266 && regno < mips_regnum (gdbarch)->dspacc + 6) 267 is_dsp = 1; 268 else if (regno == mips_regnum (gdbarch)->dspctl) 269 is_dsp = 1; 270 else 271 is_dsp = 0; 272 273 tid = get_ptrace_pid (regcache->ptid ()); 274 275 if (regno == -1 || (!is_fp && !is_dsp)) 276 { 277 mips64_elf_gregset_t regs; 278 279 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) 280 { 281 if (errno == EIO) 282 { 283 have_ptrace_regsets = 0; 284 return; 285 } 286 perror_with_name (_("Couldn't get registers")); 287 } 288 289 mips64_supply_gregset (regcache, 290 (const mips64_elf_gregset_t *) ®s); 291 } 292 293 if (regno == -1 || is_fp) 294 { 295 mips64_elf_fpregset_t fp_regs; 296 297 if (ptrace (PTRACE_GETFPREGS, tid, 0L, 298 (PTRACE_TYPE_ARG3) &fp_regs) == -1) 299 { 300 if (errno == EIO) 301 { 302 have_ptrace_regsets = 0; 303 return; 304 } 305 perror_with_name (_("Couldn't get FP registers")); 306 } 307 308 mips64_supply_fpregset (regcache, 309 (const mips64_elf_fpregset_t *) &fp_regs); 310 } 311 312 if (is_dsp) 313 linux_nat_trad_target::fetch_registers (regcache, regno); 314 else if (regno == -1 && have_dsp) 315 { 316 for (regi = mips_regnum (gdbarch)->dspacc; 317 regi < mips_regnum (gdbarch)->dspacc + 6; 318 regi++) 319 linux_nat_trad_target::fetch_registers (regcache, regi); 320 linux_nat_trad_target::fetch_registers (regcache, 321 mips_regnum (gdbarch)->dspctl); 322 } 323 } 324 325 /* Store REGNO (or all registers if REGNO == -1) to the target 326 using PTRACE_SETREGS et al. */ 327 328 void 329 mips_linux_nat_target::mips64_regsets_store_registers 330 (struct regcache *regcache, int regno) 331 { 332 struct gdbarch *gdbarch = regcache->arch (); 333 int is_fp, is_dsp; 334 int have_dsp; 335 int regi; 336 int tid; 337 338 if (regno >= mips_regnum (gdbarch)->fp0 339 && regno <= mips_regnum (gdbarch)->fp0 + 32) 340 is_fp = 1; 341 else if (regno == mips_regnum (gdbarch)->fp_control_status) 342 is_fp = 1; 343 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) 344 is_fp = 1; 345 else 346 is_fp = 0; 347 348 /* DSP registers are optional and not a part of any set. */ 349 have_dsp = mips_regnum (gdbarch)->dspctl != -1; 350 if (!have_dsp) 351 is_dsp = 0; 352 else if (regno >= mips_regnum (gdbarch)->dspacc 353 && regno < mips_regnum (gdbarch)->dspacc + 6) 354 is_dsp = 1; 355 else if (regno == mips_regnum (gdbarch)->dspctl) 356 is_dsp = 1; 357 else 358 is_dsp = 0; 359 360 tid = get_ptrace_pid (regcache->ptid ()); 361 362 if (regno == -1 || (!is_fp && !is_dsp)) 363 { 364 mips64_elf_gregset_t regs; 365 366 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) 367 perror_with_name (_("Couldn't get registers")); 368 369 mips64_fill_gregset (regcache, ®s, regno); 370 371 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) 372 perror_with_name (_("Couldn't set registers")); 373 } 374 375 if (regno == -1 || is_fp) 376 { 377 mips64_elf_fpregset_t fp_regs; 378 379 if (ptrace (PTRACE_GETFPREGS, tid, 0L, 380 (PTRACE_TYPE_ARG3) &fp_regs) == -1) 381 perror_with_name (_("Couldn't get FP registers")); 382 383 mips64_fill_fpregset (regcache, &fp_regs, regno); 384 385 if (ptrace (PTRACE_SETFPREGS, tid, 0L, 386 (PTRACE_TYPE_ARG3) &fp_regs) == -1) 387 perror_with_name (_("Couldn't set FP registers")); 388 } 389 390 if (is_dsp) 391 linux_nat_trad_target::store_registers (regcache, regno); 392 else if (regno == -1 && have_dsp) 393 { 394 for (regi = mips_regnum (gdbarch)->dspacc; 395 regi < mips_regnum (gdbarch)->dspacc + 6; 396 regi++) 397 linux_nat_trad_target::store_registers (regcache, regi); 398 linux_nat_trad_target::store_registers (regcache, 399 mips_regnum (gdbarch)->dspctl); 400 } 401 } 402 403 /* Fetch REGNO (or all registers if REGNO == -1) from the target 404 using any working method. */ 405 406 void 407 mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) 408 { 409 /* Unless we already know that PTRACE_GETREGS does not work, try it. */ 410 if (have_ptrace_regsets) 411 mips64_regsets_fetch_registers (regcache, regnum); 412 413 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall 414 back to PTRACE_PEEKUSER. */ 415 if (!have_ptrace_regsets) 416 { 417 linux_nat_trad_target::fetch_registers (regcache, regnum); 418 419 /* Fill the inaccessible zero register with zero. */ 420 if (regnum == MIPS_ZERO_REGNUM || regnum == -1) 421 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); 422 } 423 } 424 425 /* Store REGNO (or all registers if REGNO == -1) to the target 426 using any working method. */ 427 428 void 429 mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum) 430 { 431 /* Unless we already know that PTRACE_GETREGS does not work, try it. */ 432 if (have_ptrace_regsets) 433 mips64_regsets_store_registers (regcache, regnum); 434 435 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall 436 back to PTRACE_PEEKUSER. */ 437 if (!have_ptrace_regsets) 438 linux_nat_trad_target::store_registers (regcache, regnum); 439 } 440 441 /* Return the address in the core dump or inferior of register 442 REGNO. */ 443 444 CORE_ADDR 445 mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch, 446 int regno, int store_p) 447 { 448 if (mips_abi_regsize (gdbarch) == 8) 449 return mips64_linux_register_addr (gdbarch, regno, store_p); 450 else 451 return mips_linux_register_addr (gdbarch, regno, store_p); 452 } 453 454 const struct target_desc * 455 mips_linux_nat_target::read_description () 456 { 457 static int have_dsp = -1; 458 459 if (have_dsp < 0) 460 { 461 int tid = get_ptrace_pid (inferior_ptid); 462 463 errno = 0; 464 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); 465 switch (errno) 466 { 467 case 0: 468 have_dsp = 1; 469 break; 470 case EIO: 471 have_dsp = 0; 472 break; 473 default: 474 perror_with_name (_("Couldn't check DSP support")); 475 break; 476 } 477 } 478 479 /* Report that target registers are a size we know for sure 480 that we can get from ptrace. */ 481 if (_MIPS_SIM == _ABIO32) 482 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; 483 else 484 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; 485 } 486 487 /* -1 if the kernel and/or CPU do not support watch registers. 488 1 if watch_readback is valid and we can read style, num_valid 489 and the masks. 490 0 if we need to read the watch_readback. */ 491 492 static int watch_readback_valid; 493 494 /* Cached watch register read values. */ 495 496 static struct pt_watch_regs watch_readback; 497 498 static struct mips_watchpoint *current_watches; 499 500 /* The current set of watch register values for writing the 501 registers. */ 502 503 static struct pt_watch_regs watch_mirror; 504 505 static void 506 mips_show_dr (const char *func, CORE_ADDR addr, 507 int len, enum target_hw_bp_type type) 508 { 509 int i; 510 511 puts_unfiltered (func); 512 if (addr || len) 513 printf_unfiltered (" (addr=%s, len=%d, type=%s)", 514 paddress (target_gdbarch (), addr), len, 515 type == hw_write ? "data-write" 516 : (type == hw_read ? "data-read" 517 : (type == hw_access ? "data-read/write" 518 : (type == hw_execute ? "instruction-execute" 519 : "??unknown??")))); 520 puts_unfiltered (":\n"); 521 522 for (i = 0; i < MAX_DEBUG_REGISTER; i++) 523 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, 524 paddress (target_gdbarch (), 525 mips_linux_watch_get_watchlo (&watch_mirror, 526 i)), 527 paddress (target_gdbarch (), 528 mips_linux_watch_get_watchhi (&watch_mirror, 529 i))); 530 } 531 532 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can 533 handle the specified watch type. */ 534 535 int 536 mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type, 537 int cnt, int ot) 538 { 539 int i; 540 uint32_t wanted_mask, irw_mask; 541 542 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), 543 &watch_readback, 544 &watch_readback_valid, 0)) 545 return 0; 546 547 switch (type) 548 { 549 case bp_hardware_watchpoint: 550 wanted_mask = W_MASK; 551 break; 552 case bp_read_watchpoint: 553 wanted_mask = R_MASK; 554 break; 555 case bp_access_watchpoint: 556 wanted_mask = R_MASK | W_MASK; 557 break; 558 default: 559 return 0; 560 } 561 562 for (i = 0; 563 i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; 564 i++) 565 { 566 irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); 567 if ((irw_mask & wanted_mask) == wanted_mask) 568 cnt--; 569 } 570 return (cnt == 0) ? 1 : 0; 571 } 572 573 /* Target to_stopped_by_watchpoint implementation. Return 1 if 574 stopped by watchpoint. The watchhi R and W bits indicate the watch 575 register triggered. */ 576 577 bool 578 mips_linux_nat_target::stopped_by_watchpoint () 579 { 580 int n; 581 int num_valid; 582 583 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), 584 &watch_readback, 585 &watch_readback_valid, 1)) 586 return false; 587 588 num_valid = mips_linux_watch_get_num_valid (&watch_readback); 589 590 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) 591 if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) 592 return true; 593 594 return false; 595 } 596 597 /* Target to_stopped_data_address implementation. Set the address 598 where the watch triggered (if known). Return 1 if the address was 599 known. */ 600 601 bool 602 mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr) 603 { 604 /* On mips we don't know the low order 3 bits of the data address, 605 so we must return false. */ 606 return false; 607 } 608 609 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if 610 the specified region can be covered by the watch registers. */ 611 612 int 613 mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) 614 { 615 struct pt_watch_regs dummy_regs; 616 int i; 617 618 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), 619 &watch_readback, 620 &watch_readback_valid, 0)) 621 return 0; 622 623 dummy_regs = watch_readback; 624 /* Clear them out. */ 625 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) 626 mips_linux_watch_set_watchlo (&dummy_regs, i, 0); 627 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); 628 } 629 630 /* Write the mirrored watch register values for each thread. */ 631 632 static int 633 write_watchpoint_regs (void) 634 { 635 struct lwp_info *lp; 636 int tid; 637 638 ALL_LWPS (lp) 639 { 640 tid = lp->ptid.lwp (); 641 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) 642 perror_with_name (_("Couldn't write debug register")); 643 } 644 return 0; 645 } 646 647 /* linux_nat_target::low_new_thread implementation. Write the 648 mirrored watch register values for the new thread. */ 649 650 void 651 mips_linux_nat_target::low_new_thread (struct lwp_info *lp) 652 { 653 long tid = lp->ptid.lwp (); 654 655 if (!mips_linux_read_watch_registers (tid, 656 &watch_readback, 657 &watch_readback_valid, 0)) 658 return; 659 660 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) 661 perror_with_name (_("Couldn't write debug register")); 662 } 663 664 /* Target to_insert_watchpoint implementation. Try to insert a new 665 watch. Return zero on success. */ 666 667 int 668 mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, 669 enum target_hw_bp_type type, 670 struct expression *cond) 671 { 672 struct pt_watch_regs regs; 673 struct mips_watchpoint *new_watch; 674 struct mips_watchpoint **pw; 675 676 int retval; 677 678 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), 679 &watch_readback, 680 &watch_readback_valid, 0)) 681 return -1; 682 683 if (len <= 0) 684 return -1; 685 686 regs = watch_readback; 687 /* Add the current watches. */ 688 mips_linux_watch_populate_regs (current_watches, ®s); 689 690 /* Now try to add the new watch. */ 691 if (!mips_linux_watch_try_one_watch (®s, addr, len, 692 mips_linux_watch_type_to_irw (type))) 693 return -1; 694 695 /* It fit. Stick it on the end of the list. */ 696 new_watch = XNEW (struct mips_watchpoint); 697 new_watch->addr = addr; 698 new_watch->len = len; 699 new_watch->type = type; 700 new_watch->next = NULL; 701 702 pw = ¤t_watches; 703 while (*pw != NULL) 704 pw = &(*pw)->next; 705 *pw = new_watch; 706 707 watch_mirror = regs; 708 retval = write_watchpoint_regs (); 709 710 if (show_debug_regs) 711 mips_show_dr ("insert_watchpoint", addr, len, type); 712 713 return retval; 714 } 715 716 /* Target to_remove_watchpoint implementation. Try to remove a watch. 717 Return zero on success. */ 718 719 int 720 mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, 721 enum target_hw_bp_type type, 722 struct expression *cond) 723 { 724 int retval; 725 int deleted_one; 726 727 struct mips_watchpoint **pw; 728 struct mips_watchpoint *w; 729 730 /* Search for a known watch that matches. Then unlink and free 731 it. */ 732 deleted_one = 0; 733 pw = ¤t_watches; 734 while ((w = *pw)) 735 { 736 if (w->addr == addr && w->len == len && w->type == type) 737 { 738 *pw = w->next; 739 xfree (w); 740 deleted_one = 1; 741 break; 742 } 743 pw = &(w->next); 744 } 745 746 if (!deleted_one) 747 return -1; /* We don't know about it, fail doing nothing. */ 748 749 /* At this point watch_readback is known to be valid because we 750 could not have added the watch without reading it. */ 751 gdb_assert (watch_readback_valid == 1); 752 753 watch_mirror = watch_readback; 754 mips_linux_watch_populate_regs (current_watches, &watch_mirror); 755 756 retval = write_watchpoint_regs (); 757 758 if (show_debug_regs) 759 mips_show_dr ("remove_watchpoint", addr, len, type); 760 761 return retval; 762 } 763 764 /* Target to_close implementation. Free any watches and call the 765 super implementation. */ 766 767 void 768 mips_linux_nat_target::close () 769 { 770 struct mips_watchpoint *w; 771 struct mips_watchpoint *nw; 772 773 /* Clean out the current_watches list. */ 774 w = current_watches; 775 while (w) 776 { 777 nw = w->next; 778 xfree (w); 779 w = nw; 780 } 781 current_watches = NULL; 782 783 linux_nat_trad_target::close (); 784 } 785 786 void 787 _initialize_mips_linux_nat (void) 788 { 789 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, 790 &show_debug_regs, _("\ 791 Set whether to show variables that mirror the mips debug registers."), _("\ 792 Show whether to show variables that mirror the mips debug registers."), _("\ 793 Use \"on\" to enable, \"off\" to disable.\n\ 794 If enabled, the debug registers values are shown when GDB inserts\n\ 795 or removes a hardware breakpoint or watchpoint, and when the inferior\n\ 796 triggers a breakpoint or watchpoint."), 797 NULL, 798 NULL, 799 &maintenance_set_cmdlist, 800 &maintenance_show_cmdlist); 801 802 linux_target = &the_mips_linux_nat_target; 803 add_inf_child_target (&the_mips_linux_nat_target); 804 } 805