1 /* Renesas M32C target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 2004-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "gdb/sim-m32c.h" 22 #include "gdbtypes.h" 23 #include "regcache.h" 24 #include "arch-utils.h" 25 #include "frame.h" 26 #include "frame-unwind.h" 27 #include "symtab.h" 28 #include "gdbcore.h" 29 #include "value.h" 30 #include "reggroups.h" 31 #include "prologue-value.h" 32 #include "objfiles.h" 33 #include "gdbarch.h" 34 35 36 /* The m32c tdep structure. */ 37 38 static const reggroup *m32c_dma_reggroup; 39 40 /* The type of a function that moves the value of REG between CACHE or 41 BUF --- in either direction. */ 42 typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg, 43 struct regcache *cache, 44 const gdb_byte *buf); 45 46 typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg, 47 readable_regcache *cache, 48 gdb_byte *buf); 49 50 struct m32c_reg 51 { 52 /* The name of this register. */ 53 const char *name; 54 55 /* Its type. */ 56 struct type *type; 57 58 /* The architecture this register belongs to. */ 59 struct gdbarch *arch; 60 61 /* Its GDB register number. */ 62 int num; 63 64 /* Its sim register number. */ 65 int sim_num; 66 67 /* Its DWARF register number, or -1 if it doesn't have one. */ 68 int dwarf_num; 69 70 /* Register group memberships. */ 71 unsigned int general_p : 1; 72 unsigned int dma_p : 1; 73 unsigned int system_p : 1; 74 unsigned int save_restore_p : 1; 75 76 /* Functions to read its value from a regcache, and write its value 77 to a regcache. */ 78 m32c_read_reg_t *read; 79 m32c_write_reg_t *write; 80 81 /* Data for READ and WRITE functions. The exact meaning depends on 82 the specific functions selected; see the comments for those 83 functions. */ 84 struct m32c_reg *rx, *ry; 85 int n; 86 }; 87 88 89 /* An overestimate of the number of raw and pseudoregisters we will 90 have. The exact answer depends on the variant of the architecture 91 at hand, but we can use this to declare statically allocated 92 arrays, and bump it up when needed. */ 93 #define M32C_MAX_NUM_REGS (75) 94 95 /* The largest assigned DWARF register number. */ 96 #define M32C_MAX_DWARF_REGNUM (40) 97 98 99 struct m32c_gdbarch_tdep : gdbarch_tdep_base 100 { 101 /* All the registers for this variant, indexed by GDB register 102 number, and the number of registers present. */ 103 struct m32c_reg regs[M32C_MAX_NUM_REGS] {}; 104 105 /* The number of valid registers. */ 106 int num_regs = 0; 107 108 /* Interesting registers. These are pointers into REGS. */ 109 struct m32c_reg *pc = nullptr, *flg = nullptr; 110 struct m32c_reg *r0 = nullptr, *r1 = nullptr, *r2 = nullptr, *r3 = nullptr, 111 *a0 = nullptr, *a1 = nullptr; 112 struct m32c_reg *r2r0 = nullptr, *r3r2r1r0 = nullptr, *r3r1r2r0 = nullptr; 113 struct m32c_reg *sb = nullptr, *fb = nullptr, *sp = nullptr; 114 115 /* A table indexed by DWARF register numbers, pointing into 116 REGS. */ 117 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1] {}; 118 119 /* Types for this architecture. We can't use the builtin_type_foo 120 types, because they're not initialized when building a gdbarch 121 structure. */ 122 struct type *voyd = nullptr, *ptr_voyd = nullptr, *func_voyd = nullptr; 123 struct type *uint8 = nullptr, *uint16 = nullptr; 124 struct type *int8 = nullptr, *int16 = nullptr, *int32 = nullptr, 125 *int64 = nullptr; 126 127 /* The types for data address and code address registers. */ 128 struct type *data_addr_reg_type = nullptr, *code_addr_reg_type = nullptr; 129 130 /* The number of bytes a return address pushed by a 'jsr' instruction 131 occupies on the stack. */ 132 int ret_addr_bytes = 0; 133 134 /* The number of bytes an address register occupies on the stack 135 when saved by an 'enter' or 'pushm' instruction. */ 136 int push_addr_bytes = 0; 137 }; 138 139 140 /* Types. */ 141 142 static void 143 make_types (struct gdbarch *arch) 144 { 145 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 146 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; 147 int data_addr_reg_bits, code_addr_reg_bits; 148 char type_name[50]; 149 150 #if 0 151 /* This is used to clip CORE_ADDR values, so this value is 152 appropriate both on the m32c, where pointers are 32 bits long, 153 and on the m16c, where pointers are sixteen bits long, but there 154 may be code above the 64k boundary. */ 155 set_gdbarch_addr_bit (arch, 24); 156 #else 157 /* GCC uses 32 bits for addrs in the dwarf info, even though 158 only 16/24 bits are used. Setting addr_bit to 24 causes 159 errors in reading the dwarf addresses. */ 160 set_gdbarch_addr_bit (arch, 32); 161 #endif 162 163 set_gdbarch_int_bit (arch, 16); 164 switch (mach) 165 { 166 case bfd_mach_m16c: 167 data_addr_reg_bits = 16; 168 code_addr_reg_bits = 24; 169 set_gdbarch_ptr_bit (arch, 16); 170 tdep->ret_addr_bytes = 3; 171 tdep->push_addr_bytes = 2; 172 break; 173 174 case bfd_mach_m32c: 175 data_addr_reg_bits = 24; 176 code_addr_reg_bits = 24; 177 set_gdbarch_ptr_bit (arch, 32); 178 tdep->ret_addr_bytes = 4; 179 tdep->push_addr_bytes = 4; 180 break; 181 182 default: 183 gdb_assert_not_reached ("unexpected mach"); 184 } 185 186 /* The builtin_type_mumble variables are sometimes uninitialized when 187 this is called, so we avoid using them. */ 188 tdep->voyd = arch_type (arch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void"); 189 tdep->ptr_voyd 190 = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd); 191 tdep->func_voyd = lookup_function_type (tdep->voyd); 192 193 xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t", 194 gdbarch_bfd_arch_info (arch)->printable_name); 195 tdep->data_addr_reg_type 196 = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd); 197 198 xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t", 199 gdbarch_bfd_arch_info (arch)->printable_name); 200 tdep->code_addr_reg_type 201 = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd); 202 203 tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); 204 tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); 205 tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); 206 tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); 207 tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); 208 tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); 209 } 210 211 212 213 /* Register set. */ 214 215 static const char * 216 m32c_register_name (struct gdbarch *gdbarch, int num) 217 { 218 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 219 return tdep->regs[num].name; 220 } 221 222 223 static struct type * 224 m32c_register_type (struct gdbarch *arch, int reg_nr) 225 { 226 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 227 return tdep->regs[reg_nr].type; 228 } 229 230 231 static int 232 m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) 233 { 234 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 235 return tdep->regs[reg_nr].sim_num; 236 } 237 238 239 static int 240 m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) 241 { 242 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 243 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM 244 && tdep->dwarf_regs[reg_nr]) 245 return tdep->dwarf_regs[reg_nr]->num; 246 else 247 /* The DWARF CFI code expects to see -1 for invalid register 248 numbers. */ 249 return -1; 250 } 251 252 253 static int 254 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 255 const struct reggroup *group) 256 { 257 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 258 struct m32c_reg *reg = &tdep->regs[regnum]; 259 260 /* The anonymous raw registers aren't in any groups. */ 261 if (! reg->name) 262 return 0; 263 264 if (group == all_reggroup) 265 return 1; 266 267 if (group == general_reggroup 268 && reg->general_p) 269 return 1; 270 271 if (group == m32c_dma_reggroup 272 && reg->dma_p) 273 return 1; 274 275 if (group == system_reggroup 276 && reg->system_p) 277 return 1; 278 279 /* Since the m32c DWARF register numbers refer to cooked registers, not 280 raw registers, and frame_pop depends on the save and restore groups 281 containing registers the DWARF CFI will actually mention, our save 282 and restore groups are cooked registers, not raw registers. (This is 283 why we can't use the default reggroup function.) */ 284 if ((group == save_reggroup 285 || group == restore_reggroup) 286 && reg->save_restore_p) 287 return 1; 288 289 return 0; 290 } 291 292 293 /* Register move functions. We declare them here using 294 m32c_{read,write}_reg_t to check the types. */ 295 static m32c_read_reg_t m32c_raw_read; 296 static m32c_read_reg_t m32c_banked_read; 297 static m32c_read_reg_t m32c_sb_read; 298 static m32c_read_reg_t m32c_part_read; 299 static m32c_read_reg_t m32c_cat_read; 300 static m32c_read_reg_t m32c_r3r2r1r0_read; 301 302 static m32c_write_reg_t m32c_raw_write; 303 static m32c_write_reg_t m32c_banked_write; 304 static m32c_write_reg_t m32c_sb_write; 305 static m32c_write_reg_t m32c_part_write; 306 static m32c_write_reg_t m32c_cat_write; 307 static m32c_write_reg_t m32c_r3r2r1r0_write; 308 309 /* Copy the value of the raw register REG from CACHE to BUF. */ 310 static enum register_status 311 m32c_raw_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 312 { 313 return cache->raw_read (reg->num, buf); 314 } 315 316 317 /* Copy the value of the raw register REG from BUF to CACHE. */ 318 static enum register_status 319 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, 320 const gdb_byte *buf) 321 { 322 cache->raw_write (reg->num, buf); 323 324 return REG_VALID; 325 } 326 327 328 /* Return the value of the 'flg' register in CACHE. */ 329 static int 330 m32c_read_flg (readable_regcache *cache) 331 { 332 gdbarch *arch = cache->arch (); 333 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 334 ULONGEST flg; 335 336 cache->raw_read (tdep->flg->num, &flg); 337 return flg & 0xffff; 338 } 339 340 341 /* Evaluate the real register number of a banked register. */ 342 static struct m32c_reg * 343 m32c_banked_register (struct m32c_reg *reg, readable_regcache *cache) 344 { 345 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); 346 } 347 348 349 /* Move the value of a banked register from CACHE to BUF. 350 If the value of the 'flg' register in CACHE has any of the bits 351 masked in REG->n set, then read REG->ry. Otherwise, read 352 REG->rx. */ 353 static enum register_status 354 m32c_banked_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 355 { 356 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); 357 return cache->raw_read (bank_reg->num, buf); 358 } 359 360 361 /* Move the value of a banked register from BUF to CACHE. 362 If the value of the 'flg' register in CACHE has any of the bits 363 masked in REG->n set, then write REG->ry. Otherwise, write 364 REG->rx. */ 365 static enum register_status 366 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, 367 const gdb_byte *buf) 368 { 369 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); 370 cache->raw_write (bank_reg->num, buf); 371 372 return REG_VALID; 373 } 374 375 376 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a 377 banked register; on bfd_mach_m16c, it's not. */ 378 static enum register_status 379 m32c_sb_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 380 { 381 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) 382 return m32c_raw_read (reg->rx, cache, buf); 383 else 384 return m32c_banked_read (reg, cache, buf); 385 } 386 387 388 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a 389 banked register; on bfd_mach_m16c, it's not. */ 390 static enum register_status 391 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf) 392 { 393 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) 394 m32c_raw_write (reg->rx, cache, buf); 395 else 396 m32c_banked_write (reg, cache, buf); 397 398 return REG_VALID; 399 } 400 401 402 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P 403 and *LEN_P to the offset and length, in bytes, of the part REG 404 occupies in its underlying register. The offset is from the 405 lower-addressed end, regardless of the architecture's endianness. 406 (The M32C family is always little-endian, but let's keep those 407 assumptions out of here.) */ 408 static void 409 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) 410 { 411 /* The length of the containing register, of which REG is one part. */ 412 int containing_len = reg->rx->type->length (); 413 414 /* The length of one "element" in our imaginary array. */ 415 int elt_len = reg->type->length (); 416 417 /* The offset of REG's "element" from the least significant end of 418 the containing register. */ 419 int elt_offset = reg->n * elt_len; 420 421 /* If we extend off the end, trim the length of the element. */ 422 if (elt_offset + elt_len > containing_len) 423 { 424 elt_len = containing_len - elt_offset; 425 /* We shouldn't be declaring partial registers that go off the 426 end of their containing registers. */ 427 gdb_assert (elt_len > 0); 428 } 429 430 /* Flip the offset around if we're big-endian. */ 431 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 432 elt_offset = reg->rx->type->length () - elt_offset - elt_len; 433 434 *offset_p = elt_offset; 435 *len_p = elt_len; 436 } 437 438 439 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE 440 to BUF. Treating the value of the register REG->rx as an array of 441 REG->type values, where higher indices refer to more significant 442 bits, read the value of the REG->n'th element. */ 443 static enum register_status 444 m32c_part_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 445 { 446 int offset, len; 447 448 memset (buf, 0, reg->type->length ()); 449 m32c_find_part (reg, &offset, &len); 450 return cache->cooked_read_part (reg->rx->num, offset, len, buf); 451 } 452 453 454 /* Move the value of a banked register from BUF to CACHE. 455 Treating the value of the register REG->rx as an array of REG->type 456 values, where higher indices refer to more significant bits, write 457 the value of the REG->n'th element. */ 458 static enum register_status 459 m32c_part_write (struct m32c_reg *reg, struct regcache *cache, 460 const gdb_byte *buf) 461 { 462 int offset, len; 463 464 m32c_find_part (reg, &offset, &len); 465 cache->cooked_write_part (reg->rx->num, offset, len, buf); 466 467 return REG_VALID; 468 } 469 470 471 /* Move the value of REG from CACHE to BUF. REG's value is the 472 concatenation of the values of the registers REG->rx and REG->ry, 473 with REG->rx contributing the more significant bits. */ 474 static enum register_status 475 m32c_cat_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 476 { 477 int high_bytes = reg->rx->type->length (); 478 int low_bytes = reg->ry->type->length (); 479 enum register_status status; 480 481 gdb_assert (reg->type->length () == high_bytes + low_bytes); 482 483 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 484 { 485 status = cache->cooked_read (reg->rx->num, buf); 486 if (status == REG_VALID) 487 status = cache->cooked_read (reg->ry->num, buf + high_bytes); 488 } 489 else 490 { 491 status = cache->cooked_read (reg->rx->num, buf + low_bytes); 492 if (status == REG_VALID) 493 status = cache->cooked_read (reg->ry->num, buf); 494 } 495 return status; 496 } 497 498 499 /* Move the value of REG from CACHE to BUF. REG's value is the 500 concatenation of the values of the registers REG->rx and REG->ry, 501 with REG->rx contributing the more significant bits. */ 502 static enum register_status 503 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, 504 const gdb_byte *buf) 505 { 506 int high_bytes = reg->rx->type->length (); 507 int low_bytes = reg->ry->type->length (); 508 509 gdb_assert (reg->type->length () == high_bytes + low_bytes); 510 511 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 512 { 513 cache->cooked_write (reg->rx->num, buf); 514 cache->cooked_write (reg->ry->num, buf + high_bytes); 515 } 516 else 517 { 518 cache->cooked_write (reg->rx->num, buf + low_bytes); 519 cache->cooked_write (reg->ry->num, buf); 520 } 521 522 return REG_VALID; 523 } 524 525 526 /* Copy the value of the raw register REG from CACHE to BUF. REG is 527 the concatenation (from most significant to least) of r3, r2, r1, 528 and r0. */ 529 static enum register_status 530 m32c_r3r2r1r0_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) 531 { 532 gdbarch *arch = reg->arch; 533 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 534 int len = tdep->r0->type->length (); 535 enum register_status status; 536 537 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 538 { 539 status = cache->cooked_read (tdep->r0->num, buf + len * 3); 540 if (status == REG_VALID) 541 status = cache->cooked_read (tdep->r1->num, buf + len * 2); 542 if (status == REG_VALID) 543 status = cache->cooked_read (tdep->r2->num, buf + len * 1); 544 if (status == REG_VALID) 545 status = cache->cooked_read (tdep->r3->num, buf); 546 } 547 else 548 { 549 status = cache->cooked_read (tdep->r0->num, buf); 550 if (status == REG_VALID) 551 status = cache->cooked_read (tdep->r1->num, buf + len * 1); 552 if (status == REG_VALID) 553 status = cache->cooked_read (tdep->r2->num, buf + len * 2); 554 if (status == REG_VALID) 555 status = cache->cooked_read (tdep->r3->num, buf + len * 3); 556 } 557 558 return status; 559 } 560 561 562 /* Copy the value of the raw register REG from BUF to CACHE. REG is 563 the concatenation (from most significant to least) of r3, r2, r1, 564 and r0. */ 565 static enum register_status 566 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, 567 const gdb_byte *buf) 568 { 569 gdbarch *arch = reg->arch; 570 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 571 int len = tdep->r0->type->length (); 572 573 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 574 { 575 cache->cooked_write (tdep->r0->num, buf + len * 3); 576 cache->cooked_write (tdep->r1->num, buf + len * 2); 577 cache->cooked_write (tdep->r2->num, buf + len * 1); 578 cache->cooked_write (tdep->r3->num, buf); 579 } 580 else 581 { 582 cache->cooked_write (tdep->r0->num, buf); 583 cache->cooked_write (tdep->r1->num, buf + len * 1); 584 cache->cooked_write (tdep->r2->num, buf + len * 2); 585 cache->cooked_write (tdep->r3->num, buf + len * 3); 586 } 587 588 return REG_VALID; 589 } 590 591 592 static enum register_status 593 m32c_pseudo_register_read (struct gdbarch *arch, 594 readable_regcache *cache, 595 int cookednum, 596 gdb_byte *buf) 597 { 598 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 599 struct m32c_reg *reg; 600 601 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); 602 gdb_assert (arch == cache->arch ()); 603 gdb_assert (arch == tdep->regs[cookednum].arch); 604 reg = &tdep->regs[cookednum]; 605 606 return reg->read (reg, cache, buf); 607 } 608 609 610 static void 611 m32c_pseudo_register_write (struct gdbarch *arch, 612 struct regcache *cache, 613 int cookednum, 614 const gdb_byte *buf) 615 { 616 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 617 struct m32c_reg *reg; 618 619 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); 620 gdb_assert (arch == cache->arch ()); 621 gdb_assert (arch == tdep->regs[cookednum].arch); 622 reg = &tdep->regs[cookednum]; 623 624 reg->write (reg, cache, buf); 625 } 626 627 628 /* Add a register with the given fields to the end of ARCH's table. 629 Return a pointer to the newly added register. */ 630 static struct m32c_reg * 631 add_reg (struct gdbarch *arch, 632 const char *name, 633 struct type *type, 634 int sim_num, 635 m32c_read_reg_t *read, 636 m32c_write_reg_t *write, 637 struct m32c_reg *rx, 638 struct m32c_reg *ry, 639 int n) 640 { 641 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 642 struct m32c_reg *r = &tdep->regs[tdep->num_regs]; 643 644 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); 645 646 r->name = name; 647 r->type = type; 648 r->arch = arch; 649 r->num = tdep->num_regs; 650 r->sim_num = sim_num; 651 r->dwarf_num = -1; 652 r->general_p = 0; 653 r->dma_p = 0; 654 r->system_p = 0; 655 r->save_restore_p = 0; 656 r->read = read; 657 r->write = write; 658 r->rx = rx; 659 r->ry = ry; 660 r->n = n; 661 662 tdep->num_regs++; 663 664 return r; 665 } 666 667 668 /* Record NUM as REG's DWARF register number. */ 669 static void 670 set_dwarf_regnum (struct m32c_reg *reg, int num) 671 { 672 gdb_assert (num < M32C_MAX_NUM_REGS); 673 674 /* Update the reg->DWARF mapping. Only count the first number 675 assigned to this register. */ 676 if (reg->dwarf_num == -1) 677 reg->dwarf_num = num; 678 679 /* Update the DWARF->reg mapping. */ 680 gdbarch *arch = reg->arch; 681 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 682 tdep->dwarf_regs[num] = reg; 683 } 684 685 686 /* Mark REG as a general-purpose register, and return it. */ 687 static struct m32c_reg * 688 mark_general (struct m32c_reg *reg) 689 { 690 reg->general_p = 1; 691 return reg; 692 } 693 694 695 /* Mark REG as a DMA register. */ 696 static void 697 mark_dma (struct m32c_reg *reg) 698 { 699 reg->dma_p = 1; 700 } 701 702 703 /* Mark REG as a SYSTEM register, and return it. */ 704 static struct m32c_reg * 705 mark_system (struct m32c_reg *reg) 706 { 707 reg->system_p = 1; 708 return reg; 709 } 710 711 712 /* Mark REG as a save-restore register, and return it. */ 713 static struct m32c_reg * 714 mark_save_restore (struct m32c_reg *reg) 715 { 716 reg->save_restore_p = 1; 717 return reg; 718 } 719 720 721 #define FLAGBIT_B 0x0010 722 #define FLAGBIT_U 0x0080 723 724 /* Handy macros for declaring registers. These all evaluate to 725 pointers to the register declared. Macros that define two 726 registers evaluate to a pointer to the first. */ 727 728 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ 729 #define R(name, type, sim_num) \ 730 (add_reg (arch, (name), (type), (sim_num), \ 731 m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) 732 733 /* The simulator register number for a raw register named NAME. */ 734 #define SIM(name) (m32c_sim_reg_ ## name) 735 736 /* A raw unsigned 16-bit data register named NAME. 737 NAME should be an identifier, not a string. */ 738 #define R16U(name) \ 739 (R(#name, tdep->uint16, SIM (name))) 740 741 /* A raw data address register named NAME. 742 NAME should be an identifier, not a string. */ 743 #define RA(name) \ 744 (R(#name, tdep->data_addr_reg_type, SIM (name))) 745 746 /* A raw code address register named NAME. NAME should 747 be an identifier, not a string. */ 748 #define RC(name) \ 749 (R(#name, tdep->code_addr_reg_type, SIM (name))) 750 751 /* A pair of raw registers named NAME0 and NAME1, with type TYPE. 752 NAME should be an identifier, not a string. */ 753 #define RP(name, type) \ 754 (R(#name "0", (type), SIM (name ## 0)), \ 755 R(#name "1", (type), SIM (name ## 1)) - 1) 756 757 /* A raw banked general-purpose data register named NAME. 758 NAME should be an identifier, not a string. */ 759 #define RBD(name) \ 760 (R("", tdep->int16, SIM (name ## _bank0)), \ 761 R("", tdep->int16, SIM (name ## _bank1)) - 1) 762 763 /* A raw banked data address register named NAME. 764 NAME should be an identifier, not a string. */ 765 #define RBA(name) \ 766 (R("", tdep->data_addr_reg_type, SIM (name ## _bank0)), \ 767 R("", tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) 768 769 /* A cooked register named NAME referring to a raw banked register 770 from the bank selected by the current value of FLG. RAW_PAIR 771 should be a pointer to the first register in the banked pair. 772 NAME must be an identifier, not a string. */ 773 #define CB(name, raw_pair) \ 774 (add_reg (arch, #name, (raw_pair)->type, 0, \ 775 m32c_banked_read, m32c_banked_write, \ 776 (raw_pair), (raw_pair + 1), FLAGBIT_B)) 777 778 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that 779 access the top and bottom halves of the register pointed to by 780 NAME. NAME should be an identifier. */ 781 #define CHL(name, type) \ 782 (add_reg (arch, #name "h", (type), 0, \ 783 m32c_part_read, m32c_part_write, name, NULL, 1), \ 784 add_reg (arch, #name "l", (type), 0, \ 785 m32c_part_read, m32c_part_write, name, NULL, 0) - 1) 786 787 /* A register constructed by concatenating the two registers HIGH and 788 LOW, whose name is HIGHLOW and whose type is TYPE. */ 789 #define CCAT(high, low, type) \ 790 (add_reg (arch, #high #low, (type), 0, \ 791 m32c_cat_read, m32c_cat_write, (high), (low), 0)) 792 793 /* Abbreviations for marking register group membership. */ 794 #define G(reg) (mark_general (reg)) 795 #define S(reg) (mark_system (reg)) 796 #define DMA(reg) (mark_dma (reg)) 797 798 799 /* Construct the register set for ARCH. */ 800 static void 801 make_regs (struct gdbarch *arch) 802 { 803 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 804 int mach = gdbarch_bfd_arch_info (arch)->mach; 805 int num_raw_regs; 806 int num_cooked_regs; 807 808 struct m32c_reg *r0; 809 struct m32c_reg *r1; 810 struct m32c_reg *r2; 811 struct m32c_reg *r3; 812 struct m32c_reg *a0; 813 struct m32c_reg *a1; 814 struct m32c_reg *fb; 815 struct m32c_reg *sb; 816 struct m32c_reg *sp; 817 struct m32c_reg *r0hl; 818 struct m32c_reg *r1hl; 819 struct m32c_reg *r2r0; 820 struct m32c_reg *r3r1; 821 struct m32c_reg *r3r1r2r0; 822 struct m32c_reg *r3r2r1r0; 823 struct m32c_reg *a1a0; 824 825 struct m32c_reg *raw_r0_pair = RBD (r0); 826 struct m32c_reg *raw_r1_pair = RBD (r1); 827 struct m32c_reg *raw_r2_pair = RBD (r2); 828 struct m32c_reg *raw_r3_pair = RBD (r3); 829 struct m32c_reg *raw_a0_pair = RBA (a0); 830 struct m32c_reg *raw_a1_pair = RBA (a1); 831 struct m32c_reg *raw_fb_pair = RBA (fb); 832 833 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. 834 We always declare both raw registers, and deal with the distinction 835 in the pseudoregister. */ 836 struct m32c_reg *raw_sb_pair = RBA (sb); 837 838 struct m32c_reg *usp = S (RA (usp)); 839 struct m32c_reg *isp = S (RA (isp)); 840 struct m32c_reg *intb = S (RC (intb)); 841 struct m32c_reg *pc = G (RC (pc)); 842 struct m32c_reg *flg = G (R16U (flg)); 843 844 if (mach == bfd_mach_m32c) 845 { 846 S (R16U (svf)); 847 S (RC (svp)); 848 S (RC (vct)); 849 850 DMA (RP (dmd, tdep->uint8)); 851 DMA (RP (dct, tdep->uint16)); 852 DMA (RP (drc, tdep->uint16)); 853 DMA (RP (dma, tdep->data_addr_reg_type)); 854 DMA (RP (dsa, tdep->data_addr_reg_type)); 855 DMA (RP (dra, tdep->data_addr_reg_type)); 856 } 857 858 num_raw_regs = tdep->num_regs; 859 860 r0 = G (CB (r0, raw_r0_pair)); 861 r1 = G (CB (r1, raw_r1_pair)); 862 r2 = G (CB (r2, raw_r2_pair)); 863 r3 = G (CB (r3, raw_r3_pair)); 864 a0 = G (CB (a0, raw_a0_pair)); 865 a1 = G (CB (a1, raw_a1_pair)); 866 fb = G (CB (fb, raw_fb_pair)); 867 868 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. 869 Specify custom read/write functions that do the right thing. */ 870 sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, 871 m32c_sb_read, m32c_sb_write, 872 raw_sb_pair, raw_sb_pair + 1, 0)); 873 874 /* The current sp is either usp or isp, depending on the value of 875 the FLG register's U bit. */ 876 sp = G (add_reg (arch, "sp", usp->type, 0, 877 m32c_banked_read, m32c_banked_write, 878 isp, usp, FLAGBIT_U)); 879 880 r0hl = CHL (r0, tdep->int8); 881 r1hl = CHL (r1, tdep->int8); 882 CHL (r2, tdep->int8); 883 CHL (r3, tdep->int8); 884 CHL (intb, tdep->int16); 885 886 r2r0 = CCAT (r2, r0, tdep->int32); 887 r3r1 = CCAT (r3, r1, tdep->int32); 888 r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); 889 890 r3r2r1r0 891 = add_reg (arch, "r3r2r1r0", tdep->int64, 0, 892 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); 893 894 if (mach == bfd_mach_m16c) 895 a1a0 = CCAT (a1, a0, tdep->int32); 896 else 897 a1a0 = NULL; 898 899 num_cooked_regs = tdep->num_regs - num_raw_regs; 900 901 tdep->pc = pc; 902 tdep->flg = flg; 903 tdep->r0 = r0; 904 tdep->r1 = r1; 905 tdep->r2 = r2; 906 tdep->r3 = r3; 907 tdep->r2r0 = r2r0; 908 tdep->r3r2r1r0 = r3r2r1r0; 909 tdep->r3r1r2r0 = r3r1r2r0; 910 tdep->a0 = a0; 911 tdep->a1 = a1; 912 tdep->sb = sb; 913 tdep->fb = fb; 914 tdep->sp = sp; 915 916 /* Set up the DWARF register table. */ 917 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); 918 set_dwarf_regnum (r0hl + 1, 0x01); 919 set_dwarf_regnum (r0hl + 0, 0x02); 920 set_dwarf_regnum (r1hl + 1, 0x03); 921 set_dwarf_regnum (r1hl + 0, 0x04); 922 set_dwarf_regnum (r0, 0x05); 923 set_dwarf_regnum (r1, 0x06); 924 set_dwarf_regnum (r2, 0x07); 925 set_dwarf_regnum (r3, 0x08); 926 set_dwarf_regnum (a0, 0x09); 927 set_dwarf_regnum (a1, 0x0a); 928 set_dwarf_regnum (fb, 0x0b); 929 set_dwarf_regnum (sp, 0x0c); 930 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ 931 set_dwarf_regnum (sb, 0x13); 932 set_dwarf_regnum (r2r0, 0x15); 933 set_dwarf_regnum (r3r1, 0x16); 934 if (a1a0) 935 set_dwarf_regnum (a1a0, 0x17); 936 937 /* Enumerate the save/restore register group. 938 939 The regcache_save and regcache_restore functions apply their read 940 function to each register in this group. 941 942 Since frame_pop supplies frame_unwind_register as its read 943 function, the registers meaningful to the Dwarf unwinder need to 944 be in this group. 945 946 On the other hand, when we make inferior calls, save_inferior_status 947 and restore_inferior_status use them to preserve the current register 948 values across the inferior call. For this, you'd kind of like to 949 preserve all the raw registers, to protect the interrupted code from 950 any sort of bank switching the callee might have done. But we handle 951 those cases so badly anyway --- for example, it matters whether we 952 restore FLG before or after we restore the general-purpose registers, 953 but there's no way to express that --- that it isn't worth worrying 954 about. 955 956 We omit control registers like inthl: if you call a function that 957 changes those, it's probably because you wanted that change to be 958 visible to the interrupted code. */ 959 mark_save_restore (r0); 960 mark_save_restore (r1); 961 mark_save_restore (r2); 962 mark_save_restore (r3); 963 mark_save_restore (a0); 964 mark_save_restore (a1); 965 mark_save_restore (sb); 966 mark_save_restore (fb); 967 mark_save_restore (sp); 968 mark_save_restore (pc); 969 mark_save_restore (flg); 970 971 set_gdbarch_num_regs (arch, num_raw_regs); 972 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); 973 set_gdbarch_pc_regnum (arch, pc->num); 974 set_gdbarch_sp_regnum (arch, sp->num); 975 set_gdbarch_register_name (arch, m32c_register_name); 976 set_gdbarch_register_type (arch, m32c_register_type); 977 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); 978 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); 979 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); 980 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); 981 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); 982 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); 983 984 reggroup_add (arch, m32c_dma_reggroup); 985 } 986 987 988 989 /* Breakpoints. */ 990 constexpr gdb_byte m32c_break_insn[] = { 0x00 }; /* brk */ 991 992 typedef BP_MANIPULATION (m32c_break_insn) m32c_breakpoint; 993 994 995 /* Prologue analysis. */ 996 997 enum m32c_prologue_kind 998 { 999 /* This function uses a frame pointer. */ 1000 prologue_with_frame_ptr, 1001 1002 /* This function has no frame pointer. */ 1003 prologue_sans_frame_ptr, 1004 1005 /* This function sets up the stack, so its frame is the first 1006 frame on the stack. */ 1007 prologue_first_frame 1008 }; 1009 1010 struct m32c_prologue 1011 { 1012 /* For consistency with the DWARF 2 .debug_frame info generated by 1013 GCC, a frame's CFA is the address immediately after the saved 1014 return address. */ 1015 1016 /* The architecture for which we generated this prologue info. */ 1017 struct gdbarch *arch; 1018 1019 enum m32c_prologue_kind kind; 1020 1021 /* If KIND is prologue_with_frame_ptr, this is the offset from the 1022 CFA to where the frame pointer points. This is always zero or 1023 negative. */ 1024 LONGEST frame_ptr_offset; 1025 1026 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to 1027 the stack pointer --- always zero or negative. 1028 1029 Calling this a "size" is a bit misleading, but given that the 1030 stack grows downwards, using offsets for everything keeps one 1031 from going completely sign-crazy: you never change anything's 1032 sign for an ADD instruction; always change the second operand's 1033 sign for a SUB instruction; and everything takes care of 1034 itself. 1035 1036 Functions that use alloca don't have a constant frame size. But 1037 they always have frame pointers, so we must use that to find the 1038 CFA (and perhaps to unwind the stack pointer). */ 1039 LONGEST frame_size; 1040 1041 /* The address of the first instruction at which the frame has been 1042 set up and the arguments are where the debug info says they are 1043 --- as best as we can tell. */ 1044 CORE_ADDR prologue_end; 1045 1046 /* reg_offset[R] is the offset from the CFA at which register R is 1047 saved, or 1 if register R has not been saved. (Real values are 1048 always zero or negative.) */ 1049 LONGEST reg_offset[M32C_MAX_NUM_REGS]; 1050 }; 1051 1052 1053 /* The longest I've seen, anyway. */ 1054 #define M32C_MAX_INSN_LEN (9) 1055 1056 /* Processor state, for the prologue analyzer. */ 1057 struct m32c_pv_state 1058 { 1059 struct gdbarch *arch; 1060 pv_t r0, r1, r2, r3; 1061 pv_t a0, a1; 1062 pv_t sb, fb, sp; 1063 pv_t pc; 1064 struct pv_area *stack; 1065 1066 /* Bytes from the current PC, the address they were read from, 1067 and the address of the next unconsumed byte. */ 1068 gdb_byte insn[M32C_MAX_INSN_LEN]; 1069 CORE_ADDR scan_pc, next_addr; 1070 }; 1071 1072 1073 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if 1074 all went well, or non-zero if simulating the action would trash our 1075 state. */ 1076 static int 1077 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) 1078 { 1079 if (state->stack->store_would_trash (state->sp)) 1080 return 1; 1081 1082 state->sp = pv_add_constant (state->sp, -size); 1083 state->stack->store (state->sp, size, value); 1084 1085 return 0; 1086 } 1087 1088 1089 enum srcdest_kind 1090 { 1091 srcdest_reg, 1092 srcdest_partial_reg, 1093 srcdest_mem 1094 }; 1095 1096 /* A source or destination location for an m16c or m32c 1097 instruction. */ 1098 struct srcdest 1099 { 1100 /* If srcdest_reg, the location is a register pointed to by REG. 1101 If srcdest_partial_reg, the location is part of a register pointed 1102 to by REG. We don't try to handle this too well. 1103 If srcdest_mem, the location is memory whose address is ADDR. */ 1104 enum srcdest_kind kind; 1105 pv_t *reg, addr; 1106 }; 1107 1108 1109 /* Return the SIZE-byte value at LOC in STATE. */ 1110 static pv_t 1111 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) 1112 { 1113 if (loc.kind == srcdest_mem) 1114 return state->stack->fetch (loc.addr, size); 1115 else if (loc.kind == srcdest_partial_reg) 1116 return pv_unknown (); 1117 else 1118 return *loc.reg; 1119 } 1120 1121 1122 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if 1123 all went well, or non-zero if simulating the store would trash our 1124 state. */ 1125 static int 1126 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, 1127 pv_t value, int size) 1128 { 1129 if (loc.kind == srcdest_mem) 1130 { 1131 if (state->stack->store_would_trash (loc.addr)) 1132 return 1; 1133 state->stack->store (loc.addr, size, value); 1134 } 1135 else if (loc.kind == srcdest_partial_reg) 1136 *loc.reg = pv_unknown (); 1137 else 1138 *loc.reg = value; 1139 1140 return 0; 1141 } 1142 1143 1144 static int 1145 m32c_sign_ext (int v, int bits) 1146 { 1147 int mask = 1 << (bits - 1); 1148 return (v ^ mask) - mask; 1149 } 1150 1151 static unsigned int 1152 m32c_next_byte (struct m32c_pv_state *st) 1153 { 1154 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); 1155 return st->insn[st->next_addr++ - st->scan_pc]; 1156 } 1157 1158 static int 1159 m32c_udisp8 (struct m32c_pv_state *st) 1160 { 1161 return m32c_next_byte (st); 1162 } 1163 1164 1165 static int 1166 m32c_sdisp8 (struct m32c_pv_state *st) 1167 { 1168 return m32c_sign_ext (m32c_next_byte (st), 8); 1169 } 1170 1171 1172 static int 1173 m32c_udisp16 (struct m32c_pv_state *st) 1174 { 1175 int low = m32c_next_byte (st); 1176 int high = m32c_next_byte (st); 1177 1178 return low + (high << 8); 1179 } 1180 1181 1182 static int 1183 m32c_sdisp16 (struct m32c_pv_state *st) 1184 { 1185 int low = m32c_next_byte (st); 1186 int high = m32c_next_byte (st); 1187 1188 return m32c_sign_ext (low + (high << 8), 16); 1189 } 1190 1191 1192 static int 1193 m32c_udisp24 (struct m32c_pv_state *st) 1194 { 1195 int low = m32c_next_byte (st); 1196 int mid = m32c_next_byte (st); 1197 int high = m32c_next_byte (st); 1198 1199 return low + (mid << 8) + (high << 16); 1200 } 1201 1202 1203 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ 1204 static int 1205 m32c_get_src23 (unsigned char *i) 1206 { 1207 return (((i[0] & 0x70) >> 2) 1208 | ((i[1] & 0x30) >> 4)); 1209 } 1210 1211 1212 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ 1213 static int 1214 m32c_get_dest23 (unsigned char *i) 1215 { 1216 return (((i[0] & 0x0e) << 1) 1217 | ((i[1] & 0xc0) >> 6)); 1218 } 1219 1220 1221 static struct srcdest 1222 m32c_decode_srcdest4 (struct m32c_pv_state *st, 1223 int code, int size) 1224 { 1225 struct srcdest sd; 1226 1227 if (code < 6) 1228 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); 1229 else 1230 sd.kind = srcdest_mem; 1231 1232 sd.addr = pv_unknown (); 1233 sd.reg = 0; 1234 1235 switch (code) 1236 { 1237 case 0x0: sd.reg = &st->r0; break; 1238 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; 1239 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; 1240 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; 1241 1242 case 0x4: sd.reg = &st->a0; break; 1243 case 0x5: sd.reg = &st->a1; break; 1244 1245 case 0x6: sd.addr = st->a0; break; 1246 case 0x7: sd.addr = st->a1; break; 1247 1248 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; 1249 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; 1250 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; 1251 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; 1252 1253 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; 1254 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; 1255 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; 1256 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; 1257 1258 default: 1259 gdb_assert_not_reached ("unexpected srcdest4"); 1260 } 1261 1262 return sd; 1263 } 1264 1265 1266 static struct srcdest 1267 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) 1268 { 1269 struct srcdest sd; 1270 1271 sd.addr = pv_unknown (); 1272 sd.reg = 0; 1273 1274 switch (code) 1275 { 1276 case 0x12: 1277 case 0x13: 1278 case 0x10: 1279 case 0x11: 1280 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; 1281 break; 1282 1283 case 0x02: 1284 case 0x03: 1285 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; 1286 break; 1287 1288 default: 1289 sd.kind = srcdest_mem; 1290 break; 1291 1292 } 1293 1294 switch (code) 1295 { 1296 case 0x12: sd.reg = &st->r0; break; 1297 case 0x13: sd.reg = &st->r1; break; 1298 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; 1299 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; 1300 case 0x02: sd.reg = &st->a0; break; 1301 case 0x03: sd.reg = &st->a1; break; 1302 1303 case 0x00: sd.addr = st->a0; break; 1304 case 0x01: sd.addr = st->a1; break; 1305 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; 1306 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; 1307 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; 1308 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; 1309 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; 1310 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; 1311 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; 1312 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; 1313 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; 1314 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; 1315 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; 1316 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; 1317 default: 1318 gdb_assert_not_reached ("unexpected sd23"); 1319 } 1320 1321 if (ind) 1322 { 1323 sd.addr = m32c_srcdest_fetch (st, sd, 4); 1324 sd.kind = srcdest_mem; 1325 } 1326 1327 return sd; 1328 } 1329 1330 1331 /* The r16c and r32c machines have instructions with similar 1332 semantics, but completely different machine language encodings. So 1333 we break out the semantics into their own functions, and leave 1334 machine-specific decoding in m32c_analyze_prologue. 1335 1336 The following functions all expect their arguments already decoded, 1337 and they all return zero if analysis should continue past this 1338 instruction, or non-zero if analysis should stop. */ 1339 1340 1341 /* Simulate an 'enter SIZE' instruction in STATE. */ 1342 static int 1343 m32c_pv_enter (struct m32c_pv_state *state, int size) 1344 { 1345 /* If simulating this store would require us to forget 1346 everything we know about the stack frame in the name of 1347 accuracy, it would be better to just quit now. */ 1348 if (state->stack->store_would_trash (state->sp)) 1349 return 1; 1350 1351 gdbarch *arch = state->arch; 1352 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1353 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) 1354 return 1; 1355 1356 state->fb = state->sp; 1357 state->sp = pv_add_constant (state->sp, -size); 1358 1359 return 0; 1360 } 1361 1362 1363 static int 1364 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, 1365 int bit, int src, int size) 1366 { 1367 if (bit & src) 1368 { 1369 if (m32c_pv_push (state, reg, size)) 1370 return 1; 1371 } 1372 1373 return 0; 1374 } 1375 1376 1377 /* Simulate a 'pushm SRC' instruction in STATE. */ 1378 static int 1379 m32c_pv_pushm (struct m32c_pv_state *state, int src) 1380 { 1381 gdbarch *arch = state->arch; 1382 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1383 1384 /* The bits in SRC indicating which registers to save are: 1385 r0 r1 r2 r3 a0 a1 sb fb */ 1386 return 1387 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) 1388 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) 1389 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) 1390 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) 1391 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) 1392 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) 1393 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) 1394 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); 1395 } 1396 1397 /* Return non-zero if VALUE is the first incoming argument register. */ 1398 1399 static int 1400 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) 1401 { 1402 gdbarch *arch = state->arch; 1403 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1404 1405 return (value.kind == pvk_register 1406 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c 1407 ? (value.reg == tdep->r1->num) 1408 : (value.reg == tdep->r0->num)) 1409 && value.k == 0); 1410 } 1411 1412 /* Return non-zero if VALUE is an incoming argument register. */ 1413 1414 static int 1415 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) 1416 { 1417 gdbarch *arch = state->arch; 1418 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1419 1420 return (value.kind == pvk_register 1421 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c 1422 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) 1423 : (value.reg == tdep->r0->num)) 1424 && value.k == 0); 1425 } 1426 1427 /* Return non-zero if a store of VALUE to LOC is probably spilling an 1428 argument register to its stack slot in STATE. Such instructions 1429 should be included in the prologue, if possible. 1430 1431 The store is a spill if: 1432 - the value being stored is the original value of an argument register; 1433 - the value has not already been stored somewhere in STACK; and 1434 - LOC is a stack slot (e.g., a memory location whose address is 1435 relative to the original value of the SP). */ 1436 1437 static int 1438 m32c_is_arg_spill (struct m32c_pv_state *st, 1439 struct srcdest loc, 1440 pv_t value) 1441 { 1442 gdbarch *arch = st->arch; 1443 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1444 1445 return (m32c_is_arg_reg (st, value) 1446 && loc.kind == srcdest_mem 1447 && pv_is_register (loc.addr, tdep->sp->num) 1448 && ! st->stack->find_reg (st->arch, value.reg, 0)); 1449 } 1450 1451 /* Return non-zero if a store of VALUE to LOC is probably 1452 copying the struct return address into an address register 1453 for immediate use. This is basically a "spill" into the 1454 address register, instead of onto the stack. 1455 1456 The prerequisites are: 1457 - value being stored is original value of the FIRST arg register; 1458 - value has not already been stored on stack; and 1459 - LOC is an address register (a0 or a1). */ 1460 1461 static int 1462 m32c_is_struct_return (struct m32c_pv_state *st, 1463 struct srcdest loc, 1464 pv_t value) 1465 { 1466 gdbarch *arch = st->arch; 1467 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1468 1469 return (m32c_is_1st_arg_reg (st, value) 1470 && !st->stack->find_reg (st->arch, value.reg, 0) 1471 && loc.kind == srcdest_reg 1472 && (pv_is_register (*loc.reg, tdep->a0->num) 1473 || pv_is_register (*loc.reg, tdep->a1->num))); 1474 } 1475 1476 /* Return non-zero if a 'pushm' saving the registers indicated by SRC 1477 was a register save: 1478 - all the named registers should have their original values, and 1479 - the stack pointer should be at a constant offset from the 1480 original stack pointer. */ 1481 static int 1482 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) 1483 { 1484 gdbarch *arch = st->arch; 1485 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1486 1487 /* The bits in SRC indicating which registers to save are: 1488 r0 r1 r2 r3 a0 a1 sb fb */ 1489 return 1490 (pv_is_register (st->sp, tdep->sp->num) 1491 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) 1492 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) 1493 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) 1494 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) 1495 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) 1496 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) 1497 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) 1498 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); 1499 } 1500 1501 1502 /* Function for finding saved registers in a 'struct pv_area'; we pass 1503 this to pv_area::scan. 1504 1505 If VALUE is a saved register, ADDR says it was saved at a constant 1506 offset from the frame base, and SIZE indicates that the whole 1507 register was saved, record its offset in RESULT_UNTYPED. */ 1508 static void 1509 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) 1510 { 1511 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; 1512 struct gdbarch *arch = prologue->arch; 1513 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1514 1515 /* Is this the unchanged value of some register being saved on the 1516 stack? */ 1517 if (value.kind == pvk_register 1518 && value.k == 0 1519 && pv_is_register (addr, tdep->sp->num)) 1520 { 1521 /* Some registers require special handling: they're saved as a 1522 larger value than the register itself. */ 1523 CORE_ADDR saved_size = register_size (arch, value.reg); 1524 1525 if (value.reg == tdep->pc->num) 1526 saved_size = tdep->ret_addr_bytes; 1527 else if (register_type (arch, value.reg) 1528 == tdep->data_addr_reg_type) 1529 saved_size = tdep->push_addr_bytes; 1530 1531 if (size == saved_size) 1532 { 1533 /* Find which end of the saved value corresponds to our 1534 register. */ 1535 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) 1536 prologue->reg_offset[value.reg] 1537 = (addr.k + saved_size - register_size (arch, value.reg)); 1538 else 1539 prologue->reg_offset[value.reg] = addr.k; 1540 } 1541 } 1542 } 1543 1544 1545 /* Analyze the function prologue for ARCH at START, going no further 1546 than LIMIT, and place a description of what we found in 1547 PROLOGUE. */ 1548 static void 1549 m32c_analyze_prologue (struct gdbarch *arch, 1550 CORE_ADDR start, CORE_ADDR limit, 1551 struct m32c_prologue *prologue) 1552 { 1553 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1554 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; 1555 CORE_ADDR after_last_frame_related_insn; 1556 struct m32c_pv_state st; 1557 1558 st.arch = arch; 1559 st.r0 = pv_register (tdep->r0->num, 0); 1560 st.r1 = pv_register (tdep->r1->num, 0); 1561 st.r2 = pv_register (tdep->r2->num, 0); 1562 st.r3 = pv_register (tdep->r3->num, 0); 1563 st.a0 = pv_register (tdep->a0->num, 0); 1564 st.a1 = pv_register (tdep->a1->num, 0); 1565 st.sb = pv_register (tdep->sb->num, 0); 1566 st.fb = pv_register (tdep->fb->num, 0); 1567 st.sp = pv_register (tdep->sp->num, 0); 1568 st.pc = pv_register (tdep->pc->num, 0); 1569 pv_area stack (tdep->sp->num, gdbarch_addr_bit (arch)); 1570 st.stack = &stack; 1571 1572 /* Record that the call instruction has saved the return address on 1573 the stack. */ 1574 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); 1575 1576 memset (prologue, 0, sizeof (*prologue)); 1577 prologue->arch = arch; 1578 { 1579 int i; 1580 for (i = 0; i < M32C_MAX_NUM_REGS; i++) 1581 prologue->reg_offset[i] = 1; 1582 } 1583 1584 st.scan_pc = after_last_frame_related_insn = start; 1585 1586 while (st.scan_pc < limit) 1587 { 1588 pv_t pre_insn_fb = st.fb; 1589 pv_t pre_insn_sp = st.sp; 1590 1591 /* In theory we could get in trouble by trying to read ahead 1592 here, when we only know we're expecting one byte. In 1593 practice I doubt anyone will care, and it makes the rest of 1594 the code easier. */ 1595 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) 1596 /* If we can't fetch the instruction from memory, stop here 1597 and hope for the best. */ 1598 break; 1599 st.next_addr = st.scan_pc; 1600 1601 /* The assembly instructions are written as they appear in the 1602 section of the processor manuals that describe the 1603 instruction encodings. 1604 1605 When a single assembly language instruction has several 1606 different machine-language encodings, the manual 1607 distinguishes them by a number in parens, before the 1608 mnemonic. Those numbers are included, as well. 1609 1610 The srcdest decoding instructions have the same names as the 1611 analogous functions in the simulator. */ 1612 if (mach == bfd_mach_m16c) 1613 { 1614 /* (1) ENTER #imm8 */ 1615 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) 1616 { 1617 if (m32c_pv_enter (&st, st.insn[2])) 1618 break; 1619 st.next_addr += 3; 1620 } 1621 /* (1) PUSHM src */ 1622 else if (st.insn[0] == 0xec) 1623 { 1624 int src = st.insn[1]; 1625 if (m32c_pv_pushm (&st, src)) 1626 break; 1627 st.next_addr += 2; 1628 1629 if (m32c_pushm_is_reg_save (&st, src)) 1630 after_last_frame_related_insn = st.next_addr; 1631 } 1632 1633 /* (6) MOV.size:G src, dest */ 1634 else if ((st.insn[0] & 0xfe) == 0x72) 1635 { 1636 int size = (st.insn[0] & 0x01) ? 2 : 1; 1637 struct srcdest src; 1638 struct srcdest dest; 1639 pv_t src_value; 1640 st.next_addr += 2; 1641 1642 src 1643 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); 1644 dest 1645 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); 1646 src_value = m32c_srcdest_fetch (&st, src, size); 1647 1648 if (m32c_is_arg_spill (&st, dest, src_value)) 1649 after_last_frame_related_insn = st.next_addr; 1650 else if (m32c_is_struct_return (&st, dest, src_value)) 1651 after_last_frame_related_insn = st.next_addr; 1652 1653 if (m32c_srcdest_store (&st, dest, src_value, size)) 1654 break; 1655 } 1656 1657 /* (1) LDC #IMM16, sp */ 1658 else if (st.insn[0] == 0xeb 1659 && st.insn[1] == 0x50) 1660 { 1661 st.next_addr += 2; 1662 st.sp = pv_constant (m32c_udisp16 (&st)); 1663 } 1664 1665 else 1666 /* We've hit some instruction we don't know how to simulate. 1667 Strictly speaking, we should set every value we're 1668 tracking to "unknown". But we'll be optimistic, assume 1669 that we have enough information already, and stop 1670 analysis here. */ 1671 break; 1672 } 1673 else 1674 { 1675 int src_indirect = 0; 1676 int dest_indirect = 0; 1677 int i = 0; 1678 1679 gdb_assert (mach == bfd_mach_m32c); 1680 1681 /* Check for prefix bytes indicating indirect addressing. */ 1682 if (st.insn[0] == 0x41) 1683 { 1684 src_indirect = 1; 1685 i++; 1686 } 1687 else if (st.insn[0] == 0x09) 1688 { 1689 dest_indirect = 1; 1690 i++; 1691 } 1692 else if (st.insn[0] == 0x49) 1693 { 1694 src_indirect = dest_indirect = 1; 1695 i++; 1696 } 1697 1698 /* (1) ENTER #imm8 */ 1699 if (st.insn[i] == 0xec) 1700 { 1701 if (m32c_pv_enter (&st, st.insn[i + 1])) 1702 break; 1703 st.next_addr += 2; 1704 } 1705 1706 /* (1) PUSHM src */ 1707 else if (st.insn[i] == 0x8f) 1708 { 1709 int src = st.insn[i + 1]; 1710 if (m32c_pv_pushm (&st, src)) 1711 break; 1712 st.next_addr += 2; 1713 1714 if (m32c_pushm_is_reg_save (&st, src)) 1715 after_last_frame_related_insn = st.next_addr; 1716 } 1717 1718 /* (7) MOV.size:G src, dest */ 1719 else if ((st.insn[i] & 0x80) == 0x80 1720 && (st.insn[i + 1] & 0x0f) == 0x0b 1721 && m32c_get_src23 (&st.insn[i]) < 20 1722 && m32c_get_dest23 (&st.insn[i]) < 20) 1723 { 1724 struct srcdest src; 1725 struct srcdest dest; 1726 pv_t src_value; 1727 int bw = st.insn[i] & 0x01; 1728 int size = bw ? 2 : 1; 1729 st.next_addr += 2; 1730 1731 src 1732 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), 1733 size, src_indirect); 1734 dest 1735 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), 1736 size, dest_indirect); 1737 src_value = m32c_srcdest_fetch (&st, src, size); 1738 1739 if (m32c_is_arg_spill (&st, dest, src_value)) 1740 after_last_frame_related_insn = st.next_addr; 1741 1742 if (m32c_srcdest_store (&st, dest, src_value, size)) 1743 break; 1744 } 1745 /* (2) LDC #IMM24, sp */ 1746 else if (st.insn[i] == 0xd5 1747 && st.insn[i + 1] == 0x29) 1748 { 1749 st.next_addr += 2; 1750 st.sp = pv_constant (m32c_udisp24 (&st)); 1751 } 1752 else 1753 /* We've hit some instruction we don't know how to simulate. 1754 Strictly speaking, we should set every value we're 1755 tracking to "unknown". But we'll be optimistic, assume 1756 that we have enough information already, and stop 1757 analysis here. */ 1758 break; 1759 } 1760 1761 /* If this instruction changed the FB or decreased the SP (i.e., 1762 allocated more stack space), then this may be a good place to 1763 declare the prologue finished. However, there are some 1764 exceptions: 1765 1766 - If the instruction just changed the FB back to its original 1767 value, then that's probably a restore instruction. The 1768 prologue should definitely end before that. 1769 1770 - If the instruction increased the value of the SP (that is, 1771 shrunk the frame), then it's probably part of a frame 1772 teardown sequence, and the prologue should end before 1773 that. */ 1774 1775 if (! pv_is_identical (st.fb, pre_insn_fb)) 1776 { 1777 if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) 1778 after_last_frame_related_insn = st.next_addr; 1779 } 1780 else if (! pv_is_identical (st.sp, pre_insn_sp)) 1781 { 1782 /* The comparison of the constants looks odd, there, because 1783 .k is unsigned. All it really means is that the SP is 1784 lower than it was before the instruction. */ 1785 if ( pv_is_register (pre_insn_sp, tdep->sp->num) 1786 && pv_is_register (st.sp, tdep->sp->num) 1787 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) 1788 after_last_frame_related_insn = st.next_addr; 1789 } 1790 1791 st.scan_pc = st.next_addr; 1792 } 1793 1794 /* Did we load a constant value into the stack pointer? */ 1795 if (pv_is_constant (st.sp)) 1796 prologue->kind = prologue_first_frame; 1797 1798 /* Alternatively, did we initialize the frame pointer? Remember 1799 that the CFA is the address after the return address. */ 1800 if (pv_is_register (st.fb, tdep->sp->num)) 1801 { 1802 prologue->kind = prologue_with_frame_ptr; 1803 prologue->frame_ptr_offset = st.fb.k; 1804 } 1805 1806 /* Is the frame size a known constant? Remember that frame_size is 1807 actually the offset from the CFA to the SP (i.e., a negative 1808 value). */ 1809 else if (pv_is_register (st.sp, tdep->sp->num)) 1810 { 1811 prologue->kind = prologue_sans_frame_ptr; 1812 prologue->frame_size = st.sp.k; 1813 } 1814 1815 /* We haven't been able to make sense of this function's frame. Treat 1816 it as the first frame. */ 1817 else 1818 prologue->kind = prologue_first_frame; 1819 1820 /* Record where all the registers were saved. */ 1821 st.stack->scan (check_for_saved, (void *) prologue); 1822 1823 prologue->prologue_end = after_last_frame_related_insn; 1824 } 1825 1826 1827 static CORE_ADDR 1828 m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) 1829 { 1830 const char *name; 1831 CORE_ADDR func_addr, func_end, sal_end; 1832 struct m32c_prologue p; 1833 1834 /* Try to find the extent of the function that contains IP. */ 1835 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) 1836 return ip; 1837 1838 /* Find end by prologue analysis. */ 1839 m32c_analyze_prologue (gdbarch, ip, func_end, &p); 1840 /* Find end by line info. */ 1841 sal_end = skip_prologue_using_sal (gdbarch, ip); 1842 /* Return whichever is lower. */ 1843 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) 1844 return sal_end; 1845 else 1846 return p.prologue_end; 1847 } 1848 1849 1850 1851 /* Stack unwinding. */ 1852 1853 static struct m32c_prologue * 1854 m32c_analyze_frame_prologue (frame_info_ptr this_frame, 1855 void **this_prologue_cache) 1856 { 1857 if (! *this_prologue_cache) 1858 { 1859 CORE_ADDR func_start = get_frame_func (this_frame); 1860 CORE_ADDR stop_addr = get_frame_pc (this_frame); 1861 1862 /* If we couldn't find any function containing the PC, then 1863 just initialize the prologue cache, but don't do anything. */ 1864 if (! func_start) 1865 stop_addr = func_start; 1866 1867 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); 1868 m32c_analyze_prologue (get_frame_arch (this_frame), 1869 func_start, stop_addr, 1870 (struct m32c_prologue *) *this_prologue_cache); 1871 } 1872 1873 return (struct m32c_prologue *) *this_prologue_cache; 1874 } 1875 1876 1877 static CORE_ADDR 1878 m32c_frame_base (frame_info_ptr this_frame, 1879 void **this_prologue_cache) 1880 { 1881 struct m32c_prologue *p 1882 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); 1883 gdbarch *arch = get_frame_arch (this_frame); 1884 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1885 1886 /* In functions that use alloca, the distance between the stack 1887 pointer and the frame base varies dynamically, so we can't use 1888 the SP plus static information like prologue analysis to find the 1889 frame base. However, such functions must have a frame pointer, 1890 to be able to restore the SP on exit. So whenever we do have a 1891 frame pointer, use that to find the base. */ 1892 switch (p->kind) 1893 { 1894 case prologue_with_frame_ptr: 1895 { 1896 CORE_ADDR fb 1897 = get_frame_register_unsigned (this_frame, tdep->fb->num); 1898 return fb - p->frame_ptr_offset; 1899 } 1900 1901 case prologue_sans_frame_ptr: 1902 { 1903 CORE_ADDR sp 1904 = get_frame_register_unsigned (this_frame, tdep->sp->num); 1905 return sp - p->frame_size; 1906 } 1907 1908 case prologue_first_frame: 1909 return 0; 1910 1911 default: 1912 gdb_assert_not_reached ("unexpected prologue kind"); 1913 } 1914 } 1915 1916 1917 static void 1918 m32c_this_id (frame_info_ptr this_frame, 1919 void **this_prologue_cache, 1920 struct frame_id *this_id) 1921 { 1922 CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); 1923 1924 if (base) 1925 *this_id = frame_id_build (base, get_frame_func (this_frame)); 1926 /* Otherwise, leave it unset, and that will terminate the backtrace. */ 1927 } 1928 1929 1930 static struct value * 1931 m32c_prev_register (frame_info_ptr this_frame, 1932 void **this_prologue_cache, int regnum) 1933 { 1934 gdbarch *arch = get_frame_arch (this_frame); 1935 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (arch); 1936 struct m32c_prologue *p 1937 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); 1938 CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); 1939 1940 if (regnum == tdep->sp->num) 1941 return frame_unwind_got_constant (this_frame, regnum, frame_base); 1942 1943 /* If prologue analysis says we saved this register somewhere, 1944 return a description of the stack slot holding it. */ 1945 if (p->reg_offset[regnum] != 1) 1946 return frame_unwind_got_memory (this_frame, regnum, 1947 frame_base + p->reg_offset[regnum]); 1948 1949 /* Otherwise, presume we haven't changed the value of this 1950 register, and get it from the next frame. */ 1951 return frame_unwind_got_register (this_frame, regnum, regnum); 1952 } 1953 1954 1955 static const struct frame_unwind m32c_unwind = { 1956 "m32c prologue", 1957 NORMAL_FRAME, 1958 default_frame_unwind_stop_reason, 1959 m32c_this_id, 1960 m32c_prev_register, 1961 NULL, 1962 default_frame_sniffer 1963 }; 1964 1965 1966 /* Inferior calls. */ 1967 1968 /* The calling conventions, according to GCC: 1969 1970 r8c, m16c 1971 --------- 1972 First arg may be passed in r1l or r1 if it (1) fits (QImode or 1973 HImode), (2) is named, and (3) is an integer or pointer type (no 1974 structs, floats, etc). Otherwise, it's passed on the stack. 1975 1976 Second arg may be passed in r2, same restrictions (but not QImode), 1977 even if the first arg is passed on the stack. 1978 1979 Third and further args are passed on the stack. No padding is 1980 used, stack "alignment" is 8 bits. 1981 1982 m32cm, m32c 1983 ----------- 1984 1985 First arg may be passed in r0l or r0, same restrictions as above. 1986 1987 Second and further args are passed on the stack. Padding is used 1988 after QImode parameters (i.e. lower-addressed byte is the value, 1989 higher-addressed byte is the padding), stack "alignment" is 16 1990 bits. */ 1991 1992 1993 /* Return true if TYPE is a type that can be passed in registers. (We 1994 ignore the size, and pay attention only to the type code; 1995 acceptable sizes depends on which register is being considered to 1996 hold it.) */ 1997 static int 1998 m32c_reg_arg_type (struct type *type) 1999 { 2000 enum type_code code = type->code (); 2001 2002 return (code == TYPE_CODE_INT 2003 || code == TYPE_CODE_ENUM 2004 || code == TYPE_CODE_PTR 2005 || TYPE_IS_REFERENCE (type) 2006 || code == TYPE_CODE_BOOL 2007 || code == TYPE_CODE_CHAR); 2008 } 2009 2010 2011 static CORE_ADDR 2012 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2013 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2014 struct value **args, CORE_ADDR sp, 2015 function_call_return_method return_method, 2016 CORE_ADDR struct_addr) 2017 { 2018 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 2019 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2020 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 2021 CORE_ADDR cfa; 2022 int i; 2023 2024 /* The number of arguments given in this function's prototype, or 2025 zero if it has a non-prototyped function type. The m32c ABI 2026 passes arguments mentioned in the prototype differently from 2027 those in the ellipsis of a varargs function, or from those passed 2028 to a non-prototyped function. */ 2029 int num_prototyped_args = 0; 2030 2031 { 2032 struct type *func_type = value_type (function); 2033 2034 /* Dereference function pointer types. */ 2035 if (func_type->code () == TYPE_CODE_PTR) 2036 func_type = func_type->target_type (); 2037 2038 gdb_assert (func_type->code () == TYPE_CODE_FUNC || 2039 func_type->code () == TYPE_CODE_METHOD); 2040 2041 #if 0 2042 /* The ABI description in gcc/config/m32c/m32c.abi says that 2043 we need to handle prototyped and non-prototyped functions 2044 separately, but the code in GCC doesn't actually do so. */ 2045 if (TYPE_PROTOTYPED (func_type)) 2046 #endif 2047 num_prototyped_args = func_type->num_fields (); 2048 } 2049 2050 /* First, if the function returns an aggregate by value, push a 2051 pointer to a buffer for it. This doesn't affect the way 2052 subsequent arguments are allocated to registers. */ 2053 if (return_method == return_method_struct) 2054 { 2055 int ptr_len = tdep->ptr_voyd->length (); 2056 sp -= ptr_len; 2057 write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); 2058 } 2059 2060 /* Push the arguments. */ 2061 for (i = nargs - 1; i >= 0; i--) 2062 { 2063 struct value *arg = args[i]; 2064 const gdb_byte *arg_bits = value_contents (arg).data (); 2065 struct type *arg_type = value_type (arg); 2066 ULONGEST arg_size = arg_type->length (); 2067 2068 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ 2069 if (i == 0 2070 && arg_size <= 2 2071 && i < num_prototyped_args 2072 && m32c_reg_arg_type (arg_type)) 2073 { 2074 /* Extract and re-store as an integer as a terse way to make 2075 sure it ends up in the least significant end of r1. (GDB 2076 should avoid assuming endianness, even on uni-endian 2077 processors.) */ 2078 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, 2079 byte_order); 2080 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; 2081 regcache_cooked_write_unsigned (regcache, reg->num, u); 2082 } 2083 2084 /* Can it go in r2? */ 2085 else if (mach == bfd_mach_m16c 2086 && i == 1 2087 && arg_size == 2 2088 && i < num_prototyped_args 2089 && m32c_reg_arg_type (arg_type)) 2090 regcache->cooked_write (tdep->r2->num, arg_bits); 2091 2092 /* Everything else goes on the stack. */ 2093 else 2094 { 2095 sp -= arg_size; 2096 2097 /* Align the stack. */ 2098 if (mach == bfd_mach_m32c) 2099 sp &= ~1; 2100 2101 write_memory (sp, arg_bits, arg_size); 2102 } 2103 } 2104 2105 /* This is the CFA we use to identify the dummy frame. */ 2106 cfa = sp; 2107 2108 /* Push the return address. */ 2109 sp -= tdep->ret_addr_bytes; 2110 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, 2111 bp_addr); 2112 2113 /* Update the stack pointer. */ 2114 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); 2115 2116 /* We need to borrow an odd trick from the i386 target here. 2117 2118 The value we return from this function gets used as the stack 2119 address (the CFA) for the dummy frame's ID. The obvious thing is 2120 to return the new TOS. However, that points at the return 2121 address, saved on the stack, which is inconsistent with the CFA's 2122 described by GCC's DWARF 2 .debug_frame information: DWARF 2 2123 .debug_frame info uses the address immediately after the saved 2124 return address. So you end up with a dummy frame whose CFA 2125 points at the return address, but the frame for the function 2126 being called has a CFA pointing after the return address: the 2127 younger CFA is *greater than* the older CFA. The sanity checks 2128 in frame.c don't like that. 2129 2130 So we try to be consistent with the CFA's used by DWARF 2. 2131 Having a dummy frame and a real frame with the *same* CFA is 2132 tolerable. */ 2133 return cfa; 2134 } 2135 2136 2137 2138 /* Return values. */ 2139 2140 /* Return value conventions, according to GCC: 2141 2142 r8c, m16c 2143 --------- 2144 2145 QImode in r0l 2146 HImode in r0 2147 SImode in r2r0 2148 near pointer in r0 2149 far pointer in r2r0 2150 2151 Aggregate values (regardless of size) are returned by pushing a 2152 pointer to a temporary area on the stack after the args are pushed. 2153 The function fills in this area with the value. Note that this 2154 pointer on the stack does not affect how register arguments, if any, 2155 are configured. 2156 2157 m32cm, m32c 2158 ----------- 2159 Same. */ 2160 2161 /* Return non-zero if values of type TYPE are returned by storing them 2162 in a buffer whose address is passed on the stack, ahead of the 2163 other arguments. */ 2164 static int 2165 m32c_return_by_passed_buf (struct type *type) 2166 { 2167 enum type_code code = type->code (); 2168 2169 return (code == TYPE_CODE_STRUCT 2170 || code == TYPE_CODE_UNION); 2171 } 2172 2173 static enum return_value_convention 2174 m32c_return_value (struct gdbarch *gdbarch, 2175 struct value *function, 2176 struct type *valtype, 2177 struct regcache *regcache, 2178 gdb_byte *readbuf, 2179 const gdb_byte *writebuf) 2180 { 2181 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 2182 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2183 enum return_value_convention conv; 2184 ULONGEST valtype_len = valtype->length (); 2185 2186 if (m32c_return_by_passed_buf (valtype)) 2187 conv = RETURN_VALUE_STRUCT_CONVENTION; 2188 else 2189 conv = RETURN_VALUE_REGISTER_CONVENTION; 2190 2191 if (readbuf) 2192 { 2193 /* We should never be called to find values being returned by 2194 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, 2195 unless we made the call ourselves. */ 2196 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); 2197 2198 gdb_assert (valtype_len <= 8); 2199 2200 /* Anything that fits in r0 is returned there. */ 2201 if (valtype_len <= tdep->r0->type->length ()) 2202 { 2203 ULONGEST u; 2204 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); 2205 store_unsigned_integer (readbuf, valtype_len, byte_order, u); 2206 } 2207 else 2208 { 2209 /* Everything else is passed in mem0, using as many bytes as 2210 needed. This is not what the Renesas tools do, but it's 2211 what GCC does at the moment. */ 2212 struct bound_minimal_symbol mem0 2213 = lookup_minimal_symbol ("mem0", NULL, NULL); 2214 2215 if (! mem0.minsym) 2216 error (_("The return value is stored in memory at 'mem0', " 2217 "but GDB cannot find\n" 2218 "its address.")); 2219 read_memory (mem0.value_address (), readbuf, valtype_len); 2220 } 2221 } 2222 2223 if (writebuf) 2224 { 2225 /* We should never be called to store values to be returned 2226 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of 2227 finding the buffer, unless we made the call ourselves. */ 2228 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); 2229 2230 gdb_assert (valtype_len <= 8); 2231 2232 /* Anything that fits in r0 is returned there. */ 2233 if (valtype_len <= tdep->r0->type->length ()) 2234 { 2235 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, 2236 byte_order); 2237 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); 2238 } 2239 else 2240 { 2241 /* Everything else is passed in mem0, using as many bytes as 2242 needed. This is not what the Renesas tools do, but it's 2243 what GCC does at the moment. */ 2244 struct bound_minimal_symbol mem0 2245 = lookup_minimal_symbol ("mem0", NULL, NULL); 2246 2247 if (! mem0.minsym) 2248 error (_("The return value is stored in memory at 'mem0', " 2249 "but GDB cannot find\n" 2250 " its address.")); 2251 write_memory (mem0.value_address (), writebuf, valtype_len); 2252 } 2253 } 2254 2255 return conv; 2256 } 2257 2258 2259 2260 /* Trampolines. */ 2261 2262 /* The m16c and m32c use a trampoline function for indirect function 2263 calls. An indirect call looks like this: 2264 2265 ... push arguments ... 2266 ... push target function address ... 2267 jsr.a m32c_jsri16 2268 2269 The code for m32c_jsri16 looks like this: 2270 2271 m32c_jsri16: 2272 2273 # Save return address. 2274 pop.w m32c_jsri_ret 2275 pop.b m32c_jsri_ret+2 2276 2277 # Store target function address. 2278 pop.w m32c_jsri_addr 2279 2280 # Re-push return address. 2281 push.b m32c_jsri_ret+2 2282 push.w m32c_jsri_ret 2283 2284 # Call the target function. 2285 jmpi.a m32c_jsri_addr 2286 2287 Without further information, GDB will treat calls to m32c_jsri16 2288 like calls to any other function. Since m32c_jsri16 doesn't have 2289 debugging information, that normally means that GDB sets a step- 2290 resume breakpoint and lets the program continue --- which is not 2291 what the user wanted. (Giving the trampoline debugging info 2292 doesn't help: the user expects the program to stop in the function 2293 their program is calling, not in some trampoline code they've never 2294 seen before.) 2295 2296 The gdbarch_skip_trampoline_code method tells GDB how to step 2297 through such trampoline functions transparently to the user. When 2298 given the address of a trampoline function's first instruction, 2299 gdbarch_skip_trampoline_code should return the address of the first 2300 instruction of the function really being called. If GDB decides it 2301 wants to step into that function, it will set a breakpoint there 2302 and silently continue to it. 2303 2304 We recognize the trampoline by name, and extract the target address 2305 directly from the stack. This isn't great, but recognizing by its 2306 code sequence seems more fragile. */ 2307 2308 static CORE_ADDR 2309 m32c_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR stop_pc) 2310 { 2311 struct gdbarch *gdbarch = get_frame_arch (frame); 2312 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 2313 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2314 2315 /* It would be nicer to simply look up the addresses of known 2316 trampolines once, and then compare stop_pc with them. However, 2317 we'd need to ensure that that cached address got invalidated when 2318 someone loaded a new executable, and I'm not quite sure of the 2319 best way to do that. find_pc_partial_function does do some 2320 caching, so we'll see how this goes. */ 2321 const char *name; 2322 CORE_ADDR start, end; 2323 2324 if (find_pc_partial_function (stop_pc, &name, &start, &end)) 2325 { 2326 /* Are we stopped at the beginning of the trampoline function? */ 2327 if (strcmp (name, "m32c_jsri16") == 0 2328 && stop_pc == start) 2329 { 2330 /* Get the stack pointer. The return address is at the top, 2331 and the target function's address is just below that. We 2332 know it's a two-byte address, since the trampoline is 2333 m32c_jsri*16*. */ 2334 CORE_ADDR sp = get_frame_sp (get_current_frame ()); 2335 CORE_ADDR target 2336 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, 2337 2, byte_order); 2338 2339 /* What we have now is the address of a jump instruction. 2340 What we need is the destination of that jump. 2341 The opcode is 1 byte, and the destination is the next 3 bytes. */ 2342 2343 target = read_memory_unsigned_integer (target + 1, 3, byte_order); 2344 return target; 2345 } 2346 } 2347 2348 return 0; 2349 } 2350 2351 2352 /* Address/pointer conversions. */ 2353 2354 /* On the m16c, there is a 24-bit address space, but only a very few 2355 instructions can generate addresses larger than 0xffff: jumps, 2356 jumps to subroutines, and the lde/std (load/store extended) 2357 instructions. 2358 2359 Since GCC can only support one size of pointer, we can't have 2360 distinct 'near' and 'far' pointer types; we have to pick one size 2361 for everything. If we wanted to use 24-bit pointers, then GCC 2362 would have to use lde and ste for all memory references, which 2363 would be terrible for performance and code size. So the GNU 2364 toolchain uses 16-bit pointers for everything, and gives up the 2365 ability to have pointers point outside the first 64k of memory. 2366 2367 However, as a special hack, we let the linker place functions at 2368 addresses above 0xffff, as long as it also places a trampoline in 2369 the low 64k for every function whose address is taken. Each 2370 trampoline consists of a single jmp.a instruction that jumps to the 2371 function's real entry point. Pointers to functions can be 16 bits 2372 long, even though the functions themselves are at higher addresses: 2373 the pointers refer to the trampolines, not the functions. 2374 2375 This complicates things for GDB, however: given the address of a 2376 function (from debug info or linker symbols, say) which could be 2377 anywhere in the 24-bit address space, how can we find an 2378 appropriate 16-bit value to use as a pointer to it? 2379 2380 If the linker has not generated a trampoline for the function, 2381 we're out of luck. Well, I guess we could malloc some space and 2382 write a jmp.a instruction to it, but I'm not going to get into that 2383 at the moment. 2384 2385 If the linker has generated a trampoline for the function, then it 2386 also emitted a symbol for the trampoline: if the function's linker 2387 symbol is named NAME, then the function's trampoline's linker 2388 symbol is named NAME.plt. 2389 2390 So, given a code address: 2391 - We try to find a linker symbol at that address. 2392 - If we find such a symbol named NAME, we look for a linker symbol 2393 named NAME.plt. 2394 - If we find such a symbol, we assume it is a trampoline, and use 2395 its address as the pointer value. 2396 2397 And, given a function pointer: 2398 - We try to find a linker symbol at that address named NAME.plt. 2399 - If we find such a symbol, we look for a linker symbol named NAME. 2400 - If we find that, we provide that as the function's address. 2401 - If any of the above steps fail, we return the original address 2402 unchanged; it might really be a function in the low 64k. 2403 2404 See? You *knew* there was a reason you wanted to be a computer 2405 programmer! :) */ 2406 2407 static void 2408 m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, 2409 struct type *type, gdb_byte *buf, CORE_ADDR addr) 2410 { 2411 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2412 enum type_code target_code; 2413 gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); 2414 2415 target_code = type->target_type ()->code (); 2416 2417 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) 2418 { 2419 const char *func_name; 2420 char *tramp_name; 2421 struct bound_minimal_symbol tramp_msym; 2422 2423 /* Try to find a linker symbol at this address. */ 2424 struct bound_minimal_symbol func_msym 2425 = lookup_minimal_symbol_by_pc (addr); 2426 2427 if (! func_msym.minsym) 2428 error (_("Cannot convert code address %s to function pointer:\n" 2429 "couldn't find a symbol at that address, to find trampoline."), 2430 paddress (gdbarch, addr)); 2431 2432 func_name = func_msym.minsym->linkage_name (); 2433 tramp_name = (char *) xmalloc (strlen (func_name) + 5); 2434 strcpy (tramp_name, func_name); 2435 strcat (tramp_name, ".plt"); 2436 2437 /* Try to find a linker symbol for the trampoline. */ 2438 tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); 2439 2440 /* We've either got another copy of the name now, or don't need 2441 the name any more. */ 2442 xfree (tramp_name); 2443 2444 if (! tramp_msym.minsym) 2445 { 2446 CORE_ADDR ptrval; 2447 2448 /* No PLT entry found. Mask off the upper bits of the address 2449 to make a pointer. As noted in the warning to the user 2450 below, this value might be useful if converted back into 2451 an address by GDB, but will otherwise, almost certainly, 2452 be garbage. 2453 2454 Using this masked result does seem to be useful 2455 in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into 2456 PASSes. These results appear to be correct as well. 2457 2458 We print a warning here so that the user can make a 2459 determination about whether the result is useful or not. */ 2460 ptrval = addr & 0xffff; 2461 2462 warning (_("Cannot convert code address %s to function pointer:\n" 2463 "couldn't find trampoline named '%s.plt'.\n" 2464 "Returning pointer value %s instead; this may produce\n" 2465 "a useful result if converted back into an address by GDB,\n" 2466 "but will most likely not be useful otherwise."), 2467 paddress (gdbarch, addr), func_name, 2468 paddress (gdbarch, ptrval)); 2469 2470 addr = ptrval; 2471 2472 } 2473 else 2474 { 2475 /* The trampoline's address is our pointer. */ 2476 addr = tramp_msym.value_address (); 2477 } 2478 } 2479 2480 store_unsigned_integer (buf, type->length (), byte_order, addr); 2481 } 2482 2483 2484 static CORE_ADDR 2485 m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, 2486 struct type *type, const gdb_byte *buf) 2487 { 2488 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2489 CORE_ADDR ptr; 2490 enum type_code target_code; 2491 2492 gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); 2493 2494 ptr = extract_unsigned_integer (buf, type->length (), byte_order); 2495 2496 target_code = type->target_type ()->code (); 2497 2498 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) 2499 { 2500 /* See if there is a minimal symbol at that address whose name is 2501 "NAME.plt". */ 2502 struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr); 2503 2504 if (ptr_msym.minsym) 2505 { 2506 const char *ptr_msym_name = ptr_msym.minsym->linkage_name (); 2507 int len = strlen (ptr_msym_name); 2508 2509 if (len > 4 2510 && strcmp (ptr_msym_name + len - 4, ".plt") == 0) 2511 { 2512 struct bound_minimal_symbol func_msym; 2513 /* We have a .plt symbol; try to find the symbol for the 2514 corresponding function. 2515 2516 Since the trampoline contains a jump instruction, we 2517 could also just extract the jump's target address. I 2518 don't see much advantage one way or the other. */ 2519 char *func_name = (char *) xmalloc (len - 4 + 1); 2520 memcpy (func_name, ptr_msym_name, len - 4); 2521 func_name[len - 4] = '\0'; 2522 func_msym 2523 = lookup_minimal_symbol (func_name, NULL, NULL); 2524 2525 /* If we do have such a symbol, return its value as the 2526 function's true address. */ 2527 if (func_msym.minsym) 2528 ptr = func_msym.value_address (); 2529 } 2530 } 2531 else 2532 { 2533 int aspace; 2534 2535 for (aspace = 1; aspace <= 15; aspace++) 2536 { 2537 ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); 2538 2539 if (ptr_msym.minsym) 2540 ptr |= aspace << 16; 2541 } 2542 } 2543 } 2544 2545 return ptr; 2546 } 2547 2548 static void 2549 m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, 2550 int *frame_regnum, 2551 LONGEST *frame_offset) 2552 { 2553 const char *name; 2554 CORE_ADDR func_addr, func_end; 2555 struct m32c_prologue p; 2556 2557 struct regcache *regcache = get_current_regcache (); 2558 m32c_gdbarch_tdep *tdep = gdbarch_tdep<m32c_gdbarch_tdep> (gdbarch); 2559 2560 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) 2561 internal_error (_("No virtual frame pointer available")); 2562 2563 m32c_analyze_prologue (gdbarch, func_addr, pc, &p); 2564 switch (p.kind) 2565 { 2566 case prologue_with_frame_ptr: 2567 *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; 2568 *frame_offset = p.frame_ptr_offset; 2569 break; 2570 case prologue_sans_frame_ptr: 2571 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; 2572 *frame_offset = p.frame_size; 2573 break; 2574 default: 2575 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; 2576 *frame_offset = 0; 2577 break; 2578 } 2579 /* Sanity check */ 2580 if (*frame_regnum > gdbarch_num_regs (gdbarch)) 2581 internal_error (_("No virtual frame pointer available")); 2582 } 2583 2584 2585 /* Initialization. */ 2586 2587 static struct gdbarch * 2588 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2589 { 2590 struct gdbarch *gdbarch; 2591 unsigned long mach = info.bfd_arch_info->mach; 2592 2593 /* Find a candidate among the list of architectures we've created 2594 already. */ 2595 for (arches = gdbarch_list_lookup_by_info (arches, &info); 2596 arches != NULL; 2597 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2598 return arches->gdbarch; 2599 2600 m32c_gdbarch_tdep *tdep = new m32c_gdbarch_tdep; 2601 gdbarch = gdbarch_alloc (&info, tdep); 2602 2603 /* Essential types. */ 2604 make_types (gdbarch); 2605 2606 /* Address/pointer conversions. */ 2607 if (mach == bfd_mach_m16c) 2608 { 2609 set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer); 2610 set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address); 2611 } 2612 2613 /* Register set. */ 2614 make_regs (gdbarch); 2615 2616 /* Breakpoints. */ 2617 set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32c_breakpoint::kind_from_pc); 2618 set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32c_breakpoint::bp_from_kind); 2619 2620 /* Prologue analysis and unwinding. */ 2621 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2622 set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue); 2623 #if 0 2624 /* I'm dropping the dwarf2 sniffer because it has a few problems. 2625 They may be in the dwarf2 cfi code in GDB, or they may be in 2626 the debug info emitted by the upstream toolchain. I don't 2627 know which, but I do know that the prologue analyzer works better. 2628 MVS 04/13/06 */ 2629 dwarf2_append_sniffers (gdbarch); 2630 #endif 2631 frame_unwind_append_unwinder (gdbarch, &m32c_unwind); 2632 2633 /* Inferior calls. */ 2634 set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call); 2635 set_gdbarch_return_value (gdbarch, m32c_return_value); 2636 2637 /* Trampolines. */ 2638 set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code); 2639 2640 set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer); 2641 2642 /* m32c function boundary addresses are not necessarily even. 2643 Therefore, the `vbit', which indicates a pointer to a virtual 2644 member function, is stored in the delta field, rather than as 2645 the low bit of a function pointer address. 2646 2647 In order to verify this, see the definition of 2648 TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the 2649 definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ 2650 set_gdbarch_vbit_in_delta (gdbarch, 1); 2651 2652 return gdbarch; 2653 } 2654 2655 void _initialize_m32c_tdep (); 2656 void 2657 _initialize_m32c_tdep () 2658 { 2659 gdbarch_register (bfd_arch_m32c, m32c_gdbarch_init); 2660 2661 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); 2662 } 2663