1 /* Renesas M32C target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 2004-2014 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 22 #include <stdarg.h> 23 24 #include <string.h> 25 #include "gdb_assert.h" 26 #include "elf-bfd.h" 27 #include "elf/m32c.h" 28 #include "gdb/sim-m32c.h" 29 #include "dis-asm.h" 30 #include "gdbtypes.h" 31 #include "regcache.h" 32 #include "arch-utils.h" 33 #include "frame.h" 34 #include "frame-unwind.h" 35 #include "dwarf2-frame.h" 36 #include "dwarf2expr.h" 37 #include "symtab.h" 38 #include "gdbcore.h" 39 #include "value.h" 40 #include "reggroups.h" 41 #include "prologue-value.h" 42 #include "target.h" 43 44 45 /* The m32c tdep structure. */ 46 47 static struct reggroup *m32c_dma_reggroup; 48 49 struct m32c_reg; 50 51 /* The type of a function that moves the value of REG between CACHE or 52 BUF --- in either direction. */ 53 typedef enum register_status (m32c_move_reg_t) (struct m32c_reg *reg, 54 struct regcache *cache, 55 void *buf); 56 57 struct m32c_reg 58 { 59 /* The name of this register. */ 60 const char *name; 61 62 /* Its type. */ 63 struct type *type; 64 65 /* The architecture this register belongs to. */ 66 struct gdbarch *arch; 67 68 /* Its GDB register number. */ 69 int num; 70 71 /* Its sim register number. */ 72 int sim_num; 73 74 /* Its DWARF register number, or -1 if it doesn't have one. */ 75 int dwarf_num; 76 77 /* Register group memberships. */ 78 unsigned int general_p : 1; 79 unsigned int dma_p : 1; 80 unsigned int system_p : 1; 81 unsigned int save_restore_p : 1; 82 83 /* Functions to read its value from a regcache, and write its value 84 to a regcache. */ 85 m32c_move_reg_t *read, *write; 86 87 /* Data for READ and WRITE functions. The exact meaning depends on 88 the specific functions selected; see the comments for those 89 functions. */ 90 struct m32c_reg *rx, *ry; 91 int n; 92 }; 93 94 95 /* An overestimate of the number of raw and pseudoregisters we will 96 have. The exact answer depends on the variant of the architecture 97 at hand, but we can use this to declare statically allocated 98 arrays, and bump it up when needed. */ 99 #define M32C_MAX_NUM_REGS (75) 100 101 /* The largest assigned DWARF register number. */ 102 #define M32C_MAX_DWARF_REGNUM (40) 103 104 105 struct gdbarch_tdep 106 { 107 /* All the registers for this variant, indexed by GDB register 108 number, and the number of registers present. */ 109 struct m32c_reg regs[M32C_MAX_NUM_REGS]; 110 111 /* The number of valid registers. */ 112 int num_regs; 113 114 /* Interesting registers. These are pointers into REGS. */ 115 struct m32c_reg *pc, *flg; 116 struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1; 117 struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0; 118 struct m32c_reg *sb, *fb, *sp; 119 120 /* A table indexed by DWARF register numbers, pointing into 121 REGS. */ 122 struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1]; 123 124 /* Types for this architecture. We can't use the builtin_type_foo 125 types, because they're not initialized when building a gdbarch 126 structure. */ 127 struct type *voyd, *ptr_voyd, *func_voyd; 128 struct type *uint8, *uint16; 129 struct type *int8, *int16, *int32, *int64; 130 131 /* The types for data address and code address registers. */ 132 struct type *data_addr_reg_type, *code_addr_reg_type; 133 134 /* The number of bytes a return address pushed by a 'jsr' instruction 135 occupies on the stack. */ 136 int ret_addr_bytes; 137 138 /* The number of bytes an address register occupies on the stack 139 when saved by an 'enter' or 'pushm' instruction. */ 140 int push_addr_bytes; 141 }; 142 143 144 /* Types. */ 145 146 static void 147 make_types (struct gdbarch *arch) 148 { 149 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 150 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; 151 int data_addr_reg_bits, code_addr_reg_bits; 152 char type_name[50]; 153 154 #if 0 155 /* This is used to clip CORE_ADDR values, so this value is 156 appropriate both on the m32c, where pointers are 32 bits long, 157 and on the m16c, where pointers are sixteen bits long, but there 158 may be code above the 64k boundary. */ 159 set_gdbarch_addr_bit (arch, 24); 160 #else 161 /* GCC uses 32 bits for addrs in the dwarf info, even though 162 only 16/24 bits are used. Setting addr_bit to 24 causes 163 errors in reading the dwarf addresses. */ 164 set_gdbarch_addr_bit (arch, 32); 165 #endif 166 167 set_gdbarch_int_bit (arch, 16); 168 switch (mach) 169 { 170 case bfd_mach_m16c: 171 data_addr_reg_bits = 16; 172 code_addr_reg_bits = 24; 173 set_gdbarch_ptr_bit (arch, 16); 174 tdep->ret_addr_bytes = 3; 175 tdep->push_addr_bytes = 2; 176 break; 177 178 case bfd_mach_m32c: 179 data_addr_reg_bits = 24; 180 code_addr_reg_bits = 24; 181 set_gdbarch_ptr_bit (arch, 32); 182 tdep->ret_addr_bytes = 4; 183 tdep->push_addr_bytes = 4; 184 break; 185 186 default: 187 gdb_assert_not_reached ("unexpected mach"); 188 } 189 190 /* The builtin_type_mumble variables are sometimes uninitialized when 191 this is called, so we avoid using them. */ 192 tdep->voyd = arch_type (arch, TYPE_CODE_VOID, 1, "void"); 193 tdep->ptr_voyd 194 = arch_type (arch, TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / TARGET_CHAR_BIT, 195 NULL); 196 TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd; 197 TYPE_UNSIGNED (tdep->ptr_voyd) = 1; 198 tdep->func_voyd = lookup_function_type (tdep->voyd); 199 200 xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t", 201 gdbarch_bfd_arch_info (arch)->printable_name); 202 tdep->data_addr_reg_type 203 = arch_type (arch, TYPE_CODE_PTR, data_addr_reg_bits / TARGET_CHAR_BIT, 204 xstrdup (type_name)); 205 TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd; 206 TYPE_UNSIGNED (tdep->data_addr_reg_type) = 1; 207 208 xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t", 209 gdbarch_bfd_arch_info (arch)->printable_name); 210 tdep->code_addr_reg_type 211 = arch_type (arch, TYPE_CODE_PTR, code_addr_reg_bits / TARGET_CHAR_BIT, 212 xstrdup (type_name)); 213 TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd; 214 TYPE_UNSIGNED (tdep->code_addr_reg_type) = 1; 215 216 tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); 217 tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); 218 tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); 219 tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); 220 tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); 221 tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); 222 } 223 224 225 226 /* Register set. */ 227 228 static const char * 229 m32c_register_name (struct gdbarch *gdbarch, int num) 230 { 231 return gdbarch_tdep (gdbarch)->regs[num].name; 232 } 233 234 235 static struct type * 236 m32c_register_type (struct gdbarch *arch, int reg_nr) 237 { 238 return gdbarch_tdep (arch)->regs[reg_nr].type; 239 } 240 241 242 static int 243 m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) 244 { 245 return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num; 246 } 247 248 249 static int 250 m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) 251 { 252 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 253 if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM 254 && tdep->dwarf_regs[reg_nr]) 255 return tdep->dwarf_regs[reg_nr]->num; 256 else 257 /* The DWARF CFI code expects to see -1 for invalid register 258 numbers. */ 259 return -1; 260 } 261 262 263 static int 264 m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 265 struct reggroup *group) 266 { 267 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 268 struct m32c_reg *reg = &tdep->regs[regnum]; 269 270 /* The anonymous raw registers aren't in any groups. */ 271 if (! reg->name) 272 return 0; 273 274 if (group == all_reggroup) 275 return 1; 276 277 if (group == general_reggroup 278 && reg->general_p) 279 return 1; 280 281 if (group == m32c_dma_reggroup 282 && reg->dma_p) 283 return 1; 284 285 if (group == system_reggroup 286 && reg->system_p) 287 return 1; 288 289 /* Since the m32c DWARF register numbers refer to cooked registers, not 290 raw registers, and frame_pop depends on the save and restore groups 291 containing registers the DWARF CFI will actually mention, our save 292 and restore groups are cooked registers, not raw registers. (This is 293 why we can't use the default reggroup function.) */ 294 if ((group == save_reggroup 295 || group == restore_reggroup) 296 && reg->save_restore_p) 297 return 1; 298 299 return 0; 300 } 301 302 303 /* Register move functions. We declare them here using 304 m32c_move_reg_t to check the types. */ 305 static m32c_move_reg_t m32c_raw_read, m32c_raw_write; 306 static m32c_move_reg_t m32c_banked_read, m32c_banked_write; 307 static m32c_move_reg_t m32c_sb_read, m32c_sb_write; 308 static m32c_move_reg_t m32c_part_read, m32c_part_write; 309 static m32c_move_reg_t m32c_cat_read, m32c_cat_write; 310 static m32c_move_reg_t m32c_r3r2r1r0_read, m32c_r3r2r1r0_write; 311 312 313 /* Copy the value of the raw register REG from CACHE to BUF. */ 314 static enum register_status 315 m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 316 { 317 return regcache_raw_read (cache, reg->num, buf); 318 } 319 320 321 /* Copy the value of the raw register REG from BUF to CACHE. */ 322 static enum register_status 323 m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 324 { 325 regcache_raw_write (cache, reg->num, (const void *) buf); 326 327 return REG_VALID; 328 } 329 330 331 /* Return the value of the 'flg' register in CACHE. */ 332 static int 333 m32c_read_flg (struct regcache *cache) 334 { 335 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache)); 336 ULONGEST flg; 337 regcache_raw_read_unsigned (cache, tdep->flg->num, &flg); 338 return flg & 0xffff; 339 } 340 341 342 /* Evaluate the real register number of a banked register. */ 343 static struct m32c_reg * 344 m32c_banked_register (struct m32c_reg *reg, struct regcache *cache) 345 { 346 return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); 347 } 348 349 350 /* Move the value of a banked register from CACHE to BUF. 351 If the value of the 'flg' register in CACHE has any of the bits 352 masked in REG->n set, then read REG->ry. Otherwise, read 353 REG->rx. */ 354 static enum register_status 355 m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 356 { 357 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); 358 return regcache_raw_read (cache, bank_reg->num, buf); 359 } 360 361 362 /* Move the value of a banked register from BUF to CACHE. 363 If the value of the 'flg' register in CACHE has any of the bits 364 masked in REG->n set, then write REG->ry. Otherwise, write 365 REG->rx. */ 366 static enum register_status 367 m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 368 { 369 struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); 370 regcache_raw_write (cache, bank_reg->num, (const void *) buf); 371 372 return REG_VALID; 373 } 374 375 376 /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a 377 banked register; on bfd_mach_m16c, it's not. */ 378 static enum register_status 379 m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 380 { 381 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) 382 return m32c_raw_read (reg->rx, cache, buf); 383 else 384 return m32c_banked_read (reg, cache, buf); 385 } 386 387 388 /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a 389 banked register; on bfd_mach_m16c, it's not. */ 390 static enum register_status 391 m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 392 { 393 if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) 394 m32c_raw_write (reg->rx, cache, buf); 395 else 396 m32c_banked_write (reg, cache, buf); 397 398 return REG_VALID; 399 } 400 401 402 /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P 403 and *LEN_P to the offset and length, in bytes, of the part REG 404 occupies in its underlying register. The offset is from the 405 lower-addressed end, regardless of the architecture's endianness. 406 (The M32C family is always little-endian, but let's keep those 407 assumptions out of here.) */ 408 static void 409 m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) 410 { 411 /* The length of the containing register, of which REG is one part. */ 412 int containing_len = TYPE_LENGTH (reg->rx->type); 413 414 /* The length of one "element" in our imaginary array. */ 415 int elt_len = TYPE_LENGTH (reg->type); 416 417 /* The offset of REG's "element" from the least significant end of 418 the containing register. */ 419 int elt_offset = reg->n * elt_len; 420 421 /* If we extend off the end, trim the length of the element. */ 422 if (elt_offset + elt_len > containing_len) 423 { 424 elt_len = containing_len - elt_offset; 425 /* We shouldn't be declaring partial registers that go off the 426 end of their containing registers. */ 427 gdb_assert (elt_len > 0); 428 } 429 430 /* Flip the offset around if we're big-endian. */ 431 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 432 elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len; 433 434 *offset_p = elt_offset; 435 *len_p = elt_len; 436 } 437 438 439 /* Move the value of a partial register (r0h, intbl, etc.) from CACHE 440 to BUF. Treating the value of the register REG->rx as an array of 441 REG->type values, where higher indices refer to more significant 442 bits, read the value of the REG->n'th element. */ 443 static enum register_status 444 m32c_part_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 445 { 446 int offset, len; 447 448 memset (buf, 0, TYPE_LENGTH (reg->type)); 449 m32c_find_part (reg, &offset, &len); 450 return regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf); 451 } 452 453 454 /* Move the value of a banked register from BUF to CACHE. 455 Treating the value of the register REG->rx as an array of REG->type 456 values, where higher indices refer to more significant bits, write 457 the value of the REG->n'th element. */ 458 static enum register_status 459 m32c_part_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 460 { 461 int offset, len; 462 463 m32c_find_part (reg, &offset, &len); 464 regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf); 465 466 return REG_VALID; 467 } 468 469 470 /* Move the value of REG from CACHE to BUF. REG's value is the 471 concatenation of the values of the registers REG->rx and REG->ry, 472 with REG->rx contributing the more significant bits. */ 473 static enum register_status 474 m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 475 { 476 int high_bytes = TYPE_LENGTH (reg->rx->type); 477 int low_bytes = TYPE_LENGTH (reg->ry->type); 478 /* For address arithmetic. */ 479 unsigned char *cbuf = buf; 480 enum register_status status; 481 482 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); 483 484 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 485 { 486 status = regcache_cooked_read (cache, reg->rx->num, cbuf); 487 if (status == REG_VALID) 488 status = regcache_cooked_read (cache, reg->ry->num, cbuf + high_bytes); 489 } 490 else 491 { 492 status = regcache_cooked_read (cache, reg->rx->num, cbuf + low_bytes); 493 if (status == REG_VALID) 494 status = regcache_cooked_read (cache, reg->ry->num, cbuf); 495 } 496 497 return status; 498 } 499 500 501 /* Move the value of REG from CACHE to BUF. REG's value is the 502 concatenation of the values of the registers REG->rx and REG->ry, 503 with REG->rx contributing the more significant bits. */ 504 static enum register_status 505 m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 506 { 507 int high_bytes = TYPE_LENGTH (reg->rx->type); 508 int low_bytes = TYPE_LENGTH (reg->ry->type); 509 /* For address arithmetic. */ 510 unsigned char *cbuf = buf; 511 512 gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); 513 514 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 515 { 516 regcache_cooked_write (cache, reg->rx->num, cbuf); 517 regcache_cooked_write (cache, reg->ry->num, cbuf + high_bytes); 518 } 519 else 520 { 521 regcache_cooked_write (cache, reg->rx->num, cbuf + low_bytes); 522 regcache_cooked_write (cache, reg->ry->num, cbuf); 523 } 524 525 return REG_VALID; 526 } 527 528 529 /* Copy the value of the raw register REG from CACHE to BUF. REG is 530 the concatenation (from most significant to least) of r3, r2, r1, 531 and r0. */ 532 static enum register_status 533 m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, void *buf) 534 { 535 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); 536 int len = TYPE_LENGTH (tdep->r0->type); 537 enum register_status status; 538 539 /* For address arithmetic. */ 540 unsigned char *cbuf = buf; 541 542 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 543 { 544 status = regcache_cooked_read (cache, tdep->r0->num, cbuf + len * 3); 545 if (status == REG_VALID) 546 status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 2); 547 if (status == REG_VALID) 548 status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 1); 549 if (status == REG_VALID) 550 status = regcache_cooked_read (cache, tdep->r3->num, cbuf); 551 } 552 else 553 { 554 status = regcache_cooked_read (cache, tdep->r0->num, cbuf); 555 if (status == REG_VALID) 556 status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 1); 557 if (status == REG_VALID) 558 status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 2); 559 if (status == REG_VALID) 560 status = regcache_cooked_read (cache, tdep->r3->num, cbuf + len * 3); 561 } 562 563 return status; 564 } 565 566 567 /* Copy the value of the raw register REG from BUF to CACHE. REG is 568 the concatenation (from most significant to least) of r3, r2, r1, 569 and r0. */ 570 static enum register_status 571 m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, void *buf) 572 { 573 struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); 574 int len = TYPE_LENGTH (tdep->r0->type); 575 576 /* For address arithmetic. */ 577 unsigned char *cbuf = buf; 578 579 if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) 580 { 581 regcache_cooked_write (cache, tdep->r0->num, cbuf + len * 3); 582 regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 2); 583 regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 1); 584 regcache_cooked_write (cache, tdep->r3->num, cbuf); 585 } 586 else 587 { 588 regcache_cooked_write (cache, tdep->r0->num, cbuf); 589 regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 1); 590 regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 2); 591 regcache_cooked_write (cache, tdep->r3->num, cbuf + len * 3); 592 } 593 594 return REG_VALID; 595 } 596 597 598 static enum register_status 599 m32c_pseudo_register_read (struct gdbarch *arch, 600 struct regcache *cache, 601 int cookednum, 602 gdb_byte *buf) 603 { 604 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 605 struct m32c_reg *reg; 606 607 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); 608 gdb_assert (arch == get_regcache_arch (cache)); 609 gdb_assert (arch == tdep->regs[cookednum].arch); 610 reg = &tdep->regs[cookednum]; 611 612 return reg->read (reg, cache, buf); 613 } 614 615 616 static void 617 m32c_pseudo_register_write (struct gdbarch *arch, 618 struct regcache *cache, 619 int cookednum, 620 const gdb_byte *buf) 621 { 622 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 623 struct m32c_reg *reg; 624 625 gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); 626 gdb_assert (arch == get_regcache_arch (cache)); 627 gdb_assert (arch == tdep->regs[cookednum].arch); 628 reg = &tdep->regs[cookednum]; 629 630 reg->write (reg, cache, (void *) buf); 631 } 632 633 634 /* Add a register with the given fields to the end of ARCH's table. 635 Return a pointer to the newly added register. */ 636 static struct m32c_reg * 637 add_reg (struct gdbarch *arch, 638 const char *name, 639 struct type *type, 640 int sim_num, 641 m32c_move_reg_t *read, 642 m32c_move_reg_t *write, 643 struct m32c_reg *rx, 644 struct m32c_reg *ry, 645 int n) 646 { 647 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 648 struct m32c_reg *r = &tdep->regs[tdep->num_regs]; 649 650 gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); 651 652 r->name = name; 653 r->type = type; 654 r->arch = arch; 655 r->num = tdep->num_regs; 656 r->sim_num = sim_num; 657 r->dwarf_num = -1; 658 r->general_p = 0; 659 r->dma_p = 0; 660 r->system_p = 0; 661 r->save_restore_p = 0; 662 r->read = read; 663 r->write = write; 664 r->rx = rx; 665 r->ry = ry; 666 r->n = n; 667 668 tdep->num_regs++; 669 670 return r; 671 } 672 673 674 /* Record NUM as REG's DWARF register number. */ 675 static void 676 set_dwarf_regnum (struct m32c_reg *reg, int num) 677 { 678 gdb_assert (num < M32C_MAX_NUM_REGS); 679 680 /* Update the reg->DWARF mapping. Only count the first number 681 assigned to this register. */ 682 if (reg->dwarf_num == -1) 683 reg->dwarf_num = num; 684 685 /* Update the DWARF->reg mapping. */ 686 gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg; 687 } 688 689 690 /* Mark REG as a general-purpose register, and return it. */ 691 static struct m32c_reg * 692 mark_general (struct m32c_reg *reg) 693 { 694 reg->general_p = 1; 695 return reg; 696 } 697 698 699 /* Mark REG as a DMA register, and return it. */ 700 static struct m32c_reg * 701 mark_dma (struct m32c_reg *reg) 702 { 703 reg->dma_p = 1; 704 return reg; 705 } 706 707 708 /* Mark REG as a SYSTEM register, and return it. */ 709 static struct m32c_reg * 710 mark_system (struct m32c_reg *reg) 711 { 712 reg->system_p = 1; 713 return reg; 714 } 715 716 717 /* Mark REG as a save-restore register, and return it. */ 718 static struct m32c_reg * 719 mark_save_restore (struct m32c_reg *reg) 720 { 721 reg->save_restore_p = 1; 722 return reg; 723 } 724 725 726 #define FLAGBIT_B 0x0010 727 #define FLAGBIT_U 0x0080 728 729 /* Handy macros for declaring registers. These all evaluate to 730 pointers to the register declared. Macros that define two 731 registers evaluate to a pointer to the first. */ 732 733 /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ 734 #define R(name, type, sim_num) \ 735 (add_reg (arch, (name), (type), (sim_num), \ 736 m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) 737 738 /* The simulator register number for a raw register named NAME. */ 739 #define SIM(name) (m32c_sim_reg_ ## name) 740 741 /* A raw unsigned 16-bit data register named NAME. 742 NAME should be an identifier, not a string. */ 743 #define R16U(name) \ 744 (R(#name, tdep->uint16, SIM (name))) 745 746 /* A raw data address register named NAME. 747 NAME should be an identifier, not a string. */ 748 #define RA(name) \ 749 (R(#name, tdep->data_addr_reg_type, SIM (name))) 750 751 /* A raw code address register named NAME. NAME should 752 be an identifier, not a string. */ 753 #define RC(name) \ 754 (R(#name, tdep->code_addr_reg_type, SIM (name))) 755 756 /* A pair of raw registers named NAME0 and NAME1, with type TYPE. 757 NAME should be an identifier, not a string. */ 758 #define RP(name, type) \ 759 (R(#name "0", (type), SIM (name ## 0)), \ 760 R(#name "1", (type), SIM (name ## 1)) - 1) 761 762 /* A raw banked general-purpose data register named NAME. 763 NAME should be an identifier, not a string. */ 764 #define RBD(name) \ 765 (R(NULL, tdep->int16, SIM (name ## _bank0)), \ 766 R(NULL, tdep->int16, SIM (name ## _bank1)) - 1) 767 768 /* A raw banked data address register named NAME. 769 NAME should be an identifier, not a string. */ 770 #define RBA(name) \ 771 (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \ 772 R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) 773 774 /* A cooked register named NAME referring to a raw banked register 775 from the bank selected by the current value of FLG. RAW_PAIR 776 should be a pointer to the first register in the banked pair. 777 NAME must be an identifier, not a string. */ 778 #define CB(name, raw_pair) \ 779 (add_reg (arch, #name, (raw_pair)->type, 0, \ 780 m32c_banked_read, m32c_banked_write, \ 781 (raw_pair), (raw_pair + 1), FLAGBIT_B)) 782 783 /* A pair of registers named NAMEH and NAMEL, of type TYPE, that 784 access the top and bottom halves of the register pointed to by 785 NAME. NAME should be an identifier. */ 786 #define CHL(name, type) \ 787 (add_reg (arch, #name "h", (type), 0, \ 788 m32c_part_read, m32c_part_write, name, NULL, 1), \ 789 add_reg (arch, #name "l", (type), 0, \ 790 m32c_part_read, m32c_part_write, name, NULL, 0) - 1) 791 792 /* A register constructed by concatenating the two registers HIGH and 793 LOW, whose name is HIGHLOW and whose type is TYPE. */ 794 #define CCAT(high, low, type) \ 795 (add_reg (arch, #high #low, (type), 0, \ 796 m32c_cat_read, m32c_cat_write, (high), (low), 0)) 797 798 /* Abbreviations for marking register group membership. */ 799 #define G(reg) (mark_general (reg)) 800 #define S(reg) (mark_system (reg)) 801 #define DMA(reg) (mark_dma (reg)) 802 803 804 /* Construct the register set for ARCH. */ 805 static void 806 make_regs (struct gdbarch *arch) 807 { 808 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 809 int mach = gdbarch_bfd_arch_info (arch)->mach; 810 int num_raw_regs; 811 int num_cooked_regs; 812 813 struct m32c_reg *r0; 814 struct m32c_reg *r1; 815 struct m32c_reg *r2; 816 struct m32c_reg *r3; 817 struct m32c_reg *a0; 818 struct m32c_reg *a1; 819 struct m32c_reg *fb; 820 struct m32c_reg *sb; 821 struct m32c_reg *sp; 822 struct m32c_reg *r0hl; 823 struct m32c_reg *r1hl; 824 struct m32c_reg *r2hl; 825 struct m32c_reg *r3hl; 826 struct m32c_reg *intbhl; 827 struct m32c_reg *r2r0; 828 struct m32c_reg *r3r1; 829 struct m32c_reg *r3r1r2r0; 830 struct m32c_reg *r3r2r1r0; 831 struct m32c_reg *a1a0; 832 833 struct m32c_reg *raw_r0_pair = RBD (r0); 834 struct m32c_reg *raw_r1_pair = RBD (r1); 835 struct m32c_reg *raw_r2_pair = RBD (r2); 836 struct m32c_reg *raw_r3_pair = RBD (r3); 837 struct m32c_reg *raw_a0_pair = RBA (a0); 838 struct m32c_reg *raw_a1_pair = RBA (a1); 839 struct m32c_reg *raw_fb_pair = RBA (fb); 840 841 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. 842 We always declare both raw registers, and deal with the distinction 843 in the pseudoregister. */ 844 struct m32c_reg *raw_sb_pair = RBA (sb); 845 846 struct m32c_reg *usp = S (RA (usp)); 847 struct m32c_reg *isp = S (RA (isp)); 848 struct m32c_reg *intb = S (RC (intb)); 849 struct m32c_reg *pc = G (RC (pc)); 850 struct m32c_reg *flg = G (R16U (flg)); 851 852 if (mach == bfd_mach_m32c) 853 { 854 struct m32c_reg *svf = S (R16U (svf)); 855 struct m32c_reg *svp = S (RC (svp)); 856 struct m32c_reg *vct = S (RC (vct)); 857 858 struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8)); 859 struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16)); 860 struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16)); 861 struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type)); 862 struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type)); 863 struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type)); 864 } 865 866 num_raw_regs = tdep->num_regs; 867 868 r0 = G (CB (r0, raw_r0_pair)); 869 r1 = G (CB (r1, raw_r1_pair)); 870 r2 = G (CB (r2, raw_r2_pair)); 871 r3 = G (CB (r3, raw_r3_pair)); 872 a0 = G (CB (a0, raw_a0_pair)); 873 a1 = G (CB (a1, raw_a1_pair)); 874 fb = G (CB (fb, raw_fb_pair)); 875 876 /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. 877 Specify custom read/write functions that do the right thing. */ 878 sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, 879 m32c_sb_read, m32c_sb_write, 880 raw_sb_pair, raw_sb_pair + 1, 0)); 881 882 /* The current sp is either usp or isp, depending on the value of 883 the FLG register's U bit. */ 884 sp = G (add_reg (arch, "sp", usp->type, 0, 885 m32c_banked_read, m32c_banked_write, 886 isp, usp, FLAGBIT_U)); 887 888 r0hl = CHL (r0, tdep->int8); 889 r1hl = CHL (r1, tdep->int8); 890 r2hl = CHL (r2, tdep->int8); 891 r3hl = CHL (r3, tdep->int8); 892 intbhl = CHL (intb, tdep->int16); 893 894 r2r0 = CCAT (r2, r0, tdep->int32); 895 r3r1 = CCAT (r3, r1, tdep->int32); 896 r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); 897 898 r3r2r1r0 899 = add_reg (arch, "r3r2r1r0", tdep->int64, 0, 900 m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); 901 902 if (mach == bfd_mach_m16c) 903 a1a0 = CCAT (a1, a0, tdep->int32); 904 else 905 a1a0 = NULL; 906 907 num_cooked_regs = tdep->num_regs - num_raw_regs; 908 909 tdep->pc = pc; 910 tdep->flg = flg; 911 tdep->r0 = r0; 912 tdep->r1 = r1; 913 tdep->r2 = r2; 914 tdep->r3 = r3; 915 tdep->r2r0 = r2r0; 916 tdep->r3r2r1r0 = r3r2r1r0; 917 tdep->r3r1r2r0 = r3r1r2r0; 918 tdep->a0 = a0; 919 tdep->a1 = a1; 920 tdep->sb = sb; 921 tdep->fb = fb; 922 tdep->sp = sp; 923 924 /* Set up the DWARF register table. */ 925 memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); 926 set_dwarf_regnum (r0hl + 1, 0x01); 927 set_dwarf_regnum (r0hl + 0, 0x02); 928 set_dwarf_regnum (r1hl + 1, 0x03); 929 set_dwarf_regnum (r1hl + 0, 0x04); 930 set_dwarf_regnum (r0, 0x05); 931 set_dwarf_regnum (r1, 0x06); 932 set_dwarf_regnum (r2, 0x07); 933 set_dwarf_regnum (r3, 0x08); 934 set_dwarf_regnum (a0, 0x09); 935 set_dwarf_regnum (a1, 0x0a); 936 set_dwarf_regnum (fb, 0x0b); 937 set_dwarf_regnum (sp, 0x0c); 938 set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ 939 set_dwarf_regnum (sb, 0x13); 940 set_dwarf_regnum (r2r0, 0x15); 941 set_dwarf_regnum (r3r1, 0x16); 942 if (a1a0) 943 set_dwarf_regnum (a1a0, 0x17); 944 945 /* Enumerate the save/restore register group. 946 947 The regcache_save and regcache_restore functions apply their read 948 function to each register in this group. 949 950 Since frame_pop supplies frame_unwind_register as its read 951 function, the registers meaningful to the Dwarf unwinder need to 952 be in this group. 953 954 On the other hand, when we make inferior calls, save_inferior_status 955 and restore_inferior_status use them to preserve the current register 956 values across the inferior call. For this, you'd kind of like to 957 preserve all the raw registers, to protect the interrupted code from 958 any sort of bank switching the callee might have done. But we handle 959 those cases so badly anyway --- for example, it matters whether we 960 restore FLG before or after we restore the general-purpose registers, 961 but there's no way to express that --- that it isn't worth worrying 962 about. 963 964 We omit control registers like inthl: if you call a function that 965 changes those, it's probably because you wanted that change to be 966 visible to the interrupted code. */ 967 mark_save_restore (r0); 968 mark_save_restore (r1); 969 mark_save_restore (r2); 970 mark_save_restore (r3); 971 mark_save_restore (a0); 972 mark_save_restore (a1); 973 mark_save_restore (sb); 974 mark_save_restore (fb); 975 mark_save_restore (sp); 976 mark_save_restore (pc); 977 mark_save_restore (flg); 978 979 set_gdbarch_num_regs (arch, num_raw_regs); 980 set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); 981 set_gdbarch_pc_regnum (arch, pc->num); 982 set_gdbarch_sp_regnum (arch, sp->num); 983 set_gdbarch_register_name (arch, m32c_register_name); 984 set_gdbarch_register_type (arch, m32c_register_type); 985 set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); 986 set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); 987 set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); 988 set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); 989 set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); 990 set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); 991 992 reggroup_add (arch, general_reggroup); 993 reggroup_add (arch, all_reggroup); 994 reggroup_add (arch, save_reggroup); 995 reggroup_add (arch, restore_reggroup); 996 reggroup_add (arch, system_reggroup); 997 reggroup_add (arch, m32c_dma_reggroup); 998 } 999 1000 1001 1002 /* Breakpoints. */ 1003 1004 static const unsigned char * 1005 m32c_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 1006 { 1007 static unsigned char break_insn[] = { 0x00 }; /* brk */ 1008 1009 *len = sizeof (break_insn); 1010 return break_insn; 1011 } 1012 1013 1014 1015 /* Prologue analysis. */ 1016 1017 struct m32c_prologue 1018 { 1019 /* For consistency with the DWARF 2 .debug_frame info generated by 1020 GCC, a frame's CFA is the address immediately after the saved 1021 return address. */ 1022 1023 /* The architecture for which we generated this prologue info. */ 1024 struct gdbarch *arch; 1025 1026 enum { 1027 /* This function uses a frame pointer. */ 1028 prologue_with_frame_ptr, 1029 1030 /* This function has no frame pointer. */ 1031 prologue_sans_frame_ptr, 1032 1033 /* This function sets up the stack, so its frame is the first 1034 frame on the stack. */ 1035 prologue_first_frame 1036 1037 } kind; 1038 1039 /* If KIND is prologue_with_frame_ptr, this is the offset from the 1040 CFA to where the frame pointer points. This is always zero or 1041 negative. */ 1042 LONGEST frame_ptr_offset; 1043 1044 /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to 1045 the stack pointer --- always zero or negative. 1046 1047 Calling this a "size" is a bit misleading, but given that the 1048 stack grows downwards, using offsets for everything keeps one 1049 from going completely sign-crazy: you never change anything's 1050 sign for an ADD instruction; always change the second operand's 1051 sign for a SUB instruction; and everything takes care of 1052 itself. 1053 1054 Functions that use alloca don't have a constant frame size. But 1055 they always have frame pointers, so we must use that to find the 1056 CFA (and perhaps to unwind the stack pointer). */ 1057 LONGEST frame_size; 1058 1059 /* The address of the first instruction at which the frame has been 1060 set up and the arguments are where the debug info says they are 1061 --- as best as we can tell. */ 1062 CORE_ADDR prologue_end; 1063 1064 /* reg_offset[R] is the offset from the CFA at which register R is 1065 saved, or 1 if register R has not been saved. (Real values are 1066 always zero or negative.) */ 1067 LONGEST reg_offset[M32C_MAX_NUM_REGS]; 1068 }; 1069 1070 1071 /* The longest I've seen, anyway. */ 1072 #define M32C_MAX_INSN_LEN (9) 1073 1074 /* Processor state, for the prologue analyzer. */ 1075 struct m32c_pv_state 1076 { 1077 struct gdbarch *arch; 1078 pv_t r0, r1, r2, r3; 1079 pv_t a0, a1; 1080 pv_t sb, fb, sp; 1081 pv_t pc; 1082 struct pv_area *stack; 1083 1084 /* Bytes from the current PC, the address they were read from, 1085 and the address of the next unconsumed byte. */ 1086 gdb_byte insn[M32C_MAX_INSN_LEN]; 1087 CORE_ADDR scan_pc, next_addr; 1088 }; 1089 1090 1091 /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if 1092 all went well, or non-zero if simulating the action would trash our 1093 state. */ 1094 static int 1095 m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) 1096 { 1097 if (pv_area_store_would_trash (state->stack, state->sp)) 1098 return 1; 1099 1100 state->sp = pv_add_constant (state->sp, -size); 1101 pv_area_store (state->stack, state->sp, size, value); 1102 1103 return 0; 1104 } 1105 1106 1107 /* A source or destination location for an m16c or m32c 1108 instruction. */ 1109 struct srcdest 1110 { 1111 /* If srcdest_reg, the location is a register pointed to by REG. 1112 If srcdest_partial_reg, the location is part of a register pointed 1113 to by REG. We don't try to handle this too well. 1114 If srcdest_mem, the location is memory whose address is ADDR. */ 1115 enum { srcdest_reg, srcdest_partial_reg, srcdest_mem } kind; 1116 pv_t *reg, addr; 1117 }; 1118 1119 1120 /* Return the SIZE-byte value at LOC in STATE. */ 1121 static pv_t 1122 m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) 1123 { 1124 if (loc.kind == srcdest_mem) 1125 return pv_area_fetch (state->stack, loc.addr, size); 1126 else if (loc.kind == srcdest_partial_reg) 1127 return pv_unknown (); 1128 else 1129 return *loc.reg; 1130 } 1131 1132 1133 /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if 1134 all went well, or non-zero if simulating the store would trash our 1135 state. */ 1136 static int 1137 m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, 1138 pv_t value, int size) 1139 { 1140 if (loc.kind == srcdest_mem) 1141 { 1142 if (pv_area_store_would_trash (state->stack, loc.addr)) 1143 return 1; 1144 pv_area_store (state->stack, loc.addr, size, value); 1145 } 1146 else if (loc.kind == srcdest_partial_reg) 1147 *loc.reg = pv_unknown (); 1148 else 1149 *loc.reg = value; 1150 1151 return 0; 1152 } 1153 1154 1155 static int 1156 m32c_sign_ext (int v, int bits) 1157 { 1158 int mask = 1 << (bits - 1); 1159 return (v ^ mask) - mask; 1160 } 1161 1162 static unsigned int 1163 m32c_next_byte (struct m32c_pv_state *st) 1164 { 1165 gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); 1166 return st->insn[st->next_addr++ - st->scan_pc]; 1167 } 1168 1169 static int 1170 m32c_udisp8 (struct m32c_pv_state *st) 1171 { 1172 return m32c_next_byte (st); 1173 } 1174 1175 1176 static int 1177 m32c_sdisp8 (struct m32c_pv_state *st) 1178 { 1179 return m32c_sign_ext (m32c_next_byte (st), 8); 1180 } 1181 1182 1183 static int 1184 m32c_udisp16 (struct m32c_pv_state *st) 1185 { 1186 int low = m32c_next_byte (st); 1187 int high = m32c_next_byte (st); 1188 1189 return low + (high << 8); 1190 } 1191 1192 1193 static int 1194 m32c_sdisp16 (struct m32c_pv_state *st) 1195 { 1196 int low = m32c_next_byte (st); 1197 int high = m32c_next_byte (st); 1198 1199 return m32c_sign_ext (low + (high << 8), 16); 1200 } 1201 1202 1203 static int 1204 m32c_udisp24 (struct m32c_pv_state *st) 1205 { 1206 int low = m32c_next_byte (st); 1207 int mid = m32c_next_byte (st); 1208 int high = m32c_next_byte (st); 1209 1210 return low + (mid << 8) + (high << 16); 1211 } 1212 1213 1214 /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ 1215 static int 1216 m32c_get_src23 (unsigned char *i) 1217 { 1218 return (((i[0] & 0x70) >> 2) 1219 | ((i[1] & 0x30) >> 4)); 1220 } 1221 1222 1223 /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ 1224 static int 1225 m32c_get_dest23 (unsigned char *i) 1226 { 1227 return (((i[0] & 0x0e) << 1) 1228 | ((i[1] & 0xc0) >> 6)); 1229 } 1230 1231 1232 static struct srcdest 1233 m32c_decode_srcdest4 (struct m32c_pv_state *st, 1234 int code, int size) 1235 { 1236 struct srcdest sd; 1237 1238 if (code < 6) 1239 sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); 1240 else 1241 sd.kind = srcdest_mem; 1242 1243 sd.addr = pv_unknown (); 1244 sd.reg = 0; 1245 1246 switch (code) 1247 { 1248 case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break; 1249 case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; 1250 case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; 1251 case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; 1252 1253 case 0x4: sd.reg = &st->a0; break; 1254 case 0x5: sd.reg = &st->a1; break; 1255 1256 case 0x6: sd.addr = st->a0; break; 1257 case 0x7: sd.addr = st->a1; break; 1258 1259 case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; 1260 case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; 1261 case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; 1262 case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; 1263 1264 case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; 1265 case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; 1266 case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; 1267 case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; 1268 1269 default: 1270 gdb_assert_not_reached ("unexpected srcdest4"); 1271 } 1272 1273 return sd; 1274 } 1275 1276 1277 static struct srcdest 1278 m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) 1279 { 1280 struct srcdest sd; 1281 1282 sd.addr = pv_unknown (); 1283 sd.reg = 0; 1284 1285 switch (code) 1286 { 1287 case 0x12: 1288 case 0x13: 1289 case 0x10: 1290 case 0x11: 1291 sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; 1292 break; 1293 1294 case 0x02: 1295 case 0x03: 1296 sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; 1297 break; 1298 1299 default: 1300 sd.kind = srcdest_mem; 1301 break; 1302 1303 } 1304 1305 switch (code) 1306 { 1307 case 0x12: sd.reg = &st->r0; break; 1308 case 0x13: sd.reg = &st->r1; break; 1309 case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; 1310 case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; 1311 case 0x02: sd.reg = &st->a0; break; 1312 case 0x03: sd.reg = &st->a1; break; 1313 1314 case 0x00: sd.addr = st->a0; break; 1315 case 0x01: sd.addr = st->a1; break; 1316 case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; 1317 case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; 1318 case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; 1319 case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; 1320 case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; 1321 case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; 1322 case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; 1323 case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; 1324 case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; 1325 case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; 1326 case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; 1327 case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; 1328 default: 1329 gdb_assert_not_reached ("unexpected sd23"); 1330 } 1331 1332 if (ind) 1333 { 1334 sd.addr = m32c_srcdest_fetch (st, sd, 4); 1335 sd.kind = srcdest_mem; 1336 } 1337 1338 return sd; 1339 } 1340 1341 1342 /* The r16c and r32c machines have instructions with similar 1343 semantics, but completely different machine language encodings. So 1344 we break out the semantics into their own functions, and leave 1345 machine-specific decoding in m32c_analyze_prologue. 1346 1347 The following functions all expect their arguments already decoded, 1348 and they all return zero if analysis should continue past this 1349 instruction, or non-zero if analysis should stop. */ 1350 1351 1352 /* Simulate an 'enter SIZE' instruction in STATE. */ 1353 static int 1354 m32c_pv_enter (struct m32c_pv_state *state, int size) 1355 { 1356 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); 1357 1358 /* If simulating this store would require us to forget 1359 everything we know about the stack frame in the name of 1360 accuracy, it would be better to just quit now. */ 1361 if (pv_area_store_would_trash (state->stack, state->sp)) 1362 return 1; 1363 1364 if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) 1365 return 1; 1366 state->fb = state->sp; 1367 state->sp = pv_add_constant (state->sp, -size); 1368 1369 return 0; 1370 } 1371 1372 1373 static int 1374 m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, 1375 int bit, int src, int size) 1376 { 1377 if (bit & src) 1378 { 1379 if (m32c_pv_push (state, reg, size)) 1380 return 1; 1381 } 1382 1383 return 0; 1384 } 1385 1386 1387 /* Simulate a 'pushm SRC' instruction in STATE. */ 1388 static int 1389 m32c_pv_pushm (struct m32c_pv_state *state, int src) 1390 { 1391 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); 1392 1393 /* The bits in SRC indicating which registers to save are: 1394 r0 r1 r2 r3 a0 a1 sb fb */ 1395 return 1396 ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) 1397 || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) 1398 || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) 1399 || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) 1400 || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) 1401 || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) 1402 || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) 1403 || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); 1404 } 1405 1406 /* Return non-zero if VALUE is the first incoming argument register. */ 1407 1408 static int 1409 m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) 1410 { 1411 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); 1412 return (value.kind == pvk_register 1413 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c 1414 ? (value.reg == tdep->r1->num) 1415 : (value.reg == tdep->r0->num)) 1416 && value.k == 0); 1417 } 1418 1419 /* Return non-zero if VALUE is an incoming argument register. */ 1420 1421 static int 1422 m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) 1423 { 1424 struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); 1425 return (value.kind == pvk_register 1426 && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c 1427 ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) 1428 : (value.reg == tdep->r0->num)) 1429 && value.k == 0); 1430 } 1431 1432 /* Return non-zero if a store of VALUE to LOC is probably spilling an 1433 argument register to its stack slot in STATE. Such instructions 1434 should be included in the prologue, if possible. 1435 1436 The store is a spill if: 1437 - the value being stored is the original value of an argument register; 1438 - the value has not already been stored somewhere in STACK; and 1439 - LOC is a stack slot (e.g., a memory location whose address is 1440 relative to the original value of the SP). */ 1441 1442 static int 1443 m32c_is_arg_spill (struct m32c_pv_state *st, 1444 struct srcdest loc, 1445 pv_t value) 1446 { 1447 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); 1448 1449 return (m32c_is_arg_reg (st, value) 1450 && loc.kind == srcdest_mem 1451 && pv_is_register (loc.addr, tdep->sp->num) 1452 && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0)); 1453 } 1454 1455 /* Return non-zero if a store of VALUE to LOC is probably 1456 copying the struct return address into an address register 1457 for immediate use. This is basically a "spill" into the 1458 address register, instead of onto the stack. 1459 1460 The prerequisites are: 1461 - value being stored is original value of the FIRST arg register; 1462 - value has not already been stored on stack; and 1463 - LOC is an address register (a0 or a1). */ 1464 1465 static int 1466 m32c_is_struct_return (struct m32c_pv_state *st, 1467 struct srcdest loc, 1468 pv_t value) 1469 { 1470 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); 1471 1472 return (m32c_is_1st_arg_reg (st, value) 1473 && !pv_area_find_reg (st->stack, st->arch, value.reg, 0) 1474 && loc.kind == srcdest_reg 1475 && (pv_is_register (*loc.reg, tdep->a0->num) 1476 || pv_is_register (*loc.reg, tdep->a1->num))); 1477 } 1478 1479 /* Return non-zero if a 'pushm' saving the registers indicated by SRC 1480 was a register save: 1481 - all the named registers should have their original values, and 1482 - the stack pointer should be at a constant offset from the 1483 original stack pointer. */ 1484 static int 1485 m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) 1486 { 1487 struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); 1488 /* The bits in SRC indicating which registers to save are: 1489 r0 r1 r2 r3 a0 a1 sb fb */ 1490 return 1491 (pv_is_register (st->sp, tdep->sp->num) 1492 && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) 1493 && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) 1494 && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) 1495 && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) 1496 && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) 1497 && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) 1498 && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) 1499 && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); 1500 } 1501 1502 1503 /* Function for finding saved registers in a 'struct pv_area'; we pass 1504 this to pv_area_scan. 1505 1506 If VALUE is a saved register, ADDR says it was saved at a constant 1507 offset from the frame base, and SIZE indicates that the whole 1508 register was saved, record its offset in RESULT_UNTYPED. */ 1509 static void 1510 check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) 1511 { 1512 struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; 1513 struct gdbarch *arch = prologue->arch; 1514 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1515 1516 /* Is this the unchanged value of some register being saved on the 1517 stack? */ 1518 if (value.kind == pvk_register 1519 && value.k == 0 1520 && pv_is_register (addr, tdep->sp->num)) 1521 { 1522 /* Some registers require special handling: they're saved as a 1523 larger value than the register itself. */ 1524 CORE_ADDR saved_size = register_size (arch, value.reg); 1525 1526 if (value.reg == tdep->pc->num) 1527 saved_size = tdep->ret_addr_bytes; 1528 else if (register_type (arch, value.reg) 1529 == tdep->data_addr_reg_type) 1530 saved_size = tdep->push_addr_bytes; 1531 1532 if (size == saved_size) 1533 { 1534 /* Find which end of the saved value corresponds to our 1535 register. */ 1536 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) 1537 prologue->reg_offset[value.reg] 1538 = (addr.k + saved_size - register_size (arch, value.reg)); 1539 else 1540 prologue->reg_offset[value.reg] = addr.k; 1541 } 1542 } 1543 } 1544 1545 1546 /* Analyze the function prologue for ARCH at START, going no further 1547 than LIMIT, and place a description of what we found in 1548 PROLOGUE. */ 1549 static void 1550 m32c_analyze_prologue (struct gdbarch *arch, 1551 CORE_ADDR start, CORE_ADDR limit, 1552 struct m32c_prologue *prologue) 1553 { 1554 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1555 unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; 1556 CORE_ADDR after_last_frame_related_insn; 1557 struct cleanup *back_to; 1558 struct m32c_pv_state st; 1559 1560 st.arch = arch; 1561 st.r0 = pv_register (tdep->r0->num, 0); 1562 st.r1 = pv_register (tdep->r1->num, 0); 1563 st.r2 = pv_register (tdep->r2->num, 0); 1564 st.r3 = pv_register (tdep->r3->num, 0); 1565 st.a0 = pv_register (tdep->a0->num, 0); 1566 st.a1 = pv_register (tdep->a1->num, 0); 1567 st.sb = pv_register (tdep->sb->num, 0); 1568 st.fb = pv_register (tdep->fb->num, 0); 1569 st.sp = pv_register (tdep->sp->num, 0); 1570 st.pc = pv_register (tdep->pc->num, 0); 1571 st.stack = make_pv_area (tdep->sp->num, gdbarch_addr_bit (arch)); 1572 back_to = make_cleanup_free_pv_area (st.stack); 1573 1574 /* Record that the call instruction has saved the return address on 1575 the stack. */ 1576 m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); 1577 1578 memset (prologue, 0, sizeof (*prologue)); 1579 prologue->arch = arch; 1580 { 1581 int i; 1582 for (i = 0; i < M32C_MAX_NUM_REGS; i++) 1583 prologue->reg_offset[i] = 1; 1584 } 1585 1586 st.scan_pc = after_last_frame_related_insn = start; 1587 1588 while (st.scan_pc < limit) 1589 { 1590 pv_t pre_insn_fb = st.fb; 1591 pv_t pre_insn_sp = st.sp; 1592 1593 /* In theory we could get in trouble by trying to read ahead 1594 here, when we only know we're expecting one byte. In 1595 practice I doubt anyone will care, and it makes the rest of 1596 the code easier. */ 1597 if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) 1598 /* If we can't fetch the instruction from memory, stop here 1599 and hope for the best. */ 1600 break; 1601 st.next_addr = st.scan_pc; 1602 1603 /* The assembly instructions are written as they appear in the 1604 section of the processor manuals that describe the 1605 instruction encodings. 1606 1607 When a single assembly language instruction has several 1608 different machine-language encodings, the manual 1609 distinguishes them by a number in parens, before the 1610 mnemonic. Those numbers are included, as well. 1611 1612 The srcdest decoding instructions have the same names as the 1613 analogous functions in the simulator. */ 1614 if (mach == bfd_mach_m16c) 1615 { 1616 /* (1) ENTER #imm8 */ 1617 if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) 1618 { 1619 if (m32c_pv_enter (&st, st.insn[2])) 1620 break; 1621 st.next_addr += 3; 1622 } 1623 /* (1) PUSHM src */ 1624 else if (st.insn[0] == 0xec) 1625 { 1626 int src = st.insn[1]; 1627 if (m32c_pv_pushm (&st, src)) 1628 break; 1629 st.next_addr += 2; 1630 1631 if (m32c_pushm_is_reg_save (&st, src)) 1632 after_last_frame_related_insn = st.next_addr; 1633 } 1634 1635 /* (6) MOV.size:G src, dest */ 1636 else if ((st.insn[0] & 0xfe) == 0x72) 1637 { 1638 int size = (st.insn[0] & 0x01) ? 2 : 1; 1639 struct srcdest src; 1640 struct srcdest dest; 1641 pv_t src_value; 1642 st.next_addr += 2; 1643 1644 src 1645 = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); 1646 dest 1647 = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); 1648 src_value = m32c_srcdest_fetch (&st, src, size); 1649 1650 if (m32c_is_arg_spill (&st, dest, src_value)) 1651 after_last_frame_related_insn = st.next_addr; 1652 else if (m32c_is_struct_return (&st, dest, src_value)) 1653 after_last_frame_related_insn = st.next_addr; 1654 1655 if (m32c_srcdest_store (&st, dest, src_value, size)) 1656 break; 1657 } 1658 1659 /* (1) LDC #IMM16, sp */ 1660 else if (st.insn[0] == 0xeb 1661 && st.insn[1] == 0x50) 1662 { 1663 st.next_addr += 2; 1664 st.sp = pv_constant (m32c_udisp16 (&st)); 1665 } 1666 1667 else 1668 /* We've hit some instruction we don't know how to simulate. 1669 Strictly speaking, we should set every value we're 1670 tracking to "unknown". But we'll be optimistic, assume 1671 that we have enough information already, and stop 1672 analysis here. */ 1673 break; 1674 } 1675 else 1676 { 1677 int src_indirect = 0; 1678 int dest_indirect = 0; 1679 int i = 0; 1680 1681 gdb_assert (mach == bfd_mach_m32c); 1682 1683 /* Check for prefix bytes indicating indirect addressing. */ 1684 if (st.insn[0] == 0x41) 1685 { 1686 src_indirect = 1; 1687 i++; 1688 } 1689 else if (st.insn[0] == 0x09) 1690 { 1691 dest_indirect = 1; 1692 i++; 1693 } 1694 else if (st.insn[0] == 0x49) 1695 { 1696 src_indirect = dest_indirect = 1; 1697 i++; 1698 } 1699 1700 /* (1) ENTER #imm8 */ 1701 if (st.insn[i] == 0xec) 1702 { 1703 if (m32c_pv_enter (&st, st.insn[i + 1])) 1704 break; 1705 st.next_addr += 2; 1706 } 1707 1708 /* (1) PUSHM src */ 1709 else if (st.insn[i] == 0x8f) 1710 { 1711 int src = st.insn[i + 1]; 1712 if (m32c_pv_pushm (&st, src)) 1713 break; 1714 st.next_addr += 2; 1715 1716 if (m32c_pushm_is_reg_save (&st, src)) 1717 after_last_frame_related_insn = st.next_addr; 1718 } 1719 1720 /* (7) MOV.size:G src, dest */ 1721 else if ((st.insn[i] & 0x80) == 0x80 1722 && (st.insn[i + 1] & 0x0f) == 0x0b 1723 && m32c_get_src23 (&st.insn[i]) < 20 1724 && m32c_get_dest23 (&st.insn[i]) < 20) 1725 { 1726 struct srcdest src; 1727 struct srcdest dest; 1728 pv_t src_value; 1729 int bw = st.insn[i] & 0x01; 1730 int size = bw ? 2 : 1; 1731 st.next_addr += 2; 1732 1733 src 1734 = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), 1735 size, src_indirect); 1736 dest 1737 = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), 1738 size, dest_indirect); 1739 src_value = m32c_srcdest_fetch (&st, src, size); 1740 1741 if (m32c_is_arg_spill (&st, dest, src_value)) 1742 after_last_frame_related_insn = st.next_addr; 1743 1744 if (m32c_srcdest_store (&st, dest, src_value, size)) 1745 break; 1746 } 1747 /* (2) LDC #IMM24, sp */ 1748 else if (st.insn[i] == 0xd5 1749 && st.insn[i + 1] == 0x29) 1750 { 1751 st.next_addr += 2; 1752 st.sp = pv_constant (m32c_udisp24 (&st)); 1753 } 1754 else 1755 /* We've hit some instruction we don't know how to simulate. 1756 Strictly speaking, we should set every value we're 1757 tracking to "unknown". But we'll be optimistic, assume 1758 that we have enough information already, and stop 1759 analysis here. */ 1760 break; 1761 } 1762 1763 /* If this instruction changed the FB or decreased the SP (i.e., 1764 allocated more stack space), then this may be a good place to 1765 declare the prologue finished. However, there are some 1766 exceptions: 1767 1768 - If the instruction just changed the FB back to its original 1769 value, then that's probably a restore instruction. The 1770 prologue should definitely end before that. 1771 1772 - If the instruction increased the value of the SP (that is, 1773 shrunk the frame), then it's probably part of a frame 1774 teardown sequence, and the prologue should end before 1775 that. */ 1776 1777 if (! pv_is_identical (st.fb, pre_insn_fb)) 1778 { 1779 if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) 1780 after_last_frame_related_insn = st.next_addr; 1781 } 1782 else if (! pv_is_identical (st.sp, pre_insn_sp)) 1783 { 1784 /* The comparison of the constants looks odd, there, because 1785 .k is unsigned. All it really means is that the SP is 1786 lower than it was before the instruction. */ 1787 if ( pv_is_register (pre_insn_sp, tdep->sp->num) 1788 && pv_is_register (st.sp, tdep->sp->num) 1789 && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) 1790 after_last_frame_related_insn = st.next_addr; 1791 } 1792 1793 st.scan_pc = st.next_addr; 1794 } 1795 1796 /* Did we load a constant value into the stack pointer? */ 1797 if (pv_is_constant (st.sp)) 1798 prologue->kind = prologue_first_frame; 1799 1800 /* Alternatively, did we initialize the frame pointer? Remember 1801 that the CFA is the address after the return address. */ 1802 if (pv_is_register (st.fb, tdep->sp->num)) 1803 { 1804 prologue->kind = prologue_with_frame_ptr; 1805 prologue->frame_ptr_offset = st.fb.k; 1806 } 1807 1808 /* Is the frame size a known constant? Remember that frame_size is 1809 actually the offset from the CFA to the SP (i.e., a negative 1810 value). */ 1811 else if (pv_is_register (st.sp, tdep->sp->num)) 1812 { 1813 prologue->kind = prologue_sans_frame_ptr; 1814 prologue->frame_size = st.sp.k; 1815 } 1816 1817 /* We haven't been able to make sense of this function's frame. Treat 1818 it as the first frame. */ 1819 else 1820 prologue->kind = prologue_first_frame; 1821 1822 /* Record where all the registers were saved. */ 1823 pv_area_scan (st.stack, check_for_saved, (void *) prologue); 1824 1825 prologue->prologue_end = after_last_frame_related_insn; 1826 1827 do_cleanups (back_to); 1828 } 1829 1830 1831 static CORE_ADDR 1832 m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) 1833 { 1834 const char *name; 1835 CORE_ADDR func_addr, func_end, sal_end; 1836 struct m32c_prologue p; 1837 1838 /* Try to find the extent of the function that contains IP. */ 1839 if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) 1840 return ip; 1841 1842 /* Find end by prologue analysis. */ 1843 m32c_analyze_prologue (gdbarch, ip, func_end, &p); 1844 /* Find end by line info. */ 1845 sal_end = skip_prologue_using_sal (gdbarch, ip); 1846 /* Return whichever is lower. */ 1847 if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) 1848 return sal_end; 1849 else 1850 return p.prologue_end; 1851 } 1852 1853 1854 1855 /* Stack unwinding. */ 1856 1857 static struct m32c_prologue * 1858 m32c_analyze_frame_prologue (struct frame_info *this_frame, 1859 void **this_prologue_cache) 1860 { 1861 if (! *this_prologue_cache) 1862 { 1863 CORE_ADDR func_start = get_frame_func (this_frame); 1864 CORE_ADDR stop_addr = get_frame_pc (this_frame); 1865 1866 /* If we couldn't find any function containing the PC, then 1867 just initialize the prologue cache, but don't do anything. */ 1868 if (! func_start) 1869 stop_addr = func_start; 1870 1871 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); 1872 m32c_analyze_prologue (get_frame_arch (this_frame), 1873 func_start, stop_addr, *this_prologue_cache); 1874 } 1875 1876 return *this_prologue_cache; 1877 } 1878 1879 1880 static CORE_ADDR 1881 m32c_frame_base (struct frame_info *this_frame, 1882 void **this_prologue_cache) 1883 { 1884 struct m32c_prologue *p 1885 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); 1886 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 1887 1888 /* In functions that use alloca, the distance between the stack 1889 pointer and the frame base varies dynamically, so we can't use 1890 the SP plus static information like prologue analysis to find the 1891 frame base. However, such functions must have a frame pointer, 1892 to be able to restore the SP on exit. So whenever we do have a 1893 frame pointer, use that to find the base. */ 1894 switch (p->kind) 1895 { 1896 case prologue_with_frame_ptr: 1897 { 1898 CORE_ADDR fb 1899 = get_frame_register_unsigned (this_frame, tdep->fb->num); 1900 return fb - p->frame_ptr_offset; 1901 } 1902 1903 case prologue_sans_frame_ptr: 1904 { 1905 CORE_ADDR sp 1906 = get_frame_register_unsigned (this_frame, tdep->sp->num); 1907 return sp - p->frame_size; 1908 } 1909 1910 case prologue_first_frame: 1911 return 0; 1912 1913 default: 1914 gdb_assert_not_reached ("unexpected prologue kind"); 1915 } 1916 } 1917 1918 1919 static void 1920 m32c_this_id (struct frame_info *this_frame, 1921 void **this_prologue_cache, 1922 struct frame_id *this_id) 1923 { 1924 CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); 1925 1926 if (base) 1927 *this_id = frame_id_build (base, get_frame_func (this_frame)); 1928 /* Otherwise, leave it unset, and that will terminate the backtrace. */ 1929 } 1930 1931 1932 static struct value * 1933 m32c_prev_register (struct frame_info *this_frame, 1934 void **this_prologue_cache, int regnum) 1935 { 1936 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 1937 struct m32c_prologue *p 1938 = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); 1939 CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); 1940 int reg_size = register_size (get_frame_arch (this_frame), regnum); 1941 1942 if (regnum == tdep->sp->num) 1943 return frame_unwind_got_constant (this_frame, regnum, frame_base); 1944 1945 /* If prologue analysis says we saved this register somewhere, 1946 return a description of the stack slot holding it. */ 1947 if (p->reg_offset[regnum] != 1) 1948 return frame_unwind_got_memory (this_frame, regnum, 1949 frame_base + p->reg_offset[regnum]); 1950 1951 /* Otherwise, presume we haven't changed the value of this 1952 register, and get it from the next frame. */ 1953 return frame_unwind_got_register (this_frame, regnum, regnum); 1954 } 1955 1956 1957 static const struct frame_unwind m32c_unwind = { 1958 NORMAL_FRAME, 1959 default_frame_unwind_stop_reason, 1960 m32c_this_id, 1961 m32c_prev_register, 1962 NULL, 1963 default_frame_sniffer 1964 }; 1965 1966 1967 static CORE_ADDR 1968 m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame) 1969 { 1970 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1971 return frame_unwind_register_unsigned (next_frame, tdep->pc->num); 1972 } 1973 1974 1975 static CORE_ADDR 1976 m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame) 1977 { 1978 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1979 return frame_unwind_register_unsigned (next_frame, tdep->sp->num); 1980 } 1981 1982 1983 /* Inferior calls. */ 1984 1985 /* The calling conventions, according to GCC: 1986 1987 r8c, m16c 1988 --------- 1989 First arg may be passed in r1l or r1 if it (1) fits (QImode or 1990 HImode), (2) is named, and (3) is an integer or pointer type (no 1991 structs, floats, etc). Otherwise, it's passed on the stack. 1992 1993 Second arg may be passed in r2, same restrictions (but not QImode), 1994 even if the first arg is passed on the stack. 1995 1996 Third and further args are passed on the stack. No padding is 1997 used, stack "alignment" is 8 bits. 1998 1999 m32cm, m32c 2000 ----------- 2001 2002 First arg may be passed in r0l or r0, same restrictions as above. 2003 2004 Second and further args are passed on the stack. Padding is used 2005 after QImode parameters (i.e. lower-addressed byte is the value, 2006 higher-addressed byte is the padding), stack "alignment" is 16 2007 bits. */ 2008 2009 2010 /* Return true if TYPE is a type that can be passed in registers. (We 2011 ignore the size, and pay attention only to the type code; 2012 acceptable sizes depends on which register is being considered to 2013 hold it.) */ 2014 static int 2015 m32c_reg_arg_type (struct type *type) 2016 { 2017 enum type_code code = TYPE_CODE (type); 2018 2019 return (code == TYPE_CODE_INT 2020 || code == TYPE_CODE_ENUM 2021 || code == TYPE_CODE_PTR 2022 || code == TYPE_CODE_REF 2023 || code == TYPE_CODE_BOOL 2024 || code == TYPE_CODE_CHAR); 2025 } 2026 2027 2028 static CORE_ADDR 2029 m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2030 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2031 struct value **args, CORE_ADDR sp, int struct_return, 2032 CORE_ADDR struct_addr) 2033 { 2034 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2036 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 2037 CORE_ADDR cfa; 2038 int i; 2039 2040 /* The number of arguments given in this function's prototype, or 2041 zero if it has a non-prototyped function type. The m32c ABI 2042 passes arguments mentioned in the prototype differently from 2043 those in the ellipsis of a varargs function, or from those passed 2044 to a non-prototyped function. */ 2045 int num_prototyped_args = 0; 2046 2047 { 2048 struct type *func_type = value_type (function); 2049 2050 /* Dereference function pointer types. */ 2051 if (TYPE_CODE (func_type) == TYPE_CODE_PTR) 2052 func_type = TYPE_TARGET_TYPE (func_type); 2053 2054 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC || 2055 TYPE_CODE (func_type) == TYPE_CODE_METHOD); 2056 2057 #if 0 2058 /* The ABI description in gcc/config/m32c/m32c.abi says that 2059 we need to handle prototyped and non-prototyped functions 2060 separately, but the code in GCC doesn't actually do so. */ 2061 if (TYPE_PROTOTYPED (func_type)) 2062 #endif 2063 num_prototyped_args = TYPE_NFIELDS (func_type); 2064 } 2065 2066 /* First, if the function returns an aggregate by value, push a 2067 pointer to a buffer for it. This doesn't affect the way 2068 subsequent arguments are allocated to registers. */ 2069 if (struct_return) 2070 { 2071 int ptr_len = TYPE_LENGTH (tdep->ptr_voyd); 2072 sp -= ptr_len; 2073 write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); 2074 } 2075 2076 /* Push the arguments. */ 2077 for (i = nargs - 1; i >= 0; i--) 2078 { 2079 struct value *arg = args[i]; 2080 const gdb_byte *arg_bits = value_contents (arg); 2081 struct type *arg_type = value_type (arg); 2082 ULONGEST arg_size = TYPE_LENGTH (arg_type); 2083 2084 /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ 2085 if (i == 0 2086 && arg_size <= 2 2087 && i < num_prototyped_args 2088 && m32c_reg_arg_type (arg_type)) 2089 { 2090 /* Extract and re-store as an integer as a terse way to make 2091 sure it ends up in the least significant end of r1. (GDB 2092 should avoid assuming endianness, even on uni-endian 2093 processors.) */ 2094 ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, 2095 byte_order); 2096 struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; 2097 regcache_cooked_write_unsigned (regcache, reg->num, u); 2098 } 2099 2100 /* Can it go in r2? */ 2101 else if (mach == bfd_mach_m16c 2102 && i == 1 2103 && arg_size == 2 2104 && i < num_prototyped_args 2105 && m32c_reg_arg_type (arg_type)) 2106 regcache_cooked_write (regcache, tdep->r2->num, arg_bits); 2107 2108 /* Everything else goes on the stack. */ 2109 else 2110 { 2111 sp -= arg_size; 2112 2113 /* Align the stack. */ 2114 if (mach == bfd_mach_m32c) 2115 sp &= ~1; 2116 2117 write_memory (sp, arg_bits, arg_size); 2118 } 2119 } 2120 2121 /* This is the CFA we use to identify the dummy frame. */ 2122 cfa = sp; 2123 2124 /* Push the return address. */ 2125 sp -= tdep->ret_addr_bytes; 2126 write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, 2127 bp_addr); 2128 2129 /* Update the stack pointer. */ 2130 regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); 2131 2132 /* We need to borrow an odd trick from the i386 target here. 2133 2134 The value we return from this function gets used as the stack 2135 address (the CFA) for the dummy frame's ID. The obvious thing is 2136 to return the new TOS. However, that points at the return 2137 address, saved on the stack, which is inconsistent with the CFA's 2138 described by GCC's DWARF 2 .debug_frame information: DWARF 2 2139 .debug_frame info uses the address immediately after the saved 2140 return address. So you end up with a dummy frame whose CFA 2141 points at the return address, but the frame for the function 2142 being called has a CFA pointing after the return address: the 2143 younger CFA is *greater than* the older CFA. The sanity checks 2144 in frame.c don't like that. 2145 2146 So we try to be consistent with the CFA's used by DWARF 2. 2147 Having a dummy frame and a real frame with the *same* CFA is 2148 tolerable. */ 2149 return cfa; 2150 } 2151 2152 2153 static struct frame_id 2154 m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2155 { 2156 /* This needs to return a frame ID whose PC is the return address 2157 passed to m32c_push_dummy_call, and whose stack_addr is the SP 2158 m32c_push_dummy_call returned. 2159 2160 m32c_unwind_sp gives us the CFA, which is the value the SP had 2161 before the return address was pushed. */ 2162 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2163 CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num); 2164 return frame_id_build (sp, get_frame_pc (this_frame)); 2165 } 2166 2167 2168 2169 /* Return values. */ 2170 2171 /* Return value conventions, according to GCC: 2172 2173 r8c, m16c 2174 --------- 2175 2176 QImode in r0l 2177 HImode in r0 2178 SImode in r2r0 2179 near pointer in r0 2180 far pointer in r2r0 2181 2182 Aggregate values (regardless of size) are returned by pushing a 2183 pointer to a temporary area on the stack after the args are pushed. 2184 The function fills in this area with the value. Note that this 2185 pointer on the stack does not affect how register arguments, if any, 2186 are configured. 2187 2188 m32cm, m32c 2189 ----------- 2190 Same. */ 2191 2192 /* Return non-zero if values of type TYPE are returned by storing them 2193 in a buffer whose address is passed on the stack, ahead of the 2194 other arguments. */ 2195 static int 2196 m32c_return_by_passed_buf (struct type *type) 2197 { 2198 enum type_code code = TYPE_CODE (type); 2199 2200 return (code == TYPE_CODE_STRUCT 2201 || code == TYPE_CODE_UNION); 2202 } 2203 2204 static enum return_value_convention 2205 m32c_return_value (struct gdbarch *gdbarch, 2206 struct value *function, 2207 struct type *valtype, 2208 struct regcache *regcache, 2209 gdb_byte *readbuf, 2210 const gdb_byte *writebuf) 2211 { 2212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2213 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2214 enum return_value_convention conv; 2215 ULONGEST valtype_len = TYPE_LENGTH (valtype); 2216 2217 if (m32c_return_by_passed_buf (valtype)) 2218 conv = RETURN_VALUE_STRUCT_CONVENTION; 2219 else 2220 conv = RETURN_VALUE_REGISTER_CONVENTION; 2221 2222 if (readbuf) 2223 { 2224 /* We should never be called to find values being returned by 2225 RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, 2226 unless we made the call ourselves. */ 2227 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); 2228 2229 gdb_assert (valtype_len <= 8); 2230 2231 /* Anything that fits in r0 is returned there. */ 2232 if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) 2233 { 2234 ULONGEST u; 2235 regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); 2236 store_unsigned_integer (readbuf, valtype_len, byte_order, u); 2237 } 2238 else 2239 { 2240 /* Everything else is passed in mem0, using as many bytes as 2241 needed. This is not what the Renesas tools do, but it's 2242 what GCC does at the moment. */ 2243 struct minimal_symbol *mem0 2244 = lookup_minimal_symbol ("mem0", NULL, NULL); 2245 2246 if (! mem0) 2247 error (_("The return value is stored in memory at 'mem0', " 2248 "but GDB cannot find\n" 2249 "its address.")); 2250 read_memory (SYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len); 2251 } 2252 } 2253 2254 if (writebuf) 2255 { 2256 /* We should never be called to store values to be returned 2257 using RETURN_VALUE_STRUCT_CONVENTION. We have no way of 2258 finding the buffer, unless we made the call ourselves. */ 2259 gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); 2260 2261 gdb_assert (valtype_len <= 8); 2262 2263 /* Anything that fits in r0 is returned there. */ 2264 if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) 2265 { 2266 ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, 2267 byte_order); 2268 regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); 2269 } 2270 else 2271 { 2272 /* Everything else is passed in mem0, using as many bytes as 2273 needed. This is not what the Renesas tools do, but it's 2274 what GCC does at the moment. */ 2275 struct minimal_symbol *mem0 2276 = lookup_minimal_symbol ("mem0", NULL, NULL); 2277 2278 if (! mem0) 2279 error (_("The return value is stored in memory at 'mem0', " 2280 "but GDB cannot find\n" 2281 " its address.")); 2282 write_memory (SYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len); 2283 } 2284 } 2285 2286 return conv; 2287 } 2288 2289 2290 2291 /* Trampolines. */ 2292 2293 /* The m16c and m32c use a trampoline function for indirect function 2294 calls. An indirect call looks like this: 2295 2296 ... push arguments ... 2297 ... push target function address ... 2298 jsr.a m32c_jsri16 2299 2300 The code for m32c_jsri16 looks like this: 2301 2302 m32c_jsri16: 2303 2304 # Save return address. 2305 pop.w m32c_jsri_ret 2306 pop.b m32c_jsri_ret+2 2307 2308 # Store target function address. 2309 pop.w m32c_jsri_addr 2310 2311 # Re-push return address. 2312 push.b m32c_jsri_ret+2 2313 push.w m32c_jsri_ret 2314 2315 # Call the target function. 2316 jmpi.a m32c_jsri_addr 2317 2318 Without further information, GDB will treat calls to m32c_jsri16 2319 like calls to any other function. Since m32c_jsri16 doesn't have 2320 debugging information, that normally means that GDB sets a step- 2321 resume breakpoint and lets the program continue --- which is not 2322 what the user wanted. (Giving the trampoline debugging info 2323 doesn't help: the user expects the program to stop in the function 2324 their program is calling, not in some trampoline code they've never 2325 seen before.) 2326 2327 The gdbarch_skip_trampoline_code method tells GDB how to step 2328 through such trampoline functions transparently to the user. When 2329 given the address of a trampoline function's first instruction, 2330 gdbarch_skip_trampoline_code should return the address of the first 2331 instruction of the function really being called. If GDB decides it 2332 wants to step into that function, it will set a breakpoint there 2333 and silently continue to it. 2334 2335 We recognize the trampoline by name, and extract the target address 2336 directly from the stack. This isn't great, but recognizing by its 2337 code sequence seems more fragile. */ 2338 2339 static CORE_ADDR 2340 m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc) 2341 { 2342 struct gdbarch *gdbarch = get_frame_arch (frame); 2343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2344 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2345 2346 /* It would be nicer to simply look up the addresses of known 2347 trampolines once, and then compare stop_pc with them. However, 2348 we'd need to ensure that that cached address got invalidated when 2349 someone loaded a new executable, and I'm not quite sure of the 2350 best way to do that. find_pc_partial_function does do some 2351 caching, so we'll see how this goes. */ 2352 const char *name; 2353 CORE_ADDR start, end; 2354 2355 if (find_pc_partial_function (stop_pc, &name, &start, &end)) 2356 { 2357 /* Are we stopped at the beginning of the trampoline function? */ 2358 if (strcmp (name, "m32c_jsri16") == 0 2359 && stop_pc == start) 2360 { 2361 /* Get the stack pointer. The return address is at the top, 2362 and the target function's address is just below that. We 2363 know it's a two-byte address, since the trampoline is 2364 m32c_jsri*16*. */ 2365 CORE_ADDR sp = get_frame_sp (get_current_frame ()); 2366 CORE_ADDR target 2367 = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, 2368 2, byte_order); 2369 2370 /* What we have now is the address of a jump instruction. 2371 What we need is the destination of that jump. 2372 The opcode is 1 byte, and the destination is the next 3 bytes. */ 2373 2374 target = read_memory_unsigned_integer (target + 1, 3, byte_order); 2375 return target; 2376 } 2377 } 2378 2379 return 0; 2380 } 2381 2382 2383 /* Address/pointer conversions. */ 2384 2385 /* On the m16c, there is a 24-bit address space, but only a very few 2386 instructions can generate addresses larger than 0xffff: jumps, 2387 jumps to subroutines, and the lde/std (load/store extended) 2388 instructions. 2389 2390 Since GCC can only support one size of pointer, we can't have 2391 distinct 'near' and 'far' pointer types; we have to pick one size 2392 for everything. If we wanted to use 24-bit pointers, then GCC 2393 would have to use lde and ste for all memory references, which 2394 would be terrible for performance and code size. So the GNU 2395 toolchain uses 16-bit pointers for everything, and gives up the 2396 ability to have pointers point outside the first 64k of memory. 2397 2398 However, as a special hack, we let the linker place functions at 2399 addresses above 0xffff, as long as it also places a trampoline in 2400 the low 64k for every function whose address is taken. Each 2401 trampoline consists of a single jmp.a instruction that jumps to the 2402 function's real entry point. Pointers to functions can be 16 bits 2403 long, even though the functions themselves are at higher addresses: 2404 the pointers refer to the trampolines, not the functions. 2405 2406 This complicates things for GDB, however: given the address of a 2407 function (from debug info or linker symbols, say) which could be 2408 anywhere in the 24-bit address space, how can we find an 2409 appropriate 16-bit value to use as a pointer to it? 2410 2411 If the linker has not generated a trampoline for the function, 2412 we're out of luck. Well, I guess we could malloc some space and 2413 write a jmp.a instruction to it, but I'm not going to get into that 2414 at the moment. 2415 2416 If the linker has generated a trampoline for the function, then it 2417 also emitted a symbol for the trampoline: if the function's linker 2418 symbol is named NAME, then the function's trampoline's linker 2419 symbol is named NAME.plt. 2420 2421 So, given a code address: 2422 - We try to find a linker symbol at that address. 2423 - If we find such a symbol named NAME, we look for a linker symbol 2424 named NAME.plt. 2425 - If we find such a symbol, we assume it is a trampoline, and use 2426 its address as the pointer value. 2427 2428 And, given a function pointer: 2429 - We try to find a linker symbol at that address named NAME.plt. 2430 - If we find such a symbol, we look for a linker symbol named NAME. 2431 - If we find that, we provide that as the function's address. 2432 - If any of the above steps fail, we return the original address 2433 unchanged; it might really be a function in the low 64k. 2434 2435 See? You *knew* there was a reason you wanted to be a computer 2436 programmer! :) */ 2437 2438 static void 2439 m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, 2440 struct type *type, gdb_byte *buf, CORE_ADDR addr) 2441 { 2442 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2443 enum type_code target_code; 2444 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || 2445 TYPE_CODE (type) == TYPE_CODE_REF); 2446 2447 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); 2448 2449 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) 2450 { 2451 const char *func_name; 2452 char *tramp_name; 2453 struct minimal_symbol *tramp_msym; 2454 2455 /* Try to find a linker symbol at this address. */ 2456 struct bound_minimal_symbol func_msym 2457 = lookup_minimal_symbol_by_pc (addr); 2458 2459 if (! func_msym.minsym) 2460 error (_("Cannot convert code address %s to function pointer:\n" 2461 "couldn't find a symbol at that address, to find trampoline."), 2462 paddress (gdbarch, addr)); 2463 2464 func_name = SYMBOL_LINKAGE_NAME (func_msym.minsym); 2465 tramp_name = xmalloc (strlen (func_name) + 5); 2466 strcpy (tramp_name, func_name); 2467 strcat (tramp_name, ".plt"); 2468 2469 /* Try to find a linker symbol for the trampoline. */ 2470 tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); 2471 2472 /* We've either got another copy of the name now, or don't need 2473 the name any more. */ 2474 xfree (tramp_name); 2475 2476 if (! tramp_msym) 2477 { 2478 CORE_ADDR ptrval; 2479 2480 /* No PLT entry found. Mask off the upper bits of the address 2481 to make a pointer. As noted in the warning to the user 2482 below, this value might be useful if converted back into 2483 an address by GDB, but will otherwise, almost certainly, 2484 be garbage. 2485 2486 Using this masked result does seem to be useful 2487 in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into 2488 PASSes. These results appear to be correct as well. 2489 2490 We print a warning here so that the user can make a 2491 determination about whether the result is useful or not. */ 2492 ptrval = addr & 0xffff; 2493 2494 warning (_("Cannot convert code address %s to function pointer:\n" 2495 "couldn't find trampoline named '%s.plt'.\n" 2496 "Returning pointer value %s instead; this may produce\n" 2497 "a useful result if converted back into an address by GDB,\n" 2498 "but will most likely not be useful otherwise.\n"), 2499 paddress (gdbarch, addr), func_name, 2500 paddress (gdbarch, ptrval)); 2501 2502 addr = ptrval; 2503 2504 } 2505 else 2506 { 2507 /* The trampoline's address is our pointer. */ 2508 addr = SYMBOL_VALUE_ADDRESS (tramp_msym); 2509 } 2510 } 2511 2512 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr); 2513 } 2514 2515 2516 static CORE_ADDR 2517 m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, 2518 struct type *type, const gdb_byte *buf) 2519 { 2520 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2521 CORE_ADDR ptr; 2522 enum type_code target_code; 2523 2524 gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || 2525 TYPE_CODE (type) == TYPE_CODE_REF); 2526 2527 ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); 2528 2529 target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); 2530 2531 if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) 2532 { 2533 /* See if there is a minimal symbol at that address whose name is 2534 "NAME.plt". */ 2535 struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr); 2536 2537 if (ptr_msym.minsym) 2538 { 2539 const char *ptr_msym_name = SYMBOL_LINKAGE_NAME (ptr_msym.minsym); 2540 int len = strlen (ptr_msym_name); 2541 2542 if (len > 4 2543 && strcmp (ptr_msym_name + len - 4, ".plt") == 0) 2544 { 2545 struct minimal_symbol *func_msym; 2546 /* We have a .plt symbol; try to find the symbol for the 2547 corresponding function. 2548 2549 Since the trampoline contains a jump instruction, we 2550 could also just extract the jump's target address. I 2551 don't see much advantage one way or the other. */ 2552 char *func_name = xmalloc (len - 4 + 1); 2553 memcpy (func_name, ptr_msym_name, len - 4); 2554 func_name[len - 4] = '\0'; 2555 func_msym 2556 = lookup_minimal_symbol (func_name, NULL, NULL); 2557 2558 /* If we do have such a symbol, return its value as the 2559 function's true address. */ 2560 if (func_msym) 2561 ptr = SYMBOL_VALUE_ADDRESS (func_msym); 2562 } 2563 } 2564 else 2565 { 2566 int aspace; 2567 2568 for (aspace = 1; aspace <= 15; aspace++) 2569 { 2570 ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); 2571 2572 if (ptr_msym.minsym) 2573 ptr |= aspace << 16; 2574 } 2575 } 2576 } 2577 2578 return ptr; 2579 } 2580 2581 static void 2582 m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, 2583 int *frame_regnum, 2584 LONGEST *frame_offset) 2585 { 2586 const char *name; 2587 CORE_ADDR func_addr, func_end; 2588 struct m32c_prologue p; 2589 2590 struct regcache *regcache = get_current_regcache (); 2591 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2592 2593 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) 2594 internal_error (__FILE__, __LINE__, 2595 _("No virtual frame pointer available")); 2596 2597 m32c_analyze_prologue (gdbarch, func_addr, pc, &p); 2598 switch (p.kind) 2599 { 2600 case prologue_with_frame_ptr: 2601 *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; 2602 *frame_offset = p.frame_ptr_offset; 2603 break; 2604 case prologue_sans_frame_ptr: 2605 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; 2606 *frame_offset = p.frame_size; 2607 break; 2608 default: 2609 *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; 2610 *frame_offset = 0; 2611 break; 2612 } 2613 /* Sanity check */ 2614 if (*frame_regnum > gdbarch_num_regs (gdbarch)) 2615 internal_error (__FILE__, __LINE__, 2616 _("No virtual frame pointer available")); 2617 } 2618 2619 2620 /* Initialization. */ 2621 2622 static struct gdbarch * 2623 m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2624 { 2625 struct gdbarch *arch; 2626 struct gdbarch_tdep *tdep; 2627 unsigned long mach = info.bfd_arch_info->mach; 2628 2629 /* Find a candidate among the list of architectures we've created 2630 already. */ 2631 for (arches = gdbarch_list_lookup_by_info (arches, &info); 2632 arches != NULL; 2633 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2634 return arches->gdbarch; 2635 2636 tdep = xcalloc (1, sizeof (*tdep)); 2637 arch = gdbarch_alloc (&info, tdep); 2638 2639 /* Essential types. */ 2640 make_types (arch); 2641 2642 /* Address/pointer conversions. */ 2643 if (mach == bfd_mach_m16c) 2644 { 2645 set_gdbarch_address_to_pointer (arch, m32c_m16c_address_to_pointer); 2646 set_gdbarch_pointer_to_address (arch, m32c_m16c_pointer_to_address); 2647 } 2648 2649 /* Register set. */ 2650 make_regs (arch); 2651 2652 /* Disassembly. */ 2653 set_gdbarch_print_insn (arch, print_insn_m32c); 2654 2655 /* Breakpoints. */ 2656 set_gdbarch_breakpoint_from_pc (arch, m32c_breakpoint_from_pc); 2657 2658 /* Prologue analysis and unwinding. */ 2659 set_gdbarch_inner_than (arch, core_addr_lessthan); 2660 set_gdbarch_skip_prologue (arch, m32c_skip_prologue); 2661 set_gdbarch_unwind_pc (arch, m32c_unwind_pc); 2662 set_gdbarch_unwind_sp (arch, m32c_unwind_sp); 2663 #if 0 2664 /* I'm dropping the dwarf2 sniffer because it has a few problems. 2665 They may be in the dwarf2 cfi code in GDB, or they may be in 2666 the debug info emitted by the upstream toolchain. I don't 2667 know which, but I do know that the prologue analyzer works better. 2668 MVS 04/13/06 */ 2669 dwarf2_append_sniffers (arch); 2670 #endif 2671 frame_unwind_append_unwinder (arch, &m32c_unwind); 2672 2673 /* Inferior calls. */ 2674 set_gdbarch_push_dummy_call (arch, m32c_push_dummy_call); 2675 set_gdbarch_return_value (arch, m32c_return_value); 2676 set_gdbarch_dummy_id (arch, m32c_dummy_id); 2677 2678 /* Trampolines. */ 2679 set_gdbarch_skip_trampoline_code (arch, m32c_skip_trampoline_code); 2680 2681 set_gdbarch_virtual_frame_pointer (arch, m32c_virtual_frame_pointer); 2682 2683 /* m32c function boundary addresses are not necessarily even. 2684 Therefore, the `vbit', which indicates a pointer to a virtual 2685 member function, is stored in the delta field, rather than as 2686 the low bit of a function pointer address. 2687 2688 In order to verify this, see the definition of 2689 TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the 2690 definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ 2691 set_gdbarch_vbit_in_delta (arch, 1); 2692 2693 return arch; 2694 } 2695 2696 /* Provide a prototype to silence -Wmissing-prototypes. */ 2697 extern initialize_file_ftype _initialize_m32c_tdep; 2698 2699 void 2700 _initialize_m32c_tdep (void) 2701 { 2702 register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init); 2703 2704 m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); 2705 } 2706