1 /* Functions specific to running gdb native on IA-64 running 2 GNU/Linux. 3 4 Copyright (C) 1999-2017 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "defs.h" 22 #include "inferior.h" 23 #include "target.h" 24 #include "gdbcore.h" 25 #include "regcache.h" 26 #include "ia64-tdep.h" 27 #include "linux-nat.h" 28 29 #include <signal.h> 30 #include "nat/gdb_ptrace.h" 31 #include "gdb_wait.h" 32 #ifdef HAVE_SYS_REG_H 33 #include <sys/reg.h> 34 #endif 35 #include <sys/syscall.h> 36 #include <sys/user.h> 37 38 #include <asm/ptrace_offsets.h> 39 #include <sys/procfs.h> 40 41 /* Prototypes for supply_gregset etc. */ 42 #include "gregset.h" 43 44 #include "inf-ptrace.h" 45 46 /* These must match the order of the register names. 47 48 Some sort of lookup table is needed because the offsets associated 49 with the registers are all over the board. */ 50 51 static int u_offsets[] = 52 { 53 /* general registers */ 54 -1, /* gr0 not available; i.e, it's always zero. */ 55 PT_R1, 56 PT_R2, 57 PT_R3, 58 PT_R4, 59 PT_R5, 60 PT_R6, 61 PT_R7, 62 PT_R8, 63 PT_R9, 64 PT_R10, 65 PT_R11, 66 PT_R12, 67 PT_R13, 68 PT_R14, 69 PT_R15, 70 PT_R16, 71 PT_R17, 72 PT_R18, 73 PT_R19, 74 PT_R20, 75 PT_R21, 76 PT_R22, 77 PT_R23, 78 PT_R24, 79 PT_R25, 80 PT_R26, 81 PT_R27, 82 PT_R28, 83 PT_R29, 84 PT_R30, 85 PT_R31, 86 /* gr32 through gr127 not directly available via the ptrace interface. */ 87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 93 /* Floating point registers */ 94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */ 95 PT_F2, 96 PT_F3, 97 PT_F4, 98 PT_F5, 99 PT_F6, 100 PT_F7, 101 PT_F8, 102 PT_F9, 103 PT_F10, 104 PT_F11, 105 PT_F12, 106 PT_F13, 107 PT_F14, 108 PT_F15, 109 PT_F16, 110 PT_F17, 111 PT_F18, 112 PT_F19, 113 PT_F20, 114 PT_F21, 115 PT_F22, 116 PT_F23, 117 PT_F24, 118 PT_F25, 119 PT_F26, 120 PT_F27, 121 PT_F28, 122 PT_F29, 123 PT_F30, 124 PT_F31, 125 PT_F32, 126 PT_F33, 127 PT_F34, 128 PT_F35, 129 PT_F36, 130 PT_F37, 131 PT_F38, 132 PT_F39, 133 PT_F40, 134 PT_F41, 135 PT_F42, 136 PT_F43, 137 PT_F44, 138 PT_F45, 139 PT_F46, 140 PT_F47, 141 PT_F48, 142 PT_F49, 143 PT_F50, 144 PT_F51, 145 PT_F52, 146 PT_F53, 147 PT_F54, 148 PT_F55, 149 PT_F56, 150 PT_F57, 151 PT_F58, 152 PT_F59, 153 PT_F60, 154 PT_F61, 155 PT_F62, 156 PT_F63, 157 PT_F64, 158 PT_F65, 159 PT_F66, 160 PT_F67, 161 PT_F68, 162 PT_F69, 163 PT_F70, 164 PT_F71, 165 PT_F72, 166 PT_F73, 167 PT_F74, 168 PT_F75, 169 PT_F76, 170 PT_F77, 171 PT_F78, 172 PT_F79, 173 PT_F80, 174 PT_F81, 175 PT_F82, 176 PT_F83, 177 PT_F84, 178 PT_F85, 179 PT_F86, 180 PT_F87, 181 PT_F88, 182 PT_F89, 183 PT_F90, 184 PT_F91, 185 PT_F92, 186 PT_F93, 187 PT_F94, 188 PT_F95, 189 PT_F96, 190 PT_F97, 191 PT_F98, 192 PT_F99, 193 PT_F100, 194 PT_F101, 195 PT_F102, 196 PT_F103, 197 PT_F104, 198 PT_F105, 199 PT_F106, 200 PT_F107, 201 PT_F108, 202 PT_F109, 203 PT_F110, 204 PT_F111, 205 PT_F112, 206 PT_F113, 207 PT_F114, 208 PT_F115, 209 PT_F116, 210 PT_F117, 211 PT_F118, 212 PT_F119, 213 PT_F120, 214 PT_F121, 215 PT_F122, 216 PT_F123, 217 PT_F124, 218 PT_F125, 219 PT_F126, 220 PT_F127, 221 /* Predicate registers - we don't fetch these individually. */ 222 -1, -1, -1, -1, -1, -1, -1, -1, 223 -1, -1, -1, -1, -1, -1, -1, -1, 224 -1, -1, -1, -1, -1, -1, -1, -1, 225 -1, -1, -1, -1, -1, -1, -1, -1, 226 -1, -1, -1, -1, -1, -1, -1, -1, 227 -1, -1, -1, -1, -1, -1, -1, -1, 228 -1, -1, -1, -1, -1, -1, -1, -1, 229 -1, -1, -1, -1, -1, -1, -1, -1, 230 /* branch registers */ 231 PT_B0, 232 PT_B1, 233 PT_B2, 234 PT_B3, 235 PT_B4, 236 PT_B5, 237 PT_B6, 238 PT_B7, 239 /* Virtual frame pointer and virtual return address pointer. */ 240 -1, -1, 241 /* other registers */ 242 PT_PR, 243 PT_CR_IIP, /* ip */ 244 PT_CR_IPSR, /* psr */ 245 PT_CFM, /* cfm */ 246 /* kernel registers not visible via ptrace interface (?) */ 247 -1, -1, -1, -1, -1, -1, -1, -1, 248 /* hole */ 249 -1, -1, -1, -1, -1, -1, -1, -1, 250 PT_AR_RSC, 251 PT_AR_BSP, 252 PT_AR_BSPSTORE, 253 PT_AR_RNAT, 254 -1, 255 -1, /* Not available: FCR, IA32 floating control register. */ 256 -1, -1, 257 -1, /* Not available: EFLAG */ 258 -1, /* Not available: CSD */ 259 -1, /* Not available: SSD */ 260 -1, /* Not available: CFLG */ 261 -1, /* Not available: FSR */ 262 -1, /* Not available: FIR */ 263 -1, /* Not available: FDR */ 264 -1, 265 PT_AR_CCV, 266 -1, -1, -1, 267 PT_AR_UNAT, 268 -1, -1, -1, 269 PT_AR_FPSR, 270 -1, -1, -1, 271 -1, /* Not available: ITC */ 272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 273 -1, -1, -1, -1, -1, -1, -1, -1, -1, 274 PT_AR_PFS, 275 PT_AR_LC, 276 PT_AR_EC, 277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 283 -1, 284 /* nat bits - not fetched directly; instead we obtain these bits from 285 either rnat or unat or from memory. */ 286 -1, -1, -1, -1, -1, -1, -1, -1, 287 -1, -1, -1, -1, -1, -1, -1, -1, 288 -1, -1, -1, -1, -1, -1, -1, -1, 289 -1, -1, -1, -1, -1, -1, -1, -1, 290 -1, -1, -1, -1, -1, -1, -1, -1, 291 -1, -1, -1, -1, -1, -1, -1, -1, 292 -1, -1, -1, -1, -1, -1, -1, -1, 293 -1, -1, -1, -1, -1, -1, -1, -1, 294 -1, -1, -1, -1, -1, -1, -1, -1, 295 -1, -1, -1, -1, -1, -1, -1, -1, 296 -1, -1, -1, -1, -1, -1, -1, -1, 297 -1, -1, -1, -1, -1, -1, -1, -1, 298 -1, -1, -1, -1, -1, -1, -1, -1, 299 -1, -1, -1, -1, -1, -1, -1, -1, 300 -1, -1, -1, -1, -1, -1, -1, -1, 301 -1, -1, -1, -1, -1, -1, -1, -1, 302 }; 303 304 static CORE_ADDR 305 ia64_register_addr (struct gdbarch *gdbarch, int regno) 306 { 307 CORE_ADDR addr; 308 309 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) 310 error (_("Invalid register number %d."), regno); 311 312 if (u_offsets[regno] == -1) 313 addr = 0; 314 else 315 addr = (CORE_ADDR) u_offsets[regno]; 316 317 return addr; 318 } 319 320 static int 321 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno) 322 { 323 return regno < 0 324 || regno >= gdbarch_num_regs (gdbarch) 325 || u_offsets[regno] == -1; 326 } 327 328 static int 329 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno) 330 { 331 /* Rationale behind not permitting stores to bspstore... 332 333 The IA-64 architecture provides bspstore and bsp which refer 334 memory locations in the RSE's backing store. bspstore is the 335 next location which will be written when the RSE needs to write 336 to memory. bsp is the address at which r32 in the current frame 337 would be found if it were written to the backing store. 338 339 The IA-64 architecture provides read-only access to bsp and 340 read/write access to bspstore (but only when the RSE is in 341 the enforced lazy mode). It should be noted that stores 342 to bspstore also affect the value of bsp. Changing bspstore 343 does not affect the number of dirty entries between bspstore 344 and bsp, so changing bspstore by N words will also cause bsp 345 to be changed by (roughly) N as well. (It could be N-1 or N+1 346 depending upon where the NaT collection bits fall.) 347 348 OTOH, the Linux kernel provides read/write access to bsp (and 349 currently read/write access to bspstore as well). But it 350 is definitely the case that if you change one, the other 351 will change at the same time. It is more useful to gdb to 352 be able to change bsp. So in order to prevent strange and 353 undesirable things from happening when a dummy stack frame 354 is popped (after calling an inferior function), we allow 355 bspstore to be read, but not written. (Note that popping 356 a (generic) dummy stack frame causes all registers that 357 were previously read from the inferior process to be written 358 back.) */ 359 360 return regno < 0 361 || regno >= gdbarch_num_regs (gdbarch) 362 || u_offsets[regno] == -1 363 || regno == IA64_BSPSTORE_REGNUM; 364 } 365 366 void 367 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp) 368 { 369 int regi; 370 const greg_t *regp = (const greg_t *) gregsetp; 371 372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 373 { 374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM)); 375 } 376 377 /* FIXME: NAT collection bits are at index 32; gotta deal with these 378 somehow... */ 379 380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33); 381 382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 383 { 384 regcache_raw_supply (regcache, regi, 385 regp + 34 + (regi - IA64_BR0_REGNUM)); 386 } 387 388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42); 389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43); 390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44); 391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45); 392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46); 393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47); 394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48); 395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49); 396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50); 397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51); 398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52); 399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53); 400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54); 401 } 402 403 void 404 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno) 405 { 406 int regi; 407 greg_t *regp = (greg_t *) gregsetp; 408 409 #define COPY_REG(_idx_,_regi_) \ 410 if ((regno == -1) || regno == _regi_) \ 411 regcache_raw_collect (regcache, _regi_, regp + _idx_) 412 413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 414 { 415 COPY_REG (regi - IA64_GR0_REGNUM, regi); 416 } 417 418 /* FIXME: NAT collection bits at index 32? */ 419 420 COPY_REG (33, IA64_PR_REGNUM); 421 422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 423 { 424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); 425 } 426 427 COPY_REG (42, IA64_IP_REGNUM); 428 COPY_REG (43, IA64_CFM_REGNUM); 429 COPY_REG (44, IA64_PSR_REGNUM); 430 COPY_REG (45, IA64_RSC_REGNUM); 431 COPY_REG (46, IA64_BSP_REGNUM); 432 COPY_REG (47, IA64_BSPSTORE_REGNUM); 433 COPY_REG (48, IA64_RNAT_REGNUM); 434 COPY_REG (49, IA64_CCV_REGNUM); 435 COPY_REG (50, IA64_UNAT_REGNUM); 436 COPY_REG (51, IA64_FPSR_REGNUM); 437 COPY_REG (52, IA64_PFS_REGNUM); 438 COPY_REG (53, IA64_LC_REGNUM); 439 COPY_REG (54, IA64_EC_REGNUM); 440 } 441 442 /* Given a pointer to a floating point register set in /proc format 443 (fpregset_t *), unpack the register contents and supply them as gdb's 444 idea of the current floating point register values. */ 445 446 void 447 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp) 448 { 449 int regi; 450 const char *from; 451 const gdb_byte f_zero[16] = { 0 }; 452 const gdb_byte f_one[16] = 453 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; 454 455 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs 456 did the same. So ignore whatever might be recorded in fpregset_t 457 for fr0/fr1 and always supply their expected values. */ 458 459 /* fr0 is always read as zero. */ 460 regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero); 461 /* fr1 is always read as one (1.0). */ 462 regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one); 463 464 for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 465 { 466 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); 467 regcache_raw_supply (regcache, regi, from); 468 } 469 } 470 471 /* Given a pointer to a floating point register set in /proc format 472 (fpregset_t *), update the register specified by REGNO from gdb's idea 473 of the current floating point register set. If REGNO is -1, update 474 them all. */ 475 476 void 477 fill_fpregset (const struct regcache *regcache, 478 fpregset_t *fpregsetp, int regno) 479 { 480 int regi; 481 482 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 483 { 484 if ((regno == -1) || (regno == regi)) 485 regcache_raw_collect (regcache, regi, 486 &((*fpregsetp)[regi - IA64_FR0_REGNUM])); 487 } 488 } 489 490 #define IA64_PSR_DB (1UL << 24) 491 #define IA64_PSR_DD (1UL << 39) 492 493 static void 494 enable_watchpoints_in_psr (ptid_t ptid) 495 { 496 struct regcache *regcache = get_thread_regcache (ptid); 497 ULONGEST psr; 498 499 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 500 if (!(psr & IA64_PSR_DB)) 501 { 502 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware 503 watchpoints and breakpoints. */ 504 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 505 } 506 } 507 508 static long debug_registers[8]; 509 510 static void 511 store_debug_register (ptid_t ptid, int idx, long val) 512 { 513 int tid; 514 515 tid = ptid_get_lwp (ptid); 516 if (tid == 0) 517 tid = ptid_get_pid (ptid); 518 519 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val); 520 } 521 522 static void 523 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, 524 long *dbr_mask) 525 { 526 if (dbr_addr) 527 store_debug_register (ptid, 2 * idx, *dbr_addr); 528 if (dbr_mask) 529 store_debug_register (ptid, 2 * idx + 1, *dbr_mask); 530 } 531 532 static int 533 is_power_of_2 (int val) 534 { 535 int i, onecount; 536 537 onecount = 0; 538 for (i = 0; i < 8 * sizeof (val); i++) 539 if (val & (1 << i)) 540 onecount++; 541 542 return onecount <= 1; 543 } 544 545 static int 546 ia64_linux_insert_watchpoint (struct target_ops *self, 547 CORE_ADDR addr, int len, 548 enum target_hw_bp_type type, 549 struct expression *cond) 550 { 551 struct lwp_info *lp; 552 int idx; 553 long dbr_addr, dbr_mask; 554 int max_watchpoints = 4; 555 556 if (len <= 0 || !is_power_of_2 (len)) 557 return -1; 558 559 for (idx = 0; idx < max_watchpoints; idx++) 560 { 561 dbr_mask = debug_registers[idx * 2 + 1]; 562 if ((dbr_mask & (0x3UL << 62)) == 0) 563 { 564 /* Exit loop if both r and w bits clear. */ 565 break; 566 } 567 } 568 569 if (idx == max_watchpoints) 570 return -1; 571 572 dbr_addr = (long) addr; 573 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ 574 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ 575 switch (type) 576 { 577 case hw_write: 578 dbr_mask |= (1L << 62); /* Set w bit */ 579 break; 580 case hw_read: 581 dbr_mask |= (1L << 63); /* Set r bit */ 582 break; 583 case hw_access: 584 dbr_mask |= (3L << 62); /* Set both r and w bits */ 585 break; 586 default: 587 return -1; 588 } 589 590 debug_registers[2 * idx] = dbr_addr; 591 debug_registers[2 * idx + 1] = dbr_mask; 592 ALL_LWPS (lp) 593 { 594 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); 595 enable_watchpoints_in_psr (lp->ptid); 596 } 597 598 return 0; 599 } 600 601 static int 602 ia64_linux_remove_watchpoint (struct target_ops *self, 603 CORE_ADDR addr, int len, 604 enum target_hw_bp_type type, 605 struct expression *cond) 606 { 607 int idx; 608 long dbr_addr, dbr_mask; 609 int max_watchpoints = 4; 610 611 if (len <= 0 || !is_power_of_2 (len)) 612 return -1; 613 614 for (idx = 0; idx < max_watchpoints; idx++) 615 { 616 dbr_addr = debug_registers[2 * idx]; 617 dbr_mask = debug_registers[2 * idx + 1]; 618 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) 619 { 620 struct lwp_info *lp; 621 622 debug_registers[2 * idx] = 0; 623 debug_registers[2 * idx + 1] = 0; 624 dbr_addr = 0; 625 dbr_mask = 0; 626 627 ALL_LWPS (lp) 628 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); 629 630 return 0; 631 } 632 } 633 return -1; 634 } 635 636 static void 637 ia64_linux_new_thread (struct lwp_info *lp) 638 { 639 int i, any; 640 641 any = 0; 642 for (i = 0; i < 8; i++) 643 { 644 if (debug_registers[i] != 0) 645 any = 1; 646 store_debug_register (lp->ptid, i, debug_registers[i]); 647 } 648 649 if (any) 650 enable_watchpoints_in_psr (lp->ptid); 651 } 652 653 static int 654 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 655 { 656 CORE_ADDR psr; 657 siginfo_t siginfo; 658 struct regcache *regcache = get_current_regcache (); 659 660 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) 661 return 0; 662 663 if (siginfo.si_signo != SIGTRAP 664 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) 665 return 0; 666 667 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 668 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint 669 for the next instruction. */ 670 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 671 672 *addr_p = (CORE_ADDR) siginfo.si_addr; 673 return 1; 674 } 675 676 static int 677 ia64_linux_stopped_by_watchpoint (struct target_ops *ops) 678 { 679 CORE_ADDR addr; 680 return ia64_linux_stopped_data_address (ops, &addr); 681 } 682 683 static int 684 ia64_linux_can_use_hw_breakpoint (struct target_ops *self, 685 enum bptype type, 686 int cnt, int othertype) 687 { 688 return 1; 689 } 690 691 692 /* Fetch register REGNUM from the inferior. */ 693 694 static void 695 ia64_linux_fetch_register (struct regcache *regcache, int regnum) 696 { 697 struct gdbarch *gdbarch = get_regcache_arch (regcache); 698 CORE_ADDR addr; 699 size_t size; 700 PTRACE_TYPE_RET *buf; 701 pid_t pid; 702 int i; 703 704 /* r0 cannot be fetched but is always zero. */ 705 if (regnum == IA64_GR0_REGNUM) 706 { 707 const gdb_byte zero[8] = { 0 }; 708 709 gdb_assert (sizeof (zero) == register_size (gdbarch, regnum)); 710 regcache_raw_supply (regcache, regnum, zero); 711 return; 712 } 713 714 /* fr0 cannot be fetched but is always zero. */ 715 if (regnum == IA64_FR0_REGNUM) 716 { 717 const gdb_byte f_zero[16] = { 0 }; 718 719 gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum)); 720 regcache_raw_supply (regcache, regnum, f_zero); 721 return; 722 } 723 724 /* fr1 cannot be fetched but is always one (1.0). */ 725 if (regnum == IA64_FR1_REGNUM) 726 { 727 const gdb_byte f_one[16] = 728 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; 729 730 gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum)); 731 regcache_raw_supply (regcache, regnum, f_one); 732 return; 733 } 734 735 if (ia64_cannot_fetch_register (gdbarch, regnum)) 736 { 737 regcache_raw_supply (regcache, regnum, NULL); 738 return; 739 } 740 741 pid = get_ptrace_pid (regcache_get_ptid (regcache)); 742 743 /* This isn't really an address, but ptrace thinks of it as one. */ 744 addr = ia64_register_addr (gdbarch, regnum); 745 size = register_size (gdbarch, regnum); 746 747 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 748 buf = (PTRACE_TYPE_RET *) alloca (size); 749 750 /* Read the register contents from the inferior a chunk at a time. */ 751 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 752 { 753 errno = 0; 754 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0); 755 if (errno != 0) 756 error (_("Couldn't read register %s (#%d): %s."), 757 gdbarch_register_name (gdbarch, regnum), 758 regnum, safe_strerror (errno)); 759 760 addr += sizeof (PTRACE_TYPE_RET); 761 } 762 regcache_raw_supply (regcache, regnum, buf); 763 } 764 765 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this 766 for all registers. */ 767 768 static void 769 ia64_linux_fetch_registers (struct target_ops *ops, 770 struct regcache *regcache, int regnum) 771 { 772 if (regnum == -1) 773 for (regnum = 0; 774 regnum < gdbarch_num_regs (get_regcache_arch (regcache)); 775 regnum++) 776 ia64_linux_fetch_register (regcache, regnum); 777 else 778 ia64_linux_fetch_register (regcache, regnum); 779 } 780 781 /* Store register REGNUM into the inferior. */ 782 783 static void 784 ia64_linux_store_register (const struct regcache *regcache, int regnum) 785 { 786 struct gdbarch *gdbarch = get_regcache_arch (regcache); 787 CORE_ADDR addr; 788 size_t size; 789 PTRACE_TYPE_RET *buf; 790 pid_t pid; 791 int i; 792 793 if (ia64_cannot_store_register (gdbarch, regnum)) 794 return; 795 796 pid = get_ptrace_pid (regcache_get_ptid (regcache)); 797 798 /* This isn't really an address, but ptrace thinks of it as one. */ 799 addr = ia64_register_addr (gdbarch, regnum); 800 size = register_size (gdbarch, regnum); 801 802 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 803 buf = (PTRACE_TYPE_RET *) alloca (size); 804 805 /* Write the register contents into the inferior a chunk at a time. */ 806 regcache_raw_collect (regcache, regnum, buf); 807 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 808 { 809 errno = 0; 810 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); 811 if (errno != 0) 812 error (_("Couldn't write register %s (#%d): %s."), 813 gdbarch_register_name (gdbarch, regnum), 814 regnum, safe_strerror (errno)); 815 816 addr += sizeof (PTRACE_TYPE_RET); 817 } 818 } 819 820 /* Store register REGNUM back into the inferior. If REGNUM is -1, do 821 this for all registers. */ 822 823 static void 824 ia64_linux_store_registers (struct target_ops *ops, 825 struct regcache *regcache, int regnum) 826 { 827 if (regnum == -1) 828 for (regnum = 0; 829 regnum < gdbarch_num_regs (get_regcache_arch (regcache)); 830 regnum++) 831 ia64_linux_store_register (regcache, regnum); 832 else 833 ia64_linux_store_register (regcache, regnum); 834 } 835 836 837 static target_xfer_partial_ftype *super_xfer_partial; 838 839 /* Implement the to_xfer_partial target_ops method. */ 840 841 static enum target_xfer_status 842 ia64_linux_xfer_partial (struct target_ops *ops, 843 enum target_object object, 844 const char *annex, 845 gdb_byte *readbuf, const gdb_byte *writebuf, 846 ULONGEST offset, ULONGEST len, 847 ULONGEST *xfered_len) 848 { 849 if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL) 850 { 851 static long gate_table_size; 852 gdb_byte *tmp_buf; 853 long res; 854 855 /* Probe for the table size once. */ 856 if (gate_table_size == 0) 857 gate_table_size = syscall (__NR_getunwind, NULL, 0); 858 if (gate_table_size < 0) 859 return TARGET_XFER_E_IO; 860 861 if (offset >= gate_table_size) 862 return TARGET_XFER_EOF; 863 864 tmp_buf = (gdb_byte *) alloca (gate_table_size); 865 res = syscall (__NR_getunwind, tmp_buf, gate_table_size); 866 if (res < 0) 867 return TARGET_XFER_E_IO; 868 gdb_assert (res == gate_table_size); 869 870 if (offset + len > gate_table_size) 871 len = gate_table_size - offset; 872 873 memcpy (readbuf, tmp_buf + offset, len); 874 *xfered_len = len; 875 return TARGET_XFER_OK; 876 } 877 878 return super_xfer_partial (ops, object, annex, readbuf, writebuf, 879 offset, len, xfered_len); 880 } 881 882 /* For break.b instruction ia64 CPU forgets the immediate value and generates 883 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT. 884 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any 885 difference for the signals here. */ 886 887 static int 888 ia64_linux_status_is_event (int status) 889 { 890 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP 891 || WSTOPSIG (status) == SIGILL); 892 } 893 894 void _initialize_ia64_linux_nat (void); 895 896 void 897 _initialize_ia64_linux_nat (void) 898 { 899 struct target_ops *t; 900 901 /* Fill in the generic GNU/Linux methods. */ 902 t = linux_target (); 903 904 /* Override the default fetch/store register routines. */ 905 t->to_fetch_registers = ia64_linux_fetch_registers; 906 t->to_store_registers = ia64_linux_store_registers; 907 908 /* Override the default to_xfer_partial. */ 909 super_xfer_partial = t->to_xfer_partial; 910 t->to_xfer_partial = ia64_linux_xfer_partial; 911 912 /* Override watchpoint routines. */ 913 914 /* The IA-64 architecture can step over a watch point (without triggering 915 it again) if the "dd" (data debug fault disable) bit in the processor 916 status word is set. 917 918 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the 919 code there has determined that a hardware watchpoint has indeed 920 been hit. The CPU will then be able to execute one instruction 921 without triggering a watchpoint. */ 922 923 t->to_have_steppable_watchpoint = 1; 924 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint; 925 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint; 926 t->to_stopped_data_address = ia64_linux_stopped_data_address; 927 t->to_insert_watchpoint = ia64_linux_insert_watchpoint; 928 t->to_remove_watchpoint = ia64_linux_remove_watchpoint; 929 930 /* Register the target. */ 931 linux_nat_add_target (t); 932 linux_nat_set_new_thread (t, ia64_linux_new_thread); 933 linux_nat_set_status_is_event (t, ia64_linux_status_is_event); 934 } 935