1 /* Functions specific to running gdb native on IA-64 running 2 GNU/Linux. 3 4 Copyright (C) 1999-2015 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "defs.h" 22 #include "inferior.h" 23 #include "target.h" 24 #include "gdbcore.h" 25 #include "regcache.h" 26 #include "ia64-tdep.h" 27 #include "linux-nat.h" 28 29 #include <signal.h> 30 #include <sys/ptrace.h> 31 #include "gdb_wait.h" 32 #ifdef HAVE_SYS_REG_H 33 #include <sys/reg.h> 34 #endif 35 #include <sys/syscall.h> 36 #include <sys/user.h> 37 38 #include <asm/ptrace_offsets.h> 39 #include <sys/procfs.h> 40 41 /* Prototypes for supply_gregset etc. */ 42 #include "gregset.h" 43 44 /* These must match the order of the register names. 45 46 Some sort of lookup table is needed because the offsets associated 47 with the registers are all over the board. */ 48 49 static int u_offsets[] = 50 { 51 /* general registers */ 52 -1, /* gr0 not available; i.e, it's always zero. */ 53 PT_R1, 54 PT_R2, 55 PT_R3, 56 PT_R4, 57 PT_R5, 58 PT_R6, 59 PT_R7, 60 PT_R8, 61 PT_R9, 62 PT_R10, 63 PT_R11, 64 PT_R12, 65 PT_R13, 66 PT_R14, 67 PT_R15, 68 PT_R16, 69 PT_R17, 70 PT_R18, 71 PT_R19, 72 PT_R20, 73 PT_R21, 74 PT_R22, 75 PT_R23, 76 PT_R24, 77 PT_R25, 78 PT_R26, 79 PT_R27, 80 PT_R28, 81 PT_R29, 82 PT_R30, 83 PT_R31, 84 /* gr32 through gr127 not directly available via the ptrace interface. */ 85 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 91 /* Floating point registers */ 92 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */ 93 PT_F2, 94 PT_F3, 95 PT_F4, 96 PT_F5, 97 PT_F6, 98 PT_F7, 99 PT_F8, 100 PT_F9, 101 PT_F10, 102 PT_F11, 103 PT_F12, 104 PT_F13, 105 PT_F14, 106 PT_F15, 107 PT_F16, 108 PT_F17, 109 PT_F18, 110 PT_F19, 111 PT_F20, 112 PT_F21, 113 PT_F22, 114 PT_F23, 115 PT_F24, 116 PT_F25, 117 PT_F26, 118 PT_F27, 119 PT_F28, 120 PT_F29, 121 PT_F30, 122 PT_F31, 123 PT_F32, 124 PT_F33, 125 PT_F34, 126 PT_F35, 127 PT_F36, 128 PT_F37, 129 PT_F38, 130 PT_F39, 131 PT_F40, 132 PT_F41, 133 PT_F42, 134 PT_F43, 135 PT_F44, 136 PT_F45, 137 PT_F46, 138 PT_F47, 139 PT_F48, 140 PT_F49, 141 PT_F50, 142 PT_F51, 143 PT_F52, 144 PT_F53, 145 PT_F54, 146 PT_F55, 147 PT_F56, 148 PT_F57, 149 PT_F58, 150 PT_F59, 151 PT_F60, 152 PT_F61, 153 PT_F62, 154 PT_F63, 155 PT_F64, 156 PT_F65, 157 PT_F66, 158 PT_F67, 159 PT_F68, 160 PT_F69, 161 PT_F70, 162 PT_F71, 163 PT_F72, 164 PT_F73, 165 PT_F74, 166 PT_F75, 167 PT_F76, 168 PT_F77, 169 PT_F78, 170 PT_F79, 171 PT_F80, 172 PT_F81, 173 PT_F82, 174 PT_F83, 175 PT_F84, 176 PT_F85, 177 PT_F86, 178 PT_F87, 179 PT_F88, 180 PT_F89, 181 PT_F90, 182 PT_F91, 183 PT_F92, 184 PT_F93, 185 PT_F94, 186 PT_F95, 187 PT_F96, 188 PT_F97, 189 PT_F98, 190 PT_F99, 191 PT_F100, 192 PT_F101, 193 PT_F102, 194 PT_F103, 195 PT_F104, 196 PT_F105, 197 PT_F106, 198 PT_F107, 199 PT_F108, 200 PT_F109, 201 PT_F110, 202 PT_F111, 203 PT_F112, 204 PT_F113, 205 PT_F114, 206 PT_F115, 207 PT_F116, 208 PT_F117, 209 PT_F118, 210 PT_F119, 211 PT_F120, 212 PT_F121, 213 PT_F122, 214 PT_F123, 215 PT_F124, 216 PT_F125, 217 PT_F126, 218 PT_F127, 219 /* Predicate registers - we don't fetch these individually. */ 220 -1, -1, -1, -1, -1, -1, -1, -1, 221 -1, -1, -1, -1, -1, -1, -1, -1, 222 -1, -1, -1, -1, -1, -1, -1, -1, 223 -1, -1, -1, -1, -1, -1, -1, -1, 224 -1, -1, -1, -1, -1, -1, -1, -1, 225 -1, -1, -1, -1, -1, -1, -1, -1, 226 -1, -1, -1, -1, -1, -1, -1, -1, 227 -1, -1, -1, -1, -1, -1, -1, -1, 228 /* branch registers */ 229 PT_B0, 230 PT_B1, 231 PT_B2, 232 PT_B3, 233 PT_B4, 234 PT_B5, 235 PT_B6, 236 PT_B7, 237 /* Virtual frame pointer and virtual return address pointer. */ 238 -1, -1, 239 /* other registers */ 240 PT_PR, 241 PT_CR_IIP, /* ip */ 242 PT_CR_IPSR, /* psr */ 243 PT_CFM, /* cfm */ 244 /* kernel registers not visible via ptrace interface (?) */ 245 -1, -1, -1, -1, -1, -1, -1, -1, 246 /* hole */ 247 -1, -1, -1, -1, -1, -1, -1, -1, 248 PT_AR_RSC, 249 PT_AR_BSP, 250 PT_AR_BSPSTORE, 251 PT_AR_RNAT, 252 -1, 253 -1, /* Not available: FCR, IA32 floating control register. */ 254 -1, -1, 255 -1, /* Not available: EFLAG */ 256 -1, /* Not available: CSD */ 257 -1, /* Not available: SSD */ 258 -1, /* Not available: CFLG */ 259 -1, /* Not available: FSR */ 260 -1, /* Not available: FIR */ 261 -1, /* Not available: FDR */ 262 -1, 263 PT_AR_CCV, 264 -1, -1, -1, 265 PT_AR_UNAT, 266 -1, -1, -1, 267 PT_AR_FPSR, 268 -1, -1, -1, 269 -1, /* Not available: ITC */ 270 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 271 -1, -1, -1, -1, -1, -1, -1, -1, -1, 272 PT_AR_PFS, 273 PT_AR_LC, 274 PT_AR_EC, 275 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 281 -1, 282 /* nat bits - not fetched directly; instead we obtain these bits from 283 either rnat or unat or from memory. */ 284 -1, -1, -1, -1, -1, -1, -1, -1, 285 -1, -1, -1, -1, -1, -1, -1, -1, 286 -1, -1, -1, -1, -1, -1, -1, -1, 287 -1, -1, -1, -1, -1, -1, -1, -1, 288 -1, -1, -1, -1, -1, -1, -1, -1, 289 -1, -1, -1, -1, -1, -1, -1, -1, 290 -1, -1, -1, -1, -1, -1, -1, -1, 291 -1, -1, -1, -1, -1, -1, -1, -1, 292 -1, -1, -1, -1, -1, -1, -1, -1, 293 -1, -1, -1, -1, -1, -1, -1, -1, 294 -1, -1, -1, -1, -1, -1, -1, -1, 295 -1, -1, -1, -1, -1, -1, -1, -1, 296 -1, -1, -1, -1, -1, -1, -1, -1, 297 -1, -1, -1, -1, -1, -1, -1, -1, 298 -1, -1, -1, -1, -1, -1, -1, -1, 299 -1, -1, -1, -1, -1, -1, -1, -1, 300 }; 301 302 static CORE_ADDR 303 ia64_register_addr (struct gdbarch *gdbarch, int regno) 304 { 305 CORE_ADDR addr; 306 307 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) 308 error (_("Invalid register number %d."), regno); 309 310 if (u_offsets[regno] == -1) 311 addr = 0; 312 else 313 addr = (CORE_ADDR) u_offsets[regno]; 314 315 return addr; 316 } 317 318 static int 319 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno) 320 { 321 return regno < 0 322 || regno >= gdbarch_num_regs (gdbarch) 323 || u_offsets[regno] == -1; 324 } 325 326 static int 327 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno) 328 { 329 /* Rationale behind not permitting stores to bspstore... 330 331 The IA-64 architecture provides bspstore and bsp which refer 332 memory locations in the RSE's backing store. bspstore is the 333 next location which will be written when the RSE needs to write 334 to memory. bsp is the address at which r32 in the current frame 335 would be found if it were written to the backing store. 336 337 The IA-64 architecture provides read-only access to bsp and 338 read/write access to bspstore (but only when the RSE is in 339 the enforced lazy mode). It should be noted that stores 340 to bspstore also affect the value of bsp. Changing bspstore 341 does not affect the number of dirty entries between bspstore 342 and bsp, so changing bspstore by N words will also cause bsp 343 to be changed by (roughly) N as well. (It could be N-1 or N+1 344 depending upon where the NaT collection bits fall.) 345 346 OTOH, the Linux kernel provides read/write access to bsp (and 347 currently read/write access to bspstore as well). But it 348 is definitely the case that if you change one, the other 349 will change at the same time. It is more useful to gdb to 350 be able to change bsp. So in order to prevent strange and 351 undesirable things from happening when a dummy stack frame 352 is popped (after calling an inferior function), we allow 353 bspstore to be read, but not written. (Note that popping 354 a (generic) dummy stack frame causes all registers that 355 were previously read from the inferior process to be written 356 back.) */ 357 358 return regno < 0 359 || regno >= gdbarch_num_regs (gdbarch) 360 || u_offsets[regno] == -1 361 || regno == IA64_BSPSTORE_REGNUM; 362 } 363 364 void 365 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp) 366 { 367 int regi; 368 const greg_t *regp = (const greg_t *) gregsetp; 369 370 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 371 { 372 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM)); 373 } 374 375 /* FIXME: NAT collection bits are at index 32; gotta deal with these 376 somehow... */ 377 378 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33); 379 380 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 381 { 382 regcache_raw_supply (regcache, regi, 383 regp + 34 + (regi - IA64_BR0_REGNUM)); 384 } 385 386 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42); 387 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43); 388 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44); 389 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45); 390 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46); 391 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47); 392 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48); 393 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49); 394 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50); 395 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51); 396 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52); 397 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53); 398 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54); 399 } 400 401 void 402 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno) 403 { 404 int regi; 405 greg_t *regp = (greg_t *) gregsetp; 406 407 #define COPY_REG(_idx_,_regi_) \ 408 if ((regno == -1) || regno == _regi_) \ 409 regcache_raw_collect (regcache, _regi_, regp + _idx_) 410 411 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) 412 { 413 COPY_REG (regi - IA64_GR0_REGNUM, regi); 414 } 415 416 /* FIXME: NAT collection bits at index 32? */ 417 418 COPY_REG (33, IA64_PR_REGNUM); 419 420 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) 421 { 422 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); 423 } 424 425 COPY_REG (42, IA64_IP_REGNUM); 426 COPY_REG (43, IA64_CFM_REGNUM); 427 COPY_REG (44, IA64_PSR_REGNUM); 428 COPY_REG (45, IA64_RSC_REGNUM); 429 COPY_REG (46, IA64_BSP_REGNUM); 430 COPY_REG (47, IA64_BSPSTORE_REGNUM); 431 COPY_REG (48, IA64_RNAT_REGNUM); 432 COPY_REG (49, IA64_CCV_REGNUM); 433 COPY_REG (50, IA64_UNAT_REGNUM); 434 COPY_REG (51, IA64_FPSR_REGNUM); 435 COPY_REG (52, IA64_PFS_REGNUM); 436 COPY_REG (53, IA64_LC_REGNUM); 437 COPY_REG (54, IA64_EC_REGNUM); 438 } 439 440 /* Given a pointer to a floating point register set in /proc format 441 (fpregset_t *), unpack the register contents and supply them as gdb's 442 idea of the current floating point register values. */ 443 444 void 445 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp) 446 { 447 int regi; 448 const char *from; 449 const gdb_byte f_zero[16] = { 0 }; 450 const gdb_byte f_one[16] = 451 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; 452 453 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs 454 did the same. So ignore whatever might be recorded in fpregset_t 455 for fr0/fr1 and always supply their expected values. */ 456 457 /* fr0 is always read as zero. */ 458 regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero); 459 /* fr1 is always read as one (1.0). */ 460 regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one); 461 462 for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 463 { 464 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); 465 regcache_raw_supply (regcache, regi, from); 466 } 467 } 468 469 /* Given a pointer to a floating point register set in /proc format 470 (fpregset_t *), update the register specified by REGNO from gdb's idea 471 of the current floating point register set. If REGNO is -1, update 472 them all. */ 473 474 void 475 fill_fpregset (const struct regcache *regcache, 476 fpregset_t *fpregsetp, int regno) 477 { 478 int regi; 479 480 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) 481 { 482 if ((regno == -1) || (regno == regi)) 483 regcache_raw_collect (regcache, regi, 484 &((*fpregsetp)[regi - IA64_FR0_REGNUM])); 485 } 486 } 487 488 #define IA64_PSR_DB (1UL << 24) 489 #define IA64_PSR_DD (1UL << 39) 490 491 static void 492 enable_watchpoints_in_psr (ptid_t ptid) 493 { 494 struct regcache *regcache = get_thread_regcache (ptid); 495 ULONGEST psr; 496 497 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 498 if (!(psr & IA64_PSR_DB)) 499 { 500 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware 501 watchpoints and breakpoints. */ 502 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 503 } 504 } 505 506 static long debug_registers[8]; 507 508 static void 509 store_debug_register (ptid_t ptid, int idx, long val) 510 { 511 int tid; 512 513 tid = ptid_get_lwp (ptid); 514 if (tid == 0) 515 tid = ptid_get_pid (ptid); 516 517 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val); 518 } 519 520 static void 521 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, 522 long *dbr_mask) 523 { 524 if (dbr_addr) 525 store_debug_register (ptid, 2 * idx, *dbr_addr); 526 if (dbr_mask) 527 store_debug_register (ptid, 2 * idx + 1, *dbr_mask); 528 } 529 530 static int 531 is_power_of_2 (int val) 532 { 533 int i, onecount; 534 535 onecount = 0; 536 for (i = 0; i < 8 * sizeof (val); i++) 537 if (val & (1 << i)) 538 onecount++; 539 540 return onecount <= 1; 541 } 542 543 static int 544 ia64_linux_insert_watchpoint (struct target_ops *self, 545 CORE_ADDR addr, int len, int rw, 546 struct expression *cond) 547 { 548 struct lwp_info *lp; 549 int idx; 550 long dbr_addr, dbr_mask; 551 int max_watchpoints = 4; 552 553 if (len <= 0 || !is_power_of_2 (len)) 554 return -1; 555 556 for (idx = 0; idx < max_watchpoints; idx++) 557 { 558 dbr_mask = debug_registers[idx * 2 + 1]; 559 if ((dbr_mask & (0x3UL << 62)) == 0) 560 { 561 /* Exit loop if both r and w bits clear. */ 562 break; 563 } 564 } 565 566 if (idx == max_watchpoints) 567 return -1; 568 569 dbr_addr = (long) addr; 570 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ 571 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ 572 switch (rw) 573 { 574 case hw_write: 575 dbr_mask |= (1L << 62); /* Set w bit */ 576 break; 577 case hw_read: 578 dbr_mask |= (1L << 63); /* Set r bit */ 579 break; 580 case hw_access: 581 dbr_mask |= (3L << 62); /* Set both r and w bits */ 582 break; 583 default: 584 return -1; 585 } 586 587 debug_registers[2 * idx] = dbr_addr; 588 debug_registers[2 * idx + 1] = dbr_mask; 589 ALL_LWPS (lp) 590 { 591 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); 592 enable_watchpoints_in_psr (lp->ptid); 593 } 594 595 return 0; 596 } 597 598 static int 599 ia64_linux_remove_watchpoint (struct target_ops *self, 600 CORE_ADDR addr, int len, int type, 601 struct expression *cond) 602 { 603 int idx; 604 long dbr_addr, dbr_mask; 605 int max_watchpoints = 4; 606 607 if (len <= 0 || !is_power_of_2 (len)) 608 return -1; 609 610 for (idx = 0; idx < max_watchpoints; idx++) 611 { 612 dbr_addr = debug_registers[2 * idx]; 613 dbr_mask = debug_registers[2 * idx + 1]; 614 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) 615 { 616 struct lwp_info *lp; 617 618 debug_registers[2 * idx] = 0; 619 debug_registers[2 * idx + 1] = 0; 620 dbr_addr = 0; 621 dbr_mask = 0; 622 623 ALL_LWPS (lp) 624 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask); 625 626 return 0; 627 } 628 } 629 return -1; 630 } 631 632 static void 633 ia64_linux_new_thread (struct lwp_info *lp) 634 { 635 int i, any; 636 637 any = 0; 638 for (i = 0; i < 8; i++) 639 { 640 if (debug_registers[i] != 0) 641 any = 1; 642 store_debug_register (lp->ptid, i, debug_registers[i]); 643 } 644 645 if (any) 646 enable_watchpoints_in_psr (lp->ptid); 647 } 648 649 static int 650 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 651 { 652 CORE_ADDR psr; 653 siginfo_t siginfo; 654 struct regcache *regcache = get_current_regcache (); 655 656 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) 657 return 0; 658 659 if (siginfo.si_signo != SIGTRAP 660 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) 661 return 0; 662 663 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); 664 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint 665 for the next instruction. */ 666 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); 667 668 *addr_p = (CORE_ADDR) siginfo.si_addr; 669 return 1; 670 } 671 672 static int 673 ia64_linux_stopped_by_watchpoint (struct target_ops *ops) 674 { 675 CORE_ADDR addr; 676 return ia64_linux_stopped_data_address (ops, &addr); 677 } 678 679 static int 680 ia64_linux_can_use_hw_breakpoint (struct target_ops *self, 681 int type, int cnt, int othertype) 682 { 683 return 1; 684 } 685 686 687 /* Fetch register REGNUM from the inferior. */ 688 689 static void 690 ia64_linux_fetch_register (struct regcache *regcache, int regnum) 691 { 692 struct gdbarch *gdbarch = get_regcache_arch (regcache); 693 CORE_ADDR addr; 694 size_t size; 695 PTRACE_TYPE_RET *buf; 696 int pid, i; 697 698 /* r0 cannot be fetched but is always zero. */ 699 if (regnum == IA64_GR0_REGNUM) 700 { 701 const gdb_byte zero[8] = { 0 }; 702 703 gdb_assert (sizeof (zero) == register_size (gdbarch, regnum)); 704 regcache_raw_supply (regcache, regnum, zero); 705 return; 706 } 707 708 /* fr0 cannot be fetched but is always zero. */ 709 if (regnum == IA64_FR0_REGNUM) 710 { 711 const gdb_byte f_zero[16] = { 0 }; 712 713 gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum)); 714 regcache_raw_supply (regcache, regnum, f_zero); 715 return; 716 } 717 718 /* fr1 cannot be fetched but is always one (1.0). */ 719 if (regnum == IA64_FR1_REGNUM) 720 { 721 const gdb_byte f_one[16] = 722 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; 723 724 gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum)); 725 regcache_raw_supply (regcache, regnum, f_one); 726 return; 727 } 728 729 if (ia64_cannot_fetch_register (gdbarch, regnum)) 730 { 731 regcache_raw_supply (regcache, regnum, NULL); 732 return; 733 } 734 735 /* Cater for systems like GNU/Linux, that implement threads as 736 separate processes. */ 737 pid = ptid_get_lwp (inferior_ptid); 738 if (pid == 0) 739 pid = ptid_get_pid (inferior_ptid); 740 741 /* This isn't really an address, but ptrace thinks of it as one. */ 742 addr = ia64_register_addr (gdbarch, regnum); 743 size = register_size (gdbarch, regnum); 744 745 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 746 buf = alloca (size); 747 748 /* Read the register contents from the inferior a chunk at a time. */ 749 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 750 { 751 errno = 0; 752 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0); 753 if (errno != 0) 754 error (_("Couldn't read register %s (#%d): %s."), 755 gdbarch_register_name (gdbarch, regnum), 756 regnum, safe_strerror (errno)); 757 758 addr += sizeof (PTRACE_TYPE_RET); 759 } 760 regcache_raw_supply (regcache, regnum, buf); 761 } 762 763 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this 764 for all registers. */ 765 766 static void 767 ia64_linux_fetch_registers (struct target_ops *ops, 768 struct regcache *regcache, int regnum) 769 { 770 if (regnum == -1) 771 for (regnum = 0; 772 regnum < gdbarch_num_regs (get_regcache_arch (regcache)); 773 regnum++) 774 ia64_linux_fetch_register (regcache, regnum); 775 else 776 ia64_linux_fetch_register (regcache, regnum); 777 } 778 779 /* Store register REGNUM into the inferior. */ 780 781 static void 782 ia64_linux_store_register (const struct regcache *regcache, int regnum) 783 { 784 struct gdbarch *gdbarch = get_regcache_arch (regcache); 785 CORE_ADDR addr; 786 size_t size; 787 PTRACE_TYPE_RET *buf; 788 int pid, i; 789 790 if (ia64_cannot_store_register (gdbarch, regnum)) 791 return; 792 793 /* Cater for systems like GNU/Linux, that implement threads as 794 separate processes. */ 795 pid = ptid_get_lwp (inferior_ptid); 796 if (pid == 0) 797 pid = ptid_get_pid (inferior_ptid); 798 799 /* This isn't really an address, but ptrace thinks of it as one. */ 800 addr = ia64_register_addr (gdbarch, regnum); 801 size = register_size (gdbarch, regnum); 802 803 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); 804 buf = alloca (size); 805 806 /* Write the register contents into the inferior a chunk at a time. */ 807 regcache_raw_collect (regcache, regnum, buf); 808 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) 809 { 810 errno = 0; 811 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); 812 if (errno != 0) 813 error (_("Couldn't write register %s (#%d): %s."), 814 gdbarch_register_name (gdbarch, regnum), 815 regnum, safe_strerror (errno)); 816 817 addr += sizeof (PTRACE_TYPE_RET); 818 } 819 } 820 821 /* Store register REGNUM back into the inferior. If REGNUM is -1, do 822 this for all registers. */ 823 824 static void 825 ia64_linux_store_registers (struct target_ops *ops, 826 struct regcache *regcache, int regnum) 827 { 828 if (regnum == -1) 829 for (regnum = 0; 830 regnum < gdbarch_num_regs (get_regcache_arch (regcache)); 831 regnum++) 832 ia64_linux_store_register (regcache, regnum); 833 else 834 ia64_linux_store_register (regcache, regnum); 835 } 836 837 838 static target_xfer_partial_ftype *super_xfer_partial; 839 840 /* Implement the to_xfer_partial target_ops method. */ 841 842 static enum target_xfer_status 843 ia64_linux_xfer_partial (struct target_ops *ops, 844 enum target_object object, 845 const char *annex, 846 gdb_byte *readbuf, const gdb_byte *writebuf, 847 ULONGEST offset, ULONGEST len, 848 ULONGEST *xfered_len) 849 { 850 if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL) 851 { 852 static long gate_table_size; 853 gdb_byte *tmp_buf; 854 long res; 855 856 /* Probe for the table size once. */ 857 if (gate_table_size == 0) 858 gate_table_size = syscall (__NR_getunwind, NULL, 0); 859 if (gate_table_size < 0) 860 return TARGET_XFER_E_IO; 861 862 if (offset >= gate_table_size) 863 return TARGET_XFER_EOF; 864 865 tmp_buf = alloca (gate_table_size); 866 res = syscall (__NR_getunwind, tmp_buf, gate_table_size); 867 if (res < 0) 868 return TARGET_XFER_E_IO; 869 gdb_assert (res == gate_table_size); 870 871 if (offset + len > gate_table_size) 872 len = gate_table_size - offset; 873 874 memcpy (readbuf, tmp_buf + offset, len); 875 *xfered_len = len; 876 return TARGET_XFER_OK; 877 } 878 879 return super_xfer_partial (ops, object, annex, readbuf, writebuf, 880 offset, len, xfered_len); 881 } 882 883 /* For break.b instruction ia64 CPU forgets the immediate value and generates 884 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT. 885 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any 886 difference for the signals here. */ 887 888 static int 889 ia64_linux_status_is_event (int status) 890 { 891 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP 892 || WSTOPSIG (status) == SIGILL); 893 } 894 895 void _initialize_ia64_linux_nat (void); 896 897 void 898 _initialize_ia64_linux_nat (void) 899 { 900 struct target_ops *t; 901 902 /* Fill in the generic GNU/Linux methods. */ 903 t = linux_target (); 904 905 /* Override the default fetch/store register routines. */ 906 t->to_fetch_registers = ia64_linux_fetch_registers; 907 t->to_store_registers = ia64_linux_store_registers; 908 909 /* Override the default to_xfer_partial. */ 910 super_xfer_partial = t->to_xfer_partial; 911 t->to_xfer_partial = ia64_linux_xfer_partial; 912 913 /* Override watchpoint routines. */ 914 915 /* The IA-64 architecture can step over a watch point (without triggering 916 it again) if the "dd" (data debug fault disable) bit in the processor 917 status word is set. 918 919 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the 920 code there has determined that a hardware watchpoint has indeed 921 been hit. The CPU will then be able to execute one instruction 922 without triggering a watchpoint. */ 923 924 t->to_have_steppable_watchpoint = 1; 925 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint; 926 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint; 927 t->to_stopped_data_address = ia64_linux_stopped_data_address; 928 t->to_insert_watchpoint = ia64_linux_insert_watchpoint; 929 t->to_remove_watchpoint = ia64_linux_remove_watchpoint; 930 931 /* Register the target. */ 932 linux_nat_add_target (t); 933 linux_nat_set_new_thread (t, ia64_linux_new_thread); 934 linux_nat_set_status_is_event (t, ia64_linux_status_is_event); 935 } 936