1 /* Target dependent code for ARC arhitecture, for GDB. 2 3 Copyright 2005-2019 Free Software Foundation, Inc. 4 Contributed by Synopsys Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* GDB header files. */ 22 #include "defs.h" 23 #include "arch-utils.h" 24 #include "disasm.h" 25 #include "dwarf2-frame.h" 26 #include "frame-base.h" 27 #include "frame-unwind.h" 28 #include "gdbcore.h" 29 #include "gdbcmd.h" 30 #include "objfiles.h" 31 #include "prologue-value.h" 32 #include "trad-frame.h" 33 34 /* ARC header files. */ 35 #include "opcode/arc.h" 36 #include "../opcodes/arc-dis.h" 37 #include "arc-tdep.h" 38 39 /* Standard headers. */ 40 #include <algorithm> 41 42 /* Default target descriptions. */ 43 #include "features/arc-v2.c" 44 #include "features/arc-arcompact.c" 45 46 /* The frame unwind cache for ARC. */ 47 48 struct arc_frame_cache 49 { 50 /* The stack pointer at the time this frame was created; i.e. the caller's 51 stack pointer when this function was called. It is used to identify this 52 frame. */ 53 CORE_ADDR prev_sp; 54 55 /* Register that is a base for this frame - FP for normal frame, SP for 56 non-FP frames. */ 57 int frame_base_reg; 58 59 /* Offset from the previous SP to the current frame base. If GCC uses 60 `SUB SP,SP,offset` to allocate space for local variables, then it will be 61 done after setting up a frame pointer, but it still will be considered 62 part of prologue, therefore SP will be lesser than FP at the end of the 63 prologue analysis. In this case that would be an offset from old SP to a 64 new FP. But in case of non-FP frames, frame base is an SP and thus that 65 would be an offset from old SP to new SP. What is important is that this 66 is an offset from old SP to a known register, so it can be used to find 67 old SP. 68 69 Using FP is preferable, when possible, because SP can change in function 70 body after prologue due to alloca, variadic arguments or other shenanigans. 71 If that is the case in the caller frame, then PREV_SP will point to SP at 72 the moment of function call, but it will be different from SP value at the 73 end of the caller prologue. As a result it will not be possible to 74 reconstruct caller's frame and go past it in the backtrace. Those things 75 are unlikely to happen to FP - FP value at the moment of function call (as 76 stored on stack in callee prologue) is also an FP value at the end of the 77 caller's prologue. */ 78 79 LONGEST frame_base_offset; 80 81 /* Store addresses for registers saved in prologue. During prologue analysis 82 GDB stores offsets relatively to "old SP", then after old SP is evaluated, 83 offsets are replaced with absolute addresses. */ 84 struct trad_frame_saved_reg *saved_regs; 85 }; 86 87 /* Global debug flag. */ 88 89 int arc_debug; 90 91 /* List of "maintenance print arc" commands. */ 92 93 static struct cmd_list_element *maintenance_print_arc_list = NULL; 94 95 /* XML target description features. */ 96 97 static const char core_v2_feature_name[] = "org.gnu.gdb.arc.core.v2"; 98 static const char 99 core_reduced_v2_feature_name[] = "org.gnu.gdb.arc.core-reduced.v2"; 100 static const char 101 core_arcompact_feature_name[] = "org.gnu.gdb.arc.core.arcompact"; 102 static const char aux_minimal_feature_name[] = "org.gnu.gdb.arc.aux-minimal"; 103 104 /* XML target description known registers. */ 105 106 static const char *const core_v2_register_names[] = { 107 "r0", "r1", "r2", "r3", 108 "r4", "r5", "r6", "r7", 109 "r8", "r9", "r10", "r11", 110 "r12", "r13", "r14", "r15", 111 "r16", "r17", "r18", "r19", 112 "r20", "r21", "r22", "r23", 113 "r24", "r25", "gp", "fp", 114 "sp", "ilink", "r30", "blink", 115 "r32", "r33", "r34", "r35", 116 "r36", "r37", "r38", "r39", 117 "r40", "r41", "r42", "r43", 118 "r44", "r45", "r46", "r47", 119 "r48", "r49", "r50", "r51", 120 "r52", "r53", "r54", "r55", 121 "r56", "r57", "accl", "acch", 122 "lp_count", "reserved", "limm", "pcl", 123 }; 124 125 static const char *const aux_minimal_register_names[] = { 126 "pc", "status32", 127 }; 128 129 static const char *const core_arcompact_register_names[] = { 130 "r0", "r1", "r2", "r3", 131 "r4", "r5", "r6", "r7", 132 "r8", "r9", "r10", "r11", 133 "r12", "r13", "r14", "r15", 134 "r16", "r17", "r18", "r19", 135 "r20", "r21", "r22", "r23", 136 "r24", "r25", "gp", "fp", 137 "sp", "ilink1", "ilink2", "blink", 138 "r32", "r33", "r34", "r35", 139 "r36", "r37", "r38", "r39", 140 "r40", "r41", "r42", "r43", 141 "r44", "r45", "r46", "r47", 142 "r48", "r49", "r50", "r51", 143 "r52", "r53", "r54", "r55", 144 "r56", "r57", "r58", "r59", 145 "lp_count", "reserved", "limm", "pcl", 146 }; 147 148 static char *arc_disassembler_options = NULL; 149 150 /* Functions are sorted in the order as they are used in the 151 _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static 152 functions are defined before the first invocation. */ 153 154 /* Returns an unsigned value of OPERAND_NUM in instruction INSN. 155 For relative branch instructions returned value is an offset, not an actual 156 branch target. */ 157 158 static ULONGEST 159 arc_insn_get_operand_value (const struct arc_instruction &insn, 160 unsigned int operand_num) 161 { 162 switch (insn.operands[operand_num].kind) 163 { 164 case ARC_OPERAND_KIND_LIMM: 165 gdb_assert (insn.limm_p); 166 return insn.limm_value; 167 case ARC_OPERAND_KIND_SHIMM: 168 return insn.operands[operand_num].value; 169 default: 170 /* Value in instruction is a register number. */ 171 struct regcache *regcache = get_current_regcache (); 172 ULONGEST value; 173 regcache_cooked_read_unsigned (regcache, 174 insn.operands[operand_num].value, 175 &value); 176 return value; 177 } 178 } 179 180 /* Like arc_insn_get_operand_value, but returns a signed value. */ 181 182 static LONGEST 183 arc_insn_get_operand_value_signed (const struct arc_instruction &insn, 184 unsigned int operand_num) 185 { 186 switch (insn.operands[operand_num].kind) 187 { 188 case ARC_OPERAND_KIND_LIMM: 189 gdb_assert (insn.limm_p); 190 /* Convert unsigned raw value to signed one. This assumes 2's 191 complement arithmetic, but so is the LONG_MIN value from generic 192 defs.h and that assumption is true for ARC. */ 193 gdb_static_assert (sizeof (insn.limm_value) == sizeof (int)); 194 return (((LONGEST) insn.limm_value) ^ INT_MIN) - INT_MIN; 195 case ARC_OPERAND_KIND_SHIMM: 196 /* Sign conversion has been done by binutils. */ 197 return insn.operands[operand_num].value; 198 default: 199 /* Value in instruction is a register number. */ 200 struct regcache *regcache = get_current_regcache (); 201 LONGEST value; 202 regcache_cooked_read_signed (regcache, 203 insn.operands[operand_num].value, 204 &value); 205 return value; 206 } 207 } 208 209 /* Get register with base address of memory operation. */ 210 211 int 212 arc_insn_get_memory_base_reg (const struct arc_instruction &insn) 213 { 214 /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */ 215 if (insn.insn_class == PUSH || insn.insn_class == POP) 216 return ARC_SP_REGNUM; 217 218 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); 219 220 /* Other instructions all have at least two operands: operand 0 is data, 221 operand 1 is address. Operand 2 is offset from address. However, see 222 comment to arc_instruction.operands - in some cases, third operand may be 223 missing, namely if it is 0. */ 224 gdb_assert (insn.operands_count >= 2); 225 return insn.operands[1].value; 226 } 227 228 /* Get offset of a memory operation INSN. */ 229 230 CORE_ADDR 231 arc_insn_get_memory_offset (const struct arc_instruction &insn) 232 { 233 /* POP_S and PUSH_S have offset as an implicit argument in a 234 disassembler. */ 235 if (insn.insn_class == POP) 236 return 4; 237 else if (insn.insn_class == PUSH) 238 return -4; 239 240 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); 241 242 /* Other instructions all have at least two operands: operand 0 is data, 243 operand 1 is address. Operand 2 is offset from address. However, see 244 comment to arc_instruction.operands - in some cases, third operand may be 245 missing, namely if it is 0. */ 246 if (insn.operands_count < 3) 247 return 0; 248 249 CORE_ADDR value = arc_insn_get_operand_value (insn, 2); 250 /* Handle scaling. */ 251 if (insn.writeback_mode == ARC_WRITEBACK_AS) 252 { 253 /* Byte data size is not valid for AS. Halfword means shift by 1 bit. 254 Word and double word means shift by 2 bits. */ 255 gdb_assert (insn.data_size_mode != ARC_SCALING_B); 256 if (insn.data_size_mode == ARC_SCALING_H) 257 value <<= 1; 258 else 259 value <<= 2; 260 } 261 return value; 262 } 263 264 CORE_ADDR 265 arc_insn_get_branch_target (const struct arc_instruction &insn) 266 { 267 gdb_assert (insn.is_control_flow); 268 269 /* BI [c]: PC = nextPC + (c << 2). */ 270 if (insn.insn_class == BI) 271 { 272 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); 273 return arc_insn_get_linear_next_pc (insn) + (reg_value << 2); 274 } 275 /* BIH [c]: PC = nextPC + (c << 1). */ 276 else if (insn.insn_class == BIH) 277 { 278 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); 279 return arc_insn_get_linear_next_pc (insn) + (reg_value << 1); 280 } 281 /* JLI and EI. */ 282 /* JLI and EI depend on optional AUX registers. Not supported right now. */ 283 else if (insn.insn_class == JLI) 284 { 285 fprintf_unfiltered (gdb_stderr, 286 "JLI_S instruction is not supported by the GDB."); 287 return 0; 288 } 289 else if (insn.insn_class == EI) 290 { 291 fprintf_unfiltered (gdb_stderr, 292 "EI_S instruction is not supported by the GDB."); 293 return 0; 294 } 295 /* LEAVE_S: PC = BLINK. */ 296 else if (insn.insn_class == LEAVE) 297 { 298 struct regcache *regcache = get_current_regcache (); 299 ULONGEST value; 300 regcache_cooked_read_unsigned (regcache, ARC_BLINK_REGNUM, &value); 301 return value; 302 } 303 /* BBIT0/1, BRcc: PC = currentPC + operand. */ 304 else if (insn.insn_class == BBIT0 || insn.insn_class == BBIT1 305 || insn.insn_class == BRCC) 306 { 307 /* Most instructions has branch target as their sole argument. However 308 conditional brcc/bbit has it as a third operand. */ 309 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 2); 310 311 /* Offset is relative to the 4-byte aligned address of the current 312 instruction, hence last two bits should be truncated. */ 313 return pcrel_addr + align_down (insn.address, 4); 314 } 315 /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */ 316 else if (insn.insn_class == BRANCH || insn.insn_class == LOOP) 317 { 318 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 0); 319 320 /* Offset is relative to the 4-byte aligned address of the current 321 instruction, hence last two bits should be truncated. */ 322 return pcrel_addr + align_down (insn.address, 4); 323 } 324 /* J, Jcc, JL, JLcc: PC = operand. */ 325 else if (insn.insn_class == JUMP) 326 { 327 /* All jumps are single-operand. */ 328 return arc_insn_get_operand_value (insn, 0); 329 } 330 331 /* This is some new and unknown instruction. */ 332 gdb_assert_not_reached ("Unknown branch instruction."); 333 } 334 335 /* Dump INSN into gdb_stdlog. */ 336 337 void 338 arc_insn_dump (const struct arc_instruction &insn) 339 { 340 struct gdbarch *gdbarch = target_gdbarch (); 341 342 arc_print ("Dumping arc_instruction at %s\n", 343 paddress (gdbarch, insn.address)); 344 arc_print ("\tlength = %u\n", insn.length); 345 346 if (!insn.valid) 347 { 348 arc_print ("\tThis is not a valid ARC instruction.\n"); 349 return; 350 } 351 352 arc_print ("\tlength_with_limm = %u\n", insn.length + (insn.limm_p ? 4 : 0)); 353 arc_print ("\tcc = 0x%x\n", insn.condition_code); 354 arc_print ("\tinsn_class = %u\n", insn.insn_class); 355 arc_print ("\tis_control_flow = %i\n", insn.is_control_flow); 356 arc_print ("\thas_delay_slot = %i\n", insn.has_delay_slot); 357 358 CORE_ADDR next_pc = arc_insn_get_linear_next_pc (insn); 359 arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch, next_pc)); 360 361 if (insn.is_control_flow) 362 { 363 CORE_ADDR t = arc_insn_get_branch_target (insn); 364 arc_print ("\tbranch_target = %s\n", paddress (gdbarch, t)); 365 } 366 367 arc_print ("\tlimm_p = %i\n", insn.limm_p); 368 if (insn.limm_p) 369 arc_print ("\tlimm_value = 0x%08x\n", insn.limm_value); 370 371 if (insn.insn_class == STORE || insn.insn_class == LOAD 372 || insn.insn_class == PUSH || insn.insn_class == POP) 373 { 374 arc_print ("\twriteback_mode = %u\n", insn.writeback_mode); 375 arc_print ("\tdata_size_mode = %u\n", insn.data_size_mode); 376 arc_print ("\tmemory_base_register = %s\n", 377 gdbarch_register_name (gdbarch, 378 arc_insn_get_memory_base_reg (insn))); 379 /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a 380 LONGEST for a nicer representation. */ 381 arc_print ("\taddr_offset = %s\n", 382 plongest (arc_insn_get_memory_offset (insn))); 383 } 384 385 arc_print ("\toperands_count = %u\n", insn.operands_count); 386 for (unsigned int i = 0; i < insn.operands_count; ++i) 387 { 388 int is_reg = (insn.operands[i].kind == ARC_OPERAND_KIND_REG); 389 390 arc_print ("\toperand[%u] = {\n", i); 391 arc_print ("\t\tis_reg = %i\n", is_reg); 392 if (is_reg) 393 arc_print ("\t\tregister = %s\n", 394 gdbarch_register_name (gdbarch, insn.operands[i].value)); 395 /* Don't know if this value is signed or not, so print both 396 representations. This tends to look quite ugly, especially for big 397 numbers. */ 398 arc_print ("\t\tunsigned value = %s\n", 399 pulongest (arc_insn_get_operand_value (insn, i))); 400 arc_print ("\t\tsigned value = %s\n", 401 plongest (arc_insn_get_operand_value_signed (insn, i))); 402 arc_print ("\t}\n"); 403 } 404 } 405 406 CORE_ADDR 407 arc_insn_get_linear_next_pc (const struct arc_instruction &insn) 408 { 409 /* In ARC long immediate is always 4 bytes. */ 410 return (insn.address + insn.length + (insn.limm_p ? 4 : 0)); 411 } 412 413 /* Implement the "write_pc" gdbarch method. 414 415 In ARC PC register is a normal register so in most cases setting PC value 416 is a straightforward process: debugger just writes PC value. However it 417 gets trickier in case when current instruction is an instruction in delay 418 slot. In this case CPU will execute instruction at current PC value, then 419 will set PC to the current value of BTA register; also current instruction 420 cannot be branch/jump and some of the other instruction types. Thus if 421 debugger would try to just change PC value in this case, this instruction 422 will get executed, but then core will "jump" to the original branch target. 423 424 Whether current instruction is a delay-slot instruction or not is indicated 425 by DE bit in STATUS32 register indicates if current instruction is a delay 426 slot instruction. This bit is writable by debug host, which allows debug 427 host to prevent core from jumping after the delay slot instruction. It 428 also works in another direction: setting this bit will make core to treat 429 any current instructions as a delay slot instruction and to set PC to the 430 current value of BTA register. 431 432 To workaround issues with changing PC register while in delay slot 433 instruction, debugger should check for the STATUS32.DE bit and reset it if 434 it is set. No other change is required in this function. Most common 435 case, where this function might be required is calling inferior functions 436 from debugger. Generic GDB logic handles this pretty well: current values 437 of registers are stored, value of PC is changed (that is the job of this 438 function), and after inferior function is executed, GDB restores all 439 registers, include BTA and STATUS32, which also means that core is returned 440 to its original state of being halted on delay slot instructions. 441 442 This method is useless for ARC 600, because it doesn't have externally 443 exposed BTA register. In the case of ARC 600 it is impossible to restore 444 core to its state in all occasions thus core should never be halted (from 445 the perspective of debugger host) in the delay slot. */ 446 447 static void 448 arc_write_pc (struct regcache *regcache, CORE_ADDR new_pc) 449 { 450 struct gdbarch *gdbarch = regcache->arch (); 451 452 if (arc_debug) 453 debug_printf ("arc: Writing PC, new value=%s\n", 454 paddress (gdbarch, new_pc)); 455 456 regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), 457 new_pc); 458 459 ULONGEST status32; 460 regcache_cooked_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), 461 &status32); 462 463 /* Mask for DE bit is 0x40. */ 464 if (status32 & 0x40) 465 { 466 if (arc_debug) 467 { 468 debug_printf ("arc: Changing PC while in delay slot. Will " 469 "reset STATUS32.DE bit to zero. Value of STATUS32 " 470 "register is 0x%s\n", 471 phex (status32, ARC_REGISTER_SIZE)); 472 } 473 474 /* Reset bit and write to the cache. */ 475 status32 &= ~0x40; 476 regcache_cooked_write_unsigned (regcache, gdbarch_ps_regnum (gdbarch), 477 status32); 478 } 479 } 480 481 /* Implement the "virtual_frame_pointer" gdbarch method. 482 483 According to ABI the FP (r27) is used to point to the middle of the current 484 stack frame, just below the saved FP and before local variables, register 485 spill area and outgoing args. However for optimization levels above O2 and 486 in any case in leaf functions, the frame pointer is usually not set at all. 487 The exception being when handling nested functions. 488 489 We use this function to return a "virtual" frame pointer, marking the start 490 of the current stack frame as a register-offset pair. If the FP is not 491 being used, then it should return SP, with an offset of the frame size. 492 493 The current implementation doesn't actually know the frame size, nor 494 whether the FP is actually being used, so for now we just return SP and an 495 offset of zero. This is no worse than other architectures, but is needed 496 to avoid assertion failures. 497 498 TODO: Can we determine the frame size to get a correct offset? 499 500 PC is a program counter where we need the virtual FP. REG_PTR is the base 501 register used for the virtual FP. OFFSET_PTR is the offset used for the 502 virtual FP. */ 503 504 static void 505 arc_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, 506 int *reg_ptr, LONGEST *offset_ptr) 507 { 508 *reg_ptr = gdbarch_sp_regnum (gdbarch); 509 *offset_ptr = 0; 510 } 511 512 /* Implement the "dummy_id" gdbarch method. 513 514 Tear down a dummy frame created by arc_push_dummy_call (). This data has 515 to be constructed manually from the data in our hand. The stack pointer 516 and program counter can be obtained from the frame info. */ 517 518 static struct frame_id 519 arc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 520 { 521 return frame_id_build (get_frame_sp (this_frame), 522 get_frame_pc (this_frame)); 523 } 524 525 /* Implement the "push_dummy_call" gdbarch method. 526 527 Stack Frame Layout 528 529 This shows the layout of the stack frame for the general case of a 530 function call; a given function might not have a variable number of 531 arguments or local variables, or might not save any registers, so it would 532 not have the corresponding frame areas. Additionally, a leaf function 533 (i.e. one which calls no other functions) does not need to save the 534 contents of the BLINK register (which holds its return address), and a 535 function might not have a frame pointer. 536 537 The stack grows downward, so SP points below FP in memory; SP always 538 points to the last used word on the stack, not the first one. 539 540 | | | 541 | arg word N | | caller's 542 | : | | frame 543 | arg word 10 | | 544 | arg word 9 | | 545 old SP ---> +-----------------------+ --+ 546 | | | 547 | callee-saved | | 548 | registers | | 549 | including fp, blink | | 550 | | | callee's 551 new FP ---> +-----------------------+ | frame 552 | | | 553 | local | | 554 | variables | | 555 | | | 556 | register | | 557 | spill area | | 558 | | | 559 | outgoing args | | 560 | | | 561 new SP ---> +-----------------------+ --+ 562 | | 563 | unused | 564 | | 565 | 566 | 567 V 568 downwards 569 570 The list of arguments to be passed to a function is considered to be a 571 sequence of _N_ words (as though all the parameters were stored in order in 572 memory with each parameter occupying an integral number of words). Words 573 1..8 are passed in registers 0..7; if the function has more than 8 words of 574 arguments then words 9..@em N are passed on the stack in the caller's frame. 575 576 If the function has a variable number of arguments, e.g. it has a form such 577 as `function (p1, p2, ...);' and _P_ words are required to hold the values 578 of the named parameters (which are passed in registers 0..@em P -1), then 579 the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the 580 top of the frame so that the anonymous parameter words occupy a continuous 581 region. 582 583 Any arguments are already in target byte order. We just need to store 584 them! 585 586 BP_ADDR is the return address where breakpoint must be placed. NARGS is 587 the number of arguments to the function. ARGS is the arguments values (in 588 target byte order). SP is the Current value of SP register. STRUCT_RETURN 589 is TRUE if structures are returned by the function. STRUCT_ADDR is the 590 hidden address for returning a struct. Returns SP of a new frame. */ 591 592 static CORE_ADDR 593 arc_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 594 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 595 struct value **args, CORE_ADDR sp, 596 function_call_return_method return_method, 597 CORE_ADDR struct_addr) 598 { 599 if (arc_debug) 600 debug_printf ("arc: push_dummy_call (nargs = %d)\n", nargs); 601 602 int arg_reg = ARC_FIRST_ARG_REGNUM; 603 604 /* Push the return address. */ 605 regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, bp_addr); 606 607 /* Are we returning a value using a structure return instead of a normal 608 value return? If so, struct_addr is the address of the reserved space for 609 the return structure to be written on the stack, and that address is 610 passed to that function as a hidden first argument. */ 611 if (return_method == return_method_struct) 612 { 613 /* Pass the return address in the first argument register. */ 614 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); 615 616 if (arc_debug) 617 debug_printf ("arc: struct return address %s passed in R%d", 618 print_core_address (gdbarch, struct_addr), arg_reg); 619 620 arg_reg++; 621 } 622 623 if (nargs > 0) 624 { 625 unsigned int total_space = 0; 626 627 /* How much space do the arguments occupy in total? Must round each 628 argument's size up to an integral number of words. */ 629 for (int i = 0; i < nargs; i++) 630 { 631 unsigned int len = TYPE_LENGTH (value_type (args[i])); 632 unsigned int space = align_up (len, 4); 633 634 total_space += space; 635 636 if (arc_debug) 637 debug_printf ("arc: arg %d: %u bytes -> %u\n", i, len, space); 638 } 639 640 /* Allocate a buffer to hold a memory image of the arguments. */ 641 gdb_byte *memory_image = XCNEWVEC (gdb_byte, total_space); 642 643 /* Now copy all of the arguments into the buffer, correctly aligned. */ 644 gdb_byte *data = memory_image; 645 for (int i = 0; i < nargs; i++) 646 { 647 unsigned int len = TYPE_LENGTH (value_type (args[i])); 648 unsigned int space = align_up (len, 4); 649 650 memcpy (data, value_contents (args[i]), (size_t) len); 651 if (arc_debug) 652 debug_printf ("arc: copying arg %d, val 0x%08x, len %d to mem\n", 653 i, *((int *) value_contents (args[i])), len); 654 655 data += space; 656 } 657 658 /* Now load as much as possible of the memory image into registers. */ 659 data = memory_image; 660 while (arg_reg <= ARC_LAST_ARG_REGNUM) 661 { 662 if (arc_debug) 663 debug_printf ("arc: passing 0x%02x%02x%02x%02x in register R%d\n", 664 data[0], data[1], data[2], data[3], arg_reg); 665 666 /* Note we don't use write_unsigned here, since that would convert 667 the byte order, but we are already in the correct byte order. */ 668 regcache->cooked_write (arg_reg, data); 669 670 data += ARC_REGISTER_SIZE; 671 total_space -= ARC_REGISTER_SIZE; 672 673 /* All the data is now in registers. */ 674 if (total_space == 0) 675 break; 676 677 arg_reg++; 678 } 679 680 /* If there is any data left, push it onto the stack (in a single write 681 operation). */ 682 if (total_space > 0) 683 { 684 if (arc_debug) 685 debug_printf ("arc: passing %d bytes on stack\n", total_space); 686 687 sp -= total_space; 688 write_memory (sp, data, (int) total_space); 689 } 690 691 xfree (memory_image); 692 } 693 694 /* Finally, update the SP register. */ 695 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); 696 697 return sp; 698 } 699 700 /* Implement the "push_dummy_code" gdbarch method. 701 702 We don't actually push any code. We just identify where a breakpoint can 703 be inserted to which we are can return and the resume address where we 704 should be called. 705 706 ARC does not necessarily have an executable stack, so we can't put the 707 return breakpoint there. Instead we put it at the entry point of the 708 function. This means the SP is unchanged. 709 710 SP is a current stack pointer FUNADDR is an address of the function to be 711 called. ARGS is arguments to pass. NARGS is a number of args to pass. 712 VALUE_TYPE is a type of value returned. REAL_PC is a resume address when 713 the function is called. BP_ADDR is an address where breakpoint should be 714 set. Returns the updated stack pointer. */ 715 716 static CORE_ADDR 717 arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, 718 struct value **args, int nargs, struct type *value_type, 719 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 720 struct regcache *regcache) 721 { 722 *real_pc = funaddr; 723 *bp_addr = entry_point_address (); 724 return sp; 725 } 726 727 /* Implement the "cannot_fetch_register" gdbarch method. */ 728 729 static int 730 arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum) 731 { 732 /* Assume that register is readable if it is unknown. LIMM and RESERVED are 733 not real registers, but specific register numbers. They are available as 734 regnums to align architectural register numbers with GDB internal regnums, 735 but they shouldn't appear in target descriptions generated by 736 GDB-servers. */ 737 switch (regnum) 738 { 739 case ARC_RESERVED_REGNUM: 740 case ARC_LIMM_REGNUM: 741 return true; 742 default: 743 return false; 744 } 745 } 746 747 /* Implement the "cannot_store_register" gdbarch method. */ 748 749 static int 750 arc_cannot_store_register (struct gdbarch *gdbarch, int regnum) 751 { 752 /* Assume that register is writable if it is unknown. See comment in 753 arc_cannot_fetch_register about LIMM and RESERVED. */ 754 switch (regnum) 755 { 756 case ARC_RESERVED_REGNUM: 757 case ARC_LIMM_REGNUM: 758 case ARC_PCL_REGNUM: 759 return true; 760 default: 761 return false; 762 } 763 } 764 765 /* Get the return value of a function from the registers/memory used to 766 return it, according to the convention used by the ABI - 4-bytes values are 767 in the R0, while 8-byte values are in the R0-R1. 768 769 TODO: This implementation ignores the case of "complex double", where 770 according to ABI, value is returned in the R0-R3 registers. 771 772 TYPE is a returned value's type. VALBUF is a buffer for the returned 773 value. */ 774 775 static void 776 arc_extract_return_value (struct gdbarch *gdbarch, struct type *type, 777 struct regcache *regcache, gdb_byte *valbuf) 778 { 779 unsigned int len = TYPE_LENGTH (type); 780 781 if (arc_debug) 782 debug_printf ("arc: extract_return_value\n"); 783 784 if (len <= ARC_REGISTER_SIZE) 785 { 786 ULONGEST val; 787 788 /* Get the return value from one register. */ 789 regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &val); 790 store_unsigned_integer (valbuf, (int) len, 791 gdbarch_byte_order (gdbarch), val); 792 793 if (arc_debug) 794 debug_printf ("arc: returning 0x%s\n", phex (val, ARC_REGISTER_SIZE)); 795 } 796 else if (len <= ARC_REGISTER_SIZE * 2) 797 { 798 ULONGEST low, high; 799 800 /* Get the return value from two registers. */ 801 regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &low); 802 regcache_cooked_read_unsigned (regcache, ARC_R1_REGNUM, &high); 803 804 store_unsigned_integer (valbuf, ARC_REGISTER_SIZE, 805 gdbarch_byte_order (gdbarch), low); 806 store_unsigned_integer (valbuf + ARC_REGISTER_SIZE, 807 (int) len - ARC_REGISTER_SIZE, 808 gdbarch_byte_order (gdbarch), high); 809 810 if (arc_debug) 811 debug_printf ("arc: returning 0x%s%s\n", 812 phex (high, ARC_REGISTER_SIZE), 813 phex (low, ARC_REGISTER_SIZE)); 814 } 815 else 816 error (_("arc: extract_return_value: type length %u too large"), len); 817 } 818 819 820 /* Store the return value of a function into the registers/memory used to 821 return it, according to the convention used by the ABI. 822 823 TODO: This implementation ignores the case of "complex double", where 824 according to ABI, value is returned in the R0-R3 registers. 825 826 TYPE is a returned value's type. VALBUF is a buffer with the value to 827 return. */ 828 829 static void 830 arc_store_return_value (struct gdbarch *gdbarch, struct type *type, 831 struct regcache *regcache, const gdb_byte *valbuf) 832 { 833 unsigned int len = TYPE_LENGTH (type); 834 835 if (arc_debug) 836 debug_printf ("arc: store_return_value\n"); 837 838 if (len <= ARC_REGISTER_SIZE) 839 { 840 ULONGEST val; 841 842 /* Put the return value into one register. */ 843 val = extract_unsigned_integer (valbuf, (int) len, 844 gdbarch_byte_order (gdbarch)); 845 regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, val); 846 847 if (arc_debug) 848 debug_printf ("arc: storing 0x%s\n", phex (val, ARC_REGISTER_SIZE)); 849 } 850 else if (len <= ARC_REGISTER_SIZE * 2) 851 { 852 ULONGEST low, high; 853 854 /* Put the return value into two registers. */ 855 low = extract_unsigned_integer (valbuf, ARC_REGISTER_SIZE, 856 gdbarch_byte_order (gdbarch)); 857 high = extract_unsigned_integer (valbuf + ARC_REGISTER_SIZE, 858 (int) len - ARC_REGISTER_SIZE, 859 gdbarch_byte_order (gdbarch)); 860 861 regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, low); 862 regcache_cooked_write_unsigned (regcache, ARC_R1_REGNUM, high); 863 864 if (arc_debug) 865 debug_printf ("arc: storing 0x%s%s\n", 866 phex (high, ARC_REGISTER_SIZE), 867 phex (low, ARC_REGISTER_SIZE)); 868 } 869 else 870 error (_("arc_store_return_value: type length too large.")); 871 } 872 873 /* Implement the "get_longjmp_target" gdbarch method. */ 874 875 static int 876 arc_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 877 { 878 if (arc_debug) 879 debug_printf ("arc: get_longjmp_target\n"); 880 881 struct gdbarch *gdbarch = get_frame_arch (frame); 882 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 883 int pc_offset = tdep->jb_pc * ARC_REGISTER_SIZE; 884 gdb_byte buf[ARC_REGISTER_SIZE]; 885 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, ARC_FIRST_ARG_REGNUM); 886 887 if (target_read_memory (jb_addr + pc_offset, buf, ARC_REGISTER_SIZE)) 888 return 0; /* Failed to read from memory. */ 889 890 *pc = extract_unsigned_integer (buf, ARC_REGISTER_SIZE, 891 gdbarch_byte_order (gdbarch)); 892 return 1; 893 } 894 895 /* Implement the "return_value" gdbarch method. */ 896 897 static enum return_value_convention 898 arc_return_value (struct gdbarch *gdbarch, struct value *function, 899 struct type *valtype, struct regcache *regcache, 900 gdb_byte *readbuf, const gdb_byte *writebuf) 901 { 902 /* If the return type is a struct, or a union, or would occupy more than two 903 registers, the ABI uses the "struct return convention": the calling 904 function passes a hidden first parameter to the callee (in R0). That 905 parameter is the address at which the value being returned should be 906 stored. Otherwise, the result is returned in registers. */ 907 int is_struct_return = (TYPE_CODE (valtype) == TYPE_CODE_STRUCT 908 || TYPE_CODE (valtype) == TYPE_CODE_UNION 909 || TYPE_LENGTH (valtype) > 2 * ARC_REGISTER_SIZE); 910 911 if (arc_debug) 912 debug_printf ("arc: return_value (readbuf = %s, writebuf = %s)\n", 913 host_address_to_string (readbuf), 914 host_address_to_string (writebuf)); 915 916 if (writebuf != NULL) 917 { 918 /* Case 1. GDB should not ask us to set a struct return value: it 919 should know the struct return location and write the value there 920 itself. */ 921 gdb_assert (!is_struct_return); 922 arc_store_return_value (gdbarch, valtype, regcache, writebuf); 923 } 924 else if (readbuf != NULL) 925 { 926 /* Case 2. GDB should not ask us to get a struct return value: it 927 should know the struct return location and read the value from there 928 itself. */ 929 gdb_assert (!is_struct_return); 930 arc_extract_return_value (gdbarch, valtype, regcache, readbuf); 931 } 932 933 return (is_struct_return 934 ? RETURN_VALUE_STRUCT_CONVENTION 935 : RETURN_VALUE_REGISTER_CONVENTION); 936 } 937 938 /* Return the base address of the frame. For ARC, the base address is the 939 frame pointer. */ 940 941 static CORE_ADDR 942 arc_frame_base_address (struct frame_info *this_frame, void **prologue_cache) 943 { 944 return (CORE_ADDR) get_frame_register_unsigned (this_frame, ARC_FP_REGNUM); 945 } 946 947 /* Helper function that returns valid pv_t for an instruction operand: 948 either a register or a constant. */ 949 950 static pv_t 951 arc_pv_get_operand (pv_t *regs, const struct arc_instruction &insn, int operand) 952 { 953 if (insn.operands[operand].kind == ARC_OPERAND_KIND_REG) 954 return regs[insn.operands[operand].value]; 955 else 956 return pv_constant (arc_insn_get_operand_value (insn, operand)); 957 } 958 959 /* Determine whether the given disassembled instruction may be part of a 960 function prologue. If it is, the information in the frame unwind cache will 961 be updated. */ 962 963 static bool 964 arc_is_in_prologue (struct gdbarch *gdbarch, const struct arc_instruction &insn, 965 pv_t *regs, struct pv_area *stack) 966 { 967 /* It might be that currently analyzed address doesn't contain an 968 instruction, hence INSN is not valid. It likely means that address points 969 to a data, non-initialized memory, or middle of a 32-bit instruction. In 970 practice this may happen if GDB connects to a remote target that has 971 non-zeroed memory. GDB would read PC value and would try to analyze 972 prologue, but there is no guarantee that memory contents at the address 973 specified in PC is address is a valid instruction. There is not much that 974 that can be done about that. */ 975 if (!insn.valid) 976 return false; 977 978 /* Branch/jump or a predicated instruction. */ 979 if (insn.is_control_flow || insn.condition_code != ARC_CC_AL) 980 return false; 981 982 /* Store of some register. May or may not update base address register. */ 983 if (insn.insn_class == STORE || insn.insn_class == PUSH) 984 { 985 /* There is definetely at least one operand - register/value being 986 stored. */ 987 gdb_assert (insn.operands_count > 0); 988 989 /* Store at some constant address. */ 990 if (insn.operands_count > 1 991 && insn.operands[1].kind != ARC_OPERAND_KIND_REG) 992 return false; 993 994 /* Writeback modes: 995 Mode Address used Writeback value 996 -------------------------------------------------- 997 No reg + offset no 998 A/AW reg + offset reg + offset 999 AB reg reg + offset 1000 AS reg + (offset << scaling) no 1001 1002 "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However 1003 16-bit PUSH_S is a distinct instruction encoding, where offset and 1004 base register are implied through opcode. */ 1005 1006 /* Register with base memory address. */ 1007 int base_reg = arc_insn_get_memory_base_reg (insn); 1008 1009 /* Address where to write. arc_insn_get_memory_offset returns scaled 1010 value for ARC_WRITEBACK_AS. */ 1011 pv_t addr; 1012 if (insn.writeback_mode == ARC_WRITEBACK_AB) 1013 addr = regs[base_reg]; 1014 else 1015 addr = pv_add_constant (regs[base_reg], 1016 arc_insn_get_memory_offset (insn)); 1017 1018 if (stack->store_would_trash (addr)) 1019 return false; 1020 1021 if (insn.data_size_mode != ARC_SCALING_D) 1022 { 1023 /* Find the value being stored. */ 1024 pv_t store_value = arc_pv_get_operand (regs, insn, 0); 1025 1026 /* What is the size of a the stored value? */ 1027 CORE_ADDR size; 1028 if (insn.data_size_mode == ARC_SCALING_B) 1029 size = 1; 1030 else if (insn.data_size_mode == ARC_SCALING_H) 1031 size = 2; 1032 else 1033 size = ARC_REGISTER_SIZE; 1034 1035 stack->store (addr, size, store_value); 1036 } 1037 else 1038 { 1039 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) 1040 { 1041 /* If this is a double store, than write N+1 register as well. */ 1042 pv_t store_value1 = regs[insn.operands[0].value]; 1043 pv_t store_value2 = regs[insn.operands[0].value + 1]; 1044 stack->store (addr, ARC_REGISTER_SIZE, store_value1); 1045 stack->store (pv_add_constant (addr, ARC_REGISTER_SIZE), 1046 ARC_REGISTER_SIZE, store_value2); 1047 } 1048 else 1049 { 1050 pv_t store_value 1051 = pv_constant (arc_insn_get_operand_value (insn, 0)); 1052 stack->store (addr, ARC_REGISTER_SIZE * 2, store_value); 1053 } 1054 } 1055 1056 /* Is base register updated? */ 1057 if (insn.writeback_mode == ARC_WRITEBACK_A 1058 || insn.writeback_mode == ARC_WRITEBACK_AB) 1059 regs[base_reg] = pv_add_constant (regs[base_reg], 1060 arc_insn_get_memory_offset (insn)); 1061 1062 return true; 1063 } 1064 else if (insn.insn_class == MOVE) 1065 { 1066 gdb_assert (insn.operands_count == 2); 1067 1068 /* Destination argument can be "0", so nothing will happen. */ 1069 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) 1070 { 1071 int dst_regnum = insn.operands[0].value; 1072 regs[dst_regnum] = arc_pv_get_operand (regs, insn, 1); 1073 } 1074 return true; 1075 } 1076 else if (insn.insn_class == SUB) 1077 { 1078 gdb_assert (insn.operands_count == 3); 1079 1080 /* SUB 0,b,c. */ 1081 if (insn.operands[0].kind != ARC_OPERAND_KIND_REG) 1082 return true; 1083 1084 int dst_regnum = insn.operands[0].value; 1085 regs[dst_regnum] = pv_subtract (arc_pv_get_operand (regs, insn, 1), 1086 arc_pv_get_operand (regs, insn, 2)); 1087 return true; 1088 } 1089 else if (insn.insn_class == ENTER) 1090 { 1091 /* ENTER_S is a prologue-in-instruction - it saves all callee-saved 1092 registers according to given arguments thus greatly reducing code 1093 size. Which registers will be actually saved depends on arguments. 1094 1095 ENTER_S {R13-...,FP,BLINK} stores registers in following order: 1096 1097 new SP -> 1098 BLINK 1099 R13 1100 R14 1101 R15 1102 ... 1103 FP 1104 old SP -> 1105 1106 There are up to three arguments for this opcode, as presented by ARC 1107 disassembler: 1108 1) amount of general-purpose registers to be saved - this argument is 1109 always present even when it is 0; 1110 2) FP register number (27) if FP has to be stored, otherwise argument 1111 is not present; 1112 3) BLINK register number (31) if BLINK has to be stored, otherwise 1113 argument is not present. If both FP and BLINK are stored, then FP 1114 is present before BLINK in argument list. */ 1115 gdb_assert (insn.operands_count > 0); 1116 1117 int regs_saved = arc_insn_get_operand_value (insn, 0); 1118 1119 bool is_fp_saved; 1120 if (insn.operands_count > 1) 1121 is_fp_saved = (insn.operands[1].value == ARC_FP_REGNUM); 1122 else 1123 is_fp_saved = false; 1124 1125 bool is_blink_saved; 1126 if (insn.operands_count > 1) 1127 is_blink_saved = (insn.operands[insn.operands_count - 1].value 1128 == ARC_BLINK_REGNUM); 1129 else 1130 is_blink_saved = false; 1131 1132 /* Amount of bytes to be allocated to store specified registers. */ 1133 CORE_ADDR st_size = ((regs_saved + is_fp_saved + is_blink_saved) 1134 * ARC_REGISTER_SIZE); 1135 pv_t new_sp = pv_add_constant (regs[ARC_SP_REGNUM], -st_size); 1136 1137 /* Assume that if the last register (closest to new SP) can be written, 1138 then it is possible to write all of them. */ 1139 if (stack->store_would_trash (new_sp)) 1140 return false; 1141 1142 /* Current store address. */ 1143 pv_t addr = regs[ARC_SP_REGNUM]; 1144 1145 if (is_fp_saved) 1146 { 1147 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); 1148 stack->store (addr, ARC_REGISTER_SIZE, regs[ARC_FP_REGNUM]); 1149 } 1150 1151 /* Registers are stored in backward order: from GP (R26) to R13. */ 1152 for (int i = ARC_R13_REGNUM + regs_saved - 1; i >= ARC_R13_REGNUM; i--) 1153 { 1154 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); 1155 stack->store (addr, ARC_REGISTER_SIZE, regs[i]); 1156 } 1157 1158 if (is_blink_saved) 1159 { 1160 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); 1161 stack->store (addr, ARC_REGISTER_SIZE, 1162 regs[ARC_BLINK_REGNUM]); 1163 } 1164 1165 gdb_assert (pv_is_identical (addr, new_sp)); 1166 1167 regs[ARC_SP_REGNUM] = new_sp; 1168 1169 if (is_fp_saved) 1170 regs[ARC_FP_REGNUM] = regs[ARC_SP_REGNUM]; 1171 1172 return true; 1173 } 1174 1175 /* Some other architectures, like nds32 or arm, try to continue as far as 1176 possible when building a prologue cache (as opposed to when skipping 1177 prologue), so that cache will be as full as possible. However current 1178 code for ARC doesn't recognize some instructions that may modify SP, like 1179 ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't 1180 clobbered by the skipped instruction. Potential existence of extension 1181 instruction, which may do anything they want makes this even more complex, 1182 so it is just better to halt on a first unrecognized instruction. */ 1183 1184 return false; 1185 } 1186 1187 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */ 1188 1189 static int ATTRIBUTE_PRINTF (2, 3) 1190 arc_fprintf_disasm (void *stream, const char *format, ...) 1191 { 1192 return 0; 1193 } 1194 1195 struct disassemble_info 1196 arc_disassemble_info (struct gdbarch *gdbarch) 1197 { 1198 struct disassemble_info di; 1199 init_disassemble_info (&di, &null_stream, arc_fprintf_disasm); 1200 di.arch = gdbarch_bfd_arch_info (gdbarch)->arch; 1201 di.mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1202 di.endian = gdbarch_byte_order (gdbarch); 1203 di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr, 1204 unsigned int len, struct disassemble_info *info) 1205 { 1206 return target_read_code (memaddr, myaddr, len); 1207 }; 1208 return di; 1209 } 1210 1211 /* Analyze the prologue and update the corresponding frame cache for the frame 1212 unwinder for unwinding frames that doesn't have debug info. In such 1213 situation GDB attempts to parse instructions in the prologue to understand 1214 where each register is saved. 1215 1216 If CACHE is not NULL, then it will be filled with information about saved 1217 registers. 1218 1219 There are several variations of prologue which GDB may encouter. "Full" 1220 prologue looks like this: 1221 1222 sub sp,sp,<imm> ; Space for variadic arguments. 1223 push blink ; Store return address. 1224 push r13 ; Store callee saved registers (up to R26/GP). 1225 push r14 1226 push fp ; Store frame pointer. 1227 mov fp,sp ; Update frame pointer. 1228 sub sp,sp,<imm> ; Create space for local vars on the stack. 1229 1230 Depending on compiler options lots of things may change: 1231 1232 1) BLINK is not saved in leaf functions. 1233 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used. 1234 3) 16-bit versions of those instructions may be used. 1235 4) Instead of a sequence of several push'es, compiler may instead prefer to 1236 do one subtract on stack pointer and then store registers using normal 1237 store, that doesn't update SP. Like this: 1238 1239 1240 sub sp,sp,8 ; Create space for calee-saved registers. 1241 st r13,[sp,4] ; Store callee saved registers (up to R26/GP). 1242 st r14,[sp,0] 1243 1244 5) ENTER_S instruction can encode most of prologue sequence in one 1245 instruction (except for those subtracts for variadic arguments and local 1246 variables). 1247 6) GCC may use "millicode" functions from libgcc to store callee-saved 1248 registers with minimal code-size requirements. This function currently 1249 doesn't support this. 1250 1251 ENTRYPOINT is a function entry point where prologue starts. 1252 1253 LIMIT_PC is a maximum possible end address of prologue (meaning address 1254 of first instruction after the prologue). It might also point to the middle 1255 of prologue if execution has been stopped by the breakpoint at this address 1256 - in this case debugger should analyze prologue only up to this address, 1257 because further instructions haven't been executed yet. 1258 1259 Returns address of the first instruction after the prologue. */ 1260 1261 static CORE_ADDR 1262 arc_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR entrypoint, 1263 const CORE_ADDR limit_pc, struct arc_frame_cache *cache) 1264 { 1265 if (arc_debug) 1266 debug_printf ("arc: analyze_prologue (entrypoint=%s, limit_pc=%s)\n", 1267 paddress (gdbarch, entrypoint), 1268 paddress (gdbarch, limit_pc)); 1269 1270 /* Prologue values. Only core registers can be stored. */ 1271 pv_t regs[ARC_LAST_CORE_REGNUM + 1]; 1272 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) 1273 regs[i] = pv_register (i, 0); 1274 pv_area stack (ARC_SP_REGNUM, gdbarch_addr_bit (gdbarch)); 1275 1276 CORE_ADDR current_prologue_end = entrypoint; 1277 1278 /* Look at each instruction in the prologue. */ 1279 while (current_prologue_end < limit_pc) 1280 { 1281 struct arc_instruction insn; 1282 struct disassemble_info di = arc_disassemble_info (gdbarch); 1283 arc_insn_decode (current_prologue_end, &di, arc_delayed_print_insn, 1284 &insn); 1285 1286 if (arc_debug >= 2) 1287 arc_insn_dump (insn); 1288 1289 /* If this instruction is in the prologue, fields in the cache will be 1290 updated, and the saved registers mask may be updated. */ 1291 if (!arc_is_in_prologue (gdbarch, insn, regs, &stack)) 1292 { 1293 /* Found an instruction that is not in the prologue. */ 1294 if (arc_debug) 1295 debug_printf ("arc: End of prologue reached at address %s\n", 1296 paddress (gdbarch, insn.address)); 1297 break; 1298 } 1299 1300 current_prologue_end = arc_insn_get_linear_next_pc (insn); 1301 } 1302 1303 if (cache != NULL) 1304 { 1305 /* Figure out if it is a frame pointer or just a stack pointer. */ 1306 if (pv_is_register (regs[ARC_FP_REGNUM], ARC_SP_REGNUM)) 1307 { 1308 cache->frame_base_reg = ARC_FP_REGNUM; 1309 cache->frame_base_offset = -regs[ARC_FP_REGNUM].k; 1310 } 1311 else 1312 { 1313 cache->frame_base_reg = ARC_SP_REGNUM; 1314 cache->frame_base_offset = -regs[ARC_SP_REGNUM].k; 1315 } 1316 1317 /* Assign offset from old SP to all saved registers. */ 1318 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) 1319 { 1320 CORE_ADDR offset; 1321 if (stack.find_reg (gdbarch, i, &offset)) 1322 cache->saved_regs[i].addr = offset; 1323 } 1324 } 1325 1326 return current_prologue_end; 1327 } 1328 1329 /* Estimated maximum prologue length in bytes. This should include: 1330 1) Store instruction for each callee-saved register (R25 - R13 + 1) 1331 2) Two instructions for FP 1332 3) One for BLINK 1333 4) Three substract instructions for SP (for variadic args, for 1334 callee saved regs and for local vars) and assuming that those SUB use 1335 long-immediate (hence double length). 1336 5) Stores of arguments registers are considered part of prologue too 1337 (R7 - R1 + 1). 1338 This is quite an extreme case, because even with -O0 GCC will collapse first 1339 two SUBs into one and long immediate values are quite unlikely to appear in 1340 this case, but still better to overshoot a bit - prologue analysis will 1341 anyway stop at the first instruction that doesn't fit prologue, so this 1342 limit will be rarely reached. */ 1343 1344 const static int MAX_PROLOGUE_LENGTH 1345 = 4 * (ARC_R25_REGNUM - ARC_R13_REGNUM + 1 + 2 + 1 + 6 1346 + ARC_LAST_ARG_REGNUM - ARC_FIRST_ARG_REGNUM + 1); 1347 1348 /* Implement the "skip_prologue" gdbarch method. 1349 1350 Skip the prologue for the function at PC. This is done by checking from 1351 the line information read from the DWARF, if possible; otherwise, we scan 1352 the function prologue to find its end. */ 1353 1354 static CORE_ADDR 1355 arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1356 { 1357 if (arc_debug) 1358 debug_printf ("arc: skip_prologue\n"); 1359 1360 CORE_ADDR func_addr; 1361 const char *func_name; 1362 1363 /* See what the symbol table says. */ 1364 if (find_pc_partial_function (pc, &func_name, &func_addr, NULL)) 1365 { 1366 /* Found a function. */ 1367 CORE_ADDR postprologue_pc 1368 = skip_prologue_using_sal (gdbarch, func_addr); 1369 1370 if (postprologue_pc != 0) 1371 return std::max (pc, postprologue_pc); 1372 } 1373 1374 /* No prologue info in symbol table, have to analyze prologue. */ 1375 1376 /* Find an upper limit on the function prologue using the debug 1377 information. If there is no debug information about prologue end, then 1378 skip_prologue_using_sal will return 0. */ 1379 CORE_ADDR limit_pc = skip_prologue_using_sal (gdbarch, pc); 1380 1381 /* If there is no debug information at all, it is required to give some 1382 semi-arbitrary hard limit on amount of bytes to scan during prologue 1383 analysis. */ 1384 if (limit_pc == 0) 1385 limit_pc = pc + MAX_PROLOGUE_LENGTH; 1386 1387 /* Find the address of the first instruction after the prologue by scanning 1388 through it - no other information is needed, so pass NULL as a cache. */ 1389 return arc_analyze_prologue (gdbarch, pc, limit_pc, NULL); 1390 } 1391 1392 /* Implement the "print_insn" gdbarch method. 1393 1394 arc_get_disassembler () may return different functions depending on bfd 1395 type, so it is not possible to pass print_insn directly to 1396 set_gdbarch_print_insn (). Instead this wrapper function is used. It also 1397 may be used by other functions to get disassemble_info for address. It is 1398 important to note, that those print_insn from opcodes always print 1399 instruction to the stream specified in the INFO. If this is not desired, 1400 then either `print_insn` function in INFO should be set to some function 1401 that will not print, or `stream` should be different from standard 1402 gdb_stdlog. */ 1403 1404 int 1405 arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info) 1406 { 1407 /* Standard BFD "machine number" field allows libocodes disassembler to 1408 distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM 1409 and HS, which have some difference between. There are two ways to specify 1410 what is the target core: 1411 1) via the disassemble_info->disassembler_options; 1412 2) otherwise libopcodes will use private (architecture-specific) ELF 1413 header. 1414 1415 Using disassembler_options is preferable, because it comes directly from 1416 GDBserver which scanned an actual ARC core identification info. However, 1417 not all GDBservers report core architecture, so as a fallback GDB still 1418 should support analysis of ELF header. The libopcodes disassembly code 1419 uses the section to find the BFD and the BFD to find the ELF header, 1420 therefore this function should set disassemble_info->section properly. 1421 1422 disassembler_options was already set by non-target specific code with 1423 proper options obtained via gdbarch_disassembler_options (). 1424 1425 This function might be called multiple times in a sequence, reusing same 1426 disassemble_info. */ 1427 if ((info->disassembler_options == NULL) && (info->section == NULL)) 1428 { 1429 struct obj_section *s = find_pc_section (addr); 1430 if (s != NULL) 1431 info->section = s->the_bfd_section; 1432 } 1433 1434 return default_print_insn (addr, info); 1435 } 1436 1437 /* Baremetal breakpoint instructions. 1438 1439 ARC supports both big- and little-endian. However, instructions for 1440 little-endian processors are encoded in the middle-endian: half-words are 1441 in big-endian, while bytes inside the half-words are in little-endian; data 1442 is represented in the "normal" little-endian. Big-endian processors treat 1443 data and code identically. 1444 1445 Assuming the number 0x01020304, it will be presented this way: 1446 1447 Address : N N+1 N+2 N+3 1448 little-endian : 0x04 0x03 0x02 0x01 1449 big-endian : 0x01 0x02 0x03 0x04 1450 ARC middle-endian : 0x02 0x01 0x04 0x03 1451 */ 1452 1453 static const gdb_byte arc_brk_s_be[] = { 0x7f, 0xff }; 1454 static const gdb_byte arc_brk_s_le[] = { 0xff, 0x7f }; 1455 static const gdb_byte arc_brk_be[] = { 0x25, 0x6f, 0x00, 0x3f }; 1456 static const gdb_byte arc_brk_le[] = { 0x6f, 0x25, 0x3f, 0x00 }; 1457 1458 /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff 1459 (little endian) or 0xff7f (big endian). We used to insert BRK_S even 1460 instead of 32-bit instructions, which works mostly ok, unless breakpoint is 1461 inserted into delay slot instruction. In this case if branch is taken 1462 BLINK value will be set to address of instruction after delay slot, however 1463 if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S, 1464 then BLINK value will have an invalid value - it will point to the address 1465 after the BRK_S (which was there at the moment of branch execution) while 1466 it should point to the address after the 32-bit long instruction. To avoid 1467 such issues this function disassembles instruction at target location and 1468 evaluates it value. 1469 1470 ARC 600 supports only 16-bit BRK_S. 1471 1472 NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S] 1473 is much better because it doesn't commit unlike TRAP_S, so it can be set in 1474 delay slots; however it cannot be used in user-mode, hence usage of TRAP_S 1475 in GDB for user-space. */ 1476 1477 /* Implement the "breakpoint_kind_from_pc" gdbarch method. */ 1478 1479 static int 1480 arc_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 1481 { 1482 size_t length_with_limm = gdb_insn_length (gdbarch, *pcptr); 1483 1484 /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with 1485 BRK. LIMM is part of instruction length, so it can be either 4 or 8 1486 bytes for 32-bit instructions. */ 1487 if ((length_with_limm == 4 || length_with_limm == 8) 1488 && !arc_mach_is_arc600 (gdbarch)) 1489 return sizeof (arc_brk_le); 1490 else 1491 return sizeof (arc_brk_s_le); 1492 } 1493 1494 /* Implement the "sw_breakpoint_from_kind" gdbarch method. */ 1495 1496 static const gdb_byte * 1497 arc_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 1498 { 1499 *size = kind; 1500 1501 if (kind == sizeof (arc_brk_le)) 1502 { 1503 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1504 ? arc_brk_be 1505 : arc_brk_le); 1506 } 1507 else 1508 { 1509 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1510 ? arc_brk_s_be 1511 : arc_brk_s_le); 1512 } 1513 } 1514 1515 /* Implement the "unwind_pc" gdbarch method. */ 1516 1517 static CORE_ADDR 1518 arc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1519 { 1520 int pc_regnum = gdbarch_pc_regnum (gdbarch); 1521 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, pc_regnum); 1522 1523 if (arc_debug) 1524 debug_printf ("arc: unwind PC: %s\n", paddress (gdbarch, pc)); 1525 1526 return pc; 1527 } 1528 1529 /* Implement the "unwind_sp" gdbarch method. */ 1530 1531 static CORE_ADDR 1532 arc_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1533 { 1534 int sp_regnum = gdbarch_sp_regnum (gdbarch); 1535 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, sp_regnum); 1536 1537 if (arc_debug) 1538 debug_printf ("arc: unwind SP: %s\n", paddress (gdbarch, sp)); 1539 1540 return sp; 1541 } 1542 1543 /* Implement the "frame_align" gdbarch method. */ 1544 1545 static CORE_ADDR 1546 arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1547 { 1548 return align_down (sp, 4); 1549 } 1550 1551 /* Dump the frame info. Used for internal debugging only. */ 1552 1553 static void 1554 arc_print_frame_cache (struct gdbarch *gdbarch, const char *message, 1555 struct arc_frame_cache *cache, int addresses_known) 1556 { 1557 debug_printf ("arc: frame_info %s\n", message); 1558 debug_printf ("arc: prev_sp = %s\n", paddress (gdbarch, cache->prev_sp)); 1559 debug_printf ("arc: frame_base_reg = %i\n", cache->frame_base_reg); 1560 debug_printf ("arc: frame_base_offset = %s\n", 1561 plongest (cache->frame_base_offset)); 1562 1563 for (int i = 0; i <= ARC_BLINK_REGNUM; i++) 1564 { 1565 if (trad_frame_addr_p (cache->saved_regs, i)) 1566 debug_printf ("arc: saved register %s at %s %s\n", 1567 gdbarch_register_name (gdbarch, i), 1568 (addresses_known) ? "address" : "offset", 1569 paddress (gdbarch, cache->saved_regs[i].addr)); 1570 } 1571 } 1572 1573 /* Frame unwinder for normal frames. */ 1574 1575 static struct arc_frame_cache * 1576 arc_make_frame_cache (struct frame_info *this_frame) 1577 { 1578 if (arc_debug) 1579 debug_printf ("arc: frame_cache\n"); 1580 1581 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1582 1583 CORE_ADDR block_addr = get_frame_address_in_block (this_frame); 1584 CORE_ADDR entrypoint, prologue_end; 1585 if (find_pc_partial_function (block_addr, NULL, &entrypoint, &prologue_end)) 1586 { 1587 struct symtab_and_line sal = find_pc_line (entrypoint, 0); 1588 CORE_ADDR prev_pc = get_frame_pc (this_frame); 1589 if (sal.line == 0) 1590 /* No line info so use current PC. */ 1591 prologue_end = prev_pc; 1592 else if (sal.end < prologue_end) 1593 /* The next line begins after the function end. */ 1594 prologue_end = sal.end; 1595 1596 prologue_end = std::min (prologue_end, prev_pc); 1597 } 1598 else 1599 { 1600 /* If find_pc_partial_function returned nothing then there is no symbol 1601 information at all for this PC. Currently it is assumed in this case 1602 that current PC is entrypoint to function and try to construct the 1603 frame from that. This is, probably, suboptimal, for example ARM 1604 assumes in this case that program is inside the normal frame (with 1605 frame pointer). ARC, perhaps, should try to do the same. */ 1606 entrypoint = get_frame_register_unsigned (this_frame, 1607 gdbarch_pc_regnum (gdbarch)); 1608 prologue_end = entrypoint + MAX_PROLOGUE_LENGTH; 1609 } 1610 1611 /* Allocate new frame cache instance and space for saved register info. 1612 FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */ 1613 struct arc_frame_cache *cache 1614 = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache); 1615 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 1616 1617 arc_analyze_prologue (gdbarch, entrypoint, prologue_end, cache); 1618 1619 if (arc_debug) 1620 arc_print_frame_cache (gdbarch, "after prologue", cache, false); 1621 1622 CORE_ADDR unwound_fb = get_frame_register_unsigned (this_frame, 1623 cache->frame_base_reg); 1624 if (unwound_fb == 0) 1625 return cache; 1626 cache->prev_sp = unwound_fb + cache->frame_base_offset; 1627 1628 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) 1629 { 1630 if (trad_frame_addr_p (cache->saved_regs, i)) 1631 cache->saved_regs[i].addr += cache->prev_sp; 1632 } 1633 1634 if (arc_debug) 1635 arc_print_frame_cache (gdbarch, "after previous SP found", cache, true); 1636 1637 return cache; 1638 } 1639 1640 /* Implement the "this_id" frame_unwind method. */ 1641 1642 static void 1643 arc_frame_this_id (struct frame_info *this_frame, void **this_cache, 1644 struct frame_id *this_id) 1645 { 1646 if (arc_debug) 1647 debug_printf ("arc: frame_this_id\n"); 1648 1649 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1650 1651 if (*this_cache == NULL) 1652 *this_cache = arc_make_frame_cache (this_frame); 1653 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); 1654 1655 CORE_ADDR stack_addr = cache->prev_sp; 1656 1657 /* There are 4 possible situation which decide how frame_id->code_addr is 1658 evaluated: 1659 1660 1) Function is compiled with option -g. Then frame_id will be created 1661 in dwarf_* function and not in this function. NB: even if target 1662 binary is compiled with -g, some std functions like __start and _init 1663 are not, so they still will follow one of the following choices. 1664 1665 2) Function is compiled without -g and binary hasn't been stripped in 1666 any way. In this case GDB still has enough information to evaluate 1667 frame code_addr properly. This case is covered by call to 1668 get_frame_func (). 1669 1670 3) Binary has been striped with option -g (strip debug symbols). In 1671 this case there is still enough symbols for get_frame_func () to work 1672 properly, so this case is also covered by it. 1673 1674 4) Binary has been striped with option -s (strip all symbols). In this 1675 case GDB cannot get function start address properly, so we return current 1676 PC value instead. 1677 */ 1678 CORE_ADDR code_addr = get_frame_func (this_frame); 1679 if (code_addr == 0) 1680 code_addr = get_frame_register_unsigned (this_frame, 1681 gdbarch_pc_regnum (gdbarch)); 1682 1683 *this_id = frame_id_build (stack_addr, code_addr); 1684 } 1685 1686 /* Implement the "prev_register" frame_unwind method. */ 1687 1688 static struct value * 1689 arc_frame_prev_register (struct frame_info *this_frame, 1690 void **this_cache, int regnum) 1691 { 1692 if (*this_cache == NULL) 1693 *this_cache = arc_make_frame_cache (this_frame); 1694 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); 1695 1696 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1697 1698 /* If we are asked to unwind the PC, then we need to return BLINK instead: 1699 the saved value of PC points into this frame's function's prologue, not 1700 the next frame's function's resume location. */ 1701 if (regnum == gdbarch_pc_regnum (gdbarch)) 1702 regnum = ARC_BLINK_REGNUM; 1703 1704 /* SP is a special case - we should return prev_sp, because 1705 trad_frame_get_prev_register will return _current_ SP value. 1706 Alternatively we could have stored cache->prev_sp in the cache->saved 1707 regs, but here we follow the lead of AArch64, ARM and Xtensa and will 1708 leave that logic in this function, instead of prologue analyzers. That I 1709 think is a bit more clear as `saved_regs` should contain saved regs, not 1710 computable. 1711 1712 Because value has been computed, "got_constant" should be used, so that 1713 returned value will be a "not_lval" - immutable. */ 1714 1715 if (regnum == gdbarch_sp_regnum (gdbarch)) 1716 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp); 1717 1718 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum); 1719 } 1720 1721 /* Implement the "init_reg" dwarf2_frame method. */ 1722 1723 static void 1724 arc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1725 struct dwarf2_frame_state_reg *reg, 1726 struct frame_info *info) 1727 { 1728 if (regnum == gdbarch_pc_regnum (gdbarch)) 1729 /* The return address column. */ 1730 reg->how = DWARF2_FRAME_REG_RA; 1731 else if (regnum == gdbarch_sp_regnum (gdbarch)) 1732 /* The call frame address. */ 1733 reg->how = DWARF2_FRAME_REG_CFA; 1734 } 1735 1736 /* Structure defining the ARC ordinary frame unwind functions. Since we are 1737 the fallback unwinder, we use the default frame sniffer, which always 1738 accepts the frame. */ 1739 1740 static const struct frame_unwind arc_frame_unwind = { 1741 NORMAL_FRAME, 1742 default_frame_unwind_stop_reason, 1743 arc_frame_this_id, 1744 arc_frame_prev_register, 1745 NULL, 1746 default_frame_sniffer, 1747 NULL, 1748 NULL 1749 }; 1750 1751 1752 static const struct frame_base arc_normal_base = { 1753 &arc_frame_unwind, 1754 arc_frame_base_address, 1755 arc_frame_base_address, 1756 arc_frame_base_address 1757 }; 1758 1759 /* Initialize target description for the ARC. 1760 1761 Returns TRUE if input tdesc was valid and in this case it will assign TDESC 1762 and TDESC_DATA output parameters. */ 1763 1764 static int 1765 arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc, 1766 struct tdesc_arch_data **tdesc_data) 1767 { 1768 if (arc_debug) 1769 debug_printf ("arc: Target description initialization.\n"); 1770 1771 const struct target_desc *tdesc_loc = info.target_desc; 1772 1773 /* Depending on whether this is ARCompact or ARCv2 we will assign 1774 different default registers sets (which will differ in exactly two core 1775 registers). GDB will also refuse to accept register feature from invalid 1776 ISA - v2 features can be used only with v2 ARChitecture. We read 1777 bfd_arch_info, which looks like to be a safe bet here, as it looks like it 1778 is always initialized even when we don't pass any elf file to GDB at all 1779 (it uses default arch in this case). Also GDB will call this function 1780 multiple times, and if XML target description file contains architecture 1781 specifications, then GDB will set this architecture to info.bfd_arch_info, 1782 overriding value from ELF file if they are different. That means that, 1783 where matters, this value is always our best guess on what CPU we are 1784 debugging. It has been noted that architecture specified in tdesc file 1785 has higher precedence over ELF and even "set architecture" - that is, 1786 using "set architecture" command will have no effect when tdesc has "arch" 1787 tag. */ 1788 /* Cannot use arc_mach_is_arcv2 (), because gdbarch is not created yet. */ 1789 const int is_arcv2 = (info.bfd_arch_info->mach == bfd_mach_arc_arcv2); 1790 int is_reduced_rf; 1791 const char *const *core_regs; 1792 const char *core_feature_name; 1793 1794 /* If target doesn't provide a description - use default one. */ 1795 if (!tdesc_has_registers (tdesc_loc)) 1796 { 1797 if (is_arcv2) 1798 { 1799 tdesc_loc = tdesc_arc_v2; 1800 if (arc_debug) 1801 debug_printf ("arc: Using default register set for ARC v2.\n"); 1802 } 1803 else 1804 { 1805 tdesc_loc = tdesc_arc_arcompact; 1806 if (arc_debug) 1807 debug_printf ("arc: Using default register set for ARCompact.\n"); 1808 } 1809 } 1810 else 1811 { 1812 if (arc_debug) 1813 debug_printf ("arc: Using provided register set.\n"); 1814 } 1815 gdb_assert (tdesc_loc != NULL); 1816 1817 /* Now we can search for base registers. Core registers can be either full 1818 or reduced. Summary: 1819 1820 - core.v2 + aux-minimal 1821 - core-reduced.v2 + aux-minimal 1822 - core.arcompact + aux-minimal 1823 1824 NB: It is entirely feasible to have ARCompact with reduced core regs, but 1825 we ignore that because GCC doesn't support that and at the same time 1826 ARCompact is considered obsolete, so there is not much reason to support 1827 that. */ 1828 const struct tdesc_feature *feature 1829 = tdesc_find_feature (tdesc_loc, core_v2_feature_name); 1830 if (feature != NULL) 1831 { 1832 /* Confirm that register and architecture match, to prevent accidents in 1833 some situations. This code will trigger an error if: 1834 1835 1. XML tdesc doesn't specify arch explicitly, registers are for arch 1836 X, but ELF specifies arch Y. 1837 1838 2. XML tdesc specifies arch X, but contains registers for arch Y. 1839 1840 It will not protect from case where XML or ELF specify arch X, 1841 registers are for the same arch X, but the real target is arch Y. To 1842 detect this case we need to check IDENTITY register. */ 1843 if (!is_arcv2) 1844 { 1845 arc_print (_("Error: ARC v2 target description supplied for " 1846 "non-ARCv2 target.\n")); 1847 return FALSE; 1848 } 1849 1850 is_reduced_rf = FALSE; 1851 core_feature_name = core_v2_feature_name; 1852 core_regs = core_v2_register_names; 1853 } 1854 else 1855 { 1856 feature = tdesc_find_feature (tdesc_loc, core_reduced_v2_feature_name); 1857 if (feature != NULL) 1858 { 1859 if (!is_arcv2) 1860 { 1861 arc_print (_("Error: ARC v2 target description supplied for " 1862 "non-ARCv2 target.\n")); 1863 return FALSE; 1864 } 1865 1866 is_reduced_rf = TRUE; 1867 core_feature_name = core_reduced_v2_feature_name; 1868 core_regs = core_v2_register_names; 1869 } 1870 else 1871 { 1872 feature = tdesc_find_feature (tdesc_loc, 1873 core_arcompact_feature_name); 1874 if (feature != NULL) 1875 { 1876 if (is_arcv2) 1877 { 1878 arc_print (_("Error: ARCompact target description supplied " 1879 "for non-ARCompact target.\n")); 1880 return FALSE; 1881 } 1882 1883 is_reduced_rf = FALSE; 1884 core_feature_name = core_arcompact_feature_name; 1885 core_regs = core_arcompact_register_names; 1886 } 1887 else 1888 { 1889 arc_print (_("Error: Couldn't find core register feature in " 1890 "supplied target description.")); 1891 return FALSE; 1892 } 1893 } 1894 } 1895 1896 struct tdesc_arch_data *tdesc_data_loc = tdesc_data_alloc (); 1897 1898 gdb_assert (feature != NULL); 1899 int valid_p = 1; 1900 1901 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) 1902 { 1903 /* If rf16, then skip extra registers. */ 1904 if (is_reduced_rf && ((i >= ARC_R4_REGNUM && i <= ARC_R9_REGNUM) 1905 || (i >= ARC_R16_REGNUM && i <= ARC_R25_REGNUM))) 1906 continue; 1907 1908 valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, 1909 core_regs[i]); 1910 1911 /* - Ignore errors in extension registers - they are optional. 1912 - Ignore missing ILINK because it doesn't make sense for Linux. 1913 - Ignore missing ILINK2 when architecture is ARCompact, because it 1914 doesn't make sense for Linux targets. 1915 1916 In theory those optional registers should be in separate features, but 1917 that would create numerous but tiny features, which looks like an 1918 overengineering of a rather simple task. */ 1919 if (!valid_p && (i <= ARC_SP_REGNUM || i == ARC_BLINK_REGNUM 1920 || i == ARC_LP_COUNT_REGNUM || i == ARC_PCL_REGNUM 1921 || (i == ARC_R30_REGNUM && is_arcv2))) 1922 { 1923 arc_print (_("Error: Cannot find required register `%s' in " 1924 "feature `%s'.\n"), core_regs[i], core_feature_name); 1925 tdesc_data_cleanup (tdesc_data_loc); 1926 return FALSE; 1927 } 1928 } 1929 1930 /* Mandatory AUX registeres are intentionally few and are common between 1931 ARCompact and ARC v2, so same code can be used for both. */ 1932 feature = tdesc_find_feature (tdesc_loc, aux_minimal_feature_name); 1933 if (feature == NULL) 1934 { 1935 arc_print (_("Error: Cannot find required feature `%s' in supplied " 1936 "target description.\n"), aux_minimal_feature_name); 1937 tdesc_data_cleanup (tdesc_data_loc); 1938 return FALSE; 1939 } 1940 1941 for (int i = ARC_FIRST_AUX_REGNUM; i <= ARC_LAST_AUX_REGNUM; i++) 1942 { 1943 const char *name = aux_minimal_register_names[i - ARC_FIRST_AUX_REGNUM]; 1944 valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, name); 1945 if (!valid_p) 1946 { 1947 arc_print (_("Error: Cannot find required register `%s' " 1948 "in feature `%s'.\n"), 1949 name, tdesc_feature_name (feature)); 1950 tdesc_data_cleanup (tdesc_data_loc); 1951 return FALSE; 1952 } 1953 } 1954 1955 *tdesc = tdesc_loc; 1956 *tdesc_data = tdesc_data_loc; 1957 1958 return TRUE; 1959 } 1960 1961 /* Implement the type_align gdbarch function. */ 1962 1963 static ULONGEST 1964 arc_type_align (struct gdbarch *gdbarch, struct type *type) 1965 { 1966 type = check_typedef (type); 1967 return std::min<ULONGEST> (4, TYPE_LENGTH (type)); 1968 } 1969 1970 /* Implement the "init" gdbarch method. */ 1971 1972 static struct gdbarch * 1973 arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1974 { 1975 const struct target_desc *tdesc; 1976 struct tdesc_arch_data *tdesc_data; 1977 1978 if (arc_debug) 1979 debug_printf ("arc: Architecture initialization.\n"); 1980 1981 if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) 1982 return NULL; 1983 1984 /* Allocate the ARC-private target-dependent information structure, and the 1985 GDB target-independent information structure. */ 1986 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); 1987 tdep->jb_pc = -1; /* No longjmp support by default. */ 1988 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); 1989 1990 /* Data types. */ 1991 set_gdbarch_short_bit (gdbarch, 16); 1992 set_gdbarch_int_bit (gdbarch, 32); 1993 set_gdbarch_long_bit (gdbarch, 32); 1994 set_gdbarch_long_long_bit (gdbarch, 64); 1995 set_gdbarch_type_align (gdbarch, arc_type_align); 1996 set_gdbarch_float_bit (gdbarch, 32); 1997 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 1998 set_gdbarch_double_bit (gdbarch, 64); 1999 set_gdbarch_double_format (gdbarch, floatformats_ieee_double); 2000 set_gdbarch_ptr_bit (gdbarch, 32); 2001 set_gdbarch_addr_bit (gdbarch, 32); 2002 set_gdbarch_char_signed (gdbarch, 0); 2003 2004 set_gdbarch_write_pc (gdbarch, arc_write_pc); 2005 2006 set_gdbarch_virtual_frame_pointer (gdbarch, arc_virtual_frame_pointer); 2007 2008 /* tdesc_use_registers expects gdbarch_num_regs to return number of registers 2009 parsed by gdbarch_init, and then it will add all of the remaining 2010 registers and will increase number of registers. */ 2011 set_gdbarch_num_regs (gdbarch, ARC_LAST_REGNUM + 1); 2012 set_gdbarch_num_pseudo_regs (gdbarch, 0); 2013 set_gdbarch_sp_regnum (gdbarch, ARC_SP_REGNUM); 2014 set_gdbarch_pc_regnum (gdbarch, ARC_PC_REGNUM); 2015 set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM); 2016 set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */ 2017 2018 set_gdbarch_dummy_id (gdbarch, arc_dummy_id); 2019 set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call); 2020 set_gdbarch_push_dummy_code (gdbarch, arc_push_dummy_code); 2021 2022 set_gdbarch_cannot_fetch_register (gdbarch, arc_cannot_fetch_register); 2023 set_gdbarch_cannot_store_register (gdbarch, arc_cannot_store_register); 2024 2025 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2026 2027 set_gdbarch_return_value (gdbarch, arc_return_value); 2028 2029 set_gdbarch_skip_prologue (gdbarch, arc_skip_prologue); 2030 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2031 2032 set_gdbarch_breakpoint_kind_from_pc (gdbarch, arc_breakpoint_kind_from_pc); 2033 set_gdbarch_sw_breakpoint_from_kind (gdbarch, arc_sw_breakpoint_from_kind); 2034 2035 /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */ 2036 if (!arc_mach_is_arc600 (gdbarch)) 2037 set_gdbarch_decr_pc_after_break (gdbarch, 0); 2038 else 2039 set_gdbarch_decr_pc_after_break (gdbarch, 2); 2040 2041 set_gdbarch_unwind_pc (gdbarch, arc_unwind_pc); 2042 set_gdbarch_unwind_sp (gdbarch, arc_unwind_sp); 2043 2044 set_gdbarch_frame_align (gdbarch, arc_frame_align); 2045 2046 set_gdbarch_print_insn (gdbarch, arc_delayed_print_insn); 2047 2048 set_gdbarch_cannot_step_breakpoint (gdbarch, 1); 2049 2050 /* "nonsteppable" watchpoint means that watchpoint triggers before 2051 instruction is committed, therefore it is required to remove watchpoint 2052 to step though instruction that triggers it. ARC watchpoints trigger 2053 only after instruction is committed, thus there is no need to remove 2054 them. In fact on ARC watchpoint for memory writes may trigger with more 2055 significant delay, like one or two instructions, depending on type of 2056 memory where write is performed (CCM or external) and next instruction 2057 after the memory write. */ 2058 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 0); 2059 2060 /* This doesn't include possible long-immediate value. */ 2061 set_gdbarch_max_insn_length (gdbarch, 4); 2062 2063 /* Frame unwinders and sniffers. */ 2064 dwarf2_frame_set_init_reg (gdbarch, arc_dwarf2_frame_init_reg); 2065 dwarf2_append_unwinders (gdbarch); 2066 frame_unwind_append_unwinder (gdbarch, &arc_frame_unwind); 2067 frame_base_set_default (gdbarch, &arc_normal_base); 2068 2069 /* Setup stuff specific to a particular environment (baremetal or Linux). 2070 It can override functions set earlier. */ 2071 gdbarch_init_osabi (info, gdbarch); 2072 2073 if (tdep->jb_pc >= 0) 2074 set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target); 2075 2076 /* Disassembler options. Enforce CPU if it was specified in XML target 2077 description, otherwise use default method of determining CPU (ELF private 2078 header). */ 2079 if (info.target_desc != NULL) 2080 { 2081 const struct bfd_arch_info *tdesc_arch 2082 = tdesc_architecture (info.target_desc); 2083 if (tdesc_arch != NULL) 2084 { 2085 xfree (arc_disassembler_options); 2086 /* FIXME: It is not really good to change disassembler options 2087 behind the scene, because that might override options 2088 specified by the user. However as of now ARC doesn't support 2089 `set disassembler-options' hence this code is the only place 2090 where options are changed. It also changes options for all 2091 existing gdbarches, which also can be problematic, if 2092 arc_gdbarch_init will start reusing existing gdbarch 2093 instances. */ 2094 /* Target description specifies a BFD architecture, which is 2095 different from ARC cpu, as accepted by disassembler (and most 2096 other ARC tools), because cpu values are much more fine grained - 2097 there can be multiple cpu values per single BFD architecture. As 2098 a result this code should translate architecture to some cpu 2099 value. Since there is no info on exact cpu configuration, it is 2100 best to use the most feature-rich CPU, so that disassembler will 2101 recognize all instructions available to the specified 2102 architecture. */ 2103 switch (tdesc_arch->mach) 2104 { 2105 case bfd_mach_arc_arc601: 2106 arc_disassembler_options = xstrdup ("cpu=arc601"); 2107 break; 2108 case bfd_mach_arc_arc600: 2109 arc_disassembler_options = xstrdup ("cpu=arc600"); 2110 break; 2111 case bfd_mach_arc_arc700: 2112 arc_disassembler_options = xstrdup ("cpu=arc700"); 2113 break; 2114 case bfd_mach_arc_arcv2: 2115 /* Machine arcv2 has three arches: ARCv2, EM and HS; where ARCv2 2116 is treated as EM. */ 2117 if (arc_arch_is_hs (tdesc_arch)) 2118 arc_disassembler_options = xstrdup ("cpu=hs38_linux"); 2119 else 2120 arc_disassembler_options = xstrdup ("cpu=em4_fpuda"); 2121 break; 2122 default: 2123 arc_disassembler_options = NULL; 2124 break; 2125 } 2126 set_gdbarch_disassembler_options (gdbarch, 2127 &arc_disassembler_options); 2128 } 2129 } 2130 2131 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 2132 2133 return gdbarch; 2134 } 2135 2136 /* Implement the "dump_tdep" gdbarch method. */ 2137 2138 static void 2139 arc_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 2140 { 2141 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2142 2143 fprintf_unfiltered (file, "arc_dump_tdep: jb_pc = %i\n", tdep->jb_pc); 2144 } 2145 2146 /* Wrapper for "maintenance print arc" list of commands. */ 2147 2148 static void 2149 maintenance_print_arc_command (const char *args, int from_tty) 2150 { 2151 cmd_show_list (maintenance_print_arc_list, from_tty, ""); 2152 } 2153 2154 /* This command accepts single argument - address of instruction to 2155 disassemble. */ 2156 2157 static void 2158 dump_arc_instruction_command (const char *args, int from_tty) 2159 { 2160 struct value *val; 2161 if (args != NULL && strlen (args) > 0) 2162 val = evaluate_expression (parse_expression (args).get ()); 2163 else 2164 val = access_value_history (0); 2165 record_latest_value (val); 2166 2167 CORE_ADDR address = value_as_address (val); 2168 struct arc_instruction insn; 2169 struct disassemble_info di = arc_disassemble_info (target_gdbarch ()); 2170 arc_insn_decode (address, &di, arc_delayed_print_insn, &insn); 2171 arc_insn_dump (insn); 2172 } 2173 2174 void 2175 _initialize_arc_tdep (void) 2176 { 2177 gdbarch_register (bfd_arch_arc, arc_gdbarch_init, arc_dump_tdep); 2178 2179 initialize_tdesc_arc_v2 (); 2180 initialize_tdesc_arc_arcompact (); 2181 2182 /* Register ARC-specific commands with gdb. */ 2183 2184 /* Add root prefix command for "maintenance print arc" commands. */ 2185 add_prefix_cmd ("arc", class_maintenance, maintenance_print_arc_command, 2186 _("ARC-specific maintenance commands for printing GDB " 2187 "internal state."), 2188 &maintenance_print_arc_list, "maintenance print arc ", 0, 2189 &maintenanceprintlist); 2190 2191 add_cmd ("arc-instruction", class_maintenance, 2192 dump_arc_instruction_command, 2193 _("Dump arc_instruction structure for specified address."), 2194 &maintenance_print_arc_list); 2195 2196 /* Debug internals for ARC GDB. */ 2197 add_setshow_zinteger_cmd ("arc", class_maintenance, 2198 &arc_debug, 2199 _("Set ARC specific debugging."), 2200 _("Show ARC specific debugging."), 2201 _("Non-zero enables ARC specific debugging."), 2202 NULL, NULL, &setdebuglist, &showdebuglist); 2203 } 2204