1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. 2 3 Copyright (C) 1993-2016 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "doublest.h" 22 #include "frame.h" 23 #include "frame-unwind.h" 24 #include "frame-base.h" 25 #include "dwarf2-frame.h" 26 #include "inferior.h" 27 #include "symtab.h" 28 #include "value.h" 29 #include "gdbcmd.h" 30 #include "gdbcore.h" 31 #include "dis-asm.h" 32 #include "symfile.h" 33 #include "objfiles.h" 34 #include "linespec.h" 35 #include "regcache.h" 36 #include "reggroups.h" 37 #include "arch-utils.h" 38 #include "osabi.h" 39 #include "block.h" 40 #include "infcall.h" 41 #include "trad-frame.h" 42 43 #include "elf-bfd.h" 44 45 #include "alpha-tdep.h" 46 47 /* Instruction decoding. The notations for registers, immediates and 48 opcodes are the same as the one used in Compaq's Alpha architecture 49 handbook. */ 50 51 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26) 52 53 /* Memory instruction format */ 54 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21) 55 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16) 56 #define MEM_DISP(insn) \ 57 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff)) 58 59 static const int lda_opcode = 0x08; 60 static const int stq_opcode = 0x2d; 61 62 /* Branch instruction format */ 63 #define BR_RA(insn) MEM_RA(insn) 64 65 static const int br_opcode = 0x30; 66 static const int bne_opcode = 0x3d; 67 68 /* Operate instruction format */ 69 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5) 70 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000) 71 #define OPR_RA(insn) MEM_RA(insn) 72 #define OPR_RC(insn) ((insn & 0x1f)) 73 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13) 74 75 static const int subq_opcode = 0x10; 76 static const int subq_function = 0x29; 77 78 79 /* Return the name of the REGNO register. 80 81 An empty name corresponds to a register number that used to 82 be used for a virtual register. That virtual register has 83 been removed, but the index is still reserved to maintain 84 compatibility with existing remote alpha targets. */ 85 86 static const char * 87 alpha_register_name (struct gdbarch *gdbarch, int regno) 88 { 89 static const char * const register_names[] = 90 { 91 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", 92 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", 93 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", 94 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", 95 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 96 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 97 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 98 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", 99 "pc", "", "unique" 100 }; 101 102 if (regno < 0) 103 return NULL; 104 if (regno >= ARRAY_SIZE(register_names)) 105 return NULL; 106 return register_names[regno]; 107 } 108 109 static int 110 alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) 111 { 112 return (strlen (alpha_register_name (gdbarch, regno)) == 0); 113 } 114 115 static int 116 alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) 117 { 118 return (regno == ALPHA_ZERO_REGNUM 119 || strlen (alpha_register_name (gdbarch, regno)) == 0); 120 } 121 122 static struct type * 123 alpha_register_type (struct gdbarch *gdbarch, int regno) 124 { 125 if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) 126 return builtin_type (gdbarch)->builtin_data_ptr; 127 if (regno == ALPHA_PC_REGNUM) 128 return builtin_type (gdbarch)->builtin_func_ptr; 129 130 /* Don't need to worry about little vs big endian until 131 some jerk tries to port to alpha-unicosmk. */ 132 if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) 133 return builtin_type (gdbarch)->builtin_double; 134 135 return builtin_type (gdbarch)->builtin_int64; 136 } 137 138 /* Is REGNUM a member of REGGROUP? */ 139 140 static int 141 alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 142 struct reggroup *group) 143 { 144 /* Filter out any registers eliminated, but whose regnum is 145 reserved for backward compatibility, e.g. the vfp. */ 146 if (gdbarch_register_name (gdbarch, regnum) == NULL 147 || *gdbarch_register_name (gdbarch, regnum) == '\0') 148 return 0; 149 150 if (group == all_reggroup) 151 return 1; 152 153 /* Zero should not be saved or restored. Technically it is a general 154 register (just as $f31 would be a float if we represented it), but 155 there's no point displaying it during "info regs", so leave it out 156 of all groups except for "all". */ 157 if (regnum == ALPHA_ZERO_REGNUM) 158 return 0; 159 160 /* All other registers are saved and restored. */ 161 if (group == save_reggroup || group == restore_reggroup) 162 return 1; 163 164 /* All other groups are non-overlapping. */ 165 166 /* Since this is really a PALcode memory slot... */ 167 if (regnum == ALPHA_UNIQUE_REGNUM) 168 return group == system_reggroup; 169 170 /* Force the FPCR to be considered part of the floating point state. */ 171 if (regnum == ALPHA_FPCR_REGNUM) 172 return group == float_reggroup; 173 174 if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31) 175 return group == float_reggroup; 176 else 177 return group == general_reggroup; 178 } 179 180 /* The following represents exactly the conversion performed by 181 the LDS instruction. This applies to both single-precision 182 floating point and 32-bit integers. */ 183 184 static void 185 alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) 186 { 187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 188 ULONGEST mem 189 = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order); 190 ULONGEST frac = (mem >> 0) & 0x7fffff; 191 ULONGEST sign = (mem >> 31) & 1; 192 ULONGEST exp_msb = (mem >> 30) & 1; 193 ULONGEST exp_low = (mem >> 23) & 0x7f; 194 ULONGEST exp, reg; 195 196 exp = (exp_msb << 10) | exp_low; 197 if (exp_msb) 198 { 199 if (exp_low == 0x7f) 200 exp = 0x7ff; 201 } 202 else 203 { 204 if (exp_low != 0x00) 205 exp |= 0x380; 206 } 207 208 reg = (sign << 63) | (exp << 52) | (frac << 29); 209 store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg); 210 } 211 212 /* Similarly, this represents exactly the conversion performed by 213 the STS instruction. */ 214 215 static void 216 alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) 217 { 218 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 219 ULONGEST reg, mem; 220 221 reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order); 222 mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); 223 store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem); 224 } 225 226 /* The alpha needs a conversion between register and memory format if the 227 register is a floating point register and memory format is float, as the 228 register format must be double or memory format is an integer with 4 229 bytes or less, as the representation of integers in floating point 230 registers is different. */ 231 232 static int 233 alpha_convert_register_p (struct gdbarch *gdbarch, int regno, 234 struct type *type) 235 { 236 return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 237 && TYPE_LENGTH (type) != 8); 238 } 239 240 static int 241 alpha_register_to_value (struct frame_info *frame, int regnum, 242 struct type *valtype, gdb_byte *out, 243 int *optimizedp, int *unavailablep) 244 { 245 struct gdbarch *gdbarch = get_frame_arch (frame); 246 gdb_byte in[MAX_REGISTER_SIZE]; 247 248 /* Convert to TYPE. */ 249 if (!get_frame_register_bytes (frame, regnum, 0, 250 register_size (gdbarch, regnum), 251 in, optimizedp, unavailablep)) 252 return 0; 253 254 if (TYPE_LENGTH (valtype) == 4) 255 { 256 alpha_sts (gdbarch, out, in); 257 *optimizedp = *unavailablep = 0; 258 return 1; 259 } 260 261 error (_("Cannot retrieve value from floating point register")); 262 } 263 264 static void 265 alpha_value_to_register (struct frame_info *frame, int regnum, 266 struct type *valtype, const gdb_byte *in) 267 { 268 gdb_byte out[MAX_REGISTER_SIZE]; 269 270 switch (TYPE_LENGTH (valtype)) 271 { 272 case 4: 273 alpha_lds (get_frame_arch (frame), out, in); 274 break; 275 default: 276 error (_("Cannot store value in floating point register")); 277 } 278 put_frame_register (frame, regnum, out); 279 } 280 281 282 /* The alpha passes the first six arguments in the registers, the rest on 283 the stack. The register arguments are stored in ARG_REG_BUFFER, and 284 then moved into the register file; this simplifies the passing of a 285 large struct which extends from the registers to the stack, plus avoids 286 three ptrace invocations per word. 287 288 We don't bother tracking which register values should go in integer 289 regs or fp regs; we load the same values into both. 290 291 If the called function is returning a structure, the address of the 292 structure to be returned is passed as a hidden first argument. */ 293 294 static CORE_ADDR 295 alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 296 struct regcache *regcache, CORE_ADDR bp_addr, 297 int nargs, struct value **args, CORE_ADDR sp, 298 int struct_return, CORE_ADDR struct_addr) 299 { 300 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 301 int i; 302 int accumulate_size = struct_return ? 8 : 0; 303 struct alpha_arg 304 { 305 const gdb_byte *contents; 306 int len; 307 int offset; 308 }; 309 struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs); 310 struct alpha_arg *m_arg; 311 gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; 312 int required_arg_regs; 313 CORE_ADDR func_addr = find_function_addr (function, NULL); 314 315 /* The ABI places the address of the called function in T12. */ 316 regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr); 317 318 /* Set the return address register to point to the entry point 319 of the program, where a breakpoint lies in wait. */ 320 regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr); 321 322 /* Lay out the arguments in memory. */ 323 for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++) 324 { 325 struct value *arg = args[i]; 326 struct type *arg_type = check_typedef (value_type (arg)); 327 328 /* Cast argument to long if necessary as the compiler does it too. */ 329 switch (TYPE_CODE (arg_type)) 330 { 331 case TYPE_CODE_INT: 332 case TYPE_CODE_BOOL: 333 case TYPE_CODE_CHAR: 334 case TYPE_CODE_RANGE: 335 case TYPE_CODE_ENUM: 336 if (TYPE_LENGTH (arg_type) == 4) 337 { 338 /* 32-bit values must be sign-extended to 64 bits 339 even if the base data type is unsigned. */ 340 arg_type = builtin_type (gdbarch)->builtin_int32; 341 arg = value_cast (arg_type, arg); 342 } 343 if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE) 344 { 345 arg_type = builtin_type (gdbarch)->builtin_int64; 346 arg = value_cast (arg_type, arg); 347 } 348 break; 349 350 case TYPE_CODE_FLT: 351 /* "float" arguments loaded in registers must be passed in 352 register format, aka "double". */ 353 if (accumulate_size < sizeof (arg_reg_buffer) 354 && TYPE_LENGTH (arg_type) == 4) 355 { 356 arg_type = builtin_type (gdbarch)->builtin_double; 357 arg = value_cast (arg_type, arg); 358 } 359 /* Tru64 5.1 has a 128-bit long double, and passes this by 360 invisible reference. No one else uses this data type. */ 361 else if (TYPE_LENGTH (arg_type) == 16) 362 { 363 /* Allocate aligned storage. */ 364 sp = (sp & -16) - 16; 365 366 /* Write the real data into the stack. */ 367 write_memory (sp, value_contents (arg), 16); 368 369 /* Construct the indirection. */ 370 arg_type = lookup_pointer_type (arg_type); 371 arg = value_from_pointer (arg_type, sp); 372 } 373 break; 374 375 case TYPE_CODE_COMPLEX: 376 /* ??? The ABI says that complex values are passed as two 377 separate scalar values. This distinction only matters 378 for complex float. However, GCC does not implement this. */ 379 380 /* Tru64 5.1 has a 128-bit long double, and passes this by 381 invisible reference. */ 382 if (TYPE_LENGTH (arg_type) == 32) 383 { 384 /* Allocate aligned storage. */ 385 sp = (sp & -16) - 16; 386 387 /* Write the real data into the stack. */ 388 write_memory (sp, value_contents (arg), 32); 389 390 /* Construct the indirection. */ 391 arg_type = lookup_pointer_type (arg_type); 392 arg = value_from_pointer (arg_type, sp); 393 } 394 break; 395 396 default: 397 break; 398 } 399 m_arg->len = TYPE_LENGTH (arg_type); 400 m_arg->offset = accumulate_size; 401 accumulate_size = (accumulate_size + m_arg->len + 7) & ~7; 402 m_arg->contents = value_contents (arg); 403 } 404 405 /* Determine required argument register loads, loading an argument register 406 is expensive as it uses three ptrace calls. */ 407 required_arg_regs = accumulate_size / 8; 408 if (required_arg_regs > ALPHA_NUM_ARG_REGS) 409 required_arg_regs = ALPHA_NUM_ARG_REGS; 410 411 /* Make room for the arguments on the stack. */ 412 if (accumulate_size < sizeof(arg_reg_buffer)) 413 accumulate_size = 0; 414 else 415 accumulate_size -= sizeof(arg_reg_buffer); 416 sp -= accumulate_size; 417 418 /* Keep sp aligned to a multiple of 16 as the ABI requires. */ 419 sp &= ~15; 420 421 /* `Push' arguments on the stack. */ 422 for (i = nargs; m_arg--, --i >= 0;) 423 { 424 const gdb_byte *contents = m_arg->contents; 425 int offset = m_arg->offset; 426 int len = m_arg->len; 427 428 /* Copy the bytes destined for registers into arg_reg_buffer. */ 429 if (offset < sizeof(arg_reg_buffer)) 430 { 431 if (offset + len <= sizeof(arg_reg_buffer)) 432 { 433 memcpy (arg_reg_buffer + offset, contents, len); 434 continue; 435 } 436 else 437 { 438 int tlen = sizeof(arg_reg_buffer) - offset; 439 memcpy (arg_reg_buffer + offset, contents, tlen); 440 offset += tlen; 441 contents += tlen; 442 len -= tlen; 443 } 444 } 445 446 /* Everything else goes to the stack. */ 447 write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len); 448 } 449 if (struct_return) 450 store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, 451 byte_order, struct_addr); 452 453 /* Load the argument registers. */ 454 for (i = 0; i < required_arg_regs; i++) 455 { 456 regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i, 457 arg_reg_buffer + i*ALPHA_REGISTER_SIZE); 458 regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i, 459 arg_reg_buffer + i*ALPHA_REGISTER_SIZE); 460 } 461 462 /* Finally, update the stack pointer. */ 463 regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp); 464 465 return sp; 466 } 467 468 /* Extract from REGCACHE the value about to be returned from a function 469 and copy it into VALBUF. */ 470 471 static void 472 alpha_extract_return_value (struct type *valtype, struct regcache *regcache, 473 gdb_byte *valbuf) 474 { 475 struct gdbarch *gdbarch = get_regcache_arch (regcache); 476 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 477 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; 478 ULONGEST l; 479 480 switch (TYPE_CODE (valtype)) 481 { 482 case TYPE_CODE_FLT: 483 switch (TYPE_LENGTH (valtype)) 484 { 485 case 4: 486 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer); 487 alpha_sts (gdbarch, valbuf, raw_buffer); 488 break; 489 490 case 8: 491 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); 492 break; 493 494 case 16: 495 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); 496 read_memory (l, valbuf, 16); 497 break; 498 499 default: 500 internal_error (__FILE__, __LINE__, 501 _("unknown floating point width")); 502 } 503 break; 504 505 case TYPE_CODE_COMPLEX: 506 switch (TYPE_LENGTH (valtype)) 507 { 508 case 8: 509 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ 510 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); 511 break; 512 513 case 16: 514 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); 515 regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); 516 break; 517 518 case 32: 519 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); 520 read_memory (l, valbuf, 32); 521 break; 522 523 default: 524 internal_error (__FILE__, __LINE__, 525 _("unknown floating point width")); 526 } 527 break; 528 529 default: 530 /* Assume everything else degenerates to an integer. */ 531 regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); 532 store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l); 533 break; 534 } 535 } 536 537 /* Insert the given value into REGCACHE as if it was being 538 returned by a function. */ 539 540 static void 541 alpha_store_return_value (struct type *valtype, struct regcache *regcache, 542 const gdb_byte *valbuf) 543 { 544 struct gdbarch *gdbarch = get_regcache_arch (regcache); 545 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; 546 ULONGEST l; 547 548 switch (TYPE_CODE (valtype)) 549 { 550 case TYPE_CODE_FLT: 551 switch (TYPE_LENGTH (valtype)) 552 { 553 case 4: 554 alpha_lds (gdbarch, raw_buffer, valbuf); 555 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer); 556 break; 557 558 case 8: 559 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); 560 break; 561 562 case 16: 563 /* FIXME: 128-bit long doubles are returned like structures: 564 by writing into indirect storage provided by the caller 565 as the first argument. */ 566 error (_("Cannot set a 128-bit long double return value.")); 567 568 default: 569 internal_error (__FILE__, __LINE__, 570 _("unknown floating point width")); 571 } 572 break; 573 574 case TYPE_CODE_COMPLEX: 575 switch (TYPE_LENGTH (valtype)) 576 { 577 case 8: 578 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ 579 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); 580 break; 581 582 case 16: 583 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); 584 regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); 585 break; 586 587 case 32: 588 /* FIXME: 128-bit long doubles are returned like structures: 589 by writing into indirect storage provided by the caller 590 as the first argument. */ 591 error (_("Cannot set a 128-bit long double return value.")); 592 593 default: 594 internal_error (__FILE__, __LINE__, 595 _("unknown floating point width")); 596 } 597 break; 598 599 default: 600 /* Assume everything else degenerates to an integer. */ 601 /* 32-bit values must be sign-extended to 64 bits 602 even if the base data type is unsigned. */ 603 if (TYPE_LENGTH (valtype) == 4) 604 valtype = builtin_type (gdbarch)->builtin_int32; 605 l = unpack_long (valtype, valbuf); 606 regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); 607 break; 608 } 609 } 610 611 static enum return_value_convention 612 alpha_return_value (struct gdbarch *gdbarch, struct value *function, 613 struct type *type, struct regcache *regcache, 614 gdb_byte *readbuf, const gdb_byte *writebuf) 615 { 616 enum type_code code = TYPE_CODE (type); 617 618 if ((code == TYPE_CODE_STRUCT 619 || code == TYPE_CODE_UNION 620 || code == TYPE_CODE_ARRAY) 621 && gdbarch_tdep (gdbarch)->return_in_memory (type)) 622 { 623 if (readbuf) 624 { 625 ULONGEST addr; 626 regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr); 627 read_memory (addr, readbuf, TYPE_LENGTH (type)); 628 } 629 630 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 631 } 632 633 if (readbuf) 634 alpha_extract_return_value (type, regcache, readbuf); 635 if (writebuf) 636 alpha_store_return_value (type, regcache, writebuf); 637 638 return RETURN_VALUE_REGISTER_CONVENTION; 639 } 640 641 static int 642 alpha_return_in_memory_always (struct type *type) 643 { 644 return 1; 645 } 646 647 static const gdb_byte * 648 alpha_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 649 { 650 static const gdb_byte break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ 651 652 *len = sizeof(break_insn); 653 return break_insn; 654 } 655 656 657 /* This returns the PC of the first insn after the prologue. 658 If we can't find the prologue, then return 0. */ 659 660 CORE_ADDR 661 alpha_after_prologue (CORE_ADDR pc) 662 { 663 struct symtab_and_line sal; 664 CORE_ADDR func_addr, func_end; 665 666 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 667 return 0; 668 669 sal = find_pc_line (func_addr, 0); 670 if (sal.end < func_end) 671 return sal.end; 672 673 /* The line after the prologue is after the end of the function. In this 674 case, tell the caller to find the prologue the hard way. */ 675 return 0; 676 } 677 678 /* Read an instruction from memory at PC, looking through breakpoints. */ 679 680 unsigned int 681 alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) 682 { 683 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 684 gdb_byte buf[ALPHA_INSN_SIZE]; 685 int res; 686 687 res = target_read_memory (pc, buf, sizeof (buf)); 688 if (res != 0) 689 memory_error (TARGET_XFER_E_IO, pc); 690 return extract_unsigned_integer (buf, sizeof (buf), byte_order); 691 } 692 693 /* To skip prologues, I use this predicate. Returns either PC itself 694 if the code at PC does not look like a function prologue; otherwise 695 returns an address that (if we're lucky) follows the prologue. If 696 LENIENT, then we must skip everything which is involved in setting 697 up the frame (it's OK to skip more, just so long as we don't skip 698 anything which might clobber the registers which are being saved. */ 699 700 static CORE_ADDR 701 alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 702 { 703 unsigned long inst; 704 int offset; 705 CORE_ADDR post_prologue_pc; 706 gdb_byte buf[ALPHA_INSN_SIZE]; 707 708 /* Silently return the unaltered pc upon memory errors. 709 This could happen on OSF/1 if decode_line_1 tries to skip the 710 prologue for quickstarted shared library functions when the 711 shared library is not yet mapped in. 712 Reading target memory is slow over serial lines, so we perform 713 this check only if the target has shared libraries (which all 714 Alpha targets do). */ 715 if (target_read_memory (pc, buf, sizeof (buf))) 716 return pc; 717 718 /* See if we can determine the end of the prologue via the symbol table. 719 If so, then return either PC, or the PC after the prologue, whichever 720 is greater. */ 721 722 post_prologue_pc = alpha_after_prologue (pc); 723 if (post_prologue_pc != 0) 724 return max (pc, post_prologue_pc); 725 726 /* Can't determine prologue from the symbol table, need to examine 727 instructions. */ 728 729 /* Skip the typical prologue instructions. These are the stack adjustment 730 instruction and the instructions that save registers on the stack 731 or in the gcc frame. */ 732 for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE) 733 { 734 inst = alpha_read_insn (gdbarch, pc + offset); 735 736 if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */ 737 continue; 738 if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */ 739 continue; 740 if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ 741 continue; 742 if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */ 743 continue; 744 745 if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */ 746 || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */ 747 && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */ 748 continue; 749 750 if (inst == 0x47de040f) /* bis sp,sp,fp */ 751 continue; 752 if (inst == 0x47fe040f) /* bis zero,sp,fp */ 753 continue; 754 755 break; 756 } 757 return pc + offset; 758 } 759 760 /* GNU ld for alpha is so clever that the redundant GP load in function 761 entrypoint is skipped. We must therefore skip initial GP loads; otherwise 762 breakpoints in function entrypoints can also be skipped. */ 763 764 static CORE_ADDR 765 alpha_skip_entrypoint (struct gdbarch *gdbarch, CORE_ADDR pc) 766 { 767 unsigned long inst; 768 gdb_byte buf[ALPHA_INSN_SIZE]; 769 770 /* Refer to the comment in alpha_skip_prologue above. */ 771 if (target_read_memory (pc, buf, sizeof (buf))) 772 return pc; 773 774 /* Skip a GP load in the first two words in the function entrypoint. */ 775 inst = alpha_read_insn (gdbarch, pc); 776 if ((inst & 0xffff0000) != 0x27bb0000) /* ldah $gp,n($t12) */ 777 return pc; 778 inst = alpha_read_insn (gdbarch, pc + ALPHA_INSN_SIZE); 779 if ((inst & 0xffff0000) != 0x23bd0000) /* lda $gp,n($gp) */ 780 return pc; 781 782 return pc + 2 * ALPHA_INSN_SIZE; 783 } 784 785 786 static const int ldl_l_opcode = 0x2a; 787 static const int ldq_l_opcode = 0x2b; 788 static const int stl_c_opcode = 0x2e; 789 static const int stq_c_opcode = 0x2f; 790 791 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L 792 instruction and ending with a STL_C/STQ_C instruction. If such a sequence 793 is found, attempt to step through it. A breakpoint is placed at the end of 794 the sequence. */ 795 796 static int 797 alpha_deal_with_atomic_sequence (struct frame_info *frame) 798 { 799 struct gdbarch *gdbarch = get_frame_arch (frame); 800 struct address_space *aspace = get_frame_address_space (frame); 801 CORE_ADDR pc = get_frame_pc (frame); 802 CORE_ADDR breaks[2] = {-1, -1}; 803 CORE_ADDR loc = pc; 804 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ 805 unsigned int insn = alpha_read_insn (gdbarch, loc); 806 int insn_count; 807 int index; 808 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 809 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 810 int bc_insn_count = 0; /* Conditional branch instruction count. */ 811 812 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ 813 if (INSN_OPCODE (insn) != ldl_l_opcode 814 && INSN_OPCODE (insn) != ldq_l_opcode) 815 return 0; 816 817 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 818 instructions. */ 819 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 820 { 821 loc += ALPHA_INSN_SIZE; 822 insn = alpha_read_insn (gdbarch, loc); 823 824 /* Assume that there is at most one branch in the atomic 825 sequence. If a branch is found, put a breakpoint in 826 its destination address. */ 827 if (INSN_OPCODE (insn) >= br_opcode) 828 { 829 int immediate = (insn & 0x001fffff) << 2; 830 831 immediate = (immediate ^ 0x400000) - 0x400000; 832 833 if (bc_insn_count >= 1) 834 return 0; /* More than one branch found, fallback 835 to the standard single-step code. */ 836 837 breaks[1] = loc + ALPHA_INSN_SIZE + immediate; 838 839 bc_insn_count++; 840 last_breakpoint++; 841 } 842 843 if (INSN_OPCODE (insn) == stl_c_opcode 844 || INSN_OPCODE (insn) == stq_c_opcode) 845 break; 846 } 847 848 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ 849 if (INSN_OPCODE (insn) != stl_c_opcode 850 && INSN_OPCODE (insn) != stq_c_opcode) 851 return 0; 852 853 closing_insn = loc; 854 loc += ALPHA_INSN_SIZE; 855 856 /* Insert a breakpoint right after the end of the atomic sequence. */ 857 breaks[0] = loc; 858 859 /* Check for duplicated breakpoints. Check also for a breakpoint 860 placed (branch instruction's destination) anywhere in sequence. */ 861 if (last_breakpoint 862 && (breaks[1] == breaks[0] 863 || (breaks[1] >= pc && breaks[1] <= closing_insn))) 864 last_breakpoint = 0; 865 866 /* Effectively inserts the breakpoints. */ 867 for (index = 0; index <= last_breakpoint; index++) 868 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); 869 870 return 1; 871 } 872 873 874 /* Figure out where the longjmp will land. 875 We expect the first arg to be a pointer to the jmp_buf structure from 876 which we extract the PC (JB_PC) that we will land at. The PC is copied 877 into the "pc". This routine returns true on success. */ 878 879 static int 880 alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 881 { 882 struct gdbarch *gdbarch = get_frame_arch (frame); 883 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 884 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 885 CORE_ADDR jb_addr; 886 gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; 887 888 jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM); 889 890 if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size), 891 raw_buffer, tdep->jb_elt_size)) 892 return 0; 893 894 *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order); 895 return 1; 896 } 897 898 899 /* Frame unwinder for signal trampolines. We use alpha tdep bits that 900 describe the location and shape of the sigcontext structure. After 901 that, all registers are in memory, so it's easy. */ 902 /* ??? Shouldn't we be able to do this generically, rather than with 903 OSABI data specific to Alpha? */ 904 905 struct alpha_sigtramp_unwind_cache 906 { 907 CORE_ADDR sigcontext_addr; 908 }; 909 910 static struct alpha_sigtramp_unwind_cache * 911 alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame, 912 void **this_prologue_cache) 913 { 914 struct alpha_sigtramp_unwind_cache *info; 915 struct gdbarch_tdep *tdep; 916 917 if (*this_prologue_cache) 918 return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache; 919 920 info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); 921 *this_prologue_cache = info; 922 923 tdep = gdbarch_tdep (get_frame_arch (this_frame)); 924 info->sigcontext_addr = tdep->sigcontext_addr (this_frame); 925 926 return info; 927 } 928 929 /* Return the address of REGNUM in a sigtramp frame. Since this is 930 all arithmetic, it doesn't seem worthwhile to cache it. */ 931 932 static CORE_ADDR 933 alpha_sigtramp_register_address (struct gdbarch *gdbarch, 934 CORE_ADDR sigcontext_addr, int regnum) 935 { 936 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 937 938 if (regnum >= 0 && regnum < 32) 939 return sigcontext_addr + tdep->sc_regs_offset + regnum * 8; 940 else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32) 941 return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8; 942 else if (regnum == ALPHA_PC_REGNUM) 943 return sigcontext_addr + tdep->sc_pc_offset; 944 945 return 0; 946 } 947 948 /* Given a GDB frame, determine the address of the calling function's 949 frame. This will be used to create a new GDB frame struct. */ 950 951 static void 952 alpha_sigtramp_frame_this_id (struct frame_info *this_frame, 953 void **this_prologue_cache, 954 struct frame_id *this_id) 955 { 956 struct gdbarch *gdbarch = get_frame_arch (this_frame); 957 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 958 struct alpha_sigtramp_unwind_cache *info 959 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); 960 CORE_ADDR stack_addr, code_addr; 961 962 /* If the OSABI couldn't locate the sigcontext, give up. */ 963 if (info->sigcontext_addr == 0) 964 return; 965 966 /* If we have dynamic signal trampolines, find their start. 967 If we do not, then we must assume there is a symbol record 968 that can provide the start address. */ 969 if (tdep->dynamic_sigtramp_offset) 970 { 971 int offset; 972 code_addr = get_frame_pc (this_frame); 973 offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr); 974 if (offset >= 0) 975 code_addr -= offset; 976 else 977 code_addr = 0; 978 } 979 else 980 code_addr = get_frame_func (this_frame); 981 982 /* The stack address is trivially read from the sigcontext. */ 983 stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr, 984 ALPHA_SP_REGNUM); 985 stack_addr = get_frame_memory_unsigned (this_frame, stack_addr, 986 ALPHA_REGISTER_SIZE); 987 988 *this_id = frame_id_build (stack_addr, code_addr); 989 } 990 991 /* Retrieve the value of REGNUM in FRAME. Don't give up! */ 992 993 static struct value * 994 alpha_sigtramp_frame_prev_register (struct frame_info *this_frame, 995 void **this_prologue_cache, int regnum) 996 { 997 struct alpha_sigtramp_unwind_cache *info 998 = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); 999 CORE_ADDR addr; 1000 1001 if (info->sigcontext_addr != 0) 1002 { 1003 /* All integer and fp registers are stored in memory. */ 1004 addr = alpha_sigtramp_register_address (get_frame_arch (this_frame), 1005 info->sigcontext_addr, regnum); 1006 if (addr != 0) 1007 return frame_unwind_got_memory (this_frame, regnum, addr); 1008 } 1009 1010 /* This extra register may actually be in the sigcontext, but our 1011 current description of it in alpha_sigtramp_frame_unwind_cache 1012 doesn't include it. Too bad. Fall back on whatever's in the 1013 outer frame. */ 1014 return frame_unwind_got_register (this_frame, regnum, regnum); 1015 } 1016 1017 static int 1018 alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, 1019 struct frame_info *this_frame, 1020 void **this_prologue_cache) 1021 { 1022 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1023 CORE_ADDR pc = get_frame_pc (this_frame); 1024 const char *name; 1025 1026 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead 1027 look at tramp-frame.h and other simplier per-architecture 1028 sigtramp unwinders. */ 1029 1030 /* We shouldn't even bother to try if the OSABI didn't register a 1031 sigcontext_addr handler or pc_in_sigtramp hander. */ 1032 if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL) 1033 return 0; 1034 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL) 1035 return 0; 1036 1037 /* Otherwise we should be in a signal frame. */ 1038 find_pc_partial_function (pc, &name, NULL, NULL); 1039 if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name)) 1040 return 1; 1041 1042 return 0; 1043 } 1044 1045 static const struct frame_unwind alpha_sigtramp_frame_unwind = { 1046 SIGTRAMP_FRAME, 1047 default_frame_unwind_stop_reason, 1048 alpha_sigtramp_frame_this_id, 1049 alpha_sigtramp_frame_prev_register, 1050 NULL, 1051 alpha_sigtramp_frame_sniffer 1052 }; 1053 1054 1055 1056 /* Heuristic_proc_start may hunt through the text section for a long 1057 time across a 2400 baud serial line. Allows the user to limit this 1058 search. */ 1059 static int heuristic_fence_post = 0; 1060 1061 /* Attempt to locate the start of the function containing PC. We assume that 1062 the previous function ends with an about_to_return insn. Not foolproof by 1063 any means, since gcc is happy to put the epilogue in the middle of a 1064 function. But we're guessing anyway... */ 1065 1066 static CORE_ADDR 1067 alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) 1068 { 1069 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1070 CORE_ADDR last_non_nop = pc; 1071 CORE_ADDR fence = pc - heuristic_fence_post; 1072 CORE_ADDR orig_pc = pc; 1073 CORE_ADDR func; 1074 struct inferior *inf; 1075 1076 if (pc == 0) 1077 return 0; 1078 1079 /* First see if we can find the start of the function from minimal 1080 symbol information. This can succeed with a binary that doesn't 1081 have debug info, but hasn't been stripped. */ 1082 func = get_pc_function_start (pc); 1083 if (func) 1084 return func; 1085 1086 if (heuristic_fence_post == -1 1087 || fence < tdep->vm_min_address) 1088 fence = tdep->vm_min_address; 1089 1090 /* Search back for previous return; also stop at a 0, which might be 1091 seen for instance before the start of a code section. Don't include 1092 nops, since this usually indicates padding between functions. */ 1093 for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE) 1094 { 1095 unsigned int insn = alpha_read_insn (gdbarch, pc); 1096 switch (insn) 1097 { 1098 case 0: /* invalid insn */ 1099 case 0x6bfa8001: /* ret $31,($26),1 */ 1100 return last_non_nop; 1101 1102 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */ 1103 case 0x47ff041f: /* nop: bis $31,$31,$31 */ 1104 break; 1105 1106 default: 1107 last_non_nop = pc; 1108 break; 1109 } 1110 } 1111 1112 inf = current_inferior (); 1113 1114 /* It's not clear to me why we reach this point when stopping quietly, 1115 but with this test, at least we don't print out warnings for every 1116 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ 1117 if (inf->control.stop_soon == NO_STOP_QUIETLY) 1118 { 1119 static int blurb_printed = 0; 1120 1121 if (fence == tdep->vm_min_address) 1122 warning (_("Hit beginning of text section without finding \ 1123 enclosing function for address %s"), paddress (gdbarch, orig_pc)); 1124 else 1125 warning (_("Hit heuristic-fence-post without finding \ 1126 enclosing function for address %s"), paddress (gdbarch, orig_pc)); 1127 1128 if (!blurb_printed) 1129 { 1130 printf_filtered (_("\ 1131 This warning occurs if you are debugging a function without any symbols\n\ 1132 (for example, in a stripped executable). In that case, you may wish to\n\ 1133 increase the size of the search with the `set heuristic-fence-post' command.\n\ 1134 \n\ 1135 Otherwise, you told GDB there was a function where there isn't one, or\n\ 1136 (more likely) you have encountered a bug in GDB.\n")); 1137 blurb_printed = 1; 1138 } 1139 } 1140 1141 return 0; 1142 } 1143 1144 /* Fallback alpha frame unwinder. Uses instruction scanning and knows 1145 something about the traditional layout of alpha stack frames. */ 1146 1147 struct alpha_heuristic_unwind_cache 1148 { 1149 CORE_ADDR vfp; 1150 CORE_ADDR start_pc; 1151 struct trad_frame_saved_reg *saved_regs; 1152 int return_reg; 1153 }; 1154 1155 /* If a probing loop sequence starts at PC, simulate it and compute 1156 FRAME_SIZE and PC after its execution. Otherwise, return with PC and 1157 FRAME_SIZE unchanged. */ 1158 1159 static void 1160 alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc, 1161 int *frame_size) 1162 { 1163 CORE_ADDR cur_pc = *pc; 1164 int cur_frame_size = *frame_size; 1165 int nb_of_iterations, reg_index, reg_probe; 1166 unsigned int insn; 1167 1168 /* The following pattern is recognized as a probing loop: 1169 1170 lda REG_INDEX,NB_OF_ITERATIONS 1171 lda REG_PROBE,<immediate>(sp) 1172 1173 LOOP_START: 1174 stq zero,<immediate>(REG_PROBE) 1175 subq REG_INDEX,0x1,REG_INDEX 1176 lda REG_PROBE,<immediate>(REG_PROBE) 1177 bne REG_INDEX, LOOP_START 1178 1179 lda sp,<immediate>(REG_PROBE) 1180 1181 If anything different is found, the function returns without 1182 changing PC and FRAME_SIZE. Otherwise, PC will point immediately 1183 after this sequence, and FRAME_SIZE will be updated. */ 1184 1185 /* lda REG_INDEX,NB_OF_ITERATIONS */ 1186 1187 insn = alpha_read_insn (gdbarch, cur_pc); 1188 if (INSN_OPCODE (insn) != lda_opcode) 1189 return; 1190 reg_index = MEM_RA (insn); 1191 nb_of_iterations = MEM_DISP (insn); 1192 1193 /* lda REG_PROBE,<immediate>(sp) */ 1194 1195 cur_pc += ALPHA_INSN_SIZE; 1196 insn = alpha_read_insn (gdbarch, cur_pc); 1197 if (INSN_OPCODE (insn) != lda_opcode 1198 || MEM_RB (insn) != ALPHA_SP_REGNUM) 1199 return; 1200 reg_probe = MEM_RA (insn); 1201 cur_frame_size -= MEM_DISP (insn); 1202 1203 /* stq zero,<immediate>(REG_PROBE) */ 1204 1205 cur_pc += ALPHA_INSN_SIZE; 1206 insn = alpha_read_insn (gdbarch, cur_pc); 1207 if (INSN_OPCODE (insn) != stq_opcode 1208 || MEM_RA (insn) != 0x1f 1209 || MEM_RB (insn) != reg_probe) 1210 return; 1211 1212 /* subq REG_INDEX,0x1,REG_INDEX */ 1213 1214 cur_pc += ALPHA_INSN_SIZE; 1215 insn = alpha_read_insn (gdbarch, cur_pc); 1216 if (INSN_OPCODE (insn) != subq_opcode 1217 || !OPR_HAS_IMMEDIATE (insn) 1218 || OPR_FUNCTION (insn) != subq_function 1219 || OPR_LIT(insn) != 1 1220 || OPR_RA (insn) != reg_index 1221 || OPR_RC (insn) != reg_index) 1222 return; 1223 1224 /* lda REG_PROBE,<immediate>(REG_PROBE) */ 1225 1226 cur_pc += ALPHA_INSN_SIZE; 1227 insn = alpha_read_insn (gdbarch, cur_pc); 1228 if (INSN_OPCODE (insn) != lda_opcode 1229 || MEM_RA (insn) != reg_probe 1230 || MEM_RB (insn) != reg_probe) 1231 return; 1232 cur_frame_size -= MEM_DISP (insn) * nb_of_iterations; 1233 1234 /* bne REG_INDEX, LOOP_START */ 1235 1236 cur_pc += ALPHA_INSN_SIZE; 1237 insn = alpha_read_insn (gdbarch, cur_pc); 1238 if (INSN_OPCODE (insn) != bne_opcode 1239 || MEM_RA (insn) != reg_index) 1240 return; 1241 1242 /* lda sp,<immediate>(REG_PROBE) */ 1243 1244 cur_pc += ALPHA_INSN_SIZE; 1245 insn = alpha_read_insn (gdbarch, cur_pc); 1246 if (INSN_OPCODE (insn) != lda_opcode 1247 || MEM_RA (insn) != ALPHA_SP_REGNUM 1248 || MEM_RB (insn) != reg_probe) 1249 return; 1250 cur_frame_size -= MEM_DISP (insn); 1251 1252 *pc = cur_pc; 1253 *frame_size = cur_frame_size; 1254 } 1255 1256 static struct alpha_heuristic_unwind_cache * 1257 alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame, 1258 void **this_prologue_cache, 1259 CORE_ADDR start_pc) 1260 { 1261 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1262 struct alpha_heuristic_unwind_cache *info; 1263 ULONGEST val; 1264 CORE_ADDR limit_pc, cur_pc; 1265 int frame_reg, frame_size, return_reg, reg; 1266 1267 if (*this_prologue_cache) 1268 return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache; 1269 1270 info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); 1271 *this_prologue_cache = info; 1272 info->saved_regs = trad_frame_alloc_saved_regs (this_frame); 1273 1274 limit_pc = get_frame_pc (this_frame); 1275 if (start_pc == 0) 1276 start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc); 1277 info->start_pc = start_pc; 1278 1279 frame_reg = ALPHA_SP_REGNUM; 1280 frame_size = 0; 1281 return_reg = -1; 1282 1283 /* If we've identified a likely place to start, do code scanning. */ 1284 if (start_pc != 0) 1285 { 1286 /* Limit the forward search to 50 instructions. */ 1287 if (start_pc + 200 < limit_pc) 1288 limit_pc = start_pc + 200; 1289 1290 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE) 1291 { 1292 unsigned int word = alpha_read_insn (gdbarch, cur_pc); 1293 1294 if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ 1295 { 1296 if (word & 0x8000) 1297 { 1298 /* Consider only the first stack allocation instruction 1299 to contain the static size of the frame. */ 1300 if (frame_size == 0) 1301 frame_size = (-word) & 0xffff; 1302 } 1303 else 1304 { 1305 /* Exit loop if a positive stack adjustment is found, which 1306 usually means that the stack cleanup code in the function 1307 epilogue is reached. */ 1308 break; 1309 } 1310 } 1311 else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ 1312 { 1313 reg = (word & 0x03e00000) >> 21; 1314 1315 /* Ignore this instruction if we have already encountered 1316 an instruction saving the same register earlier in the 1317 function code. The current instruction does not tell 1318 us where the original value upon function entry is saved. 1319 All it says is that the function we are scanning reused 1320 that register for some computation of its own, and is now 1321 saving its result. */ 1322 if (trad_frame_addr_p(info->saved_regs, reg)) 1323 continue; 1324 1325 if (reg == 31) 1326 continue; 1327 1328 /* Do not compute the address where the register was saved yet, 1329 because we don't know yet if the offset will need to be 1330 relative to $sp or $fp (we can not compute the address 1331 relative to $sp if $sp is updated during the execution of 1332 the current subroutine, for instance when doing some alloca). 1333 So just store the offset for the moment, and compute the 1334 address later when we know whether this frame has a frame 1335 pointer or not. */ 1336 /* Hack: temporarily add one, so that the offset is non-zero 1337 and we can tell which registers have save offsets below. */ 1338 info->saved_regs[reg].addr = (word & 0xffff) + 1; 1339 1340 /* Starting with OSF/1-3.2C, the system libraries are shipped 1341 without local symbols, but they still contain procedure 1342 descriptors without a symbol reference. GDB is currently 1343 unable to find these procedure descriptors and uses 1344 heuristic_proc_desc instead. 1345 As some low level compiler support routines (__div*, __add*) 1346 use a non-standard return address register, we have to 1347 add some heuristics to determine the return address register, 1348 or stepping over these routines will fail. 1349 Usually the return address register is the first register 1350 saved on the stack, but assembler optimization might 1351 rearrange the register saves. 1352 So we recognize only a few registers (t7, t9, ra) within 1353 the procedure prologue as valid return address registers. 1354 If we encounter a return instruction, we extract the 1355 return address register from it. 1356 1357 FIXME: Rewriting GDB to access the procedure descriptors, 1358 e.g. via the minimal symbol table, might obviate this 1359 hack. */ 1360 if (return_reg == -1 1361 && cur_pc < (start_pc + 80) 1362 && (reg == ALPHA_T7_REGNUM 1363 || reg == ALPHA_T9_REGNUM 1364 || reg == ALPHA_RA_REGNUM)) 1365 return_reg = reg; 1366 } 1367 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ 1368 return_reg = (word >> 16) & 0x1f; 1369 else if (word == 0x47de040f) /* bis sp,sp,fp */ 1370 frame_reg = ALPHA_GCC_FP_REGNUM; 1371 else if (word == 0x47fe040f) /* bis zero,sp,fp */ 1372 frame_reg = ALPHA_GCC_FP_REGNUM; 1373 1374 alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size); 1375 } 1376 1377 /* If we haven't found a valid return address register yet, keep 1378 searching in the procedure prologue. */ 1379 if (return_reg == -1) 1380 { 1381 while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80)) 1382 { 1383 unsigned int word = alpha_read_insn (gdbarch, cur_pc); 1384 1385 if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ 1386 { 1387 reg = (word & 0x03e00000) >> 21; 1388 if (reg == ALPHA_T7_REGNUM 1389 || reg == ALPHA_T9_REGNUM 1390 || reg == ALPHA_RA_REGNUM) 1391 { 1392 return_reg = reg; 1393 break; 1394 } 1395 } 1396 else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ 1397 { 1398 return_reg = (word >> 16) & 0x1f; 1399 break; 1400 } 1401 1402 cur_pc += ALPHA_INSN_SIZE; 1403 } 1404 } 1405 } 1406 1407 /* Failing that, do default to the customary RA. */ 1408 if (return_reg == -1) 1409 return_reg = ALPHA_RA_REGNUM; 1410 info->return_reg = return_reg; 1411 1412 val = get_frame_register_unsigned (this_frame, frame_reg); 1413 info->vfp = val + frame_size; 1414 1415 /* Convert offsets to absolute addresses. See above about adding 1416 one to the offsets to make all detected offsets non-zero. */ 1417 for (reg = 0; reg < ALPHA_NUM_REGS; ++reg) 1418 if (trad_frame_addr_p(info->saved_regs, reg)) 1419 info->saved_regs[reg].addr += val - 1; 1420 1421 /* The stack pointer of the previous frame is computed by popping 1422 the current stack frame. */ 1423 if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM)) 1424 trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp); 1425 1426 return info; 1427 } 1428 1429 /* Given a GDB frame, determine the address of the calling function's 1430 frame. This will be used to create a new GDB frame struct. */ 1431 1432 static void 1433 alpha_heuristic_frame_this_id (struct frame_info *this_frame, 1434 void **this_prologue_cache, 1435 struct frame_id *this_id) 1436 { 1437 struct alpha_heuristic_unwind_cache *info 1438 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); 1439 1440 *this_id = frame_id_build (info->vfp, info->start_pc); 1441 } 1442 1443 /* Retrieve the value of REGNUM in FRAME. Don't give up! */ 1444 1445 static struct value * 1446 alpha_heuristic_frame_prev_register (struct frame_info *this_frame, 1447 void **this_prologue_cache, int regnum) 1448 { 1449 struct alpha_heuristic_unwind_cache *info 1450 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); 1451 1452 /* The PC of the previous frame is stored in the link register of 1453 the current frame. Frob regnum so that we pull the value from 1454 the correct place. */ 1455 if (regnum == ALPHA_PC_REGNUM) 1456 regnum = info->return_reg; 1457 1458 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 1459 } 1460 1461 static const struct frame_unwind alpha_heuristic_frame_unwind = { 1462 NORMAL_FRAME, 1463 default_frame_unwind_stop_reason, 1464 alpha_heuristic_frame_this_id, 1465 alpha_heuristic_frame_prev_register, 1466 NULL, 1467 default_frame_sniffer 1468 }; 1469 1470 static CORE_ADDR 1471 alpha_heuristic_frame_base_address (struct frame_info *this_frame, 1472 void **this_prologue_cache) 1473 { 1474 struct alpha_heuristic_unwind_cache *info 1475 = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); 1476 1477 return info->vfp; 1478 } 1479 1480 static const struct frame_base alpha_heuristic_frame_base = { 1481 &alpha_heuristic_frame_unwind, 1482 alpha_heuristic_frame_base_address, 1483 alpha_heuristic_frame_base_address, 1484 alpha_heuristic_frame_base_address 1485 }; 1486 1487 /* Just like reinit_frame_cache, but with the right arguments to be 1488 callable as an sfunc. Used by the "set heuristic-fence-post" command. */ 1489 1490 static void 1491 reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c) 1492 { 1493 reinit_frame_cache (); 1494 } 1495 1496 1497 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 1498 dummy frame. The frame ID's base needs to match the TOS value 1499 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1500 breakpoint. */ 1501 1502 static struct frame_id 1503 alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1504 { 1505 ULONGEST base; 1506 base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM); 1507 return frame_id_build (base, get_frame_pc (this_frame)); 1508 } 1509 1510 static CORE_ADDR 1511 alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1512 { 1513 ULONGEST pc; 1514 pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM); 1515 return pc; 1516 } 1517 1518 1519 /* Helper routines for alpha*-nat.c files to move register sets to and 1520 from core files. The UNIQUE pointer is allowed to be NULL, as most 1521 targets don't supply this value in their core files. */ 1522 1523 void 1524 alpha_supply_int_regs (struct regcache *regcache, int regno, 1525 const void *r0_r30, const void *pc, const void *unique) 1526 { 1527 const gdb_byte *regs = (const gdb_byte *) r0_r30; 1528 int i; 1529 1530 for (i = 0; i < 31; ++i) 1531 if (regno == i || regno == -1) 1532 regcache_raw_supply (regcache, i, regs + i * 8); 1533 1534 if (regno == ALPHA_ZERO_REGNUM || regno == -1) 1535 { 1536 const gdb_byte zero[8] = { 0 }; 1537 1538 regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero); 1539 } 1540 1541 if (regno == ALPHA_PC_REGNUM || regno == -1) 1542 regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc); 1543 1544 if (regno == ALPHA_UNIQUE_REGNUM || regno == -1) 1545 regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique); 1546 } 1547 1548 void 1549 alpha_fill_int_regs (const struct regcache *regcache, 1550 int regno, void *r0_r30, void *pc, void *unique) 1551 { 1552 gdb_byte *regs = (gdb_byte *) r0_r30; 1553 int i; 1554 1555 for (i = 0; i < 31; ++i) 1556 if (regno == i || regno == -1) 1557 regcache_raw_collect (regcache, i, regs + i * 8); 1558 1559 if (regno == ALPHA_PC_REGNUM || regno == -1) 1560 regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc); 1561 1562 if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1)) 1563 regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique); 1564 } 1565 1566 void 1567 alpha_supply_fp_regs (struct regcache *regcache, int regno, 1568 const void *f0_f30, const void *fpcr) 1569 { 1570 const gdb_byte *regs = (const gdb_byte *) f0_f30; 1571 int i; 1572 1573 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) 1574 if (regno == i || regno == -1) 1575 regcache_raw_supply (regcache, i, 1576 regs + (i - ALPHA_FP0_REGNUM) * 8); 1577 1578 if (regno == ALPHA_FPCR_REGNUM || regno == -1) 1579 regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr); 1580 } 1581 1582 void 1583 alpha_fill_fp_regs (const struct regcache *regcache, 1584 int regno, void *f0_f30, void *fpcr) 1585 { 1586 gdb_byte *regs = (gdb_byte *) f0_f30; 1587 int i; 1588 1589 for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) 1590 if (regno == i || regno == -1) 1591 regcache_raw_collect (regcache, i, 1592 regs + (i - ALPHA_FP0_REGNUM) * 8); 1593 1594 if (regno == ALPHA_FPCR_REGNUM || regno == -1) 1595 regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr); 1596 } 1597 1598 1599 1600 /* Return nonzero if the G_floating register value in REG is equal to 1601 zero for FP control instructions. */ 1602 1603 static int 1604 fp_register_zero_p (LONGEST reg) 1605 { 1606 /* Check that all bits except the sign bit are zero. */ 1607 const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1; 1608 1609 return ((reg & zero_mask) == 0); 1610 } 1611 1612 /* Return the value of the sign bit for the G_floating register 1613 value held in REG. */ 1614 1615 static int 1616 fp_register_sign_bit (LONGEST reg) 1617 { 1618 const LONGEST sign_mask = (LONGEST) 1 << 63; 1619 1620 return ((reg & sign_mask) != 0); 1621 } 1622 1623 /* alpha_software_single_step() is called just before we want to resume 1624 the inferior, if we want to single-step it but there is no hardware 1625 or kernel single-step support (NetBSD on Alpha, for example). We find 1626 the target of the coming instruction and breakpoint it. */ 1627 1628 static CORE_ADDR 1629 alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) 1630 { 1631 struct gdbarch *gdbarch = get_frame_arch (frame); 1632 unsigned int insn; 1633 unsigned int op; 1634 int regno; 1635 int offset; 1636 LONGEST rav; 1637 1638 insn = alpha_read_insn (gdbarch, pc); 1639 1640 /* Opcode is top 6 bits. */ 1641 op = (insn >> 26) & 0x3f; 1642 1643 if (op == 0x1a) 1644 { 1645 /* Jump format: target PC is: 1646 RB & ~3 */ 1647 return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3); 1648 } 1649 1650 if ((op & 0x30) == 0x30) 1651 { 1652 /* Branch format: target PC is: 1653 (new PC) + (4 * sext(displacement)) */ 1654 if (op == 0x30 /* BR */ 1655 || op == 0x34) /* BSR */ 1656 { 1657 branch_taken: 1658 offset = (insn & 0x001fffff); 1659 if (offset & 0x00100000) 1660 offset |= 0xffe00000; 1661 offset *= ALPHA_INSN_SIZE; 1662 return (pc + ALPHA_INSN_SIZE + offset); 1663 } 1664 1665 /* Need to determine if branch is taken; read RA. */ 1666 regno = (insn >> 21) & 0x1f; 1667 switch (op) 1668 { 1669 case 0x31: /* FBEQ */ 1670 case 0x36: /* FBGE */ 1671 case 0x37: /* FBGT */ 1672 case 0x33: /* FBLE */ 1673 case 0x32: /* FBLT */ 1674 case 0x35: /* FBNE */ 1675 regno += gdbarch_fp0_regnum (gdbarch); 1676 } 1677 1678 rav = get_frame_register_signed (frame, regno); 1679 1680 switch (op) 1681 { 1682 case 0x38: /* BLBC */ 1683 if ((rav & 1) == 0) 1684 goto branch_taken; 1685 break; 1686 case 0x3c: /* BLBS */ 1687 if (rav & 1) 1688 goto branch_taken; 1689 break; 1690 case 0x39: /* BEQ */ 1691 if (rav == 0) 1692 goto branch_taken; 1693 break; 1694 case 0x3d: /* BNE */ 1695 if (rav != 0) 1696 goto branch_taken; 1697 break; 1698 case 0x3a: /* BLT */ 1699 if (rav < 0) 1700 goto branch_taken; 1701 break; 1702 case 0x3b: /* BLE */ 1703 if (rav <= 0) 1704 goto branch_taken; 1705 break; 1706 case 0x3f: /* BGT */ 1707 if (rav > 0) 1708 goto branch_taken; 1709 break; 1710 case 0x3e: /* BGE */ 1711 if (rav >= 0) 1712 goto branch_taken; 1713 break; 1714 1715 /* Floating point branches. */ 1716 1717 case 0x31: /* FBEQ */ 1718 if (fp_register_zero_p (rav)) 1719 goto branch_taken; 1720 break; 1721 case 0x36: /* FBGE */ 1722 if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav)) 1723 goto branch_taken; 1724 break; 1725 case 0x37: /* FBGT */ 1726 if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav)) 1727 goto branch_taken; 1728 break; 1729 case 0x33: /* FBLE */ 1730 if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav)) 1731 goto branch_taken; 1732 break; 1733 case 0x32: /* FBLT */ 1734 if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav)) 1735 goto branch_taken; 1736 break; 1737 case 0x35: /* FBNE */ 1738 if (! fp_register_zero_p (rav)) 1739 goto branch_taken; 1740 break; 1741 } 1742 } 1743 1744 /* Not a branch or branch not taken; target PC is: 1745 pc + 4 */ 1746 return (pc + ALPHA_INSN_SIZE); 1747 } 1748 1749 int 1750 alpha_software_single_step (struct frame_info *frame) 1751 { 1752 struct gdbarch *gdbarch = get_frame_arch (frame); 1753 struct address_space *aspace = get_frame_address_space (frame); 1754 CORE_ADDR pc, next_pc; 1755 1756 pc = get_frame_pc (frame); 1757 next_pc = alpha_next_pc (frame, pc); 1758 1759 insert_single_step_breakpoint (gdbarch, aspace, next_pc); 1760 return 1; 1761 } 1762 1763 1764 /* Initialize the current architecture based on INFO. If possible, re-use an 1765 architecture from ARCHES, which is a list of architectures already created 1766 during this debugging session. 1767 1768 Called e.g. at program startup, when reading a core file, and when reading 1769 a binary file. */ 1770 1771 static struct gdbarch * 1772 alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1773 { 1774 struct gdbarch_tdep *tdep; 1775 struct gdbarch *gdbarch; 1776 1777 /* Find a candidate among extant architectures. */ 1778 arches = gdbarch_list_lookup_by_info (arches, &info); 1779 if (arches != NULL) 1780 return arches->gdbarch; 1781 1782 tdep = XNEW (struct gdbarch_tdep); 1783 gdbarch = gdbarch_alloc (&info, tdep); 1784 1785 /* Lowest text address. This is used by heuristic_proc_start() 1786 to decide when to stop looking. */ 1787 tdep->vm_min_address = (CORE_ADDR) 0x120000000LL; 1788 1789 tdep->dynamic_sigtramp_offset = NULL; 1790 tdep->sigcontext_addr = NULL; 1791 tdep->sc_pc_offset = 2 * 8; 1792 tdep->sc_regs_offset = 4 * 8; 1793 tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8; 1794 1795 tdep->jb_pc = -1; /* longjmp support not enabled by default. */ 1796 1797 tdep->return_in_memory = alpha_return_in_memory_always; 1798 1799 /* Type sizes */ 1800 set_gdbarch_short_bit (gdbarch, 16); 1801 set_gdbarch_int_bit (gdbarch, 32); 1802 set_gdbarch_long_bit (gdbarch, 64); 1803 set_gdbarch_long_long_bit (gdbarch, 64); 1804 set_gdbarch_float_bit (gdbarch, 32); 1805 set_gdbarch_double_bit (gdbarch, 64); 1806 set_gdbarch_long_double_bit (gdbarch, 64); 1807 set_gdbarch_ptr_bit (gdbarch, 64); 1808 1809 /* Register info */ 1810 set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS); 1811 set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM); 1812 set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); 1813 set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); 1814 1815 set_gdbarch_register_name (gdbarch, alpha_register_name); 1816 set_gdbarch_register_type (gdbarch, alpha_register_type); 1817 1818 set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); 1819 set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); 1820 1821 set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p); 1822 set_gdbarch_register_to_value (gdbarch, alpha_register_to_value); 1823 set_gdbarch_value_to_register (gdbarch, alpha_value_to_register); 1824 1825 set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p); 1826 1827 /* Prologue heuristics. */ 1828 set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); 1829 1830 /* Entrypoint heuristics. */ 1831 set_gdbarch_skip_entrypoint (gdbarch, alpha_skip_entrypoint); 1832 1833 /* Disassembler. */ 1834 set_gdbarch_print_insn (gdbarch, print_insn_alpha); 1835 1836 /* Call info. */ 1837 1838 set_gdbarch_return_value (gdbarch, alpha_return_value); 1839 1840 /* Settings for calling functions in the inferior. */ 1841 set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call); 1842 1843 /* Methods for saving / extracting a dummy frame's ID. */ 1844 set_gdbarch_dummy_id (gdbarch, alpha_dummy_id); 1845 1846 /* Return the unwound PC value. */ 1847 set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc); 1848 1849 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1850 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 1851 1852 set_gdbarch_breakpoint_from_pc (gdbarch, alpha_breakpoint_from_pc); 1853 set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); 1854 set_gdbarch_cannot_step_breakpoint (gdbarch, 1); 1855 1856 /* Handles single stepping of atomic sequences. */ 1857 set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence); 1858 1859 /* Hook in ABI-specific overrides, if they have been registered. */ 1860 gdbarch_init_osabi (info, gdbarch); 1861 1862 /* Now that we have tuned the configuration, set a few final things 1863 based on what the OS ABI has told us. */ 1864 1865 if (tdep->jb_pc >= 0) 1866 set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target); 1867 1868 frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind); 1869 frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind); 1870 1871 frame_base_set_default (gdbarch, &alpha_heuristic_frame_base); 1872 1873 return gdbarch; 1874 } 1875 1876 void 1877 alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 1878 { 1879 dwarf2_append_unwinders (gdbarch); 1880 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); 1881 } 1882 1883 extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */ 1884 1885 void 1886 _initialize_alpha_tdep (void) 1887 { 1888 1889 gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); 1890 1891 /* Let the user set the fence post for heuristic_proc_start. */ 1892 1893 /* We really would like to have both "0" and "unlimited" work, but 1894 command.c doesn't deal with that. So make it a var_zinteger 1895 because the user can always use "999999" or some such for unlimited. */ 1896 /* We need to throw away the frame cache when we set this, since it 1897 might change our ability to get backtraces. */ 1898 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, 1899 &heuristic_fence_post, _("\ 1900 Set the distance searched for the start of a function."), _("\ 1901 Show the distance searched for the start of a function."), _("\ 1902 If you are debugging a stripped executable, GDB needs to search through the\n\ 1903 program for the start of a function. This command sets the distance of the\n\ 1904 search. The only need to set it is when debugging a stripped executable."), 1905 reinit_frame_cache_sfunc, 1906 NULL, /* FIXME: i18n: The distance searched for 1907 the start of a function is \"%d\". */ 1908 &setlist, &showlist); 1909 } 1910