1 /* Common target dependent code for GDB on AArch64 systems. 2 3 Copyright (C) 2009-2023 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef AARCH64_TDEP_H 23 #define AARCH64_TDEP_H 24 25 #include "arch/aarch64.h" 26 #include "displaced-stepping.h" 27 #include "infrun.h" 28 #include "gdbarch.h" 29 30 /* Forward declarations. */ 31 struct gdbarch; 32 struct regset; 33 34 /* AArch64 Dwarf register numbering. */ 35 #define AARCH64_DWARF_X0 0 36 #define AARCH64_DWARF_SP 31 37 #define AARCH64_DWARF_PC 32 38 #define AARCH64_DWARF_RA_SIGN_STATE 34 39 #define AARCH64_DWARF_V0 64 40 #define AARCH64_DWARF_SVE_VG 46 41 #define AARCH64_DWARF_SVE_FFR 47 42 #define AARCH64_DWARF_SVE_P0 48 43 #define AARCH64_DWARF_SVE_Z0 96 44 45 /* Size of integer registers. */ 46 #define X_REGISTER_SIZE 8 47 #define B_REGISTER_SIZE 1 48 #define H_REGISTER_SIZE 2 49 #define S_REGISTER_SIZE 4 50 #define D_REGISTER_SIZE 8 51 #define Q_REGISTER_SIZE 16 52 53 /* Total number of general (X) registers. */ 54 #define AARCH64_X_REGISTER_COUNT 32 55 /* Total number of D registers. */ 56 #define AARCH64_D_REGISTER_COUNT 32 57 58 /* The maximum number of modified instructions generated for one 59 single-stepped instruction. */ 60 #define AARCH64_DISPLACED_MODIFIED_INSNS 1 61 62 /* Target-dependent structure in gdbarch. */ 63 struct aarch64_gdbarch_tdep : gdbarch_tdep_base 64 { 65 /* Lowest address at which instructions will appear. */ 66 CORE_ADDR lowest_pc = 0; 67 68 /* Offset to PC value in jump buffer. If this is negative, longjmp 69 support will be disabled. */ 70 int jb_pc = 0; 71 72 /* And the size of each entry in the buf. */ 73 size_t jb_elt_size = 0; 74 75 /* Types for AdvSISD registers. */ 76 struct type *vnq_type = nullptr; 77 struct type *vnd_type = nullptr; 78 struct type *vns_type = nullptr; 79 struct type *vnh_type = nullptr; 80 struct type *vnb_type = nullptr; 81 struct type *vnv_type = nullptr; 82 83 /* syscall record. */ 84 int (*aarch64_syscall_record) (struct regcache *regcache, 85 unsigned long svc_number) = nullptr; 86 87 /* The VQ value for SVE targets, or zero if SVE is not supported. */ 88 uint64_t vq = 0; 89 90 /* Returns true if the target supports SVE. */ 91 bool has_sve () const 92 { 93 return vq != 0; 94 } 95 96 int pauth_reg_base = 0; 97 int ra_sign_state_regnum = 0; 98 99 /* Returns true if the target supports pauth. */ 100 bool has_pauth () const 101 { 102 return pauth_reg_base != -1; 103 } 104 105 /* First MTE register. This is -1 if no MTE registers are available. */ 106 int mte_reg_base = 0; 107 108 /* Returns true if the target supports MTE. */ 109 bool has_mte () const 110 { 111 return mte_reg_base != -1; 112 } 113 114 /* TLS registers. This is -1 if the TLS registers are not available. */ 115 int tls_regnum_base = 0; 116 int tls_register_count = 0; 117 118 bool has_tls() const 119 { 120 return tls_regnum_base != -1; 121 } 122 123 /* The W pseudo-registers. */ 124 int w_pseudo_base = 0; 125 int w_pseudo_count = 0; 126 }; 127 128 const target_desc *aarch64_read_description (const aarch64_features &features); 129 aarch64_features 130 aarch64_features_from_target_desc (const struct target_desc *tdesc); 131 132 extern int aarch64_process_record (struct gdbarch *gdbarch, 133 struct regcache *regcache, CORE_ADDR addr); 134 135 displaced_step_copy_insn_closure_up 136 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, 137 CORE_ADDR from, CORE_ADDR to, 138 struct regcache *regs); 139 140 void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, 141 displaced_step_copy_insn_closure *dsc, 142 CORE_ADDR from, CORE_ADDR to, 143 struct regcache *regs); 144 145 bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch); 146 147 #endif /* aarch64-tdep.h */ 148