1; OpenRISC Basic Instruction Set 32-bit (ORBIS) -*- Scheme -*- 2; Copyright 2000-2014 Free Software Foundation, Inc. 3; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 4; Modified by Julius Baxter, juliusbaxter@gmail.com 5; Modified by Peter Gavin, pgavin@gmail.com 6; 7; This program is free software; you can redistribute it and/or modify 8; it under the terms of the GNU General Public License as published by 9; the Free Software Foundation; either version 3 of the License, or 10; (at your option) any later version. 11; 12; This program is distributed in the hope that it will be useful, 13; but WITHOUT ANY WARRANTY; without even the implied warranty of 14; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15; GNU General Public License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with this program; if not, see <http://www.gnu.org/licenses/> 19 20; Instruction fields. 21 22; Hardware for immediate operands 23(dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ()) 24(dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ()) 25(dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ()) 26 27; Hardware for the (internal) atomic registers 28(dsh h-atomic-reserve "atomic reserve flag" () (register BI)) 29(dsh h-atomic-address "atomic reserve address" () (register SI)) 30 31; Instruction classes. 32(dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6) 33 34; Register fields. 35(dnf f-r1 "r1" ((MACH ORBIS-MACHS)) 25 5) 36(dnf f-r2 "r2" ((MACH ORBIS-MACHS)) 20 5) 37(dnf f-r3 "r3" ((MACH ORBIS-MACHS)) 15 5) 38 39; Sub fields 40(dnf f-op-25-2 "op-25-2" ((MACH ORBIS-MACHS)) 25 2) ;; nop 41(dnf f-op-25-5 "op-25-5" ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf* 42(dnf f-op-16-1 "op-16-1" ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc 43(dnf f-op-7-4 "op-7-4" ((MACH ORBIS-MACHS)) 7 4) 44(dnf f-op-3-4 "op-3-4" ((MACH ORBIS-MACHS)) 3 4) 45(dnf f-op-9-2 "op-9-2" ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode 46(dnf f-op-9-4 "op-9-4" ((MACH ORBIS-MACHS)) 9 4) ;; 47(dnf f-op-7-8 "op-7-8" ((MACH ORBIS-MACHS)) 7 8) 48(dnf f-op-7-2 "op-7-2" ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti 49 50; Reserved fields 51(dnf f-resv-25-26 "resv-25-26" ((MACH ORBIS-MACHS) RESERVED) 25 26) 52(dnf f-resv-25-10 "resv-25-10" ((MACH ORBIS-MACHS) RESERVED) 25 10) 53(dnf f-resv-25-5 "resv-25-5" ((MACH ORBIS-MACHS) RESERVED) 25 5) 54(dnf f-resv-23-8 "resv-23-8" ((MACH ORBIS-MACHS) RESERVED) 23 8) 55(dnf f-resv-20-21 "resv-20-21" ((MACH ORBIS-MACHS) RESERVED) 20 21) 56(dnf f-resv-20-5 "resv-20-5" ((MACH ORBIS-MACHS) RESERVED) 20 5) 57(dnf f-resv-20-4 "resv-20-4" ((MACH ORBIS-MACHS) RESERVED) 20 4) 58(dnf f-resv-15-8 "resv-15-8" ((MACH ORBIS-MACHS) RESERVED) 15 8) 59(dnf f-resv-15-6 "resv-15-6" ((MACH ORBIS-MACHS) RESERVED) 15 6) 60(dnf f-resv-10-11 "resv-10-11" ((MACH ORBIS-MACHS) RESERVED) 10 11) 61(dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7) 62(dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3) 63(dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1) 64(dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4) 65(dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2) 66 67(dnf f-imm16-25-5 "imm16-25-5" ((MACH ORBIS-MACHS)) 25 5) 68(dnf f-imm16-10-11 "imm16-10-11" ((MACH ORBIS-MACHS)) 10 11) 69 70; PC relative, 26-bit (2 shifted to right) 71(df f-disp26 72 "disp26" 73 ((MACH ORBIS-MACHS) PCREL-ADDR) 74 25 75 26 76 INT 77 ((value pc) (sra IAI (sub IAI value pc) (const 2))) 78 ((value pc) (add IAI (sll IAI value (const 2)) pc)) 79 ) 80 81; PC relative, 21-bit, 13 shifted to right, aligned. 82; Note that the alignment means that we can't simplify relocations in the 83; same way as we do for pc-relative, so we use ABS-ADDR instead of PCREL-ADDR. 84(df f-disp21 85 "disp21" 86 ((MACH ORBIS-MACHS) ABS-ADDR) 87 20 88 21 89 INT 90 ((value pc) 91 (sub IAI (sra IAI value (const 13)) (sra IAI pc (const 13)))) 92 ((value pc) 93 (sll IAI (add IAI value (sra IAI pc (const 13))) (const 13))) 94 ) 95 96; Immediates. 97(dnf f-uimm16 "uimm16" ((MACH ORBIS-MACHS)) 15 16) 98(df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f) 99(dnf f-uimm6 "uimm6" ((MACH ORBIS-MACHS)) 5 6) ;; shroti 100 101(define-multi-ifield 102 (name f-uimm16-split) 103 (comment "16-bit split unsigned immediate") 104 (attrs (MACH ORBIS-MACHS)) 105 (mode UINT) 106 (subfields f-imm16-25-5 f-imm16-10-11) 107 (insert (sequence () 108 (set (ifield f-imm16-25-5) 109 (and (srl (ifield f-uimm16-split) 110 (const 11)) 111 (const #x1f))) 112 (set (ifield f-imm16-10-11) 113 (and (ifield f-uimm16-split) 114 (const #x7ff))))) 115 (extract 116 (set (ifield f-uimm16-split) 117 (trunc UHI 118 (or (sll (ifield f-imm16-25-5) 119 (const 11)) 120 (ifield f-imm16-10-11))))) 121 ) 122 123(define-multi-ifield 124 (name f-simm16-split) 125 (comment "16-bit split signed immediate") 126 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 127 (mode INT) 128 (subfields f-imm16-25-5 f-imm16-10-11) 129 (insert (sequence () 130 (set (ifield f-imm16-25-5) 131 (and (sra (ifield f-simm16-split) 132 (const 11)) 133 (const #x1f))) 134 (set (ifield f-imm16-10-11) 135 (and (ifield f-simm16-split) 136 (const #x7ff))))) 137 (extract 138 (set (ifield f-simm16-split) 139 (trunc HI 140 (or (sll (ifield f-imm16-25-5) 141 (const 11)) 142 (ifield f-imm16-10-11))))) 143 ) 144 145; Enums. 146 147; insn-opcode: bits 31-26 148(define-normal-insn-enum 149 insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode 150 (("J" #x00) 151 ("JAL" #x01) 152 ("ADRP" #x02) 153 ("BNF" #x03) 154 ("BF" #x04) 155 ("NOP" #x05) 156 ("MOVHIMACRC" #x06) 157 ("SYSTRAPSYNCS" #x08) 158 ("RFE" #x09) 159 ("VECTOR" #x0a) 160 ("JR" #x11) 161 ("JALR" #x12) 162 ("MACI" #x13) 163 ("LWA" #x1b) 164 ("CUST1" #x1c) 165 ("CUST2" #x1d) 166 ("CUST3" #x1e) 167 ("CUST4" #x1f) 168 ("LD" #x20) 169 ("LWZ" #x21) 170 ("LWS" #x22) 171 ("LBZ" #x23) 172 ("LBS" #x24) 173 ("LHZ" #x25) 174 ("LHS" #x26) 175 ("ADDI" #x27) 176 ("ADDIC" #x28) 177 ("ANDI" #x29) 178 ("ORI" #x2a) 179 ("XORI" #x2b) 180 ("MULI" #x2c) 181 ("MFSPR" #x2d) 182 ("SHROTI" #x2e) 183 ("SFI" #x2f) 184 ("MTSPR" #x30) 185 ("MAC" #x31) 186 ("FLOAT" #x32) 187 ("SWA" #x33) 188 ("SD" #x34) 189 ("SW" #x35) 190 ("SB" #x36) 191 ("SH" #x37) 192 ("ALU" #x38) 193 ("SF" #x39) 194 ("CUST5" #x3c) 195 ("CUST6" #x3d) 196 ("CUST7" #x3e) 197 ("CUST8" #x3f) 198 ) 199) 200 201(define-normal-insn-enum insn-opcode-systrapsyncs 202 "systrapsync insn opcode enums" ((MACH ORBIS-MACHS)) 203 OPC_SYSTRAPSYNCS_ f-op-25-5 204 (("SYSCALL" #x00 ) 205 ("TRAP" #x08 ) 206 ("MSYNC" #x10 ) 207 ("PSYNC" #x14 ) 208 ("CSYNC" #x18 ) 209 ) 210) 211 212(define-normal-insn-enum insn-opcode-movehimacrc 213 "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS)) 214 OPC_MOVHIMACRC_ f-op-16-1 215 (("MOVHI" #x0) 216 ("MACRC" #x1) 217 ) 218) 219 220(define-normal-insn-enum insn-opcode-mac 221 "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS)) 222 OPC_MAC_ f-op-3-4 223 (("MAC" #x1) 224 ("MSB" #x2) 225 ("MACU" #x3) 226 ("MSBU" #x4) 227 ) 228 ) 229 230(define-normal-insn-enum insn-opcode-shorts 231 "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS)) 232 OPC_SHROTS_ f-op-7-2 233 (("SLL" #x0 ) 234 ("SRL" #x1 ) 235 ("SRA" #x2 ) 236 ("ROR" #x3 ) 237 ) 238) 239 240(define-normal-insn-enum insn-opcode-extbhs 241 "extend byte/half opcode enums" ((MACH ORBIS-MACHS)) 242 OPC_EXTBHS_ f-op-9-4 243 (("EXTHS" #x0) 244 ("EXTBS" #x1) 245 ("EXTHZ" #x2) 246 ("EXTBZ" #x3) 247 ) 248) 249 250(define-normal-insn-enum insn-opcode-extws 251 "extend word opcode enums" ((MACH ORBIS-MACHS)) 252 OPC_EXTWS_ f-op-9-4 253 (("EXTWS" #x0) 254 ("EXTWZ" #x1) 255 ) 256) 257 258(define-normal-insn-enum insn-opcode-alu-regreg 259 "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS)) 260 OPC_ALU_REGREG_ f-op-3-4 261 (("ADD" #x0) 262 ("ADDC" #x1) 263 ("SUB" #x2) 264 ("AND" #x3) 265 ("OR" #x4) 266 ("XOR" #x5) 267 ("MUL" #x6) 268 ("MULD" #x7) 269 ("SHROT" #x8) 270 ("DIV" #x9) 271 ("DIVU" #xA) 272 ("MULU" #xB) 273 ("EXTBH" #xC) 274 ("EXTW" #xD) 275 ("MULDU" #xD) 276 ("CMOV" #xE) 277 ("FFL1" #xF) 278 ) 279) 280 281(define-normal-insn-enum insn-opcode-setflag 282 "setflag insn opcode enums" ((MACH ORBIS-MACHS)) 283 OPC_SF_ f-op-25-5 284 (("EQ" #x00) 285 ("NE" #x01) 286 ("GTU" #x02) 287 ("GEU" #x03) 288 ("LTU" #x04) 289 ("LEU" #x05) 290 ("GTS" #x0A) 291 ("GES" #x0B) 292 ("LTS" #x0C) 293 ("LES" #x0D) 294 ) 295) 296 297 298; Instruction operands. 299 300(dnop sys-sr "supervision register" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr f-nil) 301(dnop sys-esr0 "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0 f-nil) 302(dnop sys-epcr0 "exception PC register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0 f-nil) 303 304(dnop sys-sr-lee "SR little endian enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee f-nil) 305(dnop sys-sr-f "SR flag bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f f-nil) 306(dnop sys-sr-cy "SR carry bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy f-nil) 307(dnop sys-sr-ov "SR overflow bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov f-nil) 308(dnop sys-sr-ove "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove f-nil) 309(dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil) 310(dnop sys-cpucfgr-nd "CPUCFGR no delay bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd f-nil) 311(dnop sys-fpcsr-rm "floating point round mode" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm f-nil) 312 313(dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil) 314(dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil) 315 316(dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil) 317(dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil) 318 319(dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6) 320 321(dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1) 322(dnop rA "source register A" ((MACH ORBIS-MACHS)) h-gpr f-r2) 323(dnop rB "source register B" ((MACH ORBIS-MACHS)) h-gpr f-r3) 324 325(define-operand 326 (name disp26) 327 (comment "pc-rel 26 bit") 328 (attrs (MACH ORBIS-MACHS)) 329 (type h-iaddr) 330 (index f-disp26) 331 (handlers (parse "disp26")) 332 ) 333 334(define-operand 335 (name disp21) 336 (comment "pc-rel 21 bit") 337 (attrs (MACH ORBIS-MACHS)) 338 (type h-iaddr) 339 (index f-disp21) 340 (handlers (parse "disp21")) 341 ) 342 343(define-operand 344 (name simm16) 345 (comment "16-bit signed immediate") 346 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 347 (type h-simm16) 348 (index f-simm16) 349 (handlers (parse "simm16")) 350 ) 351 352(define-operand 353 (name uimm16) 354 (comment "16-bit unsigned immediate") 355 (attrs (MACH ORBIS-MACHS)) 356 (type h-uimm16) 357 (index f-uimm16) 358 (handlers (parse "uimm16")) 359 ) 360 361(define-operand 362 (name simm16-split) 363 (comment "split 16-bit signed immediate") 364 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 365 (type h-simm16) 366 (index f-simm16-split) 367 (handlers (parse "simm16_split")) 368) 369 370(define-operand 371 (name uimm16-split) 372 (comment "split 16-bit unsigned immediate") 373 (attrs (MACH ORBIS-MACHS)) 374 (type h-uimm16) 375 (index f-uimm16-split) 376 (handlers (parse "uimm16_split")) 377) 378 379; Instructions. 380 381; Branch releated instructions 382 383(define-pmacro (cti-link-return) 384 (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8))) 385 ) 386(define-pmacro (cti-transfer-control condition target) 387 ;; this mess is necessary because we're 388 ;; skipping the delay slot, but it's 389 ;; actually the start of the next basic 390 ;; block 391 (sequence () 392 (if condition 393 (delay 1 (set IAI pc target)) 394 (if sys-cpucfgr-nd 395 (delay 1 (set IAI pc (add pc 4)))) 396 ) 397 (if sys-cpucfgr-nd 398 (skip 1) 399 ) 400 ) 401 ) 402 403(define-pmacro 404 (define-cti 405 cti-name 406 cti-comment 407 cti-attrs 408 cti-syntax 409 cti-format 410 cti-semantics) 411 (begin 412 (dni 413 cti-name 414 cti-comment 415 (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs)) 416 cti-syntax 417 cti-format 418 (cti-semantics) 419 () 420 ) 421 ) 422 ) 423 424(define-cti 425 l-j 426 "jump (pc-relative iaddr)" 427 (!COND-CTI UNCOND-CTI) 428 "l.j ${disp26}" 429 (+ OPC_J disp26) 430 (.pmacro () 431 (cti-transfer-control 1 disp26) 432 ) 433 ) 434 435(dni l-adrp "adrp reg/disp21" 436 ((MACH ORBIS-MACHS)) 437 "l.adrp $rD,${disp21}" 438 (+ OPC_ADRP rD disp21) 439 (set UWI rD disp21) 440 () 441 ) 442 443(define-cti 444 l-jal 445 "jump and link (pc-relative iaddr)" 446 (!COND-CTI UNCOND-CTI) 447 "l.jal ${disp26}" 448 (+ OPC_JAL disp26) 449 (.pmacro () 450 (sequence () 451 (cti-link-return) 452 (cti-transfer-control 1 disp26) 453 ) 454 ) 455 ) 456 457(define-cti 458 l-jr 459 "jump register (absolute iaddr)" 460 (!COND-CTI UNCOND-CTI) 461 "l.jr $rB" 462 (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0)) 463 (.pmacro () 464 (cti-transfer-control 1 rB) 465 ) 466 ) 467 468(define-cti 469 l-jalr 470 "jump register and link (absolute iaddr)" 471 (!COND-CTI UNCOND-CTI) 472 "l.jalr $rB" 473 (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) ) 474 (.pmacro () 475 (sequence () 476 (cti-link-return) 477 (cti-transfer-control 1 rB) 478 ) 479 ) 480 ) 481 482(define-cti 483 l-bnf 484 "branch if condition bit not set (pc relative iaddr)" 485 (COND-CTI !UNCOND-CTI) 486 "l.bnf ${disp26}" 487 (+ OPC_BNF disp26) 488 (.pmacro () 489 (cti-transfer-control (not sys-sr-f) disp26) 490 ) 491 ) 492 493(define-cti 494 l-bf 495 "branch if condition bit set (pc relative iaddr)" 496 (COND-CTI !UNCOND-CTI) 497 "l.bf ${disp26}" 498 (+ OPC_BF disp26) 499 (.pmacro () 500 (cti-transfer-control sys-sr-f disp26) 501 ) 502 ) 503 504(dni l-trap "trap (exception)" 505 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 506 "l.trap ${uimm16}" 507 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16) 508 ; Do exception entry handling in C function, PC set based on SR state 509 (raise-exception EXCEPT-TRAP) 510 () 511) 512 513 514(dni l-sys "syscall (exception)" 515 ; This function may not be in delay slot 516 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 517 518 "l.sys ${uimm16}" 519 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16) 520 ; Do exception entry handling in C function, PC set based on SR state 521 (raise-exception EXCEPT-SYSCALL) 522 () 523) 524 525(dni l-msync "memory sync" 526 ((MACH ORBIS-MACHS)) 527 "l.msync" 528 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_MSYNC (f-resv-20-21 0)) 529 (nop) 530 () 531) 532 533(dni l-psync "pipeline sync" 534 ((MACH ORBIS-MACHS)) 535 "l.psync" 536 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_PSYNC (f-resv-20-21 0)) 537 (nop) 538 () 539) 540 541(dni l-csync "context sync" 542 ((MACH ORBIS-MACHS)) 543 "l.csync" 544 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_CSYNC (f-resv-20-21 0)) 545 (nop) 546 () 547) 548 549(dni l-rfe "return from exception" 550 ; This function may not be in delay slot 551 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI) 552 553 "l.rfe" 554 (+ OPC_RFE (f-resv-25-26 0)) 555 (c-call VOID "@cpu@_rfe") 556 () 557) 558 559 560; Misc instructions 561 562; l.nop with immediate must be first so it handles all l.nops in sim 563(dni l-nop-imm "nop uimm16" 564 ((MACH ORBIS-MACHS)) 565 "l.nop ${uimm16}" 566 (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 567 (c-call VOID "@cpu@_nop" (zext UWI uimm16)) 568 () 569 ) 570 571(if (application-is? SIMULATOR) 572 (begin) 573 (begin 574 (dni l-nop "nop" 575 ((MACH ORBIS-MACHS)) 576 "l.nop" 577 (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 578 (nop) 579 () 580 ) 581 ) 582) 583 584(dni l-movhi "movhi reg/uimm16" 585 ((MACH ORBIS-MACHS)) 586 "l.movhi $rD,$uimm16" 587 (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16) 588 (set UWI rD (sll UWI (zext UWI uimm16) (const 16))) 589 () 590) 591 592(dni l-macrc "macrc reg" 593 ((MACH ORBIS-MACHS)) 594 "l.macrc $rD" 595 (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0)) 596 (sequence () 597 (set UWI rD mac-maclo) 598 (set UWI mac-maclo 0) 599 (set UWI mac-machi 0) 600 ) 601 () 602) 603 604 605; System releated instructions 606 607(dni l-mfspr "mfspr" 608 ((MACH ORBIS-MACHS)) 609 "l.mfspr $rD,$rA,${uimm16}" 610 (+ OPC_MFSPR rD rA uimm16) 611 (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16)))) 612 () 613) 614 615(dni l-mtspr "mtspr" 616 ((MACH ORBIS-MACHS)) 617 "l.mtspr $rA,$rB,${uimm16-split}" 618 (+ OPC_MTSPR rA rB uimm16-split ) 619 (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB) 620 () 621) 622 623 624; Load instructions 625(define-pmacro (load-store-addr base offset size) 626 (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size)) 627 628(dni l-lwz "l.lwz reg/simm16(reg)" 629 ((MACH ORBIS-MACHS)) 630 "l.lwz $rD,${simm16}($rA)" 631 (+ OPC_LWZ rD rA simm16) 632 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 633 () 634) 635 636 637(dni l-lws "l.lws reg/simm16(reg)" 638 ((MACH ORBIS-MACHS)) 639 "l.lws $rD,${simm16}($rA)" 640 (+ OPC_LWS rD rA simm16) 641 (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4)))) 642 () 643) 644 645(dni l-lwa "l.lwa reg/simm16(reg)" 646 ((MACH ORBIS-MACHS)) 647 "l.lwa $rD,${simm16}($rA)" 648 (+ OPC_LWA rD rA simm16) 649 (sequence () 650 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 651 (set atomic-reserve (const 1)) 652 (set atomic-address (load-store-addr rA simm16 4)) 653 ) 654 () 655) 656 657(dni l-lbz "l.lbz reg/simm16(reg)" 658 ((MACH ORBIS-MACHS)) 659 "l.lbz $rD,${simm16}($rA)" 660 (+ OPC_LBZ rD rA simm16) 661 (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1)))) 662 () 663) 664 665(dni l-lbs "l.lbs reg/simm16(reg)" 666 ((MACH ORBIS-MACHS)) 667 "l.lbs $rD,${simm16}($rA)" 668 (+ OPC_LBS rD rA simm16) 669 (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1)))) 670 () 671) 672 673(dni l-lhz "l.lhz reg/simm16(reg)" 674 ((MACH ORBIS-MACHS)) 675 "l.lhz $rD,${simm16}($rA)" 676 (+ OPC_LHZ rD simm16 rA) 677 (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2)))) 678 () 679) 680 681(dni l-lhs "l.lhs reg/simm16(reg)" 682 ((MACH ORBIS-MACHS)) 683 "l.lhs $rD,${simm16}($rA)" 684 (+ OPC_LHS rD rA simm16) 685 (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2)))) 686 () 687) 688 689 690; Store instructions 691 692(define-pmacro (store-insn mnemonic opc-op mode size) 693 (begin 694 (dni (.sym l- mnemonic) 695 (.str "l." mnemonic " simm16(reg)/reg") 696 ((MACH ORBIS-MACHS)) 697 (.str "l." mnemonic " ${simm16-split}($rA),$rB") 698 (+ opc-op rA rB simm16-split) 699 (sequence ((SI addr)) 700 (set addr (load-store-addr rA simm16-split size)) 701 (set mode (mem mode addr) (trunc mode rB)) 702 (if (eq (and addr #xffffffc) atomic-address) 703 (set atomic-reserve (const 0)) 704 ) 705 ) 706 () 707 ) 708 ) 709) 710 711(store-insn sw OPC_SW USI 4) 712(store-insn sb OPC_SB UQI 1) 713(store-insn sh OPC_SH UHI 2) 714 715(dni l-swa "l.swa simm16(reg)/reg" 716 ((MACH ORBIS-MACHS)) 717 "l.swa ${simm16-split}($rA),$rB" 718 (+ OPC_SWA rA rB simm16) 719 (sequence ((SI addr) (BI flag)) 720 (set addr (load-store-addr rA simm16-split 4)) 721 (set sys-sr-f (and atomic-reserve (eq addr atomic-address))) 722 (if sys-sr-f 723 (set USI (mem USI addr) (trunc USI rB)) 724 ) 725 (set atomic-reserve (const 0)) 726 ) 727 () 728) 729 730 731; Shift and rotate instructions 732 733(define-pmacro (shift-insn mnemonic) 734 (begin 735 (dni (.sym l- mnemonic) 736 (.str "l." mnemonic " reg/reg/reg") 737 ((MACH ORBIS-MACHS)) 738 (.str "l." mnemonic " $rD,$rA,$rB") 739 (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0) 740 OPC_ALU_REGREG_SHROT ) 741 (set UWI rD (mnemonic rA rB)) 742 () 743 ) 744 (dni (.sym l- mnemonic "i") 745 (.str "l." mnemonic " reg/reg/uimm6") 746 ((MACH ORBIS-MACHS)) 747 (.str "l." mnemonic "i $rD,$rA,${uimm6}") 748 (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6) 749 (set rD (mnemonic rA uimm6)) 750 () 751 ) 752 ) 753) 754 755(shift-insn sll) 756(shift-insn srl) 757(shift-insn sra) 758(shift-insn ror) 759 760 761; Arithmetic insns 762 763; ALU op macro 764(define-pmacro (alu-insn mnemonic) 765 (begin 766 (dni (.sym l- mnemonic) 767 (.str "l." mnemonic " reg/reg/reg") 768 ((MACH ORBIS-MACHS)) 769 (.str "l." mnemonic " $rD,$rA,$rB") 770 (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 771 (set rD (mnemonic rA rB)) 772 () 773 ) 774 ) 775) 776 777(alu-insn and) 778(alu-insn or) 779(alu-insn xor) 780 781(define-pmacro (alu-carry-insn mnemonic) 782 (begin 783 (dni (.sym l- mnemonic) 784 (.str "l." mnemonic " reg/reg/reg") 785 ((MACH ORBIS-MACHS)) 786 (.str "l." mnemonic " $rD,$rA,$rB") 787 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 788 (sequence () 789 (sequence () 790 (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0)) 791 (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0)) 792 (set rD (mnemonic WI rA rB)) 793 ) 794 (if (andif sys-sr-ov sys-sr-ove) 795 (raise-exception EXCEPT-RANGE)) 796 ) 797 () 798 ) 799 ) 800 ) 801 802(alu-carry-insn add) 803(alu-carry-insn sub) 804 805(dni (l-addc) "l.addc reg/reg/reg" 806 ((MACH ORBIS-MACHS)) 807 ("l.addc $rD,$rA,$rB") 808 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC) 809 (sequence () 810 (sequence ((BI tmp-sys-sr-cy)) 811 (set BI tmp-sys-sr-cy sys-sr-cy) 812 (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy)) 813 (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy)) 814 (set rD (addc WI rA rB tmp-sys-sr-cy)) 815 ) 816 (if (andif sys-sr-ov sys-sr-ove) 817 (raise-exception EXCEPT-RANGE)) 818 ) 819 () 820) 821 822(dni (l-mul) "l.mul reg/reg/reg" 823 ((MACH ORBIS-MACHS)) 824 ("l.mul $rD,$rA,$rB") 825 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL) 826 (sequence () 827 (sequence () 828 (set BI sys-sr-ov (mul-o2flag WI rA rB)) 829 (set rD (mul WI rA rB)) 830 ) 831 (if (andif sys-sr-ov sys-sr-ove) 832 (raise-exception EXCEPT-RANGE)) 833 ) 834 () 835) 836 837(dni (l-muld) "l.muld reg/reg" 838 ((MACH ORBIS-MACHS)) 839 ("l.muld $rA,$rB") 840 (+ OPC_ALU (f-resv-25-5 0) rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULD) 841 (sequence ((DI result)) 842 (set DI result (mul DI (ext DI rA) (ext DI rB))) 843 (set SI mac-machi (subword SI result 0)) 844 (set SI mac-maclo (subword SI result 1)) 845 ) 846 () 847) 848 849(dni (l-mulu) "l.mulu reg/reg/reg" 850 ((MACH ORBIS-MACHS)) 851 ("l.mulu $rD,$rA,$rB") 852 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU) 853 (sequence () 854 (sequence () 855 (set BI sys-sr-cy (mul-o1flag UWI rA rB)) 856 (set rD (mul UWI rA rB)) 857 ) 858 (if (andif sys-sr-cy sys-sr-ove) 859 (raise-exception EXCEPT-RANGE)) 860 ) 861 () 862) 863 864(dni (l-muldu) "l.muld reg/reg" 865 ((MACH ORBIS-MACHS)) 866 ("l.muldu $rA,$rB") 867 (+ OPC_ALU (f-resv-25-5 0) rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULDU) 868 (sequence ((DI result)) 869 (set DI result (mul DI (zext DI rA) (zext DI rB))) 870 (set SI mac-machi (subword SI result 0)) 871 (set SI mac-maclo (subword SI result 1)) 872 ) 873 () 874) 875 876(dni l-div "divide (signed)" 877 ((MACH ORBIS-MACHS)) 878 "l.div $rD,$rA,$rB" 879 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV) 880 (if (ne rB 0) 881 (sequence () 882 (set BI sys-sr-ov 0) 883 (set WI rD (div WI rA rB)) 884 ) 885 (sequence () 886 (set BI sys-sr-ov 1) 887 (if sys-sr-ove 888 (raise-exception EXCEPT-RANGE)) 889 ) 890 ) 891 () 892) 893 894(dni l-divu "divide (unsigned)" 895 ((MACH ORBIS-MACHS)) 896 "l.divu $rD,$rA,$rB" 897 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU) 898 (if (ne rB 0) 899 (sequence () 900 (set BI sys-sr-cy 0) 901 (set rD (udiv UWI rA rB)) 902 ) 903 (sequence () 904 (set BI sys-sr-cy 1) 905 (if sys-sr-ove 906 (raise-exception EXCEPT-RANGE)) 907 ) 908 ) 909 () 910) 911 912(dni l-ff1 "find first '1'" 913 ((MACH ORBIS-MACHS)) 914 "l.ff1 $rD,$rA" 915 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1) 916 (set rD (c-call UWI "@cpu@_ff1" rA)) 917 () 918) 919 920(dni l-fl1 "find last '1'" 921 ((MACH ORBIS-MACHS)) 922 "l.fl1 $rD,$rA" 923 (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1) 924 (set rD (c-call UWI "@cpu@_fl1" rA)) 925 () 926) 927 928 929(define-pmacro (alu-insn-simm mnemonic) 930 (begin 931 (dni (.sym l- mnemonic "i") 932 (.str "l." mnemonic " reg/reg/simm16") 933 ((MACH ORBIS-MACHS)) 934 (.str "l." mnemonic "i $rD,$rA,$simm16") 935 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 936 (set rD (mnemonic rA (ext WI simm16))) 937 () 938 ) 939 ) 940) 941 942(define-pmacro (alu-insn-uimm mnemonic) 943 (begin 944 (dni (.sym l- mnemonic "i") 945 (.str "l." mnemonic " reg/reg/uimm16") 946 ((MACH ORBIS-MACHS)) 947 (.str "l." mnemonic "i $rD,$rA,$uimm16") 948 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16) 949 (set rD (mnemonic rA (zext UWI uimm16))) 950 () 951 ) 952 ) 953) 954 955(alu-insn-uimm and) 956(alu-insn-uimm or) 957(alu-insn-simm xor) 958 959(define-pmacro (alu-carry-insn-simm mnemonic) 960 (begin 961 (dni (.sym l- mnemonic "i") 962 (.str "l." mnemonic "i reg/reg/simm16") 963 ((MACH ORBIS-MACHS)) 964 (.str "l." mnemonic "i $rD,$rA,$simm16") 965 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 966 (sequence () 967 (sequence () 968 (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0)) 969 (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0)) 970 (set rD (mnemonic WI rA (ext WI simm16))) 971 ) 972 (if (andif sys-sr-ov sys-sr-ove) 973 (raise-exception EXCEPT-RANGE)) 974 ) 975 () 976 ) 977 ) 978 ) 979 980(alu-carry-insn-simm add) 981 982(dni (l-addic) 983 ("l.addic reg/reg/simm16") 984 ((MACH ORBIS-MACHS)) 985 ("l.addic $rD,$rA,$simm16") 986 (+ OPC_ADDIC rD rA simm16) 987 (sequence () 988 (sequence ((BI tmp-sys-sr-cy)) 989 (set BI tmp-sys-sr-cy sys-sr-cy) 990 (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 991 (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 992 (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy)) 993 ) 994 (if (andif sys-sr-ov sys-sr-ove) 995 (raise-exception EXCEPT-RANGE)) 996 ) 997 () 998) 999 1000(dni (l-muli) 1001 "l.muli reg/reg/simm16" 1002 ((MACH ORBIS-MACHS)) 1003 ("l.muli $rD,$rA,$simm16") 1004 (+ OPC_MULI rD rA simm16) 1005 (sequence () 1006 (sequence () 1007 (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16))) 1008 (set rD (mul WI rA (ext WI simm16))) 1009 ) 1010 (if (andif sys-sr-ov sys-sr-ove) 1011 (raise-exception EXCEPT-RANGE)) 1012 ) 1013 () 1014) 1015 1016(define-pmacro (extbh-insn mnemonic extop extmode truncmode) 1017 (begin 1018 (dni (.sym l- mnemonic) 1019 (.str "l." mnemonic " reg/reg") 1020 ((MACH ORBIS-MACHS)) 1021 (.str "l." mnemonic " $rD,$rA") 1022 (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH) 1023 (set rD (extop extmode (trunc truncmode rA))) 1024 () 1025 ) 1026 ) 1027 ) 1028 1029(extbh-insn exths ext WI HI) 1030(extbh-insn extbs ext WI QI) 1031(extbh-insn exthz zext UWI UHI) 1032(extbh-insn extbz zext UWI UQI) 1033 1034(define-pmacro (extw-insn mnemonic extop extmode truncmode) 1035 (begin 1036 (dni (.sym l- mnemonic) 1037 (.str "l." mnemonic " reg/reg") 1038 ((MACH ORBIS-MACHS)) 1039 (.str "l." mnemonic " $rD,$rA") 1040 (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW) 1041 (set rD (extop extmode (trunc truncmode rA))) 1042 () 1043 ) 1044 ) 1045 ) 1046 1047(extw-insn extws ext WI SI) 1048(extw-insn extwz zext USI USI) 1049 1050(dni l-cmov 1051 "l.cmov reg/reg/reg" 1052 ((MACH ORBIS-MACHS)) 1053 "l.cmov $rD,$rA,$rB" 1054 (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV) 1055 (if sys-sr-f 1056 (set UWI rD rA) 1057 (set UWI rD rB) 1058 ) 1059 () 1060 ) 1061 1062; Compare instructions 1063 1064; Ordering compare 1065(define-pmacro (sf-insn op) 1066 (begin 1067 (dni (.sym l- "sf" op "s") ; l-sfgts 1068 (.str "l.sf" op "s reg/reg") ; "l.sfgts reg/reg" 1069 ((MACH ORBIS-MACHS)) 1070 (.str "l.sf" op "s $rA,$rB") ; "l.sfgts $rA,$rB" 1071 (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0)) 1072 (set sys-sr-f (op WI rA rB)) ; (set sys-sr-f (gt WI rA rB)) 1073 () 1074 ) 1075 (dni (.sym l- "sf" op "si") ; l-sfgtsi 1076 (.str "l.sf" op "si reg/simm16") ; "l.sfgtsi reg/simm16" 1077 ((MACH ORBIS-MACHS)) 1078 (.str "l.sf" op "si $rA,$simm16") ; "l.sfgtsi $rA,$simm16" 1079 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16) ; (+ OPC_SFI OPC_SF_GTS rA simm16) 1080 (set sys-sr-f (op WI rA (ext WI simm16))) ; (set sys-sr-f (gt WI rA (ext WI simm16))) 1081 () 1082 ) 1083 (dni (.sym l- "sf" op "u") ; l-sfgtu 1084 (.str "l.sf" op "u reg/reg") ; "l.sfgtu reg/reg" 1085 ((MACH ORBIS-MACHS)) 1086 (.str "l.sf" op "u $rA,$rB") ; "l.sfgtu $rA,$rB" 1087 (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0)) 1088 (set sys-sr-f ((.sym op "u") WI rA rB)) ; (set sys-sr-f (gtu WI rA rB)) 1089 () 1090 ) 1091 ; immediate is sign extended even for unsigned compare 1092 (dni (.sym l- "sf" op "ui") ; l-sfgtui 1093 (.str "l.sf" op "ui reg/simm16") ; "l.sfgtui reg/uimm16" 1094 ((MACH ORBIS-MACHS)) 1095 (.str "l.sf" op "ui $rA,$simm16") ; "l.sfgtui $rA,$simm16" 1096 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16) ; (+ OPC_SFI OPC_SF_GTU rA simm16) 1097 (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16))) ; (set sys-sr-f (gtu WI rA (ext WI simm16))) 1098 () 1099 ) 1100 ) 1101 ) 1102 1103(sf-insn gt) 1104(sf-insn ge) 1105(sf-insn lt) 1106(sf-insn le) 1107 1108; Equality compare 1109(define-pmacro (sf-insn-eq op) 1110 (begin 1111 (dni (.sym l- "sf" op) 1112 (.str "l." op " reg/reg") 1113 ((MACH ORBIS-MACHS)) 1114 (.str "l.sf" op " $rA,$rB") 1115 (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0)) 1116 (set sys-sr-f (op WI rA rB)) 1117 () 1118 ) 1119 (dni (.sym l- "sf" op "i") 1120 (.str "l.sf" op "i reg/simm16") 1121 ((MACH ORBIS-MACHS)) 1122 (.str "l.sf" op "i $rA,$simm16") 1123 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16) 1124 (set sys-sr-f (op WI rA (ext WI simm16))) 1125 () 1126 ) 1127 ) 1128) 1129 1130(sf-insn-eq eq) 1131(sf-insn-eq ne) 1132 1133(dni l-mac 1134 "l.mac reg/reg" 1135 ((MACH ORBIS-MACHS)) 1136 "l.mac $rA,$rB" 1137 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC) 1138 (sequence () 1139 (sequence ((DI prod) (DI mac) (DI result)) 1140 (set DI prod (mul DI (ext DI rA) (ext DI rB))) 1141 (set DI mac (join DI SI mac-machi mac-maclo)) 1142 (set DI result (add prod mac)) 1143 (set SI mac-machi (subword SI result 0)) 1144 (set SI mac-maclo (subword SI result 1)) 1145 (set BI sys-sr-ov (addc-oflag prod mac 0)) 1146 ) 1147 (if (andif sys-sr-ov sys-sr-ove) 1148 (raise-exception EXCEPT-RANGE)) 1149 ) 1150 () 1151) 1152 1153(dni l-maci 1154 "l.maci reg/simm16" 1155 ((MACH ORBIS-MACHS)) 1156 "l.maci $rA,${simm16}" 1157 (+ OPC_MACI (f-resv-25-5 0) rA simm16) 1158 (sequence () 1159 (sequence ((DI prod) (DI mac) (DI result)) 1160 (set DI prod (mul DI (ext DI rA) (ext DI simm16))) 1161 (set DI mac (join DI SI mac-machi mac-maclo)) 1162 (set DI result (add mac prod)) 1163 (set SI mac-machi (subword SI result 0)) 1164 (set SI mac-maclo (subword SI result 1)) 1165 (set BI sys-sr-ov (addc-oflag prod mac 0)) 1166 ) 1167 (if (andif sys-sr-ov sys-sr-ove) 1168 (raise-exception EXCEPT-RANGE)) 1169 ) 1170 () 1171) 1172 1173(dni l-macu 1174 "l.macu reg/reg" 1175 ((MACH ORBIS-MACHS)) 1176 "l.macu $rA,$rB" 1177 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MACU) 1178 (sequence () 1179 (sequence ((DI prod) (DI mac) (DI result)) 1180 (set DI prod (mul DI (zext DI rA) (zext DI rB))) 1181 (set DI mac (join DI SI mac-machi mac-maclo)) 1182 (set DI result (add prod mac)) 1183 (set SI mac-machi (subword SI result 0)) 1184 (set SI mac-maclo (subword SI result 1)) 1185 (set BI sys-sr-cy (addc-cflag prod mac 0)) 1186 ) 1187 (if (andif sys-sr-cy sys-sr-ove) 1188 (raise-exception EXCEPT-RANGE)) 1189 ) 1190 () 1191) 1192 1193(dni l-msb 1194 "l.msb reg/reg" 1195 ((MACH ORBIS-MACHS)) 1196 "l.msb $rA,$rB" 1197 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB) 1198 (sequence () 1199 (sequence ((DI prod) (DI mac) (DI result)) 1200 (set DI prod (mul DI (ext DI rA) (ext DI rB))) 1201 (set DI mac (join DI SI mac-machi mac-maclo)) 1202 (set DI result (sub mac prod)) 1203 (set SI mac-machi (subword SI result 0)) 1204 (set SI mac-maclo (subword SI result 1)) 1205 (set BI sys-sr-ov (subc-oflag mac result 0)) 1206 ) 1207 (if (andif sys-sr-ov sys-sr-ove) 1208 (raise-exception EXCEPT-RANGE)) 1209 ) 1210 () 1211) 1212 1213(dni l-msbu 1214 "l.msbu reg/reg" 1215 ((MACH ORBIS-MACHS)) 1216 "l.msbu $rA,$rB" 1217 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSBU) 1218 (sequence () 1219 (sequence ((DI prod) (DI mac) (DI result)) 1220 (set DI prod (mul DI (zext DI rA) (zext DI rB))) 1221 (set DI mac (join DI SI mac-machi mac-maclo)) 1222 (set DI result (sub mac prod)) 1223 (set SI mac-machi (subword SI result 0)) 1224 (set SI mac-maclo (subword SI result 1)) 1225 (set BI sys-sr-cy (subc-cflag mac result 0)) 1226 ) 1227 (if (andif sys-sr-cy sys-sr-ove) 1228 (raise-exception EXCEPT-RANGE)) 1229 ) 1230 () 1231) 1232 1233(define-pmacro (cust-insn cust-num) 1234 (begin 1235 (dni (.sym l- "cust" cust-num) 1236 (.str "l.cust" cust-num) 1237 ((MACH ORBIS-MACHS)) 1238 (.str "l.cust" cust-num) 1239 (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0)) 1240 (nop) 1241 () 1242 ) 1243 ) 1244 ) 1245 1246(cust-insn "1") 1247(cust-insn "2") 1248(cust-insn "3") 1249(cust-insn "4") 1250(cust-insn "5") 1251(cust-insn "6") 1252(cust-insn "7") 1253(cust-insn "8") 1254