1 /* AArch64-specific support for ELF. 2 Copyright (C) 2009-2015 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21 #include "sysdep.h" 22 #include "elfxx-aarch64.h" 23 #include <stdarg.h> 24 #include <string.h> 25 26 #define MASK(n) ((1u << (n)) - 1) 27 28 /* Sign-extend VALUE, which has the indicated number of BITS. */ 29 30 bfd_signed_vma 31 _bfd_aarch64_sign_extend (bfd_vma value, int bits) 32 { 33 if (value & ((bfd_vma) 1 << (bits - 1))) 34 /* VALUE is negative. */ 35 value |= ((bfd_vma) - 1) << bits; 36 37 return value; 38 } 39 40 /* Decode the IMM field of ADRP. */ 41 42 uint32_t 43 _bfd_aarch64_decode_adrp_imm (uint32_t insn) 44 { 45 return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2)); 46 } 47 48 /* Reencode the imm field of add immediate. */ 49 static inline uint32_t 50 reencode_add_imm (uint32_t insn, uint32_t imm) 51 { 52 return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10); 53 } 54 55 /* Reencode the IMM field of ADR. */ 56 57 uint32_t 58 _bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm) 59 { 60 return (insn & ~((MASK (2) << 29) | (MASK (19) << 5))) 61 | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3); 62 } 63 64 /* Reencode the imm field of ld/st pos immediate. */ 65 static inline uint32_t 66 reencode_ldst_pos_imm (uint32_t insn, uint32_t imm) 67 { 68 return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10); 69 } 70 71 /* Encode the 26-bit offset of unconditional branch. */ 72 static inline uint32_t 73 reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs) 74 { 75 return (insn & ~MASK (26)) | (ofs & MASK (26)); 76 } 77 78 /* Encode the 19-bit offset of conditional branch and compare & branch. */ 79 static inline uint32_t 80 reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs) 81 { 82 return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5); 83 } 84 85 /* Decode the 19-bit offset of load literal. */ 86 static inline uint32_t 87 reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs) 88 { 89 return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5); 90 } 91 92 /* Encode the 14-bit offset of test & branch. */ 93 static inline uint32_t 94 reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs) 95 { 96 return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5); 97 } 98 99 /* Reencode the imm field of move wide. */ 100 static inline uint32_t 101 reencode_movw_imm (uint32_t insn, uint32_t imm) 102 { 103 return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5); 104 } 105 106 /* Reencode mov[zn] to movz. */ 107 static inline uint32_t 108 reencode_movzn_to_movz (uint32_t opcode) 109 { 110 return opcode | (1 << 30); 111 } 112 113 /* Reencode mov[zn] to movn. */ 114 static inline uint32_t 115 reencode_movzn_to_movn (uint32_t opcode) 116 { 117 return opcode & ~(1 << 30); 118 } 119 120 /* Return non-zero if the indicated VALUE has overflowed the maximum 121 range expressible by a unsigned number with the indicated number of 122 BITS. */ 123 124 static bfd_reloc_status_type 125 aarch64_unsigned_overflow (bfd_vma value, unsigned int bits) 126 { 127 bfd_vma lim; 128 if (bits >= sizeof (bfd_vma) * 8) 129 return bfd_reloc_ok; 130 lim = (bfd_vma) 1 << bits; 131 if (value >= lim) 132 return bfd_reloc_overflow; 133 return bfd_reloc_ok; 134 } 135 136 /* Return non-zero if the indicated VALUE has overflowed the maximum 137 range expressible by an signed number with the indicated number of 138 BITS. */ 139 140 static bfd_reloc_status_type 141 aarch64_signed_overflow (bfd_vma value, unsigned int bits) 142 { 143 bfd_signed_vma svalue = (bfd_signed_vma) value; 144 bfd_signed_vma lim; 145 146 if (bits >= sizeof (bfd_vma) * 8) 147 return bfd_reloc_ok; 148 lim = (bfd_signed_vma) 1 << (bits - 1); 149 if (svalue < -lim || svalue >= lim) 150 return bfd_reloc_overflow; 151 return bfd_reloc_ok; 152 } 153 154 /* Insert the addend/value into the instruction or data object being 155 relocated. */ 156 bfd_reloc_status_type 157 _bfd_aarch64_elf_put_addend (bfd *abfd, 158 bfd_byte *address, bfd_reloc_code_real_type r_type, 159 reloc_howto_type *howto, bfd_signed_vma addend) 160 { 161 bfd_reloc_status_type status = bfd_reloc_ok; 162 bfd_signed_vma old_addend = addend; 163 bfd_vma contents; 164 int size; 165 166 size = bfd_get_reloc_size (howto); 167 switch (size) 168 { 169 case 0: 170 return status; 171 case 2: 172 contents = bfd_get_16 (abfd, address); 173 break; 174 case 4: 175 if (howto->src_mask != 0xffffffff) 176 /* Must be 32-bit instruction, always little-endian. */ 177 contents = bfd_getl32 (address); 178 else 179 /* Must be 32-bit data (endianness dependent). */ 180 contents = bfd_get_32 (abfd, address); 181 break; 182 case 8: 183 contents = bfd_get_64 (abfd, address); 184 break; 185 default: 186 abort (); 187 } 188 189 switch (howto->complain_on_overflow) 190 { 191 case complain_overflow_dont: 192 break; 193 case complain_overflow_signed: 194 status = aarch64_signed_overflow (addend, 195 howto->bitsize + howto->rightshift); 196 break; 197 case complain_overflow_unsigned: 198 status = aarch64_unsigned_overflow (addend, 199 howto->bitsize + howto->rightshift); 200 break; 201 case complain_overflow_bitfield: 202 default: 203 abort (); 204 } 205 206 addend >>= howto->rightshift; 207 208 switch (r_type) 209 { 210 case BFD_RELOC_AARCH64_CALL26: 211 case BFD_RELOC_AARCH64_JUMP26: 212 contents = reencode_branch_ofs_26 (contents, addend); 213 break; 214 215 case BFD_RELOC_AARCH64_BRANCH19: 216 contents = reencode_cond_branch_ofs_19 (contents, addend); 217 break; 218 219 case BFD_RELOC_AARCH64_TSTBR14: 220 contents = reencode_tst_branch_ofs_14 (contents, addend); 221 break; 222 223 case BFD_RELOC_AARCH64_GOT_LD_PREL19: 224 case BFD_RELOC_AARCH64_LD_LO19_PCREL: 225 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: 226 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: 227 if (old_addend & ((1 << howto->rightshift) - 1)) 228 return bfd_reloc_overflow; 229 contents = reencode_ld_lit_ofs_19 (contents, addend); 230 break; 231 232 case BFD_RELOC_AARCH64_TLSDESC_CALL: 233 break; 234 235 case BFD_RELOC_AARCH64_ADR_GOT_PAGE: 236 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: 237 case BFD_RELOC_AARCH64_ADR_HI21_PCREL: 238 case BFD_RELOC_AARCH64_ADR_LO21_PCREL: 239 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: 240 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: 241 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: 242 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: 243 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 244 contents = _bfd_aarch64_reencode_adr_imm (contents, addend); 245 break; 246 247 case BFD_RELOC_AARCH64_ADD_LO12: 248 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC: 249 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: 250 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: 251 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: 252 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 253 /* Corresponds to: add rd, rn, #uimm12 to provide the low order 254 12 bits of the page offset following 255 BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the 256 (pc-relative) page base. */ 257 contents = reencode_add_imm (contents, addend); 258 break; 259 260 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: 261 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: 262 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: 263 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: 264 case BFD_RELOC_AARCH64_LDST128_LO12: 265 case BFD_RELOC_AARCH64_LDST16_LO12: 266 case BFD_RELOC_AARCH64_LDST32_LO12: 267 case BFD_RELOC_AARCH64_LDST64_LO12: 268 case BFD_RELOC_AARCH64_LDST8_LO12: 269 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: 270 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC: 271 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: 272 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 273 if (old_addend & ((1 << howto->rightshift) - 1)) 274 return bfd_reloc_overflow; 275 /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order 276 12 bits of the page offset following BFD_RELOC_AARCH64_ADR_HI21_PCREL 277 which computes the (pc-relative) page base. */ 278 contents = reencode_ldst_pos_imm (contents, addend); 279 break; 280 281 /* Group relocations to create high bits of a 16, 32, 48 or 64 282 bit signed data or abs address inline. Will change 283 instruction to MOVN or MOVZ depending on sign of calculated 284 value. */ 285 286 case BFD_RELOC_AARCH64_MOVW_G0_S: 287 case BFD_RELOC_AARCH64_MOVW_G1_S: 288 case BFD_RELOC_AARCH64_MOVW_G2_S: 289 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: 290 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: 291 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: 292 /* NOTE: We can only come here with movz or movn. */ 293 if (addend < 0) 294 { 295 /* Force use of MOVN. */ 296 addend = ~addend; 297 contents = reencode_movzn_to_movn (contents); 298 } 299 else 300 { 301 /* Force use of MOVZ. */ 302 contents = reencode_movzn_to_movz (contents); 303 } 304 /* fall through */ 305 306 /* Group relocations to create a 16, 32, 48 or 64 bit unsigned 307 data or abs address inline. */ 308 309 case BFD_RELOC_AARCH64_MOVW_G0: 310 case BFD_RELOC_AARCH64_MOVW_G0_NC: 311 case BFD_RELOC_AARCH64_MOVW_G1: 312 case BFD_RELOC_AARCH64_MOVW_G1_NC: 313 case BFD_RELOC_AARCH64_MOVW_G2: 314 case BFD_RELOC_AARCH64_MOVW_G2_NC: 315 case BFD_RELOC_AARCH64_MOVW_G3: 316 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 317 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: 318 contents = reencode_movw_imm (contents, addend); 319 break; 320 321 default: 322 /* Repack simple data */ 323 if (howto->dst_mask & (howto->dst_mask + 1)) 324 return bfd_reloc_notsupported; 325 326 contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask)); 327 break; 328 } 329 330 switch (size) 331 { 332 case 2: 333 bfd_put_16 (abfd, contents, address); 334 break; 335 case 4: 336 if (howto->dst_mask != 0xffffffff) 337 /* must be 32-bit instruction, always little-endian */ 338 bfd_putl32 (contents, address); 339 else 340 /* must be 32-bit data (endianness dependent) */ 341 bfd_put_32 (abfd, contents, address); 342 break; 343 case 8: 344 bfd_put_64 (abfd, contents, address); 345 break; 346 default: 347 abort (); 348 } 349 350 return status; 351 } 352 353 bfd_vma 354 _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type, 355 bfd_vma place, bfd_vma value, 356 bfd_vma addend, bfd_boolean weak_undef_p) 357 { 358 switch (r_type) 359 { 360 case BFD_RELOC_AARCH64_NONE: 361 case BFD_RELOC_AARCH64_TLSDESC_CALL: 362 break; 363 364 case BFD_RELOC_AARCH64_16_PCREL: 365 case BFD_RELOC_AARCH64_32_PCREL: 366 case BFD_RELOC_AARCH64_64_PCREL: 367 case BFD_RELOC_AARCH64_ADR_LO21_PCREL: 368 case BFD_RELOC_AARCH64_BRANCH19: 369 case BFD_RELOC_AARCH64_LD_LO19_PCREL: 370 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: 371 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: 372 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: 373 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: 374 case BFD_RELOC_AARCH64_TSTBR14: 375 if (weak_undef_p) 376 value = place; 377 value = value + addend - place; 378 break; 379 380 case BFD_RELOC_AARCH64_CALL26: 381 case BFD_RELOC_AARCH64_JUMP26: 382 value = value + addend - place; 383 break; 384 385 case BFD_RELOC_AARCH64_16: 386 case BFD_RELOC_AARCH64_32: 387 case BFD_RELOC_AARCH64_MOVW_G0: 388 case BFD_RELOC_AARCH64_MOVW_G0_NC: 389 case BFD_RELOC_AARCH64_MOVW_G0_S: 390 case BFD_RELOC_AARCH64_MOVW_G1: 391 case BFD_RELOC_AARCH64_MOVW_G1_NC: 392 case BFD_RELOC_AARCH64_MOVW_G1_S: 393 case BFD_RELOC_AARCH64_MOVW_G2: 394 case BFD_RELOC_AARCH64_MOVW_G2_NC: 395 case BFD_RELOC_AARCH64_MOVW_G2_S: 396 case BFD_RELOC_AARCH64_MOVW_G3: 397 value = value + addend; 398 break; 399 400 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: 401 case BFD_RELOC_AARCH64_ADR_HI21_PCREL: 402 if (weak_undef_p) 403 value = PG (place); 404 value = PG (value + addend) - PG (place); 405 break; 406 407 case BFD_RELOC_AARCH64_GOT_LD_PREL19: 408 value = value + addend - place; 409 break; 410 411 case BFD_RELOC_AARCH64_ADR_GOT_PAGE: 412 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: 413 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: 414 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 415 value = PG (value + addend) - PG (place); 416 break; 417 418 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: 419 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: 420 /* Caller must make sure addend is the base address of .got section. */ 421 value = value - PG (addend); 422 break; 423 424 case BFD_RELOC_AARCH64_ADD_LO12: 425 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: 426 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: 427 case BFD_RELOC_AARCH64_LDST128_LO12: 428 case BFD_RELOC_AARCH64_LDST16_LO12: 429 case BFD_RELOC_AARCH64_LDST32_LO12: 430 case BFD_RELOC_AARCH64_LDST64_LO12: 431 case BFD_RELOC_AARCH64_LDST8_LO12: 432 case BFD_RELOC_AARCH64_TLSDESC_ADD: 433 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC: 434 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: 435 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC: 436 case BFD_RELOC_AARCH64_TLSDESC_LDR: 437 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: 438 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: 439 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 440 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 441 value = PG_OFFSET (value + addend); 442 break; 443 444 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: 445 value = value + addend; 446 break; 447 448 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: 449 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: 450 value = (value + addend) & (bfd_vma) 0xffff0000; 451 break; 452 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: 453 /* Mask off low 12bits, keep all other high bits, so that the later 454 generic code could check whehter there is overflow. */ 455 value = (value + addend) & ~(bfd_vma) 0xfff; 456 break; 457 458 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: 459 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 460 value = (value + addend) & (bfd_vma) 0xffff; 461 break; 462 463 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: 464 value = (value + addend) & ~(bfd_vma) 0xffffffff; 465 value -= place & ~(bfd_vma) 0xffffffff; 466 break; 467 468 default: 469 break; 470 } 471 472 return value; 473 } 474 475 /* Hook called by the linker routine which adds symbols from an object 476 file. */ 477 478 bfd_boolean 479 _bfd_aarch64_elf_add_symbol_hook (bfd *abfd, struct bfd_link_info *info, 480 Elf_Internal_Sym *sym, 481 const char **namep ATTRIBUTE_UNUSED, 482 flagword *flagsp ATTRIBUTE_UNUSED, 483 asection **secp ATTRIBUTE_UNUSED, 484 bfd_vma *valp ATTRIBUTE_UNUSED) 485 { 486 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC 487 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE) 488 && (abfd->flags & DYNAMIC) == 0 489 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour) 490 elf_tdata (info->output_bfd)->has_gnu_symbols = TRUE; 491 492 return TRUE; 493 } 494 495 /* Support for core dump NOTE sections. */ 496 497 bfd_boolean 498 _bfd_aarch64_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) 499 { 500 int offset; 501 size_t size; 502 503 switch (note->descsz) 504 { 505 default: 506 return FALSE; 507 508 case 392: /* sizeof(struct elf_prstatus) on Linux/arm64. */ 509 /* pr_cursig */ 510 elf_tdata (abfd)->core->signal 511 = bfd_get_16 (abfd, note->descdata + 12); 512 513 /* pr_pid */ 514 elf_tdata (abfd)->core->lwpid 515 = bfd_get_32 (abfd, note->descdata + 32); 516 517 /* pr_reg */ 518 offset = 112; 519 size = 272; 520 521 break; 522 } 523 524 /* Make a ".reg/999" section. */ 525 return _bfd_elfcore_make_pseudosection (abfd, ".reg", 526 size, note->descpos + offset); 527 } 528 529 bfd_boolean 530 _bfd_aarch64_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) 531 { 532 switch (note->descsz) 533 { 534 default: 535 return FALSE; 536 537 case 136: /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64. */ 538 elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); 539 elf_tdata (abfd)->core->program 540 = _bfd_elfcore_strndup (abfd, note->descdata + 40, 16); 541 elf_tdata (abfd)->core->command 542 = _bfd_elfcore_strndup (abfd, note->descdata + 56, 80); 543 } 544 545 /* Note that for some reason, a spurious space is tacked 546 onto the end of the args in some (at least one anyway) 547 implementations, so strip it off if it exists. */ 548 549 { 550 char *command = elf_tdata (abfd)->core->command; 551 int n = strlen (command); 552 553 if (0 < n && command[n - 1] == ' ') 554 command[n - 1] = '\0'; 555 } 556 557 return TRUE; 558 } 559 560 char * 561 _bfd_aarch64_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type, 562 ...) 563 { 564 switch (note_type) 565 { 566 default: 567 return NULL; 568 569 case NT_PRPSINFO: 570 { 571 char data[136]; 572 va_list ap; 573 574 va_start (ap, note_type); 575 memset (data, 0, sizeof (data)); 576 strncpy (data + 40, va_arg (ap, const char *), 16); 577 strncpy (data + 56, va_arg (ap, const char *), 80); 578 va_end (ap); 579 580 return elfcore_write_note (abfd, buf, bufsiz, "CORE", 581 note_type, data, sizeof (data)); 582 } 583 584 case NT_PRSTATUS: 585 { 586 char data[392]; 587 va_list ap; 588 long pid; 589 int cursig; 590 const void *greg; 591 592 va_start (ap, note_type); 593 memset (data, 0, sizeof (data)); 594 pid = va_arg (ap, long); 595 bfd_put_32 (abfd, pid, data + 32); 596 cursig = va_arg (ap, int); 597 bfd_put_16 (abfd, cursig, data + 12); 598 greg = va_arg (ap, const void *); 599 memcpy (data + 112, greg, 272); 600 va_end (ap); 601 602 return elfcore_write_note (abfd, buf, bufsiz, "CORE", 603 note_type, data, sizeof (data)); 604 } 605 } 606 } 607