1;; Constraint definitions for Renesas / SuperH SH. 2;; Copyright (C) 2007, 2008 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Overview of uppercase letter constraints: 21;; Bxx: miscellaneous constraints 22;; Bsc: SCRATCH - for the scratch register in movsi_ie in the 23;; fldi0 / fldi0 cases 24;; Cxx: Constants other than only CONST_INT 25;; Css: signed 16-bit constant, literal or symbolic 26;; Csu: unsigned 16-bit constant, literal or symbolic 27;; Csy: label or symbol 28;; Cpg: non-explicit constants that can be directly loaded into a general 29;; purpose register in PIC code. like 's' except we don't allow 30;; PIC_ADDR_P 31;; IJKLMNOP: CONT_INT constants 32;; Ixx: signed xx bit 33;; J16: 0xffffffff00000000 | 0x00000000ffffffff 34;; Kxx: unsigned xx bit 35;; M: 1 36;; N: 0 37;; P27: 1 | 2 | 8 | 16 38;; Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 39;; Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128 40;; Q: pc relative load operand 41;; Rxx: reserved for exotic register classes. 42;; Sxx: extra memory (storage) constraints 43;; Sua: unaligned memory operations 44;; W: vector 45;; Z: zero in any mode 46;; 47;; unused CONST_INT constraint letters: LO 48;; unused EXTRA_CONSTRAINT letters: D T U Y 49 50;; Register constraints 51(define_register_constraint "a" "ALL_REGS" 52 "@internal") 53 54(define_register_constraint "b" "TARGET_REGS" 55 "Branch target registers.") 56 57(define_register_constraint "c" "FPSCR_REGS" 58 "Floating-point status register.") 59 60(define_register_constraint "d" "DF_REGS" 61 "Double precision floating-point register.") 62 63(define_register_constraint "e" "TARGET_FMOVD ? NO_REGS : FP_REGS" 64 "Floating-point register.") 65 66(define_register_constraint "f" "FP_REGS" 67 "Floating-point register.") 68 69(define_register_constraint "k" "SIBCALL_REGS" 70 "@internal") 71 72(define_register_constraint "l" "PR_REGS" 73 "PR register.") 74 75(define_register_constraint "t" "T_REGS" 76 "T register.") 77 78(define_register_constraint "w" "FP0_REGS" 79 "Floating-point register 0.") 80 81(define_register_constraint "x" "MAC_REGS" 82 "MACH and MACL registers.") 83 84(define_register_constraint "y" "FPUL_REGS" 85 "FPUL register.") 86 87(define_register_constraint "z" "R0_REGS" 88 "R0 register.") 89 90;; Integer constraints 91(define_constraint "I06" 92 "A signed 6-bit constant, as used in SHmedia beqi, bnei and xori." 93 (and (match_code "const_int") 94 (match_test "ival >= -32 && ival <= 31"))) 95 96(define_constraint "I08" 97 "A signed 8-bit constant, as used in add, sub, etc." 98 (and (match_code "const_int") 99 (match_test "ival >= -128 && ival <= 127"))) 100 101(define_constraint "I10" 102 "A signed 10-bit constant, as used in in SHmedia andi, ori." 103 (and (match_code "const_int") 104 (match_test "ival >= -512 && ival <= 511"))) 105 106(define_constraint "I16" 107 "A signed 16-bit constant, as used in SHmedia movi." 108 (and (match_code "const_int") 109 (match_test "ival >= -32768 && ival <= 32767"))) 110 111(define_constraint "I20" 112 "A signed 20-bit constant, as used in SH2A movi20." 113 (and (match_code "const_int") 114 (match_test "ival >= -524288 && ival <= 524287") 115 (match_test "TARGET_SH2A"))) 116 117(define_constraint "I28" 118 "A signed 28-bit constant, as used in SH2A movi20s." 119 (and (match_code "const_int") 120 (match_test "ival >= -134217728 && ival <= 134217727") 121 (match_test "(ival & 255) == 0") 122 (match_test "TARGET_SH2A"))) 123(define_constraint "J16" 124 "0xffffffff00000000 or 0x00000000ffffffff." 125 (and (match_code "const_int") 126 (match_test "CONST_OK_FOR_J16 (ival)"))) 127 128(define_constraint "K03" 129 "An unsigned 3-bit constant, as used in SH2A bclr, bset, etc." 130 (and (match_code "const_int") 131 (match_test "ival >= 0 && ival <= 7"))) 132 133(define_constraint "K08" 134 "An unsigned 8-bit constant, as used in and, or, etc." 135 (and (match_code "const_int") 136 (match_test "ival >= 0 && ival <= 255"))) 137 138(define_constraint "K12" 139 "An unsigned 8-bit constant, as used in SH2A 12-bit display." 140 (and (match_code "const_int") 141 (match_test "ival >= 0 && ival <= 4095"))) 142 143(define_constraint "K16" 144 "An unsigned 16-bit constant, as used in SHmedia shori." 145 (and (match_code "const_int") 146 (match_test "ival >= 0 && ival <= 65535"))) 147 148(define_constraint "P27" 149 "A constant for shift operand 1,2,8 or 16." 150 (and (match_code "const_int") 151 (match_test "ival == 1 || ival == 2 || ival == 8 || ival == 16"))) 152 153(define_constraint "M" 154 "Integer constant 1." 155 (and (match_code "const_int") 156 (match_test "ival == 1"))) 157 158(define_constraint "N" 159 "Integer constant 0." 160 (and (match_code "const_int") 161 (match_test "ival == 0"))) 162 163;; Floating-point constraints 164(define_constraint "G" 165 "Double constant 0." 166 (and (match_code "const_double") 167 (match_test "fp_zero_operand (op) && fldi_ok ()"))) 168 169(define_constraint "H" 170 "Double constant 1." 171 (and (match_code "const_double") 172 (match_test "fp_one_operand (op) && fldi_ok ()"))) 173 174;; Extra constraints 175(define_constraint "Q" 176 "A pc relative load operand." 177 (and (match_code "mem") 178 (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))"))) 179 180(define_constraint "Bsc" 181 "Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber 182 operand is not SCRATCH (i.e. REG) then R0 is probably being used, 183 hence mova is being used, hence do not select this pattern." 184 (match_code "scratch")) 185 186(define_constraint "Css" 187 "A signed 16-bit constant, literal or symbolic." 188 (and (match_code "const") 189 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 190 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_S16"))) 191 192(define_constraint "Csu" 193 "An unsigned 16-bit constant, literal or symbolic." 194 (and (match_code "const") 195 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 196 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_U16"))) 197 198(define_constraint "Csy" 199 "A label or a symbol." 200 (ior (match_test "NON_PIC_REFERENCE_P (op)") 201 (match_test "PIC_ADDR_P (op)"))) 202 203(define_constraint "Z" 204 "A zero in any shape or form." 205 (match_test "op == CONST0_RTX (GET_MODE (op))")) 206 207(define_constraint "W" 208 "Any vector constant we can handle." 209 (and (match_code "const_vector") 210 (ior (match_test "sh_rep_vec (op, VOIDmode)") 211 (match_test "HOST_BITS_PER_WIDE_INT >= 64 212 ? sh_const_vec (op, VOIDmode) 213 : sh_1el_vec (op, VOIDmode)")))) 214 215(define_constraint "Cpg" 216 "A non-explicit constant that can be loaded directly into a general 217 purpose register. This is like 's' except we don't allow 218 PIC_ADDR_P." 219 (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)")) 220 221(define_constraint "Pso" 222 "Integer constant with a single bit set in its lower 8-bit." 223 (and (match_code "const_int") 224 (ior (match_test "ival == 1") 225 (match_test "ival == 2") 226 (match_test "ival == 4") 227 (match_test "ival == 8") 228 (match_test "ival == 16") 229 (match_test "ival == 32") 230 (match_test "ival == 64") 231 (match_test "ival == 128")))) 232 233(define_constraint "Psz" 234 "Integer constant with a single zero bit in the lower 8-bit." 235 (and (match_code "const_int") 236 (ior (match_test "~ival == 1") 237 (match_test "~ival == 2") 238 (match_test "~ival == 4") 239 (match_test "~ival == 8") 240 (match_test "~ival == 16") 241 (match_test "~ival == 32") 242 (match_test "~ival == 64") 243 (match_test "~ival == 128")))) 244 245(define_memory_constraint "Sr0" 246 "@internal" 247 (and (match_test "memory_operand (op, GET_MODE (op))") 248 (match_test "!refers_to_regno_p (R0_REG, R0_REG + 1, op, (rtx *) 0)"))) 249 250(define_memory_constraint "Sua" 251 "@internal" 252 (and (match_test "memory_operand (op, GET_MODE (op))") 253 (match_test "GET_CODE (XEXP (op, 0)) != PLUS"))) 254 255(define_memory_constraint "Sbv" 256 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 257 (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") 258 (match_test "REG_P (XEXP (op, 0))"))) 259 260(define_memory_constraint "Sbw" 261 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 262 (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") 263 (match_test "GET_CODE (XEXP (op, 0)) == PLUS") 264 (match_test "REG_P (XEXP (XEXP (op, 0), 0))") 265 (match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))"))) 266