1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2015 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_register_constraint "k" "STACK_REG" 22 "@internal The stack register.") 23 24(define_register_constraint "Ucs" "CALLER_SAVE_REGS" 25 "@internal The caller save registers.") 26 27(define_register_constraint "w" "FP_REGS" 28 "Floating point and SIMD vector registers.") 29 30(define_register_constraint "x" "FP_LO_REGS" 31 "Floating point and SIMD vector registers V0 - V15.") 32 33(define_constraint "I" 34 "A constant that can be used with an ADD operation." 35 (and (match_code "const_int") 36 (match_test "aarch64_uimm12_shift (ival)"))) 37 38(define_constraint "J" 39 "A constant that can be used with a SUB operation (once negated)." 40 (and (match_code "const_int") 41 (match_test "aarch64_uimm12_shift (-ival)"))) 42 43;; We can't use the mode of a CONST_INT to determine the context in 44;; which it is being used, so we must have a separate constraint for 45;; each context. 46 47(define_constraint "K" 48 "A constant that can be used with a 32-bit logical operation." 49 (and (match_code "const_int") 50 (match_test "aarch64_bitmask_imm (ival, SImode)"))) 51 52(define_constraint "L" 53 "A constant that can be used with a 64-bit logical operation." 54 (and (match_code "const_int") 55 (match_test "aarch64_bitmask_imm (ival, DImode)"))) 56 57(define_constraint "M" 58 "A constant that can be used with a 32-bit MOV immediate operation." 59 (and (match_code "const_int") 60 (match_test "aarch64_move_imm (ival, SImode)"))) 61 62(define_constraint "N" 63 "A constant that can be used with a 64-bit MOV immediate operation." 64 (and (match_code "const_int") 65 (match_test "aarch64_move_imm (ival, DImode)"))) 66 67(define_constraint "S" 68 "A constraint that matches an absolute symbolic address." 69 (and (match_code "const,symbol_ref,label_ref") 70 (match_test "aarch64_symbolic_address_p (op)"))) 71 72(define_constraint "Y" 73 "Floating point constant zero." 74 (and (match_code "const_double") 75 (match_test "aarch64_float_const_zero_rtx_p (op)"))) 76 77(define_constraint "Z" 78 "Integer constant zero." 79 (match_test "op == const0_rtx")) 80 81(define_constraint "Ush" 82 "A constraint that matches an absolute symbolic address high part." 83 (and (match_code "high") 84 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) 85 86(define_constraint "Uss" 87 "@internal 88 A constraint that matches an immediate shift constant in SImode." 89 (and (match_code "const_int") 90 (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) 91 92(define_constraint "Usn" 93 "A constant that can be used with a CCMN operation (once negated)." 94 (and (match_code "const_int") 95 (match_test "IN_RANGE (ival, -31, 0)"))) 96 97(define_constraint "Usd" 98 "@internal 99 A constraint that matches an immediate shift constant in DImode." 100 (and (match_code "const_int") 101 (match_test "(unsigned HOST_WIDE_INT) ival < 64"))) 102 103(define_constraint "Usf" 104 "@internal Usf is a symbol reference." 105 (match_code "symbol_ref")) 106 107(define_constraint "UsM" 108 "@internal 109 A constraint that matches the immediate constant -1." 110 (match_test "op == constm1_rtx")) 111 112(define_constraint "Ui1" 113 "@internal 114 A constraint that matches the immediate constant +1." 115 (match_test "op == const1_rtx")) 116 117(define_constraint "Ui3" 118 "@internal 119 A constraint that matches the integers 0...4." 120 (and (match_code "const_int") 121 (match_test "(unsigned HOST_WIDE_INT) ival <= 4"))) 122 123(define_constraint "Up3" 124 "@internal 125 A constraint that matches the integers 2^(0...4)." 126 (and (match_code "const_int") 127 (match_test "(unsigned) exact_log2 (ival) <= 4"))) 128 129(define_memory_constraint "Q" 130 "A memory address which uses a single base register with no offset." 131 (and (match_code "mem") 132 (match_test "REG_P (XEXP (op, 0))"))) 133 134(define_memory_constraint "Ump" 135 "@internal 136 A memory address suitable for a load/store pair operation." 137 (and (match_code "mem") 138 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 139 PARALLEL, 1)"))) 140 141(define_memory_constraint "Utv" 142 "@internal 143 An address valid for loading/storing opaque structure 144 types wider than TImode." 145 (and (match_code "mem") 146 (match_test "aarch64_simd_mem_operand_p (op)"))) 147 148(define_constraint "Ufc" 149 "A floating point constant which can be used with an\ 150 FMOV immediate operation." 151 (and (match_code "const_double") 152 (match_test "aarch64_float_const_representable_p (op)"))) 153 154(define_constraint "Dn" 155 "@internal 156 A constraint that matches vector of immediates." 157 (and (match_code "const_vector") 158 (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op), 159 false, NULL)"))) 160 161(define_constraint "Dh" 162 "@internal 163 A constraint that matches an immediate operand valid for\ 164 AdvSIMD scalar move in HImode." 165 (and (match_code "const_int") 166 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 167 HImode)"))) 168 169(define_constraint "Dq" 170 "@internal 171 A constraint that matches an immediate operand valid for\ 172 AdvSIMD scalar move in QImode." 173 (and (match_code "const_int") 174 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 175 QImode)"))) 176 177(define_constraint "Dl" 178 "@internal 179 A constraint that matches vector of immediates for left shifts." 180 (and (match_code "const_vector") 181 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 182 true)"))) 183 184(define_constraint "Dr" 185 "@internal 186 A constraint that matches vector of immediates for right shifts." 187 (and (match_code "const_vector") 188 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 189 false)"))) 190(define_constraint "Dz" 191 "@internal 192 A constraint that matches vector of immediate zero." 193 (and (match_code "const_vector") 194 (match_test "aarch64_simd_imm_zero_p (op, GET_MODE (op))"))) 195 196(define_constraint "Dd" 197 "@internal 198 A constraint that matches an immediate operand valid for AdvSIMD scalar." 199 (and (match_code "const_int") 200 (match_test "aarch64_simd_imm_scalar_p (op, GET_MODE (op))"))) 201