12022-06-28 Release Manager 2 3 * GCC 10.4.0 released. 4 52022-06-24 Iain Buclaw <ibuclaw@gdcproject.org> 6 7 Backported from master: 8 2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org> 9 10 * config/tilepro/gen-mul-tables.cc (tilegx_emit): Adjust loop 11 condition to avoid overflow. 12 132022-06-20 Uros Bizjak <ubizjak@gmail.com> 14 15 Backported from master: 16 2022-06-17 Uroš Bizjak <ubizjak@gmail.com> 17 18 PR target/105209 19 * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. 20 * config/alpha/alpha.c (alpha_store_data_bypass_p): New function. 21 (alpha_store_data_bypass_p_1): Ditto. 22 * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead 23 of generic store_data_bypass_p. 24 (ev4_ist_c): Remove insn reservation. 25 262022-06-20 Uros Bizjak <ubizjak@gmail.com> 27 28 Backported from master: 29 2022-06-17 Uroš Bizjak <ubizjak@gmail.com> 30 31 PR target/105970 32 * config/i386/i386.c (ix86_function_arg): Assert that 33 the mode of pointer argumet is equal to ptr_mode, not Pmode. 34 352022-06-20 Segher Boessenkool <segher@kernel.crashing.org> 36 37 Backported from master: 38 2022-03-12 Segher Boessenkool <segher@kernel.crashing.org> 39 40 PR target/104829 41 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Don't output 42 "ppc" and "ppc64" based on rs6000_cpu. 43 442022-06-20 Segher Boessenkool <segher@kernel.crashing.org> 45 46 Backported from master: 47 2022-03-04 Segher Boessenkool <segher@kernel.crashing.org> 48 49 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Restructure a 50 bit. Handle most older CPUs. 51 522022-06-20 Jakub Jelinek <jakub@redhat.com> 53 54 Backported from master: 55 2022-06-18 Jakub Jelinek <jakub@redhat.com> 56 57 PR middle-end/105998 58 * varasm.c (narrowing_initializer_constant_valid_p): Check 59 SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on 60 ! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type. 61 622022-06-20 Jan Hubicka <jh@suse.cz> 63 64 Backported from master: 65 2022-06-14 Jan Hubicka <hubicka@ucw.cz> 66 67 PR ipa/105739 68 * ipa-prop.c (ipa_load_from_parm_agg): Punt on volatile loads. 69 702022-06-20 Jakub Jelinek <jakub@redhat.com> 71 72 Backported from master: 73 2022-05-27 Jakub Jelinek <jakub@redhat.com> 74 75 PR sanitizer/105729 76 * fold-const.c (fold_unary_loc): Don't optimize (X &) ((Y *) z + w) 77 to (X &) z + w if -fsanitize=null during GENERIC folding. 78 792022-06-16 Richard Earnshaw <rearnsha@arm.com> 80 81 Backported from master: 82 2022-06-15 Richard Earnshaw <rearnsha@arm.com> 83 84 PR target/105981 85 * config/arm/arm.c (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg 86 to first_reg and second_reg respectively. Initialize them correctly 87 when generating big-endian code. 88 892022-06-15 Simon Wright <simon@pushface.org> 90 91 Backported from master: 92 2022-06-12 Simon Wright <simon@pushface.org> 93 94 PR target/104871 95 * config/darwin-driver.c (darwin_find_version_from_kernel): If the OS 96 version is darwin20 (macOS 11) or greater, truncate the version to the 97 major number. 98 992022-06-15 Mark Mentovai <mark@mentovai.com> 100 101 Backported from master: 102 2022-06-12 Mark Mentovai <mark@mentovai.com> 103 104 * config/darwin-c.c: Make -mmacosx-version-min more future-proof. 105 1062022-06-15 Richard Biener <rguenther@suse.de> 107 108 Backported from master: 109 2022-05-27 Richard Biener <rguenther@suse.de> 110 111 PR tree-optimization/105726 112 * gimple-ssa-warn-restrict.c (builtin_memref::set_base_and_offset): 113 Constrain array-of-flexarray case more. 114 1152022-06-14 Vladimir N. Makarov <vmakarov@redhat.com> 116 117 PR rtl-optimization/104637 118 * lra-assigns.c (lra_split_hard_reg_for): Split hard regs as many 119 as possible on one subpass. 120 1212022-06-13 Marek Polacek <polacek@redhat.com> 122 123 Backported from master: 124 2022-03-08 Marek Polacek <polacek@redhat.com> 125 126 PR rtl-optimization/104777 127 * rtl.c (classify_insn): For ASM_OPERANDS, return JUMP_INSN only if 128 ASM_OPERANDS_LABEL_VEC has at least one element. 129 1302022-06-09 Iain Sandoe <iain@sandoe.co.uk> 131 132 Backported from master: 133 2021-09-14 Iain Sandoe <iain@sandoe.co.uk> 134 135 * Makefile.in: Remove variables related to applying no-PIE 136 to the exes on $build. 137 * configure: Regenerate. 138 * configure.ac: Remove configuration related to applying 139 no-PIE to the exes on $build. 140 1412022-06-06 Alan Modra <amodra@gmail.com> 142 143 Backported from master: 144 2020-10-24 Alan Modra <amodra@gmail.com> 145 146 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Limit 147 AND addressing to just lvx/stvx style addresses. 148 1492022-05-31 Iain Sandoe <iain@sandoe.co.uk> 150 151 * config/darwin-sections.def (objc2_class_names_section, 152 objc2_method_names_section, objc2_method_types_section): New 153 * config/darwin.c (output_objc_section_asm_op): Output new 154 sections. (darwin_objc2_section): Select new sections where 155 used. 156 (darwin_label_is_anonymous_local_objc_name): Make 157 protocol class methods linker-visible. 158 1592022-05-29 Iain Sandoe <iain@sandoe.co.uk> 160 161 Backported from master: 162 2021-11-15 Iain Sandoe <iain@sandoe.co.uk> 163 164 PR fortran/102992 165 * config/darwin.h (TARGET_DTORS_FROM_CXA_ATEXIT): New. 166 * doc/tm.texi: Regenerated. 167 * doc/tm.texi.in: Add TARGET_DTORS_FROM_CXA_ATEXIT hook. 168 * ipa.c (cgraph_build_static_cdtor_1): Return the built 169 function decl. 170 (build_cxa_atexit_decl): New. 171 (build_dso_handle_decl): New. 172 (build_cxa_dtor_registrations): New. 173 (compare_cdtor_tu_order): New. 174 (build_cxa_atexit_fns): New. 175 (ipa_cdtor_merge): If dtors_from_cxa_atexit is set, 176 process the DTORs/CTORs accordingly. 177 (pass_ipa_cdtor_merge::gate): Also run if 178 dtors_from_cxa_atexit is set. 179 * target.def (dtors_from_cxa_atexit): New hook. 180 1812022-05-29 Iain Sandoe <iain@sandoe.co.uk> 182 183 Backported from master: 184 2021-07-09 Iain Sandoe <iain@sandoe.co.uk> 185 186 PR target/100152 187 * config/i386/i386-expand.c (ix86_expand_call): If a call is 188 to a non-local-binding, or local but to a public symbol, then 189 assume that it might be indirected via the lazy symbol binder. 190 Mark R10 and R10 as clobbered in that case. 191 1922022-05-29 Iain Sandoe <iain@sandoe.co.uk> 193 Vladimir Makarov <vmakarov@redhat.com> 194 195 PR target/104117 196 * config/rs6000/rs6000.c (darwin_rs6000_legitimate_lo_sum_const_p): 197 Check for UNSPEC_MACHOPIC_OFFSET wrappers on symbolic addresses when 198 emitting PIC code. 199 (legitimate_lo_sum_address_p): Likewise. 200 (rs6000_legitimize_address): Do not apply the TLS processing to 201 Darwin. 202 * config/rs6000/darwin.md (@machopic_high_<mode>): New. 203 (@machopic_low_<mode>): New. 204 * config/rs6000/predicates.md (macho_pic_address): New. 205 2062022-05-29 Iain Sandoe <iain@sandoe.co.uk> 207 208 PR target/80556 209 * config/darwin-driver.c (darwin_driver_init): Handle exported 210 symbols and symbol lists (suppress automatic export of the TLS 211 symbols). 212 * config/darwin.c (darwin_rename_builtins): Remove workaround. 213 * config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): Likewise. 214 (REAL_LIBGCC_SPEC): Handle revised library uses. 215 * config/darwin.opt (nodefaultexport): New. 216 * config/i386/darwin.h (PR80556_WORKAROUND): Remove. 217 * config/i386/darwin32-biarch.h (PR80556_WORKAROUND): Likewise. 218 * config/i386/darwin64-biarch.h (PR80556_WORKAROUND): Likewise. 219 2202022-05-29 Iain Sandoe <iain@sandoe.co.uk> 221 222 * config/darwin-driver.c (darwin_driver_init): Revise comments, handle 223 filelist and framework options in specs instead of code. Exit from the 224 option handling early if the command line is definitely enpty. 225 * config/darwin.h (SUBTARGET_DRIVER_SELF_SPECS): Update to handle link 226 specs that are really driver ones. Remove setting for the default content 227 of weak_reference_mismatches 228 (DARWIN_CC1_SPEC): Likewise. 229 (CPP_SPEC): Likewise. 230 (SYSROOT_SPEC): Append space. 231 (LINK_SYSROOT_SPEC): Remove most driver link specs. 232 (STANDARD_STARTFILE_PREFIX_2): Update link-related specs. 233 (STARTFILE_SPEC): Likewise. 234 (ASM_MMACOSX_VERSION_MIN_SPEC): Fix line wrap. 235 (ASM_SPEC): Update driver-related specs. 236 (ASM_FINAL_SPEC): Likewise. 237 (LINK_COMMAND_SPEC_A): Update 'r' handling to skip gomp and itm when r 238 or nodefaultlibs is given. 239 (DSYMUTIL_SPEC): Do not call dsymutil for '-r' link lines. 240 Update ordering of exclusions, remove duplicate 'v' addition 241 (collect2 will add this from the main command line). 242 * config/darwin.opt: Remove now unused option aliases. 243 * config/i386/darwin.h (EXTRA_ASM_OPTS): Ensure space after opt. 244 (ASM_SPEC): Update driver-related specs. 245 2462022-05-29 Iain Sandoe <iain@sandoe.co.uk> 247 248 Backported from master: 249 2021-09-19 Iain Sandoe <iain@sandoe.co.uk> 250 251 * config/darwin.h (LINK_COMMAND_SPEC_A): Use Darwin10 252 unwinder shim as a convenience library. 253 2542022-05-29 Iain Sandoe <iain@sandoe.co.uk> 255 256 Backported from master: 257 2021-10-13 Iain Sandoe <iain@sandoe.co.uk> 258 259 * collect2.c (is_lto_object_file): Release simple-object 260 resources, close files. 261 2622022-05-29 Iain Sandoe <iain@sandoe.co.uk> 263 264 Backported from master: 265 2021-11-05 Iain Sandoe <iain@sandoe.co.uk> 266 267 * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Add LTRAMP 268 to the list of symbol prefixes that must be made linker- 269 visible. 270 2712022-05-29 Iain Sandoe <iain@sandoe.co.uk> 272 273 Backported from master: 274 2021-08-27 Iain Sandoe <iain@sandoe.co.uk> 275 276 * config/darwin.c (finalize_ctors): Add a section-start linker- 277 visible symbol. 278 (finalize_dtors): Likewise. 279 * config/darwin.h (MIN_LD64_INIT_TERM_START_LABELS): New. 280 2812022-05-29 Iain Sandoe <iain@sandoe.co.uk> 282 283 Backported from master: 284 2021-08-17 Iain Sandoe <iain@sandoe.co.uk> 285 286 * config/darwin.c (darwin_file_end): Reset and reclaim the 287 section names table at the end of compile. 288 2892022-05-29 Iain Sandoe <iain@sandoe.co.uk> 290 291 Backported from master: 292 2021-01-02 Iain Sandoe <iain@sandoe.co.uk> 293 294 * config/darwin.h (MIN_LD64_NO_COAL_SECTS): Adjust. 295 Amend handling for LD64_VERSION fallback defaults. 296 2972022-05-29 Iain Sandoe <iain@sandoe.co.uk> 298 299 * configure.ac: Handle --with-dsymutil in the same way as we 300 do for the assembler and linker. (DEFAULT_DSYMUTIL): New. 301 Extract the type and version for the dsymutil configured or 302 found by the default searches. 303 * config.in: Regenerated. 304 * configure: Regenerated. 305 * collect2.c (do_dsymutil): Handle locating dsymutil in the 306 same way as for the assembler and linker. 307 * config/darwin.h (DSYMUTIL): Delete. 308 * gcc.c: Report a configured dsymutil correctly. 309 * exec-tool.in: Allow for dsymutil. 310 * doc/install.texi: Document --with-dsymutil. 311 3122022-05-29 Iain Sandoe <iain@sandoe.co.uk> 313 314 Backported from master: 315 2021-09-28 Iain Sandoe <iain@sandoe.co.uk> 316 317 * config/rs6000/darwin.h (FIXED_R13): Add for PPC64. 318 (FIRST_SAVED_GP_REGNO): Save from R13 even when it is one 319 of the fixed regs. 320 3212022-05-29 François-Xavier Coudert <fxcoudert@gcc.gnu.org> 322 323 Backported from master: 324 2021-12-18 François-Xavier Coudert <fxcoudert@gcc.gnu.org> 325 326 * config/darwin-driver.c: Make version code more future-proof. 327 * config.gcc: Homogeneize darwin versions. 328 * configure.ac: Homogeneize darwin versions. 329 * configure: Regenerate. 330 3312022-05-29 Saagar Jha <saagar@saagarjha.com> 332 333 Backported from master: 334 2021-10-27 Saagar Jha <saagar@saagarjha.com> 335 336 * config.gcc: Adjust for Darwin21. 337 * config/darwin-c.c (macosx_version_as_macro): Likewise. 338 * config/darwin-driver.c (validate_macosx_version_min): 339 Likewise. 340 (darwin_find_version_from_kernel): Likewise. 341 3422022-05-29 Iain Sandoe <iain@sandoe.co.uk> 343 344 Backported from master: 345 2021-08-17 Iain Sandoe <iain@sandoe.co.uk> 346 347 PR target/100340 348 * config.in: Regenerate. 349 * config/i386/darwin.h (EXTRA_ASM_OPTS): New 350 (ASM_SPEC): Pass options to disable branch shortening where 351 needed. 352 * configure: Regenerate. 353 * configure.ac: Detect versions of 'as' that support the 354 optimisation which has the bug. 355 3562022-05-29 Iain Sandoe <iain@sandoe.co.uk> 357 358 Backported from master: 359 2022-03-04 Iain Sandoe <iain@sandoe.co.uk> 360 361 * config/darwin.c (darwin_fold_builtin): Make fcode an int to 362 avoid a mismatch with DECL_MD_FUNCTION_CODE(). 363 3642022-05-27 Richard Biener <rguenther@suse.de> 365 366 Backported from master: 367 2022-04-13 Richard Biener <rguenther@suse.de> 368 369 PR tree-optimization/105250 370 * fold-const.c (fold_convertible_p): Revert 371 r12-7979-geaaf77dd85c333, instead check for size equality 372 of the vector types involved. 373 3742022-05-27 Richard Biener <rguenther@suse.de> 375 376 Backported from master: 377 2022-04-04 Richard Biener <rguenther@suse.de> 378 379 PR middle-end/105140 380 * fold-const.c (fold_convertible_p): Allow a TYPE_P arg. 381 3822022-05-27 Richard Biener <rguenther@suse.de> 383 384 Backported from master: 385 2022-04-06 Richard Biener <rguenther@suse.de> 386 387 PR tree-optimization/105163 388 * tree-ssa-reassoc.c (repropagate_negates): Avoid propagating 389 negated abnormals. 390 3912022-05-27 Richard Biener <rguenther@suse.de> 392 393 Backported from master: 394 2022-04-06 Richard Biener <rguenther@suse.de> 395 396 PR tree-optimization/105173 397 * tree-ssa-reassoc.c (find_insert_point): Get extra 398 insert_before output argument and compute it. 399 (insert_stmt_before_use): Adjust. 400 (rewrite_expr_tree): Likewise. 401 4022022-05-27 Richard Biener <rguenther@suse.de> 403 404 Backported from master: 405 2022-04-29 Richard Biener <rguenther@suse.de> 406 407 PR tree-optimization/105431 408 * tree-ssa-math-opts.c (powi_as_mults_1): Make n unsigned. 409 (powi_as_mults): Use absu_hwi. 410 (gimple_expand_builtin_powi): Remove now pointless n != -n 411 check. 412 4132022-05-27 Richard Biener <rguenther@suse.de> 414 415 Backported from master: 416 2022-04-25 Richard Biener <rguenther@suse.de> 417 418 PR tree-optimization/105368 419 * tree-ssa-math-opts.c (powi_cost): Use absu_hwi. 420 4212022-05-27 Richard Biener <rguenther@suse.de> 422 423 Backported from master: 424 2022-05-11 Richard Biener <rguenther@suse.de> 425 426 PR rtl-optimization/105559 427 * cfgrtl.c (delete_insn_and_edges): Only perform search to BB_END 428 for non-debug insns. 429 4302022-05-23 Paul A. Clarke <pc@us.ibm.com> 431 432 PR target/104257 433 * config/rs6000/bmi2intrin.h: Uglify local variables. 434 * config/rs6000/emmintrin.h: Likewise. 435 * config/rs6000/mm_malloc.h: Likewise. 436 * config/rs6000/mmintrin.h: Likewise. 437 * config/rs6000/pmmintrin.h: Likewise. 438 * config/rs6000/tmmintrin.h: Likewise. 439 * config/rs6000/xmmintrin.h: Likewise. 440 4412022-05-16 Sebastian Pop <spop@amazon.com> 442 443 PR target/105162 444 * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension 445 of str array. 446 * config/aarch64/aarch64.c (aarch64_atomic_ool_func): Call 447 memmodel_from_int and handle MEMMODEL_SYNC_*. 448 (DEF0): Add __aarch64_*_sync functions. 449 4502022-05-10 Jakub Jelinek <jakub@redhat.com> 451 452 Backported from master: 453 2022-04-27 Jakub Jelinek <jakub@redhat.com> 454 455 PR sanitizer/105396 456 * asan.c (asan_redzone_buffer::emit_redzone_byte): Handle the case 457 where offset is bigger than off but smaller than m_prev_offset + 32 458 bits by pushing one or more 0 bytes. Sink the 459 m_shadow_bytes.safe_push (value); flush_if_full (); statements from 460 all cases to the end of the function. 461 4622022-05-10 Jakub Jelinek <jakub@redhat.com> 463 464 Backported from master: 465 2022-04-22 Jakub Jelinek <jakub@redhat.com> 466 467 PR rtl-optimization/105333 468 * rtlanal.c (replace_rtx): Use simplify_subreg or 469 simplify_unary_operation if CONST_SCALAR_INT_P rather than just 470 CONST_INT_P. 471 4722022-05-10 Jakub Jelinek <jakub@redhat.com> 473 474 Backported from master: 475 2022-04-19 Jakub Jelinek <jakub@redhat.com> 476 477 PR target/105257 478 * config/sparc/sparc.c (epilogue_renumber): If ORIGINAL_REGNO, 479 use gen_raw_REG instead of gen_rtx_REG and copy over also 480 ORIGINAL_REGNO. Use return 0; instead of /* fallthrough */. 481 4822022-05-10 Jakub Jelinek <jakub@redhat.com> 483 484 Backported from master: 485 2022-04-12 Jakub Jelinek <jakub@redhat.com> 486 487 PR target/105214 488 * config/i386/i386-expand.c (ix86_emit_i387_log1p): Call 489 do_pending_stack_adjust. 490 4912022-05-10 Jakub Jelinek <jakub@redhat.com> 492 493 Backported from master: 494 2022-04-12 Jakub Jelinek <jakub@redhat.com> 495 496 PR rtl-optimization/105211 497 * builtins.c (expand_builtin_int_roundingfn_2): If mathfn_built_in_1 498 fails for TREE_TYPE (arg), retry it with 499 TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) and if even that 500 fails, emit call normally. 501 5022022-05-10 Jakub Jelinek <jakub@redhat.com> 503 504 Backported from master: 505 2022-04-08 Jakub Jelinek <jakub@redhat.com> 506 507 PR tree-optimization/105189 508 * fold-const.c (make_range_step): Fix up handling of 509 (unsigned) x +[low, -] ranges for signed x if low fits into 510 typeof (x). 511 5122022-05-10 Jakub Jelinek <jakub@redhat.com> 513 514 Backported from master: 515 2022-04-06 Jakub Jelinek <jakub@redhat.com> 516 517 PR rtl-optimization/104985 518 * combine.c (struct undo): Add where.regno member. 519 (do_SUBST_MODE): Rename to ... 520 (subst_mode): ... this. Change first argument from rtx * into int, 521 operate on regno_reg_rtx[regno] and save regno into where.regno. 522 (SUBST_MODE): Remove. 523 (try_combine): Use subst_mode instead of SUBST_MODE, change first 524 argument from regno_reg_rtx[whatever] to whatever. For UNDO_MODE, use 525 regno_reg_rtx[undo->where.regno] instead of *undo->where.r. 526 (undo_to_marker): For UNDO_MODE, use regno_reg_rtx[undo->where.regno] 527 instead of *undo->where.r. 528 (simplify_set): Use subst_mode instead of SUBST_MODE, change first 529 argument from regno_reg_rtx[whatever] to whatever. 530 5312022-05-10 Jakub Jelinek <jakub@redhat.com> 532 533 Backported from master: 534 2022-04-03 Jakub Jelinek <jakub@redhat.com> 535 536 PR target/105123 537 * config/i386/i386-expand.c (ix86_expand_vector_init_general): Avoid 538 using word as target for expand_simple_binop when doing ASHIFT and 539 IOR. 540 5412022-05-10 Jakub Jelinek <jakub@redhat.com> 542 543 Backported from master: 544 2022-03-30 Jakub Jelinek <jakub@redhat.com> 545 546 PR sanitizer/105093 547 * ubsan.c (instrument_object_size): If t is equal to inner and 548 is a decl other than global var, punt. When emitting call to 549 UBSAN_OBJECT_SIZE ifn, make sure base is addressable. 550 5512022-05-10 Jakub Jelinek <jakub@redhat.com> 552 553 Backported from master: 554 2022-03-30 Jakub Jelinek <jakub@redhat.com> 555 556 PR tree-optimization/105094 557 * gimple-ssa-store-merging.c (mem_valid_for_store_merging): Punt if 558 bitsize <= 0 rather than just == 0. 559 5602022-05-10 Jakub Jelinek <jakub@redhat.com> 561 562 Backported from master: 563 2022-03-19 Jakub Jelinek <jakub@redhat.com> 564 565 PR middle-end/104971 566 * config/i386/i386-expand.c 567 (ix86_expand_builtin) <case IX86_BUILTIN_READ_FLAGS>: If ignore, 568 don't push/pop anything and just return const0_rtx. 569 5702022-05-10 Jakub Jelinek <jakub@redhat.com> 571 572 Backported from master: 573 2022-03-16 Jakub Jelinek <jakub@redhat.com> 574 575 PR target/104910 576 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Copy 577 imm rtx. 578 5792022-05-10 Jakub Jelinek <jakub@redhat.com> 580 581 Backported from master: 582 2022-03-15 Jakub Jelinek <jakub@redhat.com> 583 584 PR rtl-optimization/104814 585 * ifcvt.c (find_if_case_1, find_if_case_2): Punt if test_bb doesn't 586 end with onlyjump_p. Assume BB_END (test_bb) is always non-NULL. 587 5882022-05-10 Jakub Jelinek <jakub@redhat.com> 589 590 Backported from master: 591 2022-03-09 Jakub Jelinek <jakub@redhat.com> 592 593 PR c/104711 594 * doc/invoke.texi (-Wextra): Document that -Wshift-negative-value 595 is enabled by it only for C++11 to C++17 rather than for C++03 or 596 later. 597 (-Wshift-negative-value): Similarly (except here we stated 598 that it is enabled for C++11 or later). 599 6002022-05-10 Jakub Jelinek <jakub@redhat.com> 601 602 Backported from master: 603 2022-03-07 Jakub Jelinek <jakub@redhat.com> 604 605 PR target/104775 606 * config/s390/s390.md (*cmp_and_trap_unsigned_int<mode>): Use 607 S constraint instead of T in the last alternative. 608 6092022-05-10 Jakub Jelinek <jakub@redhat.com> 610 611 Backported from master: 612 2022-02-25 Jakub Jelinek <jakub@redhat.com> 613 Marc Glisse <marc.glisse@inria.fr> 614 615 PR tree-optimization/104675 616 * match.pd (t * 2U / 2 -> t & (~0 / 2), t / 2U * 2 -> t & ~1): 617 Restrict simplifications to INTEGRAL_TYPE_P. 618 6192022-05-10 Jakub Jelinek <jakub@redhat.com> 620 621 Backported from master: 622 2022-02-25 Jakub Jelinek <jakub@redhat.com> 623 624 PR target/104681 625 * config/rs6000/vector.md (movmisalign<mode>): Use rs6000_emit_move. 626 6272022-05-10 Jakub Jelinek <jakub@redhat.com> 628 629 Backported from master: 630 2022-02-25 Jakub Jelinek <jakub@redhat.com> 631 632 PR tree-optimization/104675 633 * match.pd (-A - 1 -> ~A, -1 - A -> ~A): Don't simplify for 634 COMPLEX_TYPE. 635 6362022-05-10 Jakub Jelinek <jakub@redhat.com> 637 638 Backported from master: 639 2022-02-19 Jakub Jelinek <jakub@redhat.com> 640 641 PR sanitizer/102656 642 * asan.c (instrument_derefs): If inner is a RESULT_DECL and access is 643 known to be within bounds, treat it like automatic variables. 644 If instrumenting access and inner is {VAR,PARM,RESULT}_DECL from 645 current function and !TREE_STATIC which is not TREE_ADDRESSABLE, mark 646 it addressable. 647 6482022-05-10 Jakub Jelinek <jakub@redhat.com> 649 650 Backported from master: 651 2022-02-17 Jakub Jelinek <jakub@redhat.com> 652 653 PR debug/104557 654 * valtrack.c (debug_lowpart_subreg): Don't call gen_rtx_raw_SUBREG 655 if expr has VOIDmode. 656 6572022-05-10 Jakub Jelinek <jakub@redhat.com> 658 659 Backported from master: 660 2022-02-16 Jakub Jelinek <jakub@redhat.com> 661 662 PR rtl-optimization/104544 663 * combine.c (try_combine): When looking for insn whose links 664 should be updated from i3 to i2, don't stop on debug insns, instead 665 skip over them. 666 6672022-05-10 Jakub Jelinek <jakub@redhat.com> 668 669 Backported from master: 670 2022-02-15 Jakub Jelinek <jakub@redhat.com> 671 672 PR debug/104517 673 * omp-low.c (task_cpyfns): New variable. 674 (delete_omp_context): Don't call finalize_task_copyfn from here. 675 (create_task_copyfn): Push task_stmt into task_cpyfns. 676 (execute_lower_omp): Call finalize_task_copyfn here on entries from 677 task_cpyfns vector and release the vector. 678 6792022-05-10 Jakub Jelinek <jakub@redhat.com> 680 681 Backported from master: 682 2022-02-12 Jakub Jelinek <jakub@redhat.com> 683 684 PR sanitizer/104449 685 * asan.c: Include tree-eh.h. 686 (handle_builtin_alloca): Handle the case when __builtin_alloca or 687 __builtin_alloca_with_align can throw. 688 6892022-05-10 Jakub Jelinek <jakub@redhat.com> 690 691 Backported from master: 692 2022-02-12 Jakub Jelinek <jakub@redhat.com> 693 694 PR target/104502 695 * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+ 696 and AVX512VL isn't available, move operands[1] to operands[0] first. 697 6982022-05-10 Jakub Jelinek <jakub@redhat.com> 699 700 Backported from master: 701 2022-02-11 Jakub Jelinek <jakub@redhat.com> 702 703 PR middle-end/104446 704 * combine.c (subst): Don't substitute CONST_INTs into RTX_AUTOINC 705 operands. 706 7072022-05-10 Jakub Jelinek <jakub@redhat.com> 708 709 Backported from master: 710 2022-02-08 Jakub Jelinek <jakub@redhat.com> 711 712 PR target/102140 713 * config/rs6000/rs6000.c (vspltis_shifted): Return false also if 714 split1 pass has finished already. 715 7162022-05-10 Jakub Jelinek <jakub@redhat.com> 717 718 Backported from master: 719 2022-01-28 Jakub Jelinek <jakub@redhat.com> 720 721 PR tree-optimization/104263 722 * gimple-ssa-store-merging.c (get_status_for_store_merging): For 723 cfun->can_throw_non_call_exceptions && cfun->eh test whether 724 last non-debug stmt in the bb is store_valid_for_store_merging_p 725 rather than last stmt. 726 7272022-05-10 Jakub Jelinek <jakub@redhat.com> 728 729 Backported from master: 730 2022-01-21 Jakub Jelinek <jakub@redhat.com> 731 732 PR rtl-optimization/102478 733 * optabs.c (prepare_cmp_insn): If !can_create_pseudo_p (), don't 734 force_reg constants and for -fnon-call-exceptions fail if copy_to_reg 735 would be needed. 736 7372022-05-10 Jakub Jelinek <jakub@redhat.com> 738 739 Backported from master: 740 2022-01-19 Jakub Jelinek <jakub@redhat.com> 741 742 PR middle-end/102860 743 * match.pd (x %[fl] y -> x % y): New simplification for 744 unsigned integral types. 745 * optabs-tree.c (optab_for_tree_code): Return unknown_optab 746 for {CEIL,FLOOR,ROUND}_{DIV,MOD}_EXPR with VECTOR_TYPE. 747 7482022-05-10 Jakub Jelinek <jakub@redhat.com> 749 750 Backported from master: 751 2022-01-06 Jakub Jelinek <jakub@redhat.com> 752 753 PR rtl-optimization/103908 754 * ifcvt.c (bb_valid_for_noce_process_p): Punt on bbs ending with 755 asm goto. 756 7572022-05-10 Jakub Jelinek <jakub@redhat.com> 758 759 Backported from master: 760 2021-12-30 Jakub Jelinek <jakub@redhat.com> 761 762 PR rtl-optimization/103860 763 * shrink-wrap.c (try_shrink_wrapping): Make sure can_get_prologue is 764 called on pro even if nothing further is pushed into vec. 765 7662022-05-10 Jakub Jelinek <jakub@redhat.com> 767 768 Backported from master: 769 2021-12-28 Jakub Jelinek <jakub@redhat.com> 770 771 PR rtl-optimization/103837 772 * loop-invariant.c (can_move_invariant_reg): Ignore DEBUG_INSNs in 773 the decisions whether to return false or continue and right before 774 returning true reset those debug insns that previously caused 775 returning false. 776 7772022-05-10 Jakub Jelinek <jakub@redhat.com> 778 779 Backported from master: 780 2021-11-27 Jakub Jelinek <jakub@redhat.com> 781 782 PR tree-optimization/103435 783 * gimple-ssa-store-merging.c (find_bswap_or_nop_finalize): Avoid UB if 784 n->range - rsize == 8, just clear both *cmpnop and *cmpxchg in that 785 case. 786 7872022-05-10 Jakub Jelinek <jakub@redhat.com> 788 789 Backported from master: 790 2021-11-24 Jakub Jelinek <jakub@redhat.com> 791 792 PR middle-end/103384 793 * omp-general.c (omp_context_selector_matches): For ACCEL_COMPILER, 794 return 0 for kind(host) and continue for kind(nohost). 795 7962022-05-10 Jakub Jelinek <jakub@redhat.com> 797 798 Backported from master: 799 2021-11-23 Jakub Jelinek <jakub@redhat.com> 800 801 PR middle-end/102431 802 * gimplify.c (replace_reduction_placeholders): Remove. 803 (note_no_context_vars): New function. 804 (gimplify_omp_loop): For OMP_PARALLEL's BIND_EXPR create a new 805 BLOCK. Use copy_tree_body_r with walk_tree instead of unshare_expr 806 and replace_reduction_placeholders for duplication of 807 OMP_CLAUSE_REDUCTION_{INIT,MERGE} expressions. Ensure all mentioned 808 automatic vars have DECL_CONTEXT set to non-NULL before doing so 809 and reset it afterwards for those vars and their corresponding 810 vars. 811 8122022-05-10 Jakub Jelinek <jakub@redhat.com> 813 814 Backported from master: 815 2021-11-17 Jakub Jelinek <jakub@redhat.com> 816 817 PR tree-optimization/103192 818 * tree-ssa-loop-im.c (move_computations_worker): Use 819 reset_flow_sensitive_info instead of manually clearing 820 SSA_NAME_RANGE_INFO and do it for all SSA_NAMEs, not just ones 821 with integral types. 822 8232022-05-10 Jakub Jelinek <jakub@redhat.com> 824 825 Backported from master: 826 2021-11-15 Jakub Jelinek <jakub@redhat.com> 827 828 PR target/103205 829 * config/i386/sync.md (atomic_bit_test_and_set<mode>, 830 atomic_bit_test_and_complement<mode>, 831 atomic_bit_test_and_reset<mode>): Use OPTAB_WIDEN instead of 832 OPTAB_DIRECT. 833 8342022-05-10 Jakub Jelinek <jakub@redhat.com> 835 836 Backported from master: 837 2021-11-11 Jakub Jelinek <jakub@redhat.com> 838 839 PR debug/101378 840 * dwarf2out.c (field_byte_offset): Do the PCC_BITFIELD_TYPE_MATTERS 841 handling only for DECL_BIT_FIELD_TYPE decls. 842 8432022-05-10 Jakub Jelinek <jakub@redhat.com> 844 845 Backported from master: 846 2021-10-10 Jakub Jelinek <jakub@redhat.com> 847 848 PR debug/102441 849 * var-tracking.c (add_stores): For cselib_sp_derived_value_p values 850 use MO_VAL_SET if loc is not sp. 851 8522022-05-10 Jakub Jelinek <jakub@redhat.com> 853 854 Backported from master: 855 2021-09-28 Jakub Jelinek <jakub@redhat.com> 856 857 PR target/102498 858 * config/i386/i386.c (standard_80387_constant_p): Don't recognize 859 special 80387 instruction XFmode constants if flag_rounding_math. 860 8612022-05-10 Jakub Jelinek <jakub@redhat.com> 862 863 Backported from master: 864 2021-09-15 Jakub Jelinek <jakub@redhat.com> 865 866 PR c++/88578 867 PR c++/102295 868 * varasm.c (output_constructor_regular_field): Instead of assertion 869 that array_size_for_constructor result is equal to size of 870 TREE_TYPE (local->val) in bytes, assert that the type size is greater 871 or equal to array_size_for_constructor result and use type size as 872 fieldsize. 873 8742022-05-10 Jakub Jelinek <jakub@redhat.com> 875 876 Backported from master: 877 2021-09-08 Jakub Jelinek <jakub@redhat.com> 878 879 PR target/102224 880 * config/i386/i386.md (xorsign<mode>3): If operands[1] is equal to 881 operands[2], emit abs<mode>2 instead. 882 (@xorsign<mode>3_1): Add early-clobber for output operand. 883 8842022-05-10 Jakub Jelinek <jakub@redhat.com> 885 886 Backported from master: 887 2021-08-23 Jakub Jelinek <jakub@redhat.com> 888 889 PR debug/101905 890 * dwarf2out.c (gen_variable_die): Add DW_AT_location for global 891 register variables already during early_dwarf if possible. 892 8932022-05-10 Jakub Jelinek <jakub@redhat.com> 894 895 Backported from master: 896 2021-07-28 Jakub Jelinek <jakub@redhat.com> 897 898 PR middle-end/101624 899 * ubsan.c (maybe_instrument_pointer_overflow, 900 instrument_object_size): Only test DECL_REGISTER on VAR_DECLs, 901 PARM_DECLs or RESULT_DECLs. 902 * sanopt.c (maybe_optimize_ubsan_ptr_ifn): Likewise. 903 9042022-05-10 Jakub Jelinek <jakub@redhat.com> 905 906 Backported from master: 907 2021-07-23 Jakub Jelinek <jakub@redhat.com> 908 909 PR rtl-optimization/101562 910 * expmed.c (store_integral_bit_field): Only use movstrict_optab 911 if the operand isn't paradoxical. 912 9132022-05-10 Jakub Jelinek <jakub@redhat.com> 914 915 Backported from master: 916 2021-07-21 Jakub Jelinek <jakub@redhat.com> 917 918 PR middle-end/101535 919 * gimplify.c (omp_check_private): Properly skip ORT_TARGET_DATA 920 contexts in which decl isn't privatized and for ORT_TARGET return 921 false if decl is mapped. 922 9232022-05-10 Jakub Jelinek <jakub@redhat.com> 924 925 Backported from master: 926 2021-07-20 Jakub Jelinek <jakub@redhat.com> 927 928 PR target/101384 929 * config/rs6000/rs6000.c (vspltis_constant): Accept EASY_VECTOR_MSB 930 only if step and copies are equal to 1. 931 9322022-05-10 Jakub Jelinek <jakub@redhat.com> 933 934 Backported from master: 935 2021-07-01 Jakub Jelinek <jakub@redhat.com> 936 937 PR middle-end/94366 938 * omp-low.c (lower_rec_input_clauses): Rename is_fp_and_or to 939 is_truth_op, set it for TRUTH_*IF_EXPR regardless of new_var's type, 940 use boolean_type_node instead of integer_type_node as NE_EXPR type. 941 (lower_reduction_clauses): Likewise. 942 9432022-05-10 Tobias Burnus <tobias@codesourcery.com> 944 945 Backported from master: 946 2021-05-04 Tobias Burnus <tobias@codesourcery.com> 947 948 * omp-low.c (lower_rec_input_clauses, lower_reduction_clauses): Handle 949 && and || with floating-point and complex arguments. 950 9512022-05-10 Jakub Jelinek <jakub@redhat.com> 952 953 Backported from master: 954 2021-07-14 Jakub Jelinek <jakub@redhat.com> 955 956 PR go/101407 957 * godump.c (godump_str_hash): New type. 958 (godump_container::pot_dummy_types): Use string_hash instead of 959 ptr_hash in the hash_set. 960 9612022-05-10 Jakub Jelinek <jakub@redhat.com> 962 963 Backported from master: 964 2021-07-01 Jakub Jelinek <jakub@redhat.com> 965 966 PR debug/101266 967 * dwarf2out.c (loc_list_from_tree_1): Handle COMPOUND_LITERAL_EXPR. 968 9692022-05-10 Jakub Jelinek <jakub@redhat.com> 970 971 Backported from master: 972 2021-06-29 Jakub Jelinek <jakub@redhat.com> 973 974 PR c++/101210 975 * match.pd ((intptr_t)x eq/ne CST to x eq/ne (typeof x) CST): Don't 976 perform the optimization in GENERIC when sanitizing and x has a 977 reference type. 978 9792022-05-10 Jakub Jelinek <jakub@redhat.com> 980 981 Backported from master: 982 2021-06-23 Jakub Jelinek <jakub@redhat.com> 983 984 PR middle-end/101167 985 * omp-low.c (lower_omp_regimplify_p): Regimplify also PARM_DECLs 986 and RESULT_DECLs that have DECL_HAS_VALUE_EXPR_P set. 987 9882022-05-10 Jakub Jelinek <jakub@redhat.com> 989 990 Backported from master: 991 2021-06-21 Jakub Jelinek <jakub@redhat.com> 992 993 PR inline-asm/100785 994 * cfgexpand.c (expand_asm_stmt): If errors are emitted, 995 remove all inputs, outputs and clobbers from the asm and 996 set template to "". 997 9982022-05-10 Jakub Jelinek <jakub@redhat.com> 999 1000 Backported from master: 1001 2021-06-18 Jakub Jelinek <jakub@redhat.com> 1002 1003 PR middle-end/101062 1004 * stor-layout.c (finish_bitfield_layout): Don't add bitfield 1005 representatives in QUAL_UNION_TYPE. 1006 10072022-05-10 Jakub Jelinek <jakub@redhat.com> 1008 1009 Backported from master: 1010 2021-06-16 Jakub Jelinek <jakub@redhat.com> 1011 1012 PR middle-end/101062 1013 * stor-layout.c (finish_bitfield_representative): For fields in unions 1014 assume nextf is always NULL. 1015 (finish_bitfield_layout): Compute bit field representatives also in 1016 unions, but handle it as if each bitfield was the only field in the 1017 aggregate. 1018 10192022-05-10 Jakub Jelinek <jakub@redhat.com> 1020 1021 Backported from master: 1022 2021-06-15 Jakub Jelinek <jakub@redhat.com> 1023 1024 PR target/101046 1025 * expr.c (expand_expr_real_2) <case VEC_PACK_FIX_TRUNC_EXPR, 1026 case VEC_PACK_TRUNC_EXPR>: Clear subtarget when changing mode. 1027 10282022-05-10 Jakub Jelinek <jakub@redhat.com> 1029 1030 Backported from master: 1031 2021-06-11 Jakub Jelinek <jakub@redhat.com> 1032 1033 PR rtl-optimization/101008 1034 * simplify-rtx.c (relational_result): New function. 1035 (simplify_logical_relational_operation, 1036 simplify_relational_operation): Use it. 1037 10382022-05-10 Jakub Jelinek <jakub@redhat.com> 1039 1040 Backported from master: 1041 2021-06-07 Jakub Jelinek <jakub@redhat.com> 1042 1043 PR target/100887 1044 * fold-const.c (fold_read_from_vector): Return NULL if trying to 1045 read from a CONSTRUCTOR with vector type elements. 1046 10472022-05-10 Jakub Jelinek <jakub@redhat.com> 1048 1049 Backported from master: 1050 2021-06-07 Jakub Jelinek <jakub@redhat.com> 1051 1052 PR middle-end/100898 1053 * tree-inline.c (copy_bb): Only use gimple_call_arg_ptr if memcpy 1054 should copy any arguments. Don't call gimple_call_num_args 1055 on id->call_stmt or call_stmt more than once. 1056 10572022-05-10 Jakub Jelinek <jakub@redhat.com> 1058 1059 Backported from master: 1060 2021-06-04 Jakub Jelinek <jakub@redhat.com> 1061 1062 PR target/100887 1063 * config/i386/i386-expand.c (ix86_expand_vector_init): Handle 1064 concatenation from half-sized modes with TImode elements. 1065 10662022-05-10 Jakub Jelinek <jakub@redhat.com> 1067 1068 Backported from master: 1069 2021-05-18 Jakub Jelinek <jakub@redhat.com> 1070 1071 PR c++/100580 1072 * function.c (push_dummy_function): Set DECL_ARTIFICIAL and 1073 DECL_ASSEMBLER_NAME on the fn_decl. 1074 10752022-05-10 Jakub Jelinek <jakub@redhat.com> 1076 1077 Backported from master: 1078 2021-05-15 Jakub Jelinek <jakub@redhat.com> 1079 1080 PR rtl-optimization/100342 1081 * regcprop.c (copy_value): When copying a source reg in a wider 1082 mode than it has recorded for the value, adjust recorded destination 1083 mode too or punt if !REG_CAN_CHANGE_MODE_P. 1084 10852022-05-10 liuhongt <hongtao.liu@intel.com> 1086 1087 Backported from master: 1088 2021-01-21 liuhongt <hongtao.liu@intel.com> 1089 1090 PR rtl-optimization/98694 1091 * regcprop.c (copy_value): If SRC had been assigned a mode 1092 narrower than the copy, we can't link DEST into the chain even 1093 they have same hard_regno_nregs(i.e. HImode/SImode in i386 1094 backend). 1095 10962022-05-10 Jakub Jelinek <jakub@redhat.com> 1097 1098 Backported from master: 1099 2021-05-12 Jakub Jelinek <jakub@redhat.com> 1100 1101 PR middle-end/100508 1102 * cfgexpand.c (expand_debug_expr): For DEBUG_EXPR_DECL with vector 1103 type, don't reuse DECL_RTL if it has different mode, instead force 1104 creation of a new DEBUG_EXPR. 1105 11062022-05-10 Jakub Jelinek <jakub@redhat.com> 1107 1108 Backported from master: 1109 2021-05-11 Jakub Jelinek <jakub@redhat.com> 1110 1111 PR middle-end/100471 1112 * omp-low.c (lower_omp_task_reductions): For OMP_TASKLOOP, if data 1113 is 0, bypass the reduction loop including 1114 GOMP_taskgroup_reduction_unregister call. 1115 11162022-05-10 Eric Botcazou <ebotcazou@adacore.com> 1117 1118 PR target/105292 1119 * config/sparc/sparc.c (sparc_vectorize_vec_perm_const): Return 1120 true only for 8-byte vector modes. 1121 11222022-05-06 Michael Meissner <meissner@linux.ibm.com> 1123 1124 Backported from master: 1125 2022-05-06 Michael Meissner <meissner@linux.ibm.com> 1126 1127 PR target/102059 1128 * config/rs6000/rs6000.c (rs6000_can_inline_p): Ignore -mpower8-fusion 1129 option for inlining purposes. 1130 11312022-05-06 Richard Biener <rguenther@suse.de> 1132 1133 Backported from master: 1134 2022-04-08 Richard Biener <rguenther@suse.de> 1135 1136 PR tree-optimization/105198 1137 * tree-predcom.c (find_looparound_phi): Check whether 1138 the found memory location of the entry value is clobbered 1139 inbetween the value we want to use and loop entry. 1140 11412022-05-06 Richard Biener <rguenther@suse.de> 1142 1143 Backported from master: 1144 2022-02-07 Richard Biener <rguenther@suse.de> 1145 1146 PR middle-end/104402 1147 * gimple-expr.c (is_gimple_condexpr): _Complex typed 1148 compares are not valid. 1149 * tree-cfg.c (verify_gimple_assign_ternary): For COND_EXPR 1150 check is_gimple_condexpr. 1151 11522022-04-27 Hongyu Wang <hongyu.wang@intel.com> 1153 1154 Backported from master: 1155 2022-04-25 Hongyu Wang <hongyu.wang@intel.com> 1156 1157 PR target/105339 1158 * config/i386/avx512fintrin.h (_mm512_scalef_round_pd): 1159 Add parentheses for parameters and djust format. 1160 (_mm512_mask_scalef_round_pd): Ditto. 1161 (_mm512_maskz_scalef_round_pd): Ditto. 1162 (_mm512_scalef_round_ps): Ditto. 1163 (_mm512_mask_scalef_round_ps): Ditto. 1164 (_mm512_maskz_scalef_round_ps): Ditto. 1165 (_mm_scalef_round_sd): Use _mm_undefined_pd. 1166 (_mm_scalef_round_ss): Use _mm_undefined_ps. 1167 (_mm_mask_scalef_round_sd): New macro. 1168 (_mm_mask_scalef_round_ss): Ditto. 1169 (_mm_maskz_scalef_round_sd): Ditto. 1170 (_mm_maskz_scalef_round_ss): Ditto. 1171 11722022-04-21 Richard Biener <rguenther@suse.de> 1173 1174 Backported from master: 1175 2022-01-20 Richard Biener <rguenther@suse.de> 1176 1177 PR middle-end/100786 1178 * gimple-fold.c (get_symbol_constant_value): Only return 1179 values of compatible type to the symbol. 1180 11812022-04-21 Richard Biener <rguenther@suse.de> 1182 1183 Backported from master: 1184 2021-11-23 Richard Biener <rguenther@suse.de> 1185 1186 PR tree-optimization/103361 1187 * gimple-loop-jam.c (adjust_unroll_factor): Use lambda_int 1188 for the dependence distance. 1189 * tree-data-ref.c (print_lambda_vector): Properly print a lambda_int. 1190 11912022-04-21 Richard Biener <rguenther@suse.de> 1192 1193 Backported from master: 1194 2021-12-07 Richard Biener <rguenther@suse.de> 1195 1196 PR tree-optimization/103596 1197 * tree-ssa-sccvn.c (eliminate_dom_walker::eliminate_stmt): 1198 Note we are not propagating into a PHI argument to may_propagate_copy. 1199 * tree-ssa-propagate.h (may_propagate_copy): Add 1200 argument specifying whether we propagate into a PHI arg. 1201 * tree-ssa-propagate.c (may_propagate_copy): Likewise. 1202 When not doing so we can replace an abnormal with 1203 something else. 1204 (may_propagate_into_stmt): Update may_propagate_copy calls. 1205 (replace_exp_1): Move propagation checking code to 1206 propagate_value and rename to ... 1207 (replace_exp): ... this and elide previous wrapper. 1208 (propagate_value): Perform checking with adjusted 1209 may_propagate_copy call and dispatch to replace_exp. 1210 12112022-04-21 Richard Biener <rguenther@suse.de> 1212 1213 Backported from master: 1214 2022-02-03 Richard Biener <rguenther@suse.de> 1215 1216 PR debug/104337 1217 * tree-nrv.c (pass_nrv::execute): Remove tieing result and found 1218 together via DECL_ABSTRACT_ORIGIN. 1219 12202022-04-21 Richard Biener <rguenther@suse.de> 1221 1222 Backported from master: 1223 2022-03-09 Richard Biener <rguenther@suse.de> 1224 1225 PR middle-end/104786 1226 * cfgexpand.c (expand_asm_stmt): Do not generate a copy 1227 for VLAs without an upper size bound. 1228 12292022-04-21 Richard Biener <rguenther@suse.de> 1230 1231 Backported from master: 1232 2022-04-12 Richard Biener <rguenther@suse.de> 1233 1234 PR tree-optimization/105226 1235 * tree-vect-loop-manip.c (vect_loop_versioning): Verify 1236 we can split the exit of an outer loop we choose to version. 1237 12382022-04-21 Richard Biener <rguenther@suse.de> 1239 1240 Backported from master: 1241 2022-03-28 Richard Biener <rguenther@suse.de> 1242 1243 PR tree-optimization/105070 1244 * tree-switch-conversion.h 1245 (bit_test_cluster::hoist_edge_and_branch_if_true): Add location 1246 argument. 1247 * tree-switch-conversion.c 1248 (bit_test_cluster::hoist_edge_and_branch_if_true): Annotate 1249 cond with location. 1250 (bit_test_cluster::emit): Annotate all generated expressions 1251 with location. 1252 12532022-04-05 Martin Jambor <mjambor@suse.cz> 1254 1255 Backported from master: 1256 2022-03-31 Martin Jambor <mjambor@suse.cz> 1257 1258 PR ipa/103083 1259 * ipa-prop.h (ipa_ancestor_jf_data): New flag keep_null; 1260 (ipa_get_jf_ancestor_keep_null): New function. 1261 * ipa-prop.c (ipa_set_ancestor_jf): Initialize keep_null field of the 1262 ancestor function. 1263 (compute_complex_assign_jump_func): Pass false to keep_null 1264 parameter of ipa_set_ancestor_jf. 1265 (compute_complex_ancestor_jump_func): Pass true to keep_null 1266 parameter of ipa_set_ancestor_jf. 1267 (update_jump_functions_after_inlining): Carry over keep_null from the 1268 original ancestor jump-function or merge them. 1269 (ipa_write_jump_function): Stream keep_null flag. 1270 (ipa_read_jump_function): Likewise. 1271 (ipa_print_node_jump_functions_for_edge): Print the new flag. 1272 * ipa-cp.c (class ipcp_bits_lattice): Make various getters const. New 1273 member function known_nonzero_p. 1274 (ipcp_bits_lattice::known_nonzero_p): New. 1275 (ipcp_bits_lattice::meet_with_1): New parameter drop_all_ones, 1276 observe it. 1277 (ipcp_bits_lattice::meet_with): Likewise. 1278 (propagate_bits_across_jump_function): Simplify. Pass true in 1279 drop_all_ones when it is necessary. 1280 (propagate_aggs_across_jump_function): Take care of keep_null 1281 flag. 1282 (ipa_get_jf_ancestor_result): Propagate NULL accross keep_null 1283 jump functions. 1284 12852022-03-26 H.J. Lu <hjl.tools@gmail.com> 1286 1287 Backported from master: 1288 2022-03-26 H.J. Lu <hjl.tools@gmail.com> 1289 1290 PR target/105052 1291 * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3): 1292 Replace "Yv" with "x". 1293 (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise. 1294 (ssse3_psign<mode>3): Likewise. 1295 12962022-03-18 Peter Bergner <bergner@linux.ibm.com> 1297 1298 Backported from master: 1299 2022-03-04 Peter Bergner <bergner@linux.ibm.com> 1300 1301 PR target/87496 1302 PR target/104208 1303 * config/rs6000/rs6000.c (rs6000_option_override_internal): Make the 1304 ISA 2.06 requirement for -mabi=ieeelongdouble conditional on 1305 -mlong-double-128. 1306 Move the -mabi=ieeelongdouble and -mabi=ibmlongdouble error checking 1307 from here... 1308 * common/config/rs6000/rs6000-common.c (rs6000_handle_option): 1309 ... to here. 1310 13112022-03-16 Richard Biener <rguenther@suse.de> 1312 1313 Backported from master: 1314 2022-02-09 Richard Biener <rguenther@suse.de> 1315 1316 PR target/104453 1317 * config/i386/i386.c (ix86_gimple_fold_builtin): Guard shift 1318 folding for NULL LHS. 1319 13202022-03-16 Richard Biener <rguenther@suse.de> 1321 1322 Backported from master: 1323 2022-02-14 Richard Biener <rguenther@suse.de> 1324 1325 PR tree-optimization/104511 1326 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid 1327 touching DFP <-> FP conversions. 1328 13292022-03-16 Richard Biener <rguenther@suse.de> 1330 1331 Backported from master: 1332 2022-01-20 Richard Biener <rguenther@suse.de> 1333 1334 PR target/100784 1335 * config/i386/i386.c (ix86_gimple_fold_builtin): Check for 1336 LHS before folding __builtin_ia32_shufpd and friends. 1337 13382022-03-12 Michael Meissner <meissner@the-meissners.org> 1339 1340 PR target/99708 1341 * config/rs6000/rs6000-c.c: Revert 2022-03-05 patch. 1342 13432022-03-06 Michael Meissner <meissner@the-meissners.org> 1344 1345 PR target/104253 1346 * config/rs6000/rs6000.c (init_float128_ibm): Update the 1347 conversion functions used to convert IFmode types. Backport 1348 change made to the master branch on 2022-02-14. 1349 13502022-03-06 Michael Meissner <meissner@the-meissners.org> 1351 1352 PR target/99708 1353 * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define 1354 __SIZEOF_IBM128__ if the IBM 128-bit long double type is created. 1355 Define __SIZEOF_FLOAT128__ if the IEEE 128-bit floating point type 1356 is created. Backport change to master branch on 2022-02-17. 1357 13582022-02-17 Richard Biener <rguenther@suse.de> 1359 1360 Backported from master: 1361 2021-11-15 Richard Biener <rguenther@suse.de> 1362 1363 PR tree-optimization/103237 1364 * tree-vect-loop.c (vect_is_simple_reduction): Fail for 1365 double reductions with multiple inner loop LC PHI nodes. 1366 13672022-02-17 Richard Biener <rguenther@suse.de> 1368 1369 Backported from master: 1370 2021-11-22 Richard Biener <rguenther@suse.de> 1371 1372 PR middle-end/103181 1373 PR middle-end/103248 1374 * tree-eh.c (operation_could_trap_helper_p): Properly 1375 check vector constants for a zero element for integer 1376 division. Separate floating point and integer division code. 1377 Properly handle fixed-point RDIV_EXPR. 1378 13792022-02-17 Richard Biener <rguenther@suse.de> 1380 1381 Backported from master: 1382 2021-11-08 Richard Biener <rguenther@suse.de> 1383 1384 PR tree-optimization/102798 1385 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): 1386 Only copy points-to info to newly generated SSA names. 1387 13882022-02-17 Richard Biener <rguenther@suse.de> 1389 1390 Backported from master: 1391 2021-10-15 Richard Biener <rguenther@suse.de> 1392 1393 PR ipa/102762 1394 * tree-inline.c (copy_bb): Avoid underflowing nargs. 1395 13962022-02-17 Richard Biener <rguenther@suse.de> 1397 1398 Backported from master: 1399 2021-06-08 Richard Biener <rguenther@suse.de> 1400 1401 PR tree-optimization/100923 1402 * tree-ssa-sccvn.c (valueize_refs_1): Take a pointer to 1403 the operand vector to be valueized. 1404 (valueize_refs): Likewise. 1405 (valueize_shared_reference_ops_from_ref): Adjust. 1406 (valueize_shared_reference_ops_from_call): Likewise. 1407 (vn_reference_lookup_3): Likewise. 1408 (vn_reference_lookup_pieces): Likewise. Re-valueize 1409 with honoring availability when we are about to create 1410 the ao_ref and valueized before. 1411 (vn_reference_lookup): Likewise. 1412 (vn_reference_insert_pieces): Adjust. 1413 14142022-02-17 Richard Biener <rguenther@suse.de> 1415 1416 Backported from master: 1417 2021-06-22 Richard Biener <rguenther@suse.de> 1418 1419 PR tree-optimization/101158 1420 * tree-vect-slp.c (vect_build_slp_tree_1): Move same operand 1421 checking after checking for matching operation. 1422 14232022-02-15 Kewen Lin <linkw@linux.ibm.com> 1424 1425 Backported from master: 1426 2022-02-07 Kewen Lin <linkw@linux.ibm.com> 1427 1428 PR target/103627 1429 * config/rs6000/rs6000.c (rs6000_option_override_internal): Move the 1430 hunk affecting VSX and ALTIVEC to appropriate place. 1431 14322022-02-15 Kewen Lin <linkw@linux.ibm.com> 1433 1434 Backported from master: 1435 2022-02-07 Kewen Lin <linkw@linux.ibm.com> 1436 1437 PR target/103627 1438 * config/rs6000/rs6000.c (rs6000_option_override_internal): Disable 1439 MMA if !TARGET_VSX. 1440 14412022-02-14 Maciej W. Rozycki <macro@embecosm.com> 1442 1443 Backported from master: 1444 2022-02-08 Maciej W. Rozycki <macro@embecosm.com> 1445 1446 * config/riscv/t-riscv (riscv-sr.o): Add $(TM_H) dependency. 1447 14482022-02-13 Alan Modra <amodra@gmail.com> 1449 1450 Backported from master: 1451 2020-10-01 Alan Modra <amodra@gmail.com> 1452 1453 * config/rs6000/ppc-asm.h: Support __PCREL__ code. 1454 14552022-02-10 Uros Bizjak <ubizjak@gmail.com> 1456 1457 Backported from master: 1458 2022-02-10 Uroš Bizjak <ubizjak@gmail.com> 1459 1460 PR target/104469 1461 * config/i386/sse.md (vec_unpacks_float_lo_v4si): 1462 Change operand 1 constraint to register_operand. 1463 14642022-02-09 Uroš Bizjak <ubizjak@gmail.com> 1465 1466 PR target/104458 1467 * config/i386/i386-expand.c (ix86_split_idivmod): 1468 Force operands[2] and operands[3] into a register.. 1469 14702022-02-09 liuhongt <hongtao.liu@intel.com> 1471 1472 PR target/104451 1473 * config/i386/sse.md (<insn><mode>3): lowpart_subreg 1474 operands[2] from SImode to QImode. 1475 14762022-02-03 Sebastian Huber <sebastian.huber@embedded-brains.de> 1477 1478 PR target/104090 1479 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Use also 1480 rs6000_cpu. 1481 14822022-02-02 Xi Ruoyao <xry111@mengyan1223.wang> 1483 1484 Backported from master: 1485 2022-02-01 Xi Ruoyao <xry111@mengyan1223.wang> 1486 1487 PR middle-end/95115 1488 * fold-const.c (const_binop): Do not fold NaN result from 1489 non-NaN operands. 1490 14912022-01-15 Peter Bergner <bergner@linux.ibm.com> 1492 1493 Backported from master: 1494 2021-11-16 Peter Bergner <bergner@linux.ibm.com> 1495 1496 PR target/102976 1497 * config/rs6000/mma.md (*vsx_assemble_pair): Add early-clobber for 1498 output operand. 1499 (*mma_assemble_acc): Likewise. 1500 15012022-01-15 Peter Bergner <bergner@linux.ibm.com> 1502 1503 * config/rs6000/mma.md (UNSPEC_VSX_ASSEMBLE): New unspec. 1504 (vsx_assemble_pair): Use mma_assemble_input_operand. 1505 Expand into UNSPEC_VSX_ASSEMBLE wrapper. 1506 (*vsx_assemble_pair): New define_insn_and_split. 1507 * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle 1508 UNSPEC_VSX_ASSEMBLE. 1509 15102022-01-15 Peter Bergner <bergner@linux.ibm.com> 1511 1512 Backported from master: 1513 2021-09-14 Peter Bergner <bergner@linux.ibm.com> 1514 1515 * config/rs6000/mma.md (unspecv): Add UNSPECV_MMA_XXSETACCZ. 1516 (*movpxi): Remove 'O' alternative. 1517 (mma_xxsetaccz): Change to define_insn. Use UNSPECV_MMA_XXSETACCZ. 1518 Add comment. 1519 * config/rs6000/rs6000.c (rs6000_rtx_costs): Handle UNSPEC_VOLATILE. 1520 15212022-01-14 Eric Botcazou <ebotcazou@adacore.com> 1522 1523 * ipa-param-manipulation.c (ipa_dump_adjusted_parameters): Dump 1524 reverse flag as "reverse" for the sake of consistency. 1525 * ipa-sra.c: Fix copyright year. 1526 (ipa_sra_function_summaries::duplicate): Copy the reverse flag. 1527 (dump_isra_access): Tweak dump line. 1528 (isra_write_node_summary): Write the reverse flag. 1529 (isra_read_node_info): Read it. 1530 (pull_accesses_from_callee): Test its consistency and copy it. 1531 15322022-01-12 Richard Biener <rguenther@suse.de> 1533 1534 Backported from master: 1535 2020-11-26 Richard Biener <rguenther@suse.de> 1536 1537 PR tree-optimization/97953 1538 * gimple-ssa-evrp-analyze.c 1539 (evrp_range_analyzer::record_ranges_from_incoming_edge): Make 1540 sure the condition post-dominates the SSA definition before 1541 recording into SSA_NAME_RANGE_INFO. 1542 15432022-01-10 Eric Botcazou <ebotcazou@adacore.com> 1544 1545 PR target/103465 1546 * coretypes.h (unwind_info_type): Swap UI_SEH and UI_TARGET. 1547 15482021-12-16 Martin Liska <mliska@suse.cz> 1549 1550 Backported from master: 1551 2021-12-15 Martin Liska <mliska@suse.cz> 1552 1553 PR target/103661 1554 * config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0 1555 as API expects that non-zero values are returned (do that 1556 it mask == 31). 1557 For "avx512vbmi2" argument, we return now 1 << 31, which is a 1558 negative integer value. 1559 15602021-12-15 Kewen Lin <linkw@linux.ibm.com> 1561 1562 Backported from master: 1563 2021-11-30 Kewen Lin <linkw@linux.ibm.com> 1564 1565 PR target/102347 1566 * config/rs6000/rs6000-call.c (rs6000_builtin_decl): Remove builtin mask 1567 check. 1568 15692021-12-01 Martin Jambor <mjambor@suse.cz> 1570 1571 Backported from master: 1572 2021-11-30 Martin Jambor <mjambor@suse.cz> 1573 1574 PR ipa/103267 1575 * ipa-sra.c (scan_function): Also check ECF_LOOPING_CONST_OR_PURE flag. 1576 15772021-11-30 Eric Botcazou <ebotcazou@adacore.com> 1578 1579 PR target/103274 1580 * config/i386/i386.c (ix86_output_call_insn): Beef up comment about 1581 nops emitted with SEH. 1582 * config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to 1583 the cold section, emit a nop before the directive if the previous 1584 active instruction is a call. 1585 15862021-11-25 Jan Hubicka <jh@suse.cz> 1587 1588 Backported from master: 1589 2021-11-20 Jan Hubicka <hubicka@ucw.cz> 1590 1591 PR ipa/103052 1592 * ipa-pure-const.c (propagate_pure_const): Fix merging of loping flag. 1593 15942021-11-23 Bill Schmidt <wschmidt@linux.ibm.com> 1595 1596 PR target/101985 1597 * config/rs6000/altivec.h (vec_cpsgn): Swap operand order. 1598 15992021-11-22 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 1600 1601 Backported from master: 1602 2021-11-19 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 1603 1604 * config/s390/s390.md (define_peephole2): Variable insn points 1605 to the first matched insn. Use peep2_next_insn(1) to refer to 1606 the second matched insn. 1607 16082021-11-15 Kewen Lin <linkw@linux.ibm.com> 1609 1610 Backported from master: 1611 2021-11-11 Kewen Lin <linkw@linux.ibm.com> 1612 1613 * doc/invoke.texi: Change references to "future cpu" to "power10", 1614 "-mcpu=future" to "-mcpu=power10". Adjust words for float128. 1615 16162021-11-09 Richard Biener <rguenther@suse.de> 1617 1618 Backported from master: 1619 2021-10-13 Richard Biener <rguenther@suse.de> 1620 1621 PR ipa/102714 1622 * ipa-sra.c (ptr_parm_has_nonarg_uses): Fix volatileness 1623 check. 1624 16252021-11-09 Richard Biener <rguenther@suse.de> 1626 1627 Backported from master: 1628 2021-05-19 Richard Biener <rguenther@suse.de> 1629 1630 PR middle-end/100672 1631 * fold-const.c (fold_negate_expr_1): Use element_precision. 1632 (negate_expr_p): Likewise. 1633 16342021-11-09 Richard Biener <rguenther@suse.de> 1635 1636 PR tree-optimization/100253 1637 * tree-vect-stmts.c (vectorizable_load): Do not assume 1638 element alignment when DR_MISALIGNMENT is -1. 1639 (vectorizable_store): Likewise. 1640 16412021-11-08 Kewen Lin <linkw@linux.ibm.com> 1642 1643 Backported from master: 1644 2021-10-26 Kewen Lin <linkw@linux.ibm.com> 1645 1646 PR tree-optimization/102789 1647 * tree-vect-loop-manip.c (vect_update_inits_of_drs): Do not 1648 update inits of simd_lane_access. 1649 16502021-11-03 Vladimir N. Makarov <vmakarov@redhat.com> 1651 1652 PR rtl-optimization/102842 1653 * lra-constraints.c (match_reload): Ignore out in checking values 1654 of outs. 1655 (curr_insn_transform): Collect outputs before doing reloads of operands. 1656 16572021-11-02 Martin Jambor <mjambor@suse.cz> 1658 1659 Backported from master: 1660 2021-10-21 Martin Jambor <mjambor@suse.cz> 1661 1662 PR tree-optimization/102505 1663 * tree-sra.c (totally_scalarize_subtree): Check that the 1664 encountered field fits within the acces we would like to put it 1665 in. 1666 16672021-10-28 Eric Botcazou <ebotcazou@adacore.com> 1668 1669 * doc/invoke.texi (%X): Remove obsolete reference to -Wl. 1670 16712021-10-27 Uroš Bizjak <ubizjak@gmail.com> 1672 1673 PR target/102761 1674 * config/i386/i386.c (ix86_print_operand_address): 1675 Error out for non-address_operand asm operands. 1676 16772021-10-26 Piotr Kubaj <pkubaj@FreeBSD.org> 1678 1679 Backported from master: 1680 2021-10-16 Piotr Kubaj <pkubaj@FreeBSD.org> 1681 1682 * configure.ac: Treat powerpc64*-*-freebsd* the same as 1683 powerpc64-*-freebsd*. 1684 * configure: Regenerate. 1685 16862021-10-24 John David Anglin <danglin@gcc.gnu.org> 1687 1688 * config/pa/pa.md: Don't use 'G' constraint in integer move patterns. 1689 16902021-10-21 H.J. Lu <hjl.tools@gmail.com> 1691 1692 Backported from master: 1693 2021-10-21 H.J. Lu <hjl.tools@gmail.com> 1694 1695 PR target/98667 1696 * doc/invoke.texi: Document -fcf-protection requires i686 or 1697 new. 1698 16992021-10-15 John David Anglin <danglin@gcc.gnu.org> 1700 1701 * config/pa/pa.md: Consistently use "rG" constraint for copy 1702 instruction in move patterns. 1703 17042021-10-14 John David Anglin <danglin@gcc.gnu.org> 1705 1706 * config/pa/pa.md (cbranchsf4): Disable if TARGET_SOFT_FLOAT. 1707 (cbranchdf4): Likewise. 1708 Add missing move patterns for TARGET_SOFT_FLOAT. 1709 17102021-10-13 John David Anglin <danglin@gcc.gnu.org> 1711 1712 * config/pa/pa.md (muldi3): Add support for inlining 64-bit 1713 multiplication on 32-bit PA 1.1 and 2.0 targets. 1714 17152021-10-13 Richard Biener <rguenther@suse.de> 1716 1717 Backported from master: 1718 2021-08-25 Richard Biener <rguenther@suse.de> 1719 1720 PR tree-optimization/102046 1721 * tree-vect-slp.c (vect_build_slp_tree_2): Conservatively 1722 update ->any_pattern when swapping operands. 1723 17242021-10-13 Richard Biener <rguenther@suse.de> 1725 1726 Backported from master: 1727 2021-08-17 Richard Biener <rguenther@suse.de> 1728 1729 PR tree-optimization/101925 1730 * tree-ssa-sccvn.c (copy_reference_ops_from_ref): Set 1731 reverse on COMPONENT_REF and ARRAY_REF according to 1732 what reverse_storage_order_for_component_p does. 1733 (vn_reference_eq): Compare reversed on reference ops. 1734 (reverse_storage_order_for_component_p): New overload. 1735 (vn_reference_lookup_3): Check reverse_storage_order_for_component_p 1736 on the reference looked up. 1737 17382021-10-13 Richard Biener <rguenther@suse.de> 1739 1740 Backported from master: 1741 2021-08-17 Richard Biener <rguenther@suse.de> 1742 1743 PR tree-optimization/101373 1744 PR tree-optimization/101868 1745 * tree-ssa-pre.c (prune_clobbered_mems): Also prune trapping 1746 references when the BB may not return. 1747 17482021-10-13 Richard Biener <rguenther@suse.de> 1749 1750 Backported from master: 1751 2021-08-10 Richard Biener <rguenther@suse.de> 1752 1753 PR middle-end/101824 1754 * tree-nested.c (get_frame_field): Mark the COMPONENT_REF as 1755 volatile in case the variable was. 1756 17572021-10-12 Eric Botcazou <ebotcazou@adacore.com> 1758 1759 PR target/102588 1760 * config/sparc/sparc-modes.def (OI): New integer mode. 1761 17622021-10-11 Diane Meirowitz <diane.meirowitz@oracle.com> 1763 1764 Backported from master: 1765 2021-10-11 Diane Meirowitz <diane.meirowitz@oracle.com> 1766 1767 * doc/invoke.texi: Add link to UndefinedBehaviorSanitizer 1768 documentation, mention UBSAN_OPTIONS, similar to what is done 1769 for AddressSanitizer. 1770 17712021-10-11 Andrew Pinski <apinski@marvell.com> 1772 1773 PR tree-optimization/102622 1774 * tree-ssa-phiopt.c (conditional_replacement): Set neg 1775 to false for one bit signed types. 1776 17772021-10-01 Eric Botcazou <ebotcazou@adacore.com> 1778 1779 * explow.c: Include langhooks.h. 1780 (set_stack_check_libfunc): Build a proper function type. 1781 17822021-10-01 Eric Botcazou <ebotcazou@adacore.com> 1783 1784 PR c++/64697 1785 * config/i386/i386.c (legitimate_pic_address_disp_p): For PE-COFF do 1786 not return true for external weak function symbols in medium model. 1787 17882021-09-22 Kewen Lin <linkw@linux.ibm.com> 1789 1790 Backported from master: 1791 2021-09-22 Kewen Lin <linkw@linux.ibm.com> 1792 1793 * ipa-fnsummary.c (inline_read_section): Unpack a dummy bit 1794 to keep consistent with the side of streaming out. 1795 17962021-09-21 Segher Boessenkool <segher@kernel.crashing.org> 1797 1798 Backported from master: 1799 2021-09-08 Segher Boessenkool <segher@kernel.crashing.org> 1800 1801 PR target/102107 1802 * config/rs6000/rs6000-logue.c (rs6000_emit_epilogue): For ELFv2 use 1803 r11 instead of r12 for restoring CR. 1804 18052021-09-21 Segher Boessenkool <segher@kernel.crashing.org> 1806 1807 Backported from master: 1808 2021-09-03 Segher Boessenkool <segher@kernel.crashing.org> 1809 1810 PR target/102107 1811 * config/rs6000/rs6000-logue.c (rs6000_emit_prologue): On ELFv2 use r11 1812 instead of r12 for CR save, in all cases. 1813 18142021-09-17 Eric Botcazou <ebotcazou@adacore.com> 1815 1816 PR rtl-optimization/102306 1817 * combine.c (try_combine): Abort the combination if we are about to 1818 duplicate volatile references. 1819 18202021-09-16 Daniel Cederman <cederman@gaisler.com> 1821 1822 * config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5 1823 * config/sparc/sparc.c (struct processor_costs): Add LEON5 costs 1824 (leon5_adjust_cost): Increase cost of store with data dependency 1825 on ALU instruction and FPU anti-dependencies. 1826 (sparc_option_override): Add LEON5 costs 1827 (sparc_adjust_cost): Add LEON5 cost adjustments 1828 * config/sparc/sparc.h: Add LEON5 1829 * config/sparc/sparc.md: Include LEON5 scheduling information 1830 * config/sparc/sparc.opt: Add LEON5 1831 * doc/invoke.texi: Add LEON5 1832 * config/sparc/leon5.md: New file. 1833 18342021-09-16 Daniel Cederman <cederman@gaisler.com> 1835 1836 * config/sparc/sparc.md (stack_protect_setsi): Add NOP to prevent 1837 sensitive sequence for B2BST errata workaround. 1838 18392021-09-16 Daniel Cederman <cederman@gaisler.com> 1840 1841 * config/sparc/sparc.c (sparc_do_work_around_errata): Do not begin 1842 functions with atomic instruction in the UT700 errata workaround. 1843 18442021-09-16 Daniel Cederman <cederman@gaisler.com> 1845 1846 * config/sparc/sparc.c (next_active_non_empty_insn): New function 1847 that returns next active non empty assembly instruction. 1848 (sparc_do_work_around_errata): Use new function. 1849 18502021-09-16 Daniel Cederman <cederman@gaisler.com> 1851 1852 * config/sparc/sparc.c (store_insn_p): Add predicate for store 1853 attributes. 1854 (load_insn_p): Add predicate for load attributes. 1855 (sparc_do_work_around_errata): Use new predicates. 1856 18572021-09-16 Andreas Larsson <andreas@gaisler.com> 1858 1859 * config/sparc/sparc.c (dump_target_flag_bits): Print bit names for 1860 LEON and LEON3. 1861 18622021-09-14 Xionghu Luo <luoxhu@linux.ibm.com> 1863 1864 Backported from master: 1865 2021-09-07 Xionghu Luo <luoxhu@linux.ibm.com> 1866 1867 PR target/97142 1868 * config/rs6000/rs6000.md (fmod<mode>3): New define_expand. 1869 (remainder<mode>3): Likewise. 1870 18712021-09-08 Jonathan Wakely <jwakely@redhat.com> 1872 1873 Backported from master: 1874 2021-09-08 Jonathan Wakely <jwakely@redhat.com> 1875 1876 PR c++/60318 1877 * doc/trouble.texi (Copy Assignment): Fix description of 1878 behaviour and fix code in example. 1879 18802021-09-06 Richard Biener <rguenther@suse.de> 1881 1882 Backported from master: 1883 2021-07-12 Richard Biener <rguenther@suse.de> 1884 1885 PR tree-optimization/101394 1886 * tree-ssa-pre.c (do_pre_regular_insertion): Avoid inserting 1887 copies from abnormals for a full redundancy. 1888 18892021-09-06 Richard Biener <rguenther@suse.de> 1890 1891 Backported from master: 1892 2021-07-05 Richard Biener <rguenther@suse.de> 1893 1894 PR middle-end/101291 1895 * cfgloopmanip.c (loop_version): Set the loop copy of the 1896 versioned loop to the new loop. 1897 18982021-09-06 Richard Biener <rguenther@suse.de> 1899 1900 Backported from master: 1901 2021-07-07 Richard Biener <rguenther@suse.de> 1902 1903 PR tree-optimization/101173 1904 PR tree-optimization/101280 1905 * gimple-loop-interchange.cc 1906 (tree_loop_interchange::valid_data_dependences): Properly 1907 guard all dependence checks with DDR_REVERSED_P or its 1908 inverse. 1909 19102021-09-06 Richard Biener <rguenther@suse.de> 1911 1912 Backported from master: 1913 2021-06-24 Richard Biener <rguenther@suse.de> 1914 1915 PR tree-optimization/101105 1916 * tree-vect-data-refs.c (vect_prune_runtime_alias_test_list): 1917 Only ignore steps when they are equal or scalar order is preserved. 1918 19192021-09-06 Richard Biener <rguenther@suse.de> 1920 1921 Backported from master: 1922 2021-06-11 Richard Biener <rguenther@suse.de> 1923 1924 PR middle-end/101009 1925 * tree-data-ref.c (build_classic_dist_vector_1): Make sure 1926 to set *init_b to true when we encounter a constant equal 1927 index pair. 1928 (compute_affine_dependence): Also dump the actual DR_REF. 1929 19302021-09-03 Peter Bergner <bergner@linux.ibm.com> 1931 1932 Backported from master: 1933 2021-08-19 Peter Bergner <bergner@linux.ibm.com> 1934 1935 PR target/101849 1936 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Cast 1937 pointer to __vector_pair *. 1938 19392021-09-03 Peter Bergner <bergner@linux.ibm.com> 1940 1941 Backported from master: 1942 2021-07-07 Peter Bergner <bergner@linux.ibm.com> 1943 1944 * config/rs6000/rs6000-call.c (mma_init_builtins): Use VSX_BUILTIN_LXVP 1945 and VSX_BUILTIN_STXVP. 1946 19472021-09-03 Peter Bergner <bergner@linux.ibm.com> 1948 1949 Backported from master: 1950 2021-07-02 Peter Bergner <bergner@linux.ibm.com> 1951 1952 * config/rs6000/rs6000-builtin.def (BU_MMA_PAIR_LD, BU_MMA_PAIR_ST): 1953 New macros. 1954 (__builtin_vsx_lxvp, __builtin_vsx_stxvp): New built-ins. 1955 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Expand 1956 lxvp and stxvp built-ins. 1957 (mma_init_builtins): Handle lxvp and stxvp built-ins. 1958 (builtin_function_type): Likewise. 1959 * doc/extend.texi (__builtin_vsx_lxvp, __builtin_mma_stxvp): Document. 1960 19612021-09-03 Peter Bergner <bergner@linux.ibm.com> 1962 1963 * config/rs6000/rs6000-call.c (mma_init_builtins): Test for 1964 MMA_BUILTIN_DISASSEMBLE_ACC and VSX_BUILTIN_DISASSEMBLE_PAIR. 1965 (rs6000_gimple_fold_mma_builtin): Likewise. 1966 19672021-08-31 Thomas Schwinge <thomas@codesourcery.com> 1968 1969 Backported from master: 1970 2021-08-31 Thomas Schwinge <thomas@codesourcery.com> 1971 1972 * tree.c (walk_tree_1) <OMP_CLAUSE_TILE>: Handle three operands. 1973 19742021-08-27 konglin1 <lingling.kong@intel.com> 1975 1976 PR target/101472 1977 * config/i386/sse.md: (<avx512>scattersi<mode>): Add mask operand to 1978 UNSPEC_VSIBADDR. 1979 (<avx512>scattersi<mode>): Likewise. 1980 (*avx512f_scattersi<VI48F:mode>): Merge mask operand to set_dest. 1981 (*avx512f_scatterdi<VI48F:mode>): Likewise 1982 19832021-08-25 konglin1 <lingling.kong@intel.com> 1984 1985 PR target/101471 1986 * config/i386/avx512dqintrin.h (_mm512_fpclass_ps_mask): Fix 1987 macro define in O0. 1988 (_mm512_mask_fpclass_ps_mask): Ditto. 1989 19902021-08-24 Richard Earnshaw <rearnsha@arm.com> 1991 1992 Backported from master: 1993 2021-08-24 Richard Earnshaw <rearnsha@arm.com> 1994 1995 PR target/102035 1996 * config/arm/arm.md (attribute arch): Add fix_vlldm. 1997 (arch_enabled): Use it. 1998 * config/arm/vfp.md (lazy_store_multiple_insn): Add alternative to 1999 use when erratum mitigation is needed. 2000 20012021-08-24 Richard Earnshaw <rearnsha@arm.com> 2002 2003 Backported from master: 2004 2021-08-24 Richard Earnshaw <rearnsha@arm.com> 2005 2006 PR target/102035 2007 * config/arm/arm.opt (mfix-cmse-cve-2021-35465): New option. 2008 * doc/invoke.texi (Arm Options): Document it. 2009 * config/arm/arm-cpus.in (quirk_vlldm): New feature bit. 2010 (ALL_QUIRKS): Add quirk_vlldm. 2011 (cortex-m33): Add quirk_vlldm. 2012 (cortex-m35p, cortex-m55): Likewise. 2013 * config/arm/arm.c (arm_option_override): Enable fix_vlldm if 2014 targetting an affected CPU and not explicitly controlled on 2015 the command line. 2016 20172021-08-24 Richard Earnshaw <rearnsha@arm.com> 2018 2019 Backported from master: 2020 2021-08-24 Richard Earnshaw <rearnsha@arm.com> 2021 2022 * config/arm/vfp.md (lazy_store_multiple_insn): Rewrite as valid RTL. 2023 (lazy_load_multiple_insn): Likewise. 2024 20252021-08-24 Richard Biener <rguenther@suse.de> 2026 2027 Backported from master: 2028 2021-08-23 Richard Biener <rguenther@suse.de> 2029 2030 PR ipa/97565 2031 * tree-ssa-structalias.c (ipa_pta_execute): Check in_other_partition 2032 in addition to has_gimple_body. 2033 20342021-08-23 Richard Earnshaw <rearnsha@arm.com> 2035 2036 Backported from master: 2037 2021-08-05 Richard Earnshaw <rearnsha@arm.com> 2038 2039 PR target/101723 2040 * config/arm/arm-cpus.in (generic-armv7-a): Add quirk to suppress 2041 writing .cpu directive in asm output. 2042 * config/arm/arm.c (arm_identify_fpu_from_isa): New variable. 2043 (arm_last_printed_arch_string): Delete. 2044 (arm_last-printed_fpu_string): Delete. 2045 (arm_configure_build_target): If use of floating-point/SIMD is 2046 disabled, remove all fp/simd related features from the target ISA. 2047 (last_arm_targ_options): New variable. 2048 (arm_print_asm_arch_directives): Add new parameters. Change order 2049 of emitted directives and handle all cases here. 2050 (arm_file_start): Always call arm_print_asm_arch_directives, move 2051 all generation of .arch/.arch_extension here. 2052 (arm_file_end): Call arm_print_asm_arch. 2053 (arm_declare_function_name): Call arm_print_asm_arch_directives 2054 instead of printing .arch/.fpu directives directly. 2055 20562021-08-23 Richard Earnshaw <rearnsha@arm.com> 2057 2058 Backported from master: 2059 2021-08-05 Richard Earnshaw <rearnsha@arm.com> 2060 2061 * config/arm/arm.c (arm_configure_build_target): Don't call 2062 arm_option_reconfigure_globals. 2063 (arm_option_restore): Call arm_option_reconfigure_globals after 2064 reconfiguring the target. 2065 * config/arm/arm-c.c (arm_pragma_target_parse): Likewise. 2066 20672021-08-23 Richard Earnshaw <rearnsha@arm.com> 2068 2069 Backported from master: 2070 2021-08-05 Richard Earnshaw <rearnsha@arm.com> 2071 2072 * config/arm/arm.c (arm_configure_build_target): Ensure the target's 2073 arch_name is always set. 2074 20752021-08-23 Christophe Lyon <christophe.lyon@foss.st.com> 2076 2077 Backported from master: 2078 2021-08-23 Christophe Lyon <christophe.lyon@foss.st.com> 2079 2080 * config/arm/arm_mve.h: Fix __arm_vctp16q return type. 2081 20822021-08-19 Richard Earnshaw <rearnsha@arm.com> 2083 2084 Backported from master: 2085 2021-05-27 Richard Earnshaw <rearnsha@arm.com> 2086 2087 PR target/100767 2088 * config/arm/arm.c (arm_configure_build_target): Remove parameter 2089 opts_set, directly check opts parameters for being non-null. 2090 (arm_option_restore): Update call to arm_configure_build_target. 2091 (arm_option_override): Likewise. 2092 (arm_can_inline_p): Likewise. 2093 (arm_valid_target_attribute_tree): Likewise. 2094 * config/arm/arm-c.c (arm_pragma_target_parse): Likewise. 2095 * config/arm/arm-protos.h (arm_configure_build_target): Adjust 2096 prototype. 2097 20982021-08-17 Richard Sandiford <richard.sandiford@arm.com> 2099 2100 Backported from master: 2101 2021-08-03 Richard Sandiford <richard.sandiford@arm.com> 2102 2103 * doc/invoke.texi: Document -mtune=neoverse-512tvb and 2104 -mcpu=neoverse-512tvb. 2105 * config/aarch64/aarch64-cores.def (neoverse-512tvb): New entry. 2106 * config/aarch64/aarch64-tune.md: Regenerate. 2107 21082021-08-17 Richard Sandiford <richard.sandiford@arm.com> 2109 2110 Backported from master: 2111 2021-04-28 Richard Sandiford <richard.sandiford@arm.com> 2112 2113 PR target/100305 2114 * config/aarch64/constraints.md (Utq): Require the address to 2115 be valid for both the element mode and for V2DImode. 2116 21172021-08-13 Martin Liska <mliska@suse.cz> 2118 2119 PR gcov-profile/100788 2120 * coverage.c (coverage_begin_function): Update function 2121 beginning when #line macro is used. 2122 21232021-07-31 Xi Ruoyao <xry111@mengyan1223.wang> 2124 2125 Backported from master: 2126 2021-07-30 Xi Ruoyao <xry111@mengyan1223.wang> 2127 2128 PR target/94780 2129 * config/mips/mips.c (mips_atomic_assign_expand_fenv): Use 2130 TARGET_EXPR instead of MODIFY_EXPR. 2131 21322021-07-28 Martin Sebor <msebor@redhat.com> 2133 2134 PR c/99295 2135 * doc/extend.texi (attribute malloc): Reword and clarify nonaliasing 2136 property. 2137 21382021-07-20 Martin Jambor <mjambor@suse.cz> 2139 2140 Backported from master: 2141 2021-07-08 Martin Jambor <mjambor@suse.cz> 2142 2143 PR ipa/101066 2144 * ipa-sra.c (class isra_call_summary): New member 2145 m_before_any_store, initialize it in the constructor. 2146 (isra_call_summary::dump): Dump the new field. 2147 (ipa_sra_call_summaries::duplicate): Copy it. 2148 (process_scan_results): Set it. 2149 (isra_write_edge_summary): Stream it. 2150 (isra_read_edge_summary): Likewise. 2151 (param_splitting_across_edge): Only override 2152 safe_to_import_accesses if m_before_any_store is set. 2153 21542021-07-20 Uroš Bizjak <ubizjak@gmail.com> 2155 2156 PR target/100182 2157 * config/i386/sync.md (define_peephole2 atomic_storedi_fpu): 2158 Remove. 2159 (define_peephole2 atomic_loaddi_fpu): Ditto. 2160 21612021-07-19 Bill Schmidt <wschmidt@linux.ibm.com> 2162 2163 PR target/101129 2164 * config/rs6000/rs6000-p8swap.c (has_part_mult): New. 2165 (rs6000_analyze_swaps): Insns containing a subreg of a mult are 2166 not swappable. 2167 21682021-07-19 Segher Boessenkool <segher@kernel.crashing.org> 2169 2170 PR rtl-optimization/99927 2171 * combine.c (distribute_notes) [REG_UNUSED]: If the register already 2172 is dead, just drop it. 2173 21742021-07-02 Eric Botcazou <ebotcazou@adacore.com> 2175 2176 * config/i386/i386.c (asm_preferred_eh_data_format): Always use the 2177 PIC encodings for PE-COFF targets. 2178 21792021-06-24 Uros Bizjak <ubizjak@gmail.com> 2180 2181 Backported from master: 2182 2021-06-23 Uroš Bizjak <ubizjak@gmail.com> 2183 2184 PR target/101175 2185 * config/i386/i386.md (bsr_rex64): Add zero-flag setting RTX. 2186 (bsr): Ditto. 2187 (*bsrhi): Remove. 2188 (clz<mode>2): Update RTX pattern for additions. 2189 21902021-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2191 2192 Backported from master: 2193 2021-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2194 2195 PR target/100856 2196 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function 2197 derived from arm_canon_arch. 2198 (arm_canon_arch_option): Call it. 2199 (arm_canon_arch_multilib_option): New function. 2200 * config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup. 2201 * config/arm/arm.h (arm_canon_arch_multilib_option): New prototype. 2202 (CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro. 2203 (MULTILIB_ARCH_CANONICAL_SPECS): New macro. 2204 (DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS. 2205 * config/arm/arm.opt (mlibarch): New option. 2206 * config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use 2207 of march on RHS with mlibarch. 2208 22092021-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2210 2211 Backported from master: 2212 2021-06-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2213 2214 PR target/101016 2215 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, 2216 int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for 2217 the polymorphic variants matching code. 2218 (__arm_vld1q_z): Likewise. 2219 (__arm_vld2q): Likewise. 2220 (__arm_vld4q): Likewise. 2221 (__arm_vldrbq_gather_offset): Likewise. 2222 (__arm_vldrbq_gather_offset_z): Likewise. 2223 22242021-06-18 Peter Bergner <bergner@linux.ibm.com> 2225 2226 Backported from master: 2227 2021-06-14 Peter Bergner <bergner@linux.ibm.com> 2228 2229 PR target/100777 2230 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Use 2231 create_tmp_reg_or_ssa_name(). 2232 22332021-06-18 Peter Bergner <bergner@linux.ibm.com> 2234 2235 Backported from master: 2236 2021-06-10 Peter Bergner <bergner@linux.ibm.com> 2237 2238 * config/rs6000/rs6000-builtin.def (build_pair): New built-in. 2239 (build_acc): Likewise. 2240 * config/rs6000/rs6000-call.c (mma_expand_builtin): Swap assemble 2241 source operands in little-endian mode. 2242 (rs6000_gimple_fold_mma_builtin): Handle VSX_BUILTIN_BUILD_PAIR. 2243 (mma_init_builtins): Likewise. 2244 * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle endianness 2245 ordering for the MMA assemble and build source operands. 2246 * doc/extend.texi (__builtin_vsx_build_acc, __builtin_mma_build_pair): 2247 Document. 2248 (__builtin_mma_assemble_acc, __builtin_mma_assemble_pair): Remove 2249 documentation. 2250 22512021-06-18 Peter Bergner <bergner@linux.ibm.com> 2252 2253 Backported from master: 2254 2021-05-31 Peter Bergner <bergner@linux.ibm.com> 2255 2256 PR target/99842 2257 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow 2258 indexed form addresses. 2259 22602021-06-17 Marius Hillenbrand <mhillen@linux.ibm.com> 2261 2262 Backported from master: 2263 2021-06-17 Marius Hillenbrand <mhillen@linux.ibm.com> 2264 2265 PR target/100871 2266 * config/s390/vecintrin.h (vec_doublee): Fix to use 2267 __builtin_s390_vflls. 2268 (vec_floate): Fix to use __builtin_s390_vflrd. 2269 22702021-06-16 Richard Biener <rguenther@suse.de> 2271 2272 Backported from master: 2273 2021-06-14 Richard Biener <rguenther@suse.de> 2274 2275 PR tree-optimization/100934 2276 * tree-ssa-dom.c (pass_dominator::execute): Properly 2277 mark irreducible regions. 2278 22792021-06-16 Richard Biener <rguenther@suse.de> 2280 2281 Backported from master: 2282 2021-05-28 Richard Biener <rguenther@suse.de> 2283 2284 PR ipa/100791 2285 * tree-inline.c (copy_bb): When processing __builtin_va_arg_pack 2286 copy fntype from original call. 2287 22882021-06-16 Richard Biener <rguenther@suse.de> 2289 2290 Backported from master: 2291 2021-05-11 Richard Biener <rguenther@suse.de> 2292 2293 PR ipa/100513 2294 * ipa-param-manipulation.c 2295 (ipa_param_body_adjustments::modify_call_stmt): Avoid 2296 altering SSA_NAME_DEF_STMT by adjusting the calls LHS 2297 via gimple_call_lhs_ptr. 2298 22992021-06-16 Richard Biener <rguenther@suse.de> 2300 2301 Backported from master: 2302 2021-05-11 Richard Biener <rguenther@suse.de> 2303 2304 PR middle-end/100509 2305 * gimple-fold.c (fold_gimple_assign): Only call 2306 get_symbol_constant_value on register type symbols. 2307 23082021-06-16 Richard Biener <rguenther@suse.de> 2309 2310 Backported from master: 2311 2021-05-10 Richard Biener <rguenther@suse.de> 2312 2313 PR tree-optimization/100492 2314 * tree-loop-distribution.c (find_seed_stmts_for_distribution): 2315 Find nothing when the loop contains an irreducible region. 2316 23172021-06-04 Alex Coplan <alex.coplan@arm.com> 2318 2319 Backported from master: 2320 2021-05-19 Alex Coplan <alex.coplan@arm.com> 2321 2322 PR target/100333 2323 * config/arm/arm.md (nonsecure_call_internal): Always ensure 2324 callee's address is in a register. 2325 23262021-06-02 Vladimir N. Makarov <vmakarov@redhat.com> 2327 2328 Backported from master: 2329 2021-01-21 Vladimir N. Makarov <vmakarov@redhat.com> 2330 2331 PR rtl-optimization/98777 2332 * lra-int.h (lra_pmode_pseudo): New extern. 2333 * lra.c (lra_pmode_pseudo): New global. 2334 (lra): Set it up. 2335 * lra-eliminations.c (eliminate_regs_in_insn): Use it. 2336 23372021-06-02 Vladimir N. Makarov <vmakarov@redhat.com> 2338 2339 Backported from master: 2340 2021-01-20 Vladimir N. Makarov <vmakarov@redhat.com> 2341 2342 PR rtl-optimization/98722 2343 * lra-eliminations.c (eliminate_regs_in_insn): Check that target 2344 has no 3-op add insn to transform insns containing two pluses. 2345 23462021-06-02 Vladimir N. Makarov <vmakarov@redhat.com> 2347 2348 Backported from master: 2349 2021-01-12 Vladimir N. Makarov <vmakarov@redhat.com> 2350 2351 PR target/97969 2352 * lra-eliminations.c (eliminate_regs_in_insn): Add transformation 2353 of pattern 'plus (plus (hard reg, const), pseudo)'. 2354 23552021-06-02 Uros Bizjak <ubizjak@gmail.com> 2356 2357 Backported from master: 2358 2021-06-02 Uroš Bizjak <ubizjak@gmail.com> 2359 2360 * config/i386/sse.md (abs<MMXMODEI:mode>2): 2361 Change define_insn to define_expand. 2362 23632021-06-01 Alex Coplan <alex.coplan@arm.com> 2364 2365 Backported from master: 2366 2021-05-11 Alex Coplan <alex.coplan@arm.com> 2367 2368 PR target/99725 2369 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): 2370 Avoid emitting CFA adjusts on the sp if we have the fp. 2371 23722021-05-25 Alex Coplan <alex.coplan@arm.com> 2373 2374 Backported from master: 2375 2021-05-10 Alex Coplan <alex.coplan@arm.com> 2376 2377 PR target/99960 2378 * config/arm/mve.md (*mve_mov<mode>): Simplify output code. Use 2379 vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores. 2380 23812021-05-20 Alex Coplan <alex.coplan@arm.com> 2382 Christophe Lyon <christophe.lyon@linaro.org> 2383 2384 PR target/99977 2385 * config/arm/arm.c (arm_split_compare_and_swap): Fix up codegen 2386 with negative immediates: ensure we expand cbranchsi4_scratch 2387 correctly and ensure we satisfy its constraints. 2388 * config/arm/sync.md 2389 (@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): Don't 2390 attempt to tie two output operands together with constraints; 2391 collapse two alternatives. 2392 (@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise. 2393 * config/arm/thumb1.md (cbranchsi4_neg_late): New. 2394 23952021-05-19 Jonathan Wakely <jwakely@redhat.com> 2396 2397 Backported from master: 2398 2021-05-19 Jonathan Wakely <jwakely@redhat.com> 2399 2400 * doc/cpp.texi (Common Predefined Macros): Update documentation 2401 for the __GXX_EXPERIMENTAL_CXX0X__ macro. 2402 24032021-05-17 Richard Biener <rguenther@suse.de> 2404 2405 Backported from master: 2406 2021-01-28 Richard Biener <rguenther@suse.de> 2407 2408 PR rtl-optimization/80960 2409 * dse.c (check_mem_read_rtx): Call get_addr on the 2410 offsetted address. 2411 24122021-05-17 Richard Biener <rguenther@suse.de> 2413 2414 Backported from master: 2415 2021-05-12 Richard Biener <rguenther@suse.de> 2416 2417 PR tree-optimization/100566 2418 * tree-ssa-sccvn.c (dominated_by_p_w_unex): Properly handle 2419 allow_back for all edge queries. 2420 24212021-05-13 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2422 2423 Backported from master: 2424 2021-05-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2425 Joe Ramsay <joe.ramsay@arm.com> 2426 2427 PR target/100419 2428 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. 2429 (__arm_vcmpneq): Remove duplicate definition. 2430 (__arm_vstrwq_scatter_offset_p): Likewise. 2431 (__arm_vmaxq_x): Likewise. 2432 (__arm_vmlsdavaq): Likewise. 2433 (__arm_vmlsdavaxq): Likewise. 2434 (__arm_vmlsdavq_p): Likewise. 2435 (__arm_vmlsdavxq_p): Likewise. 2436 (__arm_vrmlaldavhaq): Likewise. 2437 (__arm_vstrbq_p): Likewise. 2438 (__arm_vstrbq_scatter_offset): Likewise. 2439 (__arm_vstrbq_scatter_offset_p): Likewise. 2440 (__arm_vstrdq_scatter_offset): Likewise. 2441 (__arm_vstrdq_scatter_offset_p): Likewise. 2442 (__arm_vstrdq_scatter_shifted_offset): Likewise. 2443 (__arm_vstrdq_scatter_shifted_offset_p): Likewise. 2444 24452021-05-13 Richard Earnshaw <rearnsha@arm.com> 2446 2447 PR target/100563 2448 * config/arm/arm.c (arm_canonicalize_comparison): Correctly 2449 canonicalize DImode inequality comparisons against the 2450 maximum integral value. 2451 24522021-05-12 Martin Sebor <msebor@redhat.com> 2453 2454 PR middle-end/100571 2455 * calls.c (maybe_warn_rdwr_sizes): Clear object size if it can't 2456 be determined. 2457 24582021-05-12 Alex Coplan <alex.coplan@arm.com> 2459 2460 Backported from master: 2461 2021-05-11 Alex Coplan <alex.coplan@arm.com> 2462 2463 PR target/99988 2464 * config/aarch64/aarch64-bti-insert.c (aarch64_bti_j_insn_p): New. 2465 (rest_of_insert_bti): Avoid inserting duplicate bti j insns for 2466 jump table targets. 2467 24682021-05-11 Geng Qi <gengqi@linux.alibaba.com> 2469 2470 Backported from master: 2471 2021-04-30 Geng Qi <gengqi@linux.alibaba.com> 2472 2473 * config/riscv/riscv.opt (march=,mabi=): Negative itself. 2474 24752021-05-10 Segher Boessenkool <segher@kernel.crashing.org> 2476 2477 Backported from master: 2478 2021-04-20 Segher Boessenkool <segher@kernel.crashing.org> 2479 2480 PR target/100108 2481 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Do not consider 2482 OPTION_MASK_ISEL. 2483 24842021-05-06 Roman Zhuykov <zhroma@ispras.ru> 2485 2486 Backported from master: 2487 2021-04-30 Roman Zhuykov <zhroma@ispras.ru> 2488 2489 PR rtl-optimization/100225 2490 PR rtl-optimization/84878 2491 * modulo-sched.c (sms_schedule): Use note_stores to skip loops 2492 where we have an instruction which touches (writes) any hard 2493 register from df->regular_block_artificial_uses set. 2494 Allow not-single-set instruction only right before basic block 2495 tail. 2496 24972021-05-06 Andre Vieira <andre.simoesdiasvieira@arm.com> 2498 2499 Backported from master: 2500 2020-09-15 Andre Vieira <andre.simoesdiasvieira@arm.com> 2501 2502 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Do not 2503 check +D32 for CMSE if -mfloat-abi=soft 2504 25052021-05-06 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 2506 2507 Backported from master: 2508 2020-06-23 Andre Vieira <andre.simoesdiasvieira@arm.com> 2509 2510 PR target/95646 2511 * config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use 2512 'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'. 2513 25142021-05-05 Eric Botcazou <ebotcazou@adacore.com> 2515 2516 PR target/100402 2517 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, 2518 always return the establisher frame for __builtin_frame_address (0). 2519 25202021-05-05 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 2521 2522 Backported from master: 2523 2021-05-05 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 2524 2525 PR rtl-optimization/100263 2526 * postreload.c (move2add_valid_value_p): Ensure register can 2527 change mode. 2528 25292021-05-05 Richard Biener <rguenther@suse.de> 2530 2531 PR tree-optimization/98786 2532 * tree-ssa-phiopt.c (factor_out_conditional_conversion): Avoid 2533 adding new uses of abnormals. 2534 25352021-05-05 Richard Biener <rguenther@suse.de> 2536 2537 Backported from master: 2538 2021-04-27 Richard Biener <rguenther@suse.de> 2539 2540 PR tree-optimization/100278 2541 * tree-ssa-pre.c (compute_avail): Give up when we cannot 2542 adjust TBAA beacuse of mismatching bases. 2543 25442021-05-04 Jakub Jelinek <jakub@redhat.com> 2545 2546 Backported from master: 2547 2021-05-02 Jakub Jelinek <jakub@redhat.com> 2548 2549 PR target/100375 2550 * config/nvptx/nvptx.c (nvptx_sese_pseudo): Use NULL instead of 0 2551 as first argument of pseudo_node_t constructors. 2552 25532021-05-04 Jakub Jelinek <jakub@redhat.com> 2554 2555 Backported from master: 2556 2021-04-29 Jakub Jelinek <jakub@redhat.com> 2557 2558 PR target/100302 2559 * config/aarch64/aarch64.c (aarch64_add_offset_1_temporaries): Use 2560 absu_hwi instead of abs_hwi. 2561 25622021-05-04 Jakub Jelinek <jakub@redhat.com> 2563 2564 Backported from master: 2565 2021-04-27 Jakub Jelinek <jakub@redhat.com> 2566 2567 PR rtl-optimization/100254 2568 * cfgcleanup.c (outgoing_edges_match): Check REG_EH_REGION on 2569 last1 and last2 insns rather than BB_END (bb1) and BB_END (bb2) insns. 2570 25712021-05-04 Jakub Jelinek <jakub@redhat.com> 2572 2573 Backported from master: 2574 2021-04-26 Jakub Jelinek <jakub@redhat.com> 2575 2576 PR debug/100255 2577 * vmsdbgout.c (ASM_OUTPUT_DEBUG_STRING, vmsdbgout_begin_block, 2578 vmsdbgout_end_block, lookup_filename, vmsdbgout_source_line): Remove 2579 register keywords. 2580 25812021-05-04 Alex Coplan <alex.coplan@arm.com> 2582 2583 Backported from master: 2584 2021-04-23 Alex Coplan <alex.coplan@arm.com> 2585 2586 PR rtl-optimization/100230 2587 * early-remat.c (early_remat::sort_candidates): Use delete[] 2588 instead of delete for array allocated with new[]. 2589 25902021-04-30 David Edelsohn <dje.gcc@gmail.com> 2591 2592 Backported from master: 2593 2021-04-27 David Edelsohn <dje.gcc@gmail.com> 2594 2595 * config/rs6000/aix.h (SUBTARGET_DRIVER_SELF_SPECS): New. 2596 * config/rs6000/aix64.opt (m64): New. 2597 (m32): New. 2598 25992021-04-30 Richard Biener <rguenther@suse.de> 2600 2601 PR tree-optimization/96513 2602 * tree-vect-slp.c (struct vdhs_data): New. 2603 (vect_detect_hybrid_slp): New walker. 2604 (vect_detect_hybrid_slp): Rewrite. 2605 26062021-04-29 Richard Earnshaw <rearnsha@arm.com> 2607 2608 Backported from master: 2609 2021-04-28 Richard Earnshaw <rearnsha@arm.com> 2610 2611 PR target/100311 2612 * config/arm/arm.c (arm_hard_regno_mode_ok): Only allow VPR to be 2613 used in HImode. 2614 26152021-04-28 Uros Bizjak <ubizjak@gmail.com> 2616 2617 Backported from master: 2618 2021-04-23 Uroš Bizjak <ubizjak@gmail.com> 2619 2620 PR target/100182 2621 * config/i386/sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2): 2622 Copy operand 3 to operand 4. Use sse_reg_operand 2623 as operand 3 predicate. 2624 (FILD_ATOMIC/FIST_ATOMIC FP load peephole2 with mem blockage): Ditto. 2625 (LDX_ATOMIC/STX_ATOMIC FP load peephole2): Ditto. 2626 (LDX_ATOMIC/LDX_ATOMIC FP load peephole2 with mem blockage): Ditto. 2627 (FILD_ATOMIC/FIST_ATOMIC FP store peephole2): 2628 Copy operand 1 to operand 0. 2629 (FILD_ATOMIC/FIST_ATOMIC FP store peephole2 with mem blockage): Ditto. 2630 (LDX_ATOMIC/STX_ATOMIC FP store peephole2): Ditto. 2631 (LDX_ATOMIC/LDX_ATOMIC FP store peephole2 with mem blockage): Ditto. 2632 26332021-04-26 Alex Coplan <alex.coplan@arm.com> 2634 2635 Backported from master: 2636 2021-04-08 Alex Coplan <alex.coplan@arm.com> 2637 2638 PR target/99647 2639 * config/arm/iterators.md (MVE_vecs): New. 2640 (V_elem): Also handle V2DF. 2641 * config/arm/mve.md (*mve_mov<mode>): Rename to ... 2642 (*mve_vdup<mode>): ... this. Remove second alternative since 2643 vec_duplicate of const_int is not canonical RTL, and we don't 2644 want to match symbol_refs. 2645 (*mve_vec_duplicate<mode>): Delete (pattern is redundant). 2646 26472021-04-26 Richard Biener <rguenther@suse.de> 2648 2649 Backported from master: 2650 2021-04-13 Richard Biener <rguenther@suse.de> 2651 2652 PR tree-optimization/100053 2653 * tree-ssa-sccvn.c (vn_nary_op_get_predicated_value): Do 2654 not use optimistic dominance queries for backedges to validate 2655 predicated values. 2656 (dominated_by_p_w_unex): Add parameter to ignore executable 2657 state on backedges. 2658 (rpo_elim::eliminate_avail): Adjust. 2659 26602021-04-26 Richard Biener <rguenther@suse.de> 2661 2662 Backported from master: 2663 2021-04-07 Richard Biener <rguenther@suse.de> 2664 2665 PR tree-optimization/99954 2666 * tree-loop-distribution.c: Include tree-affine.h. 2667 (generate_memcpy_builtin): Try using tree-affine to prove 2668 non-overlap. 2669 (loop_distribution::classify_builtin_ldst): Always classify 2670 as PKIND_MEMMOVE. 2671 26722021-04-26 Richard Biener <rguenther@suse.de> 2673 2674 Backported from master: 2675 2021-04-06 Richard Biener <rguenther@suse.de> 2676 2677 PR tree-optimization/99880 2678 * tree-vect-loop.c (maybe_set_vectorized_backedge_value): Only 2679 set vectorized defs of relevant PHIs. 2680 26812021-04-24 Richard Sandiford <richard.sandiford@arm.com> 2682 2683 PR rtl-optimization/96796 2684 * lra-constraints.c (in_class_p): Add a default-false 2685 allow_all_reload_class_changes_p parameter. Do not treat 2686 reload moves specially when the parameter is true. 2687 (get_reload_reg): Try to narrow the class of an existing OP_OUT 2688 reload if we're reloading a reload pseudo in a reload instruction. 2689 26902021-04-23 YiFei Zhu <zhuyifei1999@gmail.com> 2691 2692 Backported from master: 2693 2021-04-23 YiFei Zhu <zhuyifei1999@gmail.com> 2694 2695 * config/bpf/bpf.h (ASM_OUTPUT_ALIGNED_BSS): Use .type and .lcomm. 2696 26972021-04-23 YiFei Zhu <zhuyifei1999@gmail.com> 2698 2699 Backported from master: 2700 2021-04-23 YiFei Zhu <zhuyifei1999@gmail.com> 2701 2702 * config/bpf/bpf.h (FUNCTION_BOUNDARY): Set to 64. 2703 27042021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2705 2706 Backported from master: 2707 2021-04-14 Richard Sandiford <richard.sandiford@arm.com> 2708 2709 PR rtl-optimization/99929 2710 * rtl.h (same_vector_encodings_p): New function. 2711 * cse.c (exp_equiv_p): Check that CONST_VECTORs have the same encoding. 2712 * cselib.c (rtx_equal_for_cselib_1): Likewise. 2713 * jump.c (rtx_renumbered_equal_p): Likewise. 2714 * lra-constraints.c (operands_match_p): Likewise. 2715 * reload.c (operands_match_p): Likewise. 2716 * rtl.c (rtx_equal_p_cb, rtx_equal_p): Likewise. 2717 27182021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2719 2720 Backported from master: 2721 2021-03-31 Richard Sandiford <richard.sandiford@arm.com> 2722 2723 PR target/98119 2724 * config/aarch64/aarch64.c 2725 (aarch64_vectorize_preferred_vector_alignment): Query the size 2726 of the provided SVE vector; do not assume that all SVE vectors 2727 have the same size. 2728 27292021-04-23 Bin Cheng <bin.cheng@linux.alibaba.com> 2730 2731 Backported from master: 2732 2021-04-07 Bin Cheng <bin.cheng@linux.alibaba.com> 2733 2734 PR tree-optimization/98736 2735 * tree-loop-distribution.c 2736 * (loop_distribution::bb_top_order_init): 2737 Compute RPO with programing order preserved by calling function 2738 rev_post_order_and_mark_dfs_back_seme. 2739 27402021-04-23 Richard Biener <rguenther@suse.de> 2741 2742 Backported from master: 2743 2020-07-31 Richard Biener <rguenther@suse.de> 2744 2745 * cfganal.h (rev_post_order_and_mark_dfs_back_seme): Adjust 2746 prototype. 2747 * cfganal.c (rpoamdbs_bb_data): New struct with pre BB data. 2748 (tag_header): New helper. 2749 (cmp_edge_dest_pre): Likewise. 2750 (rev_post_order_and_mark_dfs_back_seme): Compute SCCs, 2751 find SCC exits and perform a DFS walk with extra edges to 2752 compute a RPO with adjacent SCC members when requesting an 2753 iteration optimized order and populate the toplevel SCC array. 2754 * tree-ssa-sccvn.c (do_rpo_vn): Remove ad-hoc computation 2755 of max_rpo and fill it in from SCC extent info instead. 2756 27572021-04-23 Richard Biener <rguenther@suse.de> 2758 2759 Backported from master: 2760 2020-07-20 Richard Biener <rguenther@suse.de> 2761 2762 * cfganal.c (rev_post_order_and_mark_dfs_back_seme): Remove 2763 write-only post array. 2764 27652021-04-23 Alex Coplan <alex.coplan@arm.com> 2766 2767 Backported from master: 2768 2021-04-06 Alex Coplan <alex.coplan@arm.com> 2769 2770 PR target/99748 2771 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Also use base 2772 PCS for [su]fix_optab. 2773 27742021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2775 2776 Backported from master: 2777 2021-04-14 Richard Sandiford <richard.sandiford@arm.com> 2778 2779 PR target/99249 2780 * config/aarch64/aarch64.c (aarch64_expand_sve_const_vector_sel): 2781 New function. 2782 (aarch64_expand_sve_const_vector): Use it for nelts_per_pattern==2. 2783 27842021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2785 2786 Backported from master: 2787 2021-03-31 Richard Sandiford <richard.sandiford@arm.com> 2788 2789 PR rtl-optimization/97141 2790 PR rtl-optimization/98726 2791 * emit-rtl.c (valid_for_const_vector_p): Return true for 2792 CONST_POLY_INT_P. 2793 * rtx-vector-builder.h (rtx_vector_builder::step): Return a 2794 poly_wide_int instead of a wide_int. 2795 (rtx_vector_builder::apply_set): Take a poly_wide_int instead 2796 of a wide_int. 2797 * rtx-vector-builder.c (rtx_vector_builder::apply_set): Likewise. 2798 * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): Return 2799 false for CONST_VECTORs that cannot be forced to memory. 2800 * config/aarch64/aarch64-simd.md (mov<mode>): If a CONST_VECTOR 2801 is too complex to force to memory, build it up from individual 2802 elements instead. 2803 28042021-04-23 Richard Biener <rguenther@suse.de> 2805 2806 Backported from master: 2807 2021-01-26 Richard Biener <rguenther@suse.de> 2808 2809 PR middle-end/98726 2810 * tree.h (vector_cst_int_elt): Remove. 2811 * tree.c (vector_cst_int_elt): Use poly_wide_int for computations, 2812 make static. 2813 28142021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2815 2816 Backported from master: 2817 2021-03-30 Richard Sandiford <richard.sandiford@arm.com> 2818 2819 PR target/98136 2820 * config/aarch64/aarch64.md (mov<mode>): Pass multi-instruction 2821 CONST_INTs to aarch64_expand_mov_immediate when called after RA. 2822 28232021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2824 2825 Backported from master: 2826 2021-03-31 Richard Sandiford <richard.sandiford@arm.com> 2827 2828 PR tree-optimization/98268 2829 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Call 2830 recompute_tree_invariant_for_addr_expr after successfully 2831 folding a TARGET_MEM_REF that occurs inside an ADDR_EXPR. 2832 28332021-04-23 Richard Sandiford <richard.sandiford@arm.com> 2834 2835 Backported from master: 2836 2021-03-31 Richard Sandiford <richard.sandiford@arm.com> 2837 2838 PR tree-optimization/99726 2839 * tree-data-ref.c (create_intersect_range_checks_index): Bail 2840 out if there is more than one access function SCEV for the loop 2841 being versioned. 2842 28432021-04-22 Alex Coplan <alex.coplan@arm.com> 2844 2845 PR target/99216 2846 * config/aarch64/aarch64-sve-builtins.cc 2847 (function_builder::add_function): Add placeholder_p argument, use 2848 placeholder decls if this is set. 2849 (function_builder::add_unique_function): Instead of conditionally adding 2850 direct overloads, unconditionally add either a direct overload or a 2851 placeholder. 2852 (function_builder::add_overloaded_function): Set placeholder_p if we're 2853 using C++ overloads. Use the obstack for string storage instead 2854 of relying on the tree nodes. 2855 (function_builder::add_overloaded_functions): Don't return early for 2856 m_direct_overloads: we need to add placeholders. 2857 * config/aarch64/aarch64-sve-builtins.h 2858 (function_builder::add_function): Add placeholder_p argument. 2859 * lto-streamer.h (LTO_minor_version): Bump. 2860 28612021-04-21 Jakub Jelinek <jakub@redhat.com> 2862 2863 Backported from master: 2864 2021-04-21 Jakub Jelinek <jakub@redhat.com> 2865 2866 PR rtl-optimization/100148 2867 * cprop.c (constprop_register): Use next_nondebug_insn instead of 2868 NEXT_INSN. 2869 28702021-04-20 Jakub Jelinek <jakub@redhat.com> 2871 2872 Backported from master: 2873 2021-04-16 Jakub Jelinek <jakub@redhat.com> 2874 2875 PR target/99767 2876 * tree-vect-loop.c (vect_transform_loop): Don't remove just 2877 dead scalar .MASK_LOAD calls, but also dead .COND_* calls - replace 2878 them by their last argument. 2879 28802021-04-20 Jakub Jelinek <jakub@redhat.com> 2881 2882 Backported from master: 2883 2021-04-12 Jakub Jelinek <jakub@redhat.com> 2884 2885 PR rtl-optimization/99905 2886 * combine.c (expand_compound_operation): If pos + len > modewidth, 2887 perform the right shift by pos in inner_mode and then convert to mode, 2888 instead of trying to simplify a shift of rtx with inner_mode by pos 2889 as if it was a shift in mode. 2890 28912021-04-20 Jakub Jelinek <jakub@redhat.com> 2892 2893 Backported from master: 2894 2021-04-12 Jakub Jelinek <jakub@redhat.com> 2895 2896 PR debug/99830 2897 * combine.c (simplify_and_const_int_1): Don't optimize varop 2898 away if it has side-effects. 2899 29002021-04-20 Jakub Jelinek <jakub@redhat.com> 2901 2902 Backported from master: 2903 2021-04-10 Jakub Jelinek <jakub@redhat.com> 2904 2905 PR lto/99849 2906 * expr.c (expand_expr_addr_expr_1): Test is_global_var rather than 2907 just TREE_STATIC on COMPOUND_LITERAL_EXPR_DECLs. 2908 29092021-04-20 Jakub Jelinek <jakub@redhat.com> 2910 2911 Backported from master: 2912 2021-04-10 Jakub Jelinek <jakub@redhat.com> 2913 2914 PR rtl-optimization/98601 2915 * rtlanal.c (rtx_addr_can_trap_p_1): Allow in assert unknown size 2916 not just for BLKmode, but also for VOIDmode. For STRICT_ALIGNMENT 2917 unaligned_mems handle VOIDmode like BLKmode. 2918 29192021-04-20 Jakub Jelinek <jakub@redhat.com> 2920 2921 Backported from master: 2922 2021-04-03 Jakub Jelinek <jakub@redhat.com> 2923 2924 PR rtl-optimization/99863 2925 * dse.c (replace_read): Drop regs_live argument. Instead of 2926 regs_live, use store_insn->fixed_regs_live if non-NULL, 2927 otherwise punt if insns sequence clobbers or sets any hard 2928 registers. 2929 29302021-04-19 Tobias Burnus <tobias@codesourcery.com> 2931 2932 Backported from master: 2933 2020-11-27 Tobias Burnus <tobias@codesourcery.com> 2934 2935 PR c/97880 2936 * omp-expand.c (expand_oacc_collapse_init, expand_oacc_collapse_vars): 2937 Use now passed diff_type. 2938 (expand_oacc_for): Take largest type for diff_type, taking tiling 2939 and collapsing into account. 2940 29412021-04-19 Eric Botcazou <ebotcazou@adacore.com> 2942 2943 * config/i386/winnt.c (i386_pe_seh_cold_init): Properly deal with 2944 frames larger than the SEH maximum frame size. 2945 29462021-04-18 Hafiz Abid Qadeer <abidh@codesourcery.com> 2947 2948 Backported from master: 2949 2021-04-11 Hafiz Abid Qadeer <abidh@codesourcery.com> 2950 2951 PR middle-end/98088 2952 * omp-expand.c (expand_oacc_collapse_init): Update condition in 2953 a gcc_assert. 2954 29552021-04-16 Tamar Christina <tamar.christina@arm.com> 2956 2957 Backported from master: 2958 2021-04-16 Tamar Christina <tamar.christina@arm.com> 2959 2960 PR target/100048 2961 * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>): New. 2962 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_trn): Use new 2963 TRN optab. 2964 * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): New. 2965 29662021-04-08 Richard Biener <rguenther@suse.de> 2967 2968 PR lto/99898 2969 * lto-streamer.h (LTO_minor_version): Bump. 2970 29712021-04-08 Release Manager 2972 2973 * GCC 10.3.0 released. 2974 29752021-04-04 Iain Sandoe <iain@sandoe.co.uk> 2976 2977 Backported from master: 2978 2021-04-03 Iain Sandoe <iain@sandoe.co.uk> 2979 2980 * config/darwin.c (machopic_legitimize_pic_address): Check 2981 that the current pic register is one of the hard reg set 2982 before setting liveness. 2983 29842021-04-02 Jakub Jelinek <jakub@redhat.com> 2985 2986 Backported from master: 2987 2020-10-23 Jakub Jelinek <jakub@redhat.com> 2988 2989 * Makefile.in (PLUGIN_HEADERS): Add gomp-constants.h and $(EXPR_H). 2990 (s-header-vars): Accept not just spaces but also tabs between *_H name 2991 and =. Handle common/config/ headers similarly to config. Don't 2992 throw away everything from first ... to last / on the remaining 2993 string, instead skip just ... to corresponding last / without 2994 intervening spaces and tabs. 2995 (install-plugin): Treat common/config headers like config headers. 2996 * config/i386/t-i386 (TM_H): Add 2997 $(srcdir)/common/config/i386/i386-cpuinfo.h. 2998 29992021-04-01 Jakub Jelinek <jakub@redhat.com> 3000 3001 PR c++/98481 3002 * common.opt (fabi-version): Default to 14. 3003 30042021-04-01 Martin Jambor <mjambor@suse.cz> 3005 3006 Backported from master: 3007 2021-04-01 Martin Jambor <mjambor@suse.cz> 3008 3009 PR tree-optimization/97009 3010 * tree-sra.c (access_or_its_child_written): New function. 3011 (propagate_subaccesses_from_rhs): Use it instead of a simple grp_write 3012 test. 3013 30142021-04-01 Richard Biener <rguenther@suse.de> 3015 3016 PR tree-optimization/99856 3017 * tree-vect-patterns.c (vect_recog_over_widening_pattern): Promote 3018 precision to vector element precision. 3019 30202021-03-31 Jan Hubicka <jh@suse.cz> 3021 3022 Backported from master: 3023 2021-03-31 Jan Hubicka <hubicka@ucw.cz> 3024 3025 PR ipa/98265 3026 * cif-code.def (USES_COMDAT_LOCAL): Make CIF_FINAL_NORMAL. 3027 30282021-03-31 Vladimir N. Makarov <vmakarov@redhat.com> 3029 3030 PR rtl-optimization/96264 3031 * lra-remat.c (reg_overlap_for_remat_p): Check also output insn 3032 hard regs. 3033 30342021-03-31 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> 3035 3036 PR tree-optimization/97849 3037 * tree-if-conv.c (tree_if_conversion): Move ssa_name 3038 replacement code from ifcvt_local_dce to this function 3039 before calling do_rpo_vn. 3040 30412021-03-31 Jakub Jelinek <jakub@redhat.com> 3042 3043 Backported from master: 3044 2021-03-31 Jakub Jelinek <jakub@redhat.com> 3045 Richard Sandiford <richard.sandiford@arm.com> 3046 3047 PR target/99813 3048 * config/aarch64/aarch64.md (*add<mode>3_poly_1): Swap Uai and Uav 3049 constraints on operands[2] and similarly 0 and rk constraints 3050 on operands[1] corresponding to that. 3051 30522021-03-31 Jan Hubicka <hubicka@ucw.cz> 3053 3054 * common/config/i386/i386-common.c (ARRAY_SIZE): Make pta_size signed. 3055 30562021-03-31 Martin Liska <mliska@suse.cz> 3057 3058 Backported from master: 3059 2021-03-24 Martin Liska <mliska@suse.cz> 3060 3061 PR target/99753 3062 * common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one 3063 error. 3064 * config/i386/i386-options.c (ix86_option_override_internal): 3065 Add run-time assert. 3066 30672021-03-31 Jan Hubicka <jh@suse.cz> 3068 3069 Backported from master: 3070 2021-03-18 Jan Hubicka <hubicka@ucw.cz> 3071 3072 * config/i386/x86-tune-costs.h (struct processor_costs): Fix costs of 3073 integer divides1. 3074 30752021-03-31 Jan Hubicka <hubicka@ucw.cz> 3076 3077 * config/i386/x86-tune-costs.h (struct processor_costs): Remove 3078 mask register costs. 3079 30802021-03-31 Jan Hubicka <jh@suse.cz> 3081 3082 Backported from master: 3083 2021-03-15 Jan Hubicka <hubicka@ucw.cz> 3084 3085 * config/i386/i386-options.c (processor_cost_table): Add znver3_cost. 3086 * config/i386/x86-tune-costs.h (znver3_cost): New gobal variable; copy 3087 of znver2_cost. 3088 30892021-03-31 Jan Hubicka <jh@suse.cz> 3090 3091 * common/config/i386/i386-common.c: Add znver3. 3092 * common/config/i386/i386-cpuinfo.h (enum processor_types): Add 3093 AMDFAM19H 3094 (enum processor_subtypes): Add AMDFAM19H_ZNVER3. 3095 (processor_alias_table): Add znver3 and AMDFAM19H entry. 3096 * common/config/i386/i386-cpuinfo.h (processor_types): Add 3097 AMDFAM19H. 3098 (processor_subtypes): AMDFAM19H_ZNVER3. 3099 * config.gcc (i[34567]86-*-linux* | ...): Likewise. 3100 * config/i386/driver-i386.c: (host_detect_local_cpu): Let 3101 -march=native recognize znver3 processors. 3102 * config/i386/i386-c.c (ix86_target_macros_internal): Add 3103 znver3. 3104 * config/i386/i386-options.c (m_znver3): New definition. 3105 (m_ZNVER): Include m_znver3. 3106 (processor_cost_table): Add znver3. 3107 * config/i386/i386.c (ix86_reassociation_width): Likewise. 3108 * config/i386/i386.h (TARGET_znver3): New definition. 3109 (enum processor_type): Add PROCESSOR_ZNVER3. 3110 * config/i386/i386.md (define_attr "cpu"): Add znver3. 3111 * config/i386/x86-tune-sched.c: (ix86_issue_rate): Likewise. 3112 (ix86_adjust_cost): Likewise. 3113 * config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS): 3114 Likewise. 3115 * config/i386/znver1.md: Add new reservations for znver3. 3116 * doc/extend.texi: Add details about znver3. 3117 * doc/invoke.texi: Likewise. 3118 31192021-03-31 H.J. Lu <hjl.tools@gmail.com> 3120 3121 Backported from master: 3122 2020-06-24 H.J. Lu <hjl.tools@gmail.com> 3123 3124 PR target/95842 3125 * common/config/i386/i386-common.c (processor_alias_table): Add 3126 processor model and priority to each entry. 3127 (pta_size): Updated with -6. 3128 (num_arch_names): New. 3129 * common/config/i386/i386-cpuinfo.h: New file. 3130 * config/i386/i386-builtins.c (feature_priority): Removed. 3131 (processor_model): Likewise. 3132 (_arch_names_table): Likewise. 3133 (arch_names_table): Likewise. 3134 (_isa_names_table): Replace P_ZERO with P_NONE. 3135 (get_builtin_code_for_version): Replace P_ZERO with P_NONE. Use 3136 processor_alias_table. 3137 (fold_builtin_cpu): Replace arch_names_table with 3138 processor_alias_table. 3139 * config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h". 3140 (pta): Add model and priority. 3141 (num_arch_names): New. 3142 31432021-03-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3144 3145 PR target/99037 3146 * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Use 3147 aarch64_simd_or_scalar_imm_zero to match zeroes. Remove pattern 3148 matching const_int 0. 3149 (move_lo_quad_internal_be_<mode>): Likewise. 3150 (move_lo_quad_<mode>): Update for the above. 3151 * config/aarch64/iterators.md (VQ_2E): Delete. 3152 31532021-03-30 Jakub Jelinek <jakub@redhat.com> 3154 3155 PR tree-optimization/99777 3156 * fold-const.c (extract_muldiv_1): For conversions, punt on casts from 3157 types other than scalar integral types. 3158 31592021-03-30 Jakub Jelinek <jakub@redhat.com> 3160 3161 PR debug/99334 3162 * dwarf2out.h (struct dw_fde_node): Add rule18 member. 3163 * dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp) 3164 assignment with drap_reg active, queue reg save for hfp with offset 0 3165 and flush queued reg saves. When handling a push with rule18, 3166 defer queueing reg save for hfp and just assert the offset is 0. 3167 (scan_trace): Assert that fde->rule18 is false. 3168 31692021-03-30 Jakub Jelinek <jakub@redhat.com> 3170 3171 PR debug/99388 3172 * dwarf2out.c (insert_float): Change return type from void to 3173 unsigned, handle GET_MODE_SIZE (mode) == 2 and return element size. 3174 (mem_loc_descriptor, loc_descriptor, add_const_value_attribute): 3175 Adjust callers. 3176 31772021-03-30 Richard Biener <rguenther@suse.de> 3178 3179 PR tree-optimization/99824 3180 * stor-layout.c (set_min_and_max_values_for_integral_type): 3181 Assert the precision is within the bounds of 3182 WIDE_INT_MAX_PRECISION. 3183 * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Use 3184 the outermost component ref only to lower the access size 3185 and initialize that from the access type. 3186 31872021-03-29 Alex Coplan <alex.coplan@arm.com> 3188 3189 Backported from master: 3190 2021-03-22 Alex Coplan <alex.coplan@arm.com> 3191 3192 PR target/97252 3193 * config/arm/arm-protos.h (neon_make_constant): Add generate 3194 argument to guard emitting insns, default to true. 3195 * config/arm/arm.c (arm_legitimate_constant_p_1): Reject 3196 CONST_VECTORs which neon_make_constant can't handle. 3197 (neon_vdup_constant): Add generate argument, avoid emitting 3198 insns if it's not set. 3199 (neon_make_constant): Plumb new generate argument through. 3200 * config/arm/constraints.md (Ui): New. Use it... 3201 * config/arm/mve.md (*mve_mov<mode>): ... here. 3202 * config/arm/vec-common.md (movv8hf): Use neon_make_constant to 3203 synthesize constants. 3204 32052021-03-28 David Edelsohn <dje.gcc@gmail.com> 3206 3207 Backported from master: 3208 2021-03-28 David Edelsohn <dje.gcc@gmail.com> 3209 3210 * config/rs6000/rs6000.c (rs6000_output_dwarf_dtprel): Do not add 3211 XCOFF TLS reloc decorations. 3212 32132021-03-26 Iain Buclaw <ibuclaw@gdcproject.org> 3214 3215 Backported from master: 3216 2021-03-26 Iain Buclaw <ibuclaw@gdcproject.org> 3217 3218 PR ipa/99466 3219 * tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak 3220 TLS declarations as public. 3221 32222021-03-25 Stam Markianos-Wright <stam.markianos-wright@arm.com> 3223 3224 PR tree-optimization/96974 3225 * tree-vect-stmts.c (vect_get_vector_types_for_stmt): Replace assert 3226 with graceful exit. 3227 32282021-03-25 Xionghu Luo <luoxhu@linux.ibm.com> 3229 3230 Backported from master: 3231 2021-03-25 Xionghu Luo <luoxhu@linux.ibm.com> 3232 3233 PR target/97329 3234 * config/rs6000/rs6000.c (power8_costs): Change l2 cache 3235 from 256 to 512. 3236 32372021-03-24 Iain Sandoe <iain@sandoe.co.uk> 3238 3239 * config/darwin.c (output_objc_section_asm_op): Avoid extra 3240 objective-c section switches unless the linker needs them. 3241 * config/darwin.c (darwin_objc2_section): Allow for 3242 values > 1 to represent the next runtime. 3243 (darwin_objc1_section): Likewise. 3244 * config/darwin.c (darwin_globalize_label): Add protocol 3245 meta-data labels to the set that are global. Make a subset of 3246 metadate symbols global. 3247 (darwin_label_is_anonymous_local_objc_name): Make a subset of 3248 metadata symbols linker-visible. 3249 (darwin_override_options): Track more target OS versions, make 3250 the next_runtime version track this (unless it's set to 0 for 3251 GNU runtime). 3252 * config/darwin.h (NEXT_OBJC_RUNTIME): Set the default 3253 next runtime value to be 10.5.8. 3254 32552021-03-24 Jakub Jelinek <jakub@redhat.com> 3256 3257 PR target/99540 3258 * config/aarch64/aarch64.c (aarch64_add_offset): Tell 3259 expand_mult to perform an unsigned rather than a signed 3260 multiplication. 3261 32622021-03-24 Richard Biener <rguenther@suse.de> 3263 3264 Backported from master: 3265 2021-03-15 Richard Biener <rguenther@suse.de> 3266 3267 PR tree-optimization/98834 3268 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle missing 3269 subsetting by truncating the access size. 3270 32712021-03-24 Richard Biener <rguenther@suse.de> 3272 3273 Backported from master: 3274 2021-02-08 Richard Biener <rguenther@suse.de> 3275 3276 PR lto/96591 3277 * tree.c (walk_tree_1): Walk VECTOR_CST elements. 3278 32792021-03-24 Richard Biener <rguenther@suse.de> 3280 3281 Backported from master: 3282 2021-03-22 Richard Biener <rguenther@suse.de> 3283 3284 PR tree-optimization/99694 3285 * tree-ssa-sccvn.c (visit_phi): Ignore edges with the 3286 PHI result. 3287 32882021-03-23 H.J. Lu <hjl.tools@gmail.com> 3289 3290 Backported from master: 3291 2021-03-23 H.J. Lu <hjl.tools@gmail.com> 3292 3293 PR target/99704 3294 * config/i386/cpuid.h (__cpuid): Add __volatile__. 3295 (__cpuid_count): Likewise. 3296 32972021-03-22 Iain Sandoe <iain@sandoe.co.uk> 3298 3299 Backported from master: 3300 2020-10-10 Iain Sandoe <iain@sandoe.co.uk> 3301 3302 * config/darwin-sections.def (objc2_data_section): New. 3303 (objc2_ivar_section): New. 3304 * config/darwin.c (darwin_objc2_section): Act on Protocol and 3305 ivar refs. 3306 33072021-03-22 Iain Sandoe <iain@sandoe.co.uk> 3308 3309 Backported from master: 3310 2020-10-10 Iain Sandoe <iain@sandoe.co.uk> 3311 3312 * config/darwin-sections.def (objc2_class_names_section, 3313 objc2_method_names_section, objc2_method_types_section): New 3314 * config/darwin.c (output_objc_section_asm_op): Output new 3315 sections. (darwin_objc2_section): Select new sections where 3316 used. 3317 33182021-03-22 David Edelsohn <dje.gcc@gmail.com> 3319 3320 Backported from master: 3321 2021-01-30 David Edelsohn <dje.gcc@gmail.com> 3322 3323 * config/rs6000/rs6000.opt (mabi=vec-extabi): New. 3324 (mabi=vec-default): New. 3325 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define 3326 __EXTABI__ for AIX Vector extended ABI. 3327 * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print AIX Vector 3328 extabi info. 3329 (conditional_register_usage): If AIX vec_extabi enabled, vs20-vs31 3330 are non-volatile. 3331 * doc/invoke.texi (PowerPC mabi): Add AIX vec-extabi and vec-default. 3332 33332021-03-22 Kito Cheng <kito.cheng@sifive.com> 3334 3335 Backported from master: 3336 2021-03-22 Kito Cheng <kito.cheng@sifive.com> 3337 3338 PR target/99702 3339 * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value 3340 after type checking. 3341 33422021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3343 3344 Backported from master: 3345 2021-03-01 Iain Sandoe <iain@sandoe.co.uk> 3346 3347 PR target/44107 3348 PR target/48097 3349 * config/darwin-protos.h (darwin_should_restore_cfa_state): New. 3350 * config/darwin.c (darwin_should_restore_cfa_state): New. 3351 * config/darwin.h (TARGET_ASM_SHOULD_RESTORE_CFA_STATE): New. 3352 * doc/tm.texi: Regenerated. 3353 * doc/tm.texi.in: Document TARGET_ASM_SHOULD_RESTORE_CFA_STATE. 3354 * dwarf2cfi.c (connect_traces): If the target requests, restore 3355 the CFA expression after a DW_CFA_restore. 3356 * target.def (TARGET_ASM_SHOULD_RESTORE_CFA_STATE): New hook. 3357 33582021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3359 3360 * config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move the spec 3361 for the Darwin10 unwinder stub from here .. 3362 * config/darwin.h (LINK_COMMAND_SPEC_A): ... to here. 3363 here... 3364 * config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move from here.. 3365 * config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): ... to here. 3366 * config/darwin9.h (STACK_CHECK_STATIC_BUILTIN): Move from here.. 3367 * config/darwin.h (STACK_CHECK_STATIC_BUILTIN): .. to here. 3368 * config.gcc: Compute default version information 3369 from the configured target. Likewise defaults for 3370 ld64. Delete reference to the now removed darwin8.h 3371 * config/darwin10.h: Removed. 3372 * config/darwin12.h: Removed. 3373 * config/darwin9.h: Removed. 3374 * config/rs6000/darwin8.h: Removed. 3375 33762021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3377 3378 Backported from master: 3379 2021-01-02 Iain Sandoe <iain@sandoe.co.uk> 3380 3381 * config/darwin.h (DSYMUTIL_SPEC): Default to DWARF 3382 (ASM_DEBUG_SPEC):Only define if the assembler supports 3383 stabs. 3384 (PREFERRED_DEBUGGING_TYPE): Default to DWARF. 3385 (DARWIN_PREFER_DWARF): Define. 3386 * config/darwin9.h (PREFERRED_DEBUGGING_TYPE): Remove. 3387 (DARWIN_PREFER_DWARF): Likewise 3388 (DSYMUTIL_SPEC): Likewise. 3389 (COLLECT_RUN_DSYMUTIL): Likewise. 3390 (ASM_DEBUG_SPEC): Likewise. 3391 (ASM_DEBUG_OPTION_SPEC): Likewise. 3392 33932021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3394 3395 Backported from master: 3396 2020-08-03 Iain Sandoe <iain@sandoe.co.uk> 3397 3398 * config/darwin.h (ASM_DECLARE_FUNCTION_NAME): UNDEF before 3399 use. 3400 (DEF_MIN_OSX_VERSION): Only define if there's no existing 3401 def. 3402 34032021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3404 3405 Backported from master: 3406 2020-11-22 Iain Sandoe <iain@sandoe.co.uk> 3407 3408 * config/darwin-c.c (struct f_align_stack): Rename 3409 to type from align_stack to f_align_stack. 3410 (push_field_alignment): Likewise. 3411 (pop_field_alignment): Likewise. 3412 34132021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3414 3415 Backported from master: 3416 2020-10-10 Iain Sandoe <iain@sandoe.co.uk> 3417 3418 * config/darwin.c (darwin_emit_local_bss): Amend section names to 3419 match system tools. (darwin_output_aligned_bss): Likewise. 3420 34212021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3422 3423 Backported from master: 3424 2020-09-07 Iain Sandoe <iain@sandoe.co.uk> 3425 3426 * config/darwin.c (darwin_libc_has_function): Report sincos 3427 available from 10.9. 3428 34292021-03-21 Iain Sandoe <iain@sandoe.co.uk> 3430 3431 Backported from master: 3432 2020-08-03 Iain Sandoe <iain@sandoe.co.uk> 3433 3434 * config/darwin.c (IN_TARGET_CODE): Remove. 3435 (darwin_mergeable_constant_section): Handle poly-int machine modes. 3436 (machopic_select_rtx_section): Likewise. 3437 34382021-03-20 John David Anglin <danglin@gcc.gnu.org> 3439 3440 * config/pa/pa.c (import_milli): Use memcpy instead of strncpy. 3441 34422021-03-19 Jakub Jelinek <jakub@redhat.com> 3443 3444 Backported from master: 3445 2021-03-16 Jakub Jelinek <jakub@redhat.com> 3446 3447 PR target/99563 3448 * config/i386/i386.h (struct machine_function): Add 3449 has_explicit_vzeroupper bitfield. 3450 * config/i386/i386-expand.c (ix86_expand_builtin): Set 3451 cfun->machine->has_explicit_vzeroupper when expanding 3452 IX86_BUILTIN_VZEROUPPER. 3453 * config/i386/i386-features.c (rest_of_handle_insert_vzeroupper): 3454 Do the mode switching only when TARGET_VZEROUPPER, expensive 3455 optimizations turned on and not optimizing for size. 3456 (pass_insert_vzeroupper::gate): Enable even when 3457 cfun->machine->has_explicit_vzeroupper is set. 3458 34592021-03-19 Jakub Jelinek <jakub@redhat.com> 3460 3461 Backported from master: 3462 2021-03-16 Jakub Jelinek <jakub@redhat.com> 3463 3464 PR target/99542 3465 * config/aarch64/aarch64.c 3466 (aarch64_simd_clone_compute_vecsize_and_simdlen): If not a function 3467 definition, walk TYPE_ARG_TYPES list if non-NULL for argument types 3468 instead of DECL_ARGUMENTS. Ignore types for uniform arguments. 3469 34702021-03-19 Jakub Jelinek <jakub@redhat.com> 3471 3472 Backported from master: 3473 2021-03-11 Jakub Jelinek <jakub@redhat.com> 3474 3475 PR ipa/99517 3476 * ipa-icf-gimple.c (func_checker::compare_gimple_call): For internal 3477 function calls with lhs fail if the lhs don't have compatible types. 3478 34792021-03-19 Jakub Jelinek <jakub@redhat.com> 3480 3481 Backported from master: 3482 2021-03-04 Jakub Jelinek <jakub@redhat.com> 3483 3484 PR middle-end/93235 3485 * expmed.c (store_bit_field_using_insv): Return false of xop0 is a 3486 SUBREG and a SUBREG to op_mode can't be created. 3487 34882021-03-19 Jakub Jelinek <jakub@redhat.com> 3489 3490 Backported from master: 3491 2021-03-03 Jakub Jelinek <jakub@redhat.com> 3492 3493 PR target/99085 3494 * cfgrtl.c (fixup_partitions): When changing some bbs from hot to cold 3495 partitions, if in non-layout mode after reorder_blocks also move 3496 affected blocks to ensure a single partition transition. 3497 34982021-03-19 Jakub Jelinek <jakub@redhat.com> 3499 3500 Backported from master: 3501 2021-02-24 Jakub Jelinek <jakub@redhat.com> 3502 3503 PR tree-optimization/99225 3504 * fold-const.c (fold_binary_loc) <case NE_EXPR>: In (x & (1 << y)) != 0 3505 to ((x >> y) & 1) != 0 simplifications use build_one_cst instead of 3506 build_int_cst (..., 1). Formatting fixes. 3507 35082021-03-19 Jakub Jelinek <jakub@redhat.com> 3509 3510 Backported from master: 3511 2021-02-23 Jakub Jelinek <jakub@redhat.com> 3512 3513 PR tree-optimization/99204 3514 * fold-const.c (fold_read_from_constant_string): Check that 3515 tree_fits_uhwi_p (index) rather than just that index is INTEGER_CST. 3516 35172021-03-19 Jakub Jelinek <jakub@redhat.com> 3518 3519 Backported from master: 3520 2021-02-19 Jakub Jelinek <jakub@redhat.com> 3521 3522 PR ipa/99034 3523 * tree-cfg.c (gimple_merge_blocks): If bb a starts with eh landing 3524 pad or non-local label, put FORCED_LABELs from bb b after that label 3525 rather than before it. 3526 35272021-03-19 Jakub Jelinek <jakub@redhat.com> 3528 3529 Backported from master: 3530 2021-02-15 Jakub Jelinek <jakub@redhat.com> 3531 3532 PR tree-optimization/99079 3533 * match.pd (A % (pow2pcst << N) -> A & ((pow2pcst << N) - 1)): Remove 3534 useless tree_nop_conversion_p (type, TREE_TYPE (@3)) check. Instead 3535 require both type and TREE_TYPE (@1) to be integral types and either 3536 type having smaller or equal precision, or TREE_TYPE (@1) being 3537 unsigned type, or type being signed type. If TREE_TYPE (@1) 3538 doesn't have wrapping overflow, perform the subtraction of one in 3539 unsigned type. 3540 35412021-03-19 Jakub Jelinek <jakub@redhat.com> 3542 3543 Backported from master: 3544 2021-02-10 Jakub Jelinek <jakub@redhat.com> 3545 3546 PR c++/99035 3547 * varasm.c (declare_weak): For -fsyntax-only, allow even 3548 TREE_ASM_WRITTEN function decls. 3549 35502021-03-19 Jakub Jelinek <jakub@redhat.com> 3551 3552 Backported from master: 3553 2021-02-10 Jakub Jelinek <jakub@redhat.com> 3554 3555 PR middle-end/99007 3556 * gimplify.c (gimplify_scan_omp_clauses): For MEM_REF on reductions, 3557 temporarily disable gimplify_ctxp->into_ssa around gimplify_expr 3558 calls. 3559 35602021-03-19 Jakub Jelinek <jakub@redhat.com> 3561 3562 Backported from master: 3563 2021-02-03 Jakub Jelinek <jakub@redhat.com> 3564 3565 PR middle-end/97487 3566 * ifcvt.c (noce_can_force_operand): New function. 3567 (noce_emit_move_insn): Use it. 3568 (noce_try_sign_mask): Likewise. Formatting fix. 3569 35702021-03-19 Jakub Jelinek <jakub@redhat.com> 3571 3572 Backported from master: 3573 2021-02-03 Jakub Jelinek <jakub@redhat.com> 3574 3575 PR middle-end/97971 3576 * lra-constraints.c (process_alt_operands): For inline asm, don't call 3577 fatal_insn, but instead return false. 3578 35792021-03-19 Jakub Jelinek <jakub@redhat.com> 3580 3581 Backported from master: 3582 2021-02-03 Jakub Jelinek <jakub@redhat.com> 3583 3584 PR tree-optimization/98287 3585 * config/i386/mmx.md (<insn><mode>3): For shifts don't enable expander 3586 for V1DImode. 3587 35882021-03-19 Eric Botcazou <ebotcazou@adacore.com> 3589 3590 PR middle-end/99641 3591 * fold-const.c (native_encode_initializer) <CONSTRUCTOR>: For an 3592 array type, do the computation of the current position in sizetype. 3593 35942021-03-18 Sinan Lin <sinan@isrc.iscas.ac.cn> 3595 3596 Backported from master: 3597 2021-03-18 Sinan Lin <sinan@isrc.iscas.ac.cn> 3598 Kito Cheng <kito.cheng@sifive.com> 3599 3600 * config/riscv/riscv.c (riscv_block_move_straight): Change type 3601 to unsigned HOST_WIDE_INT for parameter and local variable with 3602 HOST_WIDE_INT type. 3603 (riscv_adjust_block_mem): Ditto. 3604 (riscv_block_move_loop): Ditto. 3605 (riscv_expand_block_move): Ditto. 3606 36072021-03-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3608 3609 Backported from master: 3610 2021-03-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3611 3612 * config/aarch64/aarch64.c (aarch64_adjust_generic_arch_tuning): Define. 3613 (aarch64_override_options_internal): Use it. 3614 (generic_tunings): Add AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS to 3615 tune_flags. 3616 36172021-03-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3618 3619 Backported from master: 3620 2021-03-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3621 3622 * config/aarch64/aarch64-builtins.c (aarch64_expand_rng_builtin): Use EQ 3623 to compare against CC_REG rather than NE. 3624 36252021-03-17 Peter Bergner <bergner@linux.ibm.com> 3626 3627 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Handle 3628 disassembling a vector pair vector by vector in little-endian mode. 3629 36302021-03-16 Martin Jambor <mjambor@suse.cz> 3631 3632 Backported from master: 3633 2021-03-05 Martin Jambor <mjambor@suse.cz> 3634 3635 PR ipa/98078 3636 * cgraph.c (cgraph_edge::set_call_stmt): Do not update all 3637 corresponding speculative edges if we are about to resolve 3638 sepculation. Make edge direct (and so resolve speculations) before 3639 removing it from call_site_hash. 3640 (cgraph_edge::make_direct): Relax the initial assert to allow calling 3641 the function on speculative direct edges. 3642 36432021-03-16 Richard Biener <rguenther@suse.de> 3644 3645 Backported from master: 3646 2021-02-24 Richard Biener <rguenther@suse.de> 3647 3648 PR c/99224 3649 * builtins.c (fold_builtin_next_arg): Avoid NULL arg. 3650 36512021-03-16 Richard Biener <rguenther@suse.de> 3652 3653 Backported from master: 3654 2021-02-25 Richard Biener <rguenther@suse.de> 3655 3656 PR tree-optimization/99253 3657 * tree-vect-loop.c (check_reduction_path): First compute 3658 code, then verify out-of-loop uses. 3659 36602021-03-15 Tobias Burnus <tobias@codesourcery.com> 3661 3662 Backported from master: 3663 2021-03-08 Tobias Burnus <tobias@codesourcery.com> 3664 3665 PR fortran/97927 3666 * tree-nested.c (convert_local_reference_stmt): Avoid calling 3667 lookup_field_for_decl for Fortran module (= namespace context). 3668 36692021-03-15 Andre Vieira <andre.simoesdiasvieira@arm.com> 3670 3671 Backported from master: 3672 2021-02-22 Andre Vieira <andre.simoesdiasvieira@arm.com> 3673 3674 PR rtl-optimization/98791 3675 * ira-conflicts.c (process_regs_for_copy): Don't create allocno copies 3676 for unordered modes. 3677 36782021-03-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3679 3680 * config/aarch64/aarch64.c (neoversen2_tunings): Set 3681 AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune_flags. 3682 36832021-03-11 Alex Coplan <alex.coplan@arm.com> 3684 3685 Backported from master: 3686 2021-03-04 Alex Coplan <alex.coplan@arm.com> 3687 3688 PR target/99381 3689 * config/aarch64/aarch64-sve-builtins.cc 3690 (function_resolver::require_vector_type): Handle error_mark_node. 3691 36922021-03-10 Peter Bergner <bergner@linux.ibm.com> 3693 3694 Backported from master: 3695 2021-03-08 Peter Bergner <bergner@linux.ibm.com> 3696 3697 PR target/98959 3698 * config/rs6000/rs6000.c (rs6000_emit_le_vsx_permute): Add an assert 3699 to ensure we do not have an Altivec style address. 3700 * config/rs6000/vsx.md (*vsx_le_perm_load_<mode>): Disable if passed 3701 an Altivec style address. 3702 (*vsx_le_perm_store_<mode>): Likewise. 3703 (splitters after *vsx_le_perm_store_<mode>): Likewise. 3704 (vsx_load_<mode>): Disable special expander if passed an Altivec 3705 style address. 3706 (vsx_store_<mode>): Likewise. 3707 37082021-03-10 Peter Bergner <bergner@linux.ibm.com> 3709 3710 Backported from master: 3711 2021-02-26 Peter Bergner <bergner@linux.ibm.com> 3712 3713 PR target/99279 3714 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Replace assert 3715 with an "if" test. 3716 37172021-03-10 Peter Bergner <bergner@linux.ibm.com> 3718 3719 Backported from master: 3720 2021-02-23 Peter Bergner <bergner@linux.ibm.com> 3721 3722 * config/rs6000/mma.md (mma_assemble_pair): Rename from this... 3723 (vsx_assemble_pair): ...to this. 3724 * config/rs6000/rs6000-builtin.def (BU_MMA_V2, BU_MMA_V3, 3725 BU_COMPAT): New macros. 3726 (mma_assemble_pair): Rename from this... 3727 (vsx_assemble_pair): ...to this. 3728 (mma_disassemble_pair): Rename from this... 3729 (vsx_disassemble_pair): ...to this. 3730 (mma_assemble_pair): New compatibility built-in. 3731 (mma_disassemble_pair): Likewise. 3732 * config/rs6000/rs6000-call.c (struct builtin_compatibility): New. 3733 (RS6000_BUILTIN_COMPAT): Define. 3734 (bdesc_compat): New. 3735 (rs6000_gimple_fold_mma_builtin): Use VSX_BUILTIN_ASSEMBLE_PAIR. 3736 (rs6000_init_builtins): Register compatibility built-ins. 3737 (mma_init_builtins): Use VSX_BUILTIN_ASSEMBLE_PAIR, 3738 and VSX_BUILTIN_DISASSEMBLE_PAIR. 3739 * doc/extend.texi (__builtin_mma_assemble_pair): Rename from this... 3740 (__builtin_vsx_assemble_pair): ...to this. 3741 (__builtin_mma_disassemble_pair): Rename from this... 3742 (__builtin_vsx_disassemble_pair): ...to this. 3743 37442021-03-10 Peter Bergner <bergner@linux.ibm.com> 3745 3746 Backported from master: 3747 2021-02-11 Peter Bergner <bergner@linux.ibm.com> 3748 3749 PR target/99041 3750 * config/rs6000/predicates.md (mma_assemble_input_operand): Restrict 3751 memory addresses that are legal for quad word accesses. 3752 37532021-03-09 Eric Botcazou <ebotcazou@adacore.com> 3754 3755 PR c++/90448 3756 * calls.c (initialize_argument_information): When the argument 3757 is passed by reference, do not make a copy in a thunk only if 3758 the argument is already in memory. Remove redundant test for 3759 the case of callee copy. 3760 37612021-03-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3762 3763 * config/aarch64/aarch64-tuning-flags.def (cse_sve_vl_constants): 3764 Define. 3765 * config/aarch64/aarch64.md (add<mode>3): Force CONST_POLY_INT immediates 3766 into a register when the above is enabled. 3767 * config/aarch64/aarch64.c (neoversev1_tunings): 3768 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. 3769 (aarch64_rtx_costs): Use AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. 3770 37712021-03-04 Jason Merrill <jason@redhat.com> 3772 3773 PR c++/96078 3774 * cgraphunit.c (process_function_and_variable_attributes): Don't 3775 warn about flatten on an alias if the target also has it. 3776 * cgraph.h (symtab_node::get_alias_target_tree): New. 3777 37782021-03-03 Eric Botcazou <ebotcazou@adacore.com> 3779 3780 PR target/99234 3781 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, 3782 point back the hard frame pointer to its default location when the 3783 frame is larger than SEH_MAX_FRAME_SIZE. 3784 37852021-03-03 Richard Biener <rguenther@suse.de> 3786 3787 Backported from master: 3788 2021-01-20 Richard Biener <rguenther@suse.de> 3789 3790 PR tree-optimization/98758 3791 * tree-data-ref.c (int_divides_p): Use lambda_int arguments. 3792 (lambda_matrix_right_hermite): Avoid undefinedness with 3793 signed integer abs and multiplication. 3794 (analyze_subscript_affine_affine): Use lambda_int. 3795 37962021-03-03 Richard Biener <rguenther@suse.de> 3797 3798 Backported from master: 3799 2021-01-13 Richard Biener <rguenther@suse.de> 3800 3801 PR tree-optimization/98640 3802 * tree-ssa-sccvn.c (visit_nary_op): Do not try to 3803 handle plus or minus from a truncated operand to be 3804 sign-extended. 3805 38062021-03-03 Richard Biener <rguenther@suse.de> 3807 3808 Backported from master: 3809 2021-01-11 Richard Biener <rguenther@suse.de> 3810 3811 PR tree-optimization/98526 3812 * tree-vect-loop.c (vect_model_reduction_cost): Remove costing 3813 of the actual reduction op for the regular case. 3814 (vectorizable_reduction): Cost the stmts 3815 vect_transform_reduction produces here. 3816 38172021-03-03 Richard Biener <rguenther@suse.de> 3818 3819 PR tree-optimization/97897 3820 * tree-complex.c (complex_propagate::visit_stmt): Make sure 3821 abnormally used SSA names are VARYING. 3822 (complex_propagate::visit_phi): Likewise. 3823 38242021-03-03 Tom de Vries <tdevries@suse.de> 3825 3826 Backported from master: 3827 2021-02-05 Tom de Vries <tdevries@suse.de> 3828 3829 PR debug/98656 3830 * tree-switch-conversion.c (jump_table_cluster::emit): Add loc 3831 argument. 3832 (bit_test_cluster::emit): Reuse location_t for newly created 3833 gswitch statement. 3834 (switch_decision_tree::try_switch_expansion): Preserve 3835 location_t. 3836 * tree-switch-conversion.h: Change function signatures. 3837 38382021-03-02 Jan Hubicka <jh@suse.cz> 3839 3840 Backported from master: 3841 2021-03-01 Jan Hubicka <jh@suse.cz> 3842 3843 PR ipa/98338 3844 * ipa-fnsummary.c (compute_fn_summary): Fix sanity check. 3845 38462021-03-02 Kito Cheng <kito.cheng@sifive.com> 3847 3848 Backported from master: 3849 2020-07-09 Kito Cheng <kito.cheng@sifive.com> 3850 3851 * config/riscv/riscv.md (get_thread_pointer<mode>): New. 3852 (TP_REGNUM): Ditto. 3853 * doc/extend.texi (Target Builtins): Add RISC-V built-in section. 3854 Document __builtin_thread_pointer. 3855 38562021-03-01 Richard Earnshaw <rearnsha@arm.com> 3857 3858 PR target/99271 3859 * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): New pattern. 3860 (nonsecure_call_value_reg_thumb2_fpcxt): Likewise. 3861 (nonsecure_call_reg_thumb2): Restrict to using r4 for the callee 3862 address and disable when the FPCXT is not available. 3863 (nonsecure_call_value_reg_thumb2): Likewise. 3864 38652021-03-01 Eric Botcazou <ebotcazou@adacore.com> 3866 3867 PR target/99234 3868 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, 3869 point the hard frame pointer to the SSE register save area instead 3870 of the general register save area. Perform only minimal adjustment 3871 for small frames if it is initially not correctly aligned. 3872 (ix86_expand_prologue): Remove early saves for a SEH target. 3873 * config/i386/winnt.c (struct seh_frame_state): Document constraint. 3874 38752021-02-23 Qian Jianhua <qianjh@cn.fujitsu.com> 3876 3877 * config/aarch64/aarch64-cost-tables.h (a64fx_extra_costs): New. 3878 * config/aarch64/aarch64.c (a64fx_addrcost_table): New. 3879 (a64fx_regmove_cost, a64fx_vector_cost): New. 3880 (a64fx_tunings): Use the new added cost tables. 3881 38822021-02-22 John David Anglin <danglin@gcc.gnu.org> 3883 3884 PR target/85074 3885 * config/pa/pa.c (TARGET_ASM_CAN_OUTPUT_MI_THUNK): Define as 3886 hook_bool_const_tree_hwi_hwi_const_tree_true. 3887 (pa_asm_output_mi_thunk): Add support for nonzero vcall_offset. 3888 38892021-02-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 3890 3891 * config/aarch64/aarch64-tuning-flags.def (prefer_advsimd_autovec): Define. 3892 * config/aarch64/aarch64.c (neoversev1_tunings): Use it. 3893 (aarch64_override_options_internal): Adjust aarch64_autovec_preference 3894 param when prefer_advsimd_autovec is enabled. 3895 38962021-02-15 Eric Botcazou <ebotcazou@adacore.com> 3897 3898 * df-core.c (df_worklist_dataflow_doublequeue): Use proper cast. 3899 39002021-02-11 Eric Botcazou <ebotcazou@adacore.com> 3901 3902 * config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to 3903 the cold section, emit a nop before the directive if the previous 3904 active instruction can throw. 3905 39062021-02-09 Eric Botcazou <ebotcazou@adacore.com> 3907 3908 PR rtl-optimization/96015 3909 * reorg.c (skip_consecutive_labels): Minor comment tweaks. 3910 (relax_delay_slots): When deleting a jump to the next active 3911 instruction over a barrier, first delete the barrier if the 3912 jump is the only way to reach the target label. 3913 39142021-02-04 Vladimir N. Makarov <vmakarov@redhat.com> 3915 3916 PR target/97701 3917 * lra-constraints.c (in_class_p): Don't narrow class only for REG 3918 or MEM. 3919 39202021-02-03 Richard Biener <rguenther@suse.de> 3921 Jakub Jelinek <jakub@redhat.com> 3922 3923 PR rtl-optimization/98863 3924 * config/i386/i386-features.c (remove_partial_avx_dependency): 3925 Do not perform DF analysis. 3926 (pass_data_remove_partial_avx_dependency): Remove 3927 TODO_df_finish. 3928 39292021-02-03 Richard Biener <rguenther@suse.de> 3930 3931 Backported from master: 3932 2021-02-01 Richard Biener <rguenther@suse.de> 3933 3934 PR rtl-optimization/98863 3935 * config/i386/i386-features.c (convert_scalars_to_vector): 3936 Set DF_RD_PRUNE_DEAD_DEFS. 3937 39382021-02-03 Richard Biener <rguenther@suse.de> 3939 3940 Backported from master: 3941 2021-01-29 Richard Biener <rguenther@suse.de> 3942 3943 PR rtl-optimization/98144 3944 * df.h (df_mir_bb_info): Add con_visited member. 3945 * df-problems.c (df_mir_alloc): Initialize con_visited, 3946 do not fully populate IN and OUT. 3947 (df_mir_reset): Likewise. 3948 (df_mir_confluence_0): Set con_visited. 3949 (df_mir_confluence_n): Properly handle implicitely 3950 fully populated IN and OUT as designated by con_visited 3951 and update con_visited accordingly. 3952 39532021-02-01 Richard Biener <rguenther@suse.de> 3954 3955 Backported from master: 3956 2021-01-29 Richard Biener <rguenther@suse.de> 3957 3958 PR rtl-optimization/98863 3959 * gcse.c (gcse_or_cprop_is_too_expensive): Use unsigned 3960 HOST_WIDE_INT for the memory estimate. 3961 39622021-02-01 Kito Cheng <kito.cheng@sifive.com> 3963 3964 Backported from master: 3965 2020-11-06 Kito Cheng <kito.cheng@sifive.com> 3966 3967 PR target/96307 3968 * toplev.c (process_options): Remove param_asan_stack checking for kasan 3969 option checking. 3970 39712021-01-31 Eric Botcazou <ebotcazou@adacore.com> 3972 3973 * system.h (SIZE_MAX): Define if not already defined. 3974 39752021-01-29 Jakub Jelinek <jakub@redhat.com> 3976 3977 PR debug/98331 3978 * cfgbuild.c (find_bb_boundaries): Reset debug_insn when seeing 3979 a BARRIER. 3980 39812021-01-29 Jakub Jelinek <jakub@redhat.com> 3982 3983 PR target/98853 3984 * config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use 3985 %w0, %w1 and %2 instead of %0, %1 and %2. 3986 39872021-01-29 Jakub Jelinek <jakub@redhat.com> 3988 3989 PR target/98681 3990 * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p): 3991 Use UINTVAL (shft_amnt) and UINTVAL (mask) instead of INTVAL (shft_amnt) 3992 and INTVAL (mask). Add && INTVAL (mask) > 0 condition. 3993 39942021-01-29 Jakub Jelinek <jakub@redhat.com> 3995 3996 PR testsuite/98771 3997 * fold-const-call.c (host_size_t_cst_p): Renamed to ... 3998 (size_t_cst_p): ... this. Check and store unsigned HOST_WIDE_INT 3999 value rather than host size_t. 4000 (fold_const_call): Change type of s2 from size_t to 4001 unsigned HOST_WIDE_INT. Use size_t_cst_p instead of 4002 host_size_t_cst_p. For strncmp calls, pass MIN (s2, SIZE_MAX) 4003 instead of s2 as last argument. 4004 40052021-01-29 Jakub Jelinek <jakub@redhat.com> 4006 4007 PR testsuite/97301 4008 * config/rs6000/mmintrin.h (__m64): Add __may_alias__ attribute. 4009 40102021-01-29 Jakub Jelinek <jakub@redhat.com> 4011 4012 PR tree-optimization/90248 4013 * match.pd (X cmp 0.0 ? 1.0 : -1.0 -> copysign(1, +-X), 4014 X cmp 0.0 ? -1.0 : +1.0 -> copysign(1, -+X)): Remove 4015 simplifications. 4016 (X * (X cmp 0.0 ? 1.0 : -1.0) -> +-abs(X), 4017 X * (X cmp 0.0 ? -1.0 : 1.0) -> +-abs(X)): New simplifications. 4018 40192021-01-29 Jakub Jelinek <jakub@redhat.com> 4020 4021 PR tree-optimization/98255 4022 * tree-dfa.c (get_ref_base_and_extent): For ARRAY_REFs, sign 4023 extend index - low_bound from sizetype's precision rather than index 4024 precision. 4025 (get_addr_base_and_unit_offset_1): Likewise. 4026 * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Likewise. 4027 * gimple-fold.c (fold_const_aggregate_ref_1): Likewise. 4028 40292021-01-29 Bin Cheng <bin.cheng@linux.alibaba.com> 4030 Richard Biener <rguenther@suse.de> 4031 4032 PR tree-optimization/97627 4033 * tree-ssa-loop-niter.c (number_of_iterations_exit_assumptions): 4034 Do not analyze fake edges. 4035 40362021-01-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 4037 4038 Backported from master: 4039 2021-01-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 4040 4041 PR tree-optimization/98766 4042 * tree-ssa-math-opts.c (convert_mult_to_fma): Use maybe_le when 4043 comparing against type size with param_avoid_fma_max_bits. 4044 40452021-01-26 Martin Liska <mliska@suse.cz> 4046 4047 PR gcov-profile/98739 4048 * common.opt: Add missing equal symbol. 4049 40502021-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de> 4051 4052 Backported from master: 4053 2021-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de> 4054 4055 * config/rtems.h (STARTFILE_SPEC): Remove qnolinkcmds. 4056 (ENDFILE_SPEC): Evaluate qnolinkcmds. 4057 40582021-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de> 4059 4060 Backported from master: 4061 2021-01-25 Sebastian Huber <sebastian.huber@embedded-brains.de> 4062 4063 * config/rtems.h (STARTFILE_SPEC): Remove nostdlib and 4064 nostartfiles handling since this is already done by 4065 LINK_COMMAND_SPEC. Evaluate qnolinkcmds. 4066 (ENDFILE_SPEC): Remove nostdlib and nostartfiles handling since this 4067 is already done by LINK_COMMAND_SPEC. 4068 (LIB_SPECS): Remove nostdlib and nodefaultlibs handling since 4069 this is already done by LINK_COMMAND_SPEC. Remove qnolinkcmds 4070 evaluation. 4071 40722021-01-25 Claudiu Zissulescu <claziss@gmail.com> 4073 4074 Backported from master: 4075 2020-12-11 Claudiu Zissulescu <claziss@synopsys.com> 4076 4077 * config/arc/arc.md (mpyd<su_optab>_arcv2hs): New template 4078 pattern. 4079 (*pmpyd<su_optab>_arcv2hs): Likewise. 4080 (*pmpyd<su_optab>_imm_arcv2hs): Likewise. 4081 (mpyd_arcv2hs): Moved into above template. 4082 (mpyd_imm_arcv2hs): Moved into above template. 4083 (mpydu_arcv2hs): Likewise. 4084 (mpydu_imm_arcv2hs): Likewise. 4085 (su_optab): New optab prefix for sign/zero-extending operations. 4086 40872021-01-22 Richard Sandiford <richard.sandiford@arm.com> 4088 4089 Backported from master: 4090 2021-01-20 Richard Sandiford <richard.sandiford@arm.com> 4091 4092 PR tree-optimization/98535 4093 * tree-vect-slp.c (duplicate_and_interleave): Use quick_grow_cleared. 4094 If the high and low permutes are the same, remove the high permutes 4095 from the working set and only continue with the low ones. 4096 40972021-01-21 Christophe Lyon <christophe.lyon@linaro.org> 4098 4099 * config/arm/arm_mve.h (__arm_vcmpneq_s8): Fix return type. 4100 41012021-01-19 Martin Jambor <mjambor@suse.cz> 4102 4103 Backported from master: 4104 2021-01-19 Martin Jambor <mjambor@suse.cz> 4105 4106 PR ipa/98690 4107 * ipa-sra.c (ssa_name_only_returned_p): New parameter fun. Check 4108 whether non-call exceptions allow removal of a statement. 4109 (isra_analyze_call): Pass the appropriate function to 4110 ssa_name_only_returned_p. 4111 41122021-01-19 Daniel Hellstrom <daniel@gaisler.com> 4113 4114 Backported from master: 4115 2021-01-19 Daniel Hellstrom <daniel@gaisler.com> 4116 4117 * config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add 4118 built-in define __FIX_LEON3FT_TN0018. 4119 41202021-01-14 Thomas Schwinge <thomas@codesourcery.com> 4121 4122 Backported from master: 4123 2021-01-14 Thomas Schwinge <thomas@codesourcery.com> 4124 4125 * config/gcn/mkoffload.c (main): Create an offload image only in 4126 64-bit configurations. 4127 41282021-01-13 Samuel Thibault <samuel.thibault@ens-lyon.org> 4129 4130 Backported from master: 4131 2021-01-13 Samuel Thibault <samuel.thibault@ens-lyon.org> 4132 4133 * config.gcc [$target == *-*-gnu*]: Enable 4134 'default_gnu_indirect_function'. 4135 41362021-01-12 Richard Biener <rguenther@suse.de> 4137 4138 Backported from master: 4139 2021-01-06 Richard Biener <rguenther@suse.de> 4140 4141 PR tree-optimization/98513 4142 * value-range.cc (intersect_ranges): Compare the upper bounds 4143 for the expected relation. 4144 41452021-01-12 Richard Biener <rguenther@suse.de> 4146 4147 Backported from master: 4148 2021-01-04 Richard Biener <rguenther@suse.de> 4149 4150 PR tree-optimization/98282 4151 * tree-ssa-sccvn.c (vn_get_stmt_kind): Classify tcc_reference on 4152 invariants as VN_NARY. 4153 41542021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4155 4156 Backported from master: 4157 2020-12-31 Richard Sandiford <richard.sandiford@arm.com> 4158 4159 PR tree-optimization/94994 4160 * tree-vect-data-refs.c (vect_vfa_align): Use dr_alignment. 4161 41622021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4163 4164 Backported from master: 4165 2021-01-04 Richard Sandiford <richard.sandiford@arm.com> 4166 4167 PR tree-optimization/95401 4168 * config/aarch64/aarch64-sve-builtins.cc 4169 (gimple_folder::load_store_cookie): Use bits rather than bytes 4170 for the alignment argument to IFN_MASK_LOAD and IFN_MASK_STORE. 4171 * gimple-fold.c (gimple_fold_mask_load_store_mem_ref): Likewise. 4172 * tree-vect-stmts.c (vectorizable_store): Likewise. 4173 (vectorizable_load): Likewise. 4174 41752021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4176 4177 Backported from master: 4178 2021-01-05 Richard Sandiford <richard.sandiford@arm.com> 4179 4180 PR rtl-optimization/97144 4181 * recog.c (constrain_operands): Initialize matching_operand 4182 for each alternative, rather than only doing it once. 4183 41842021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4185 4186 Backported from master: 4187 2020-12-31 Richard Sandiford <richard.sandiford@arm.com> 4188 4189 PR rtl-optimization/98214 4190 * genmodes.c (emit_insn_modes_h): Emit a definition of CONST_MODE_MASK. 4191 (emit_mode_mask): Treat mode_mask_array as non-constant if adj_nunits. 4192 (emit_mode_adjustments): Update GET_MODE_MASK when updating 4193 GET_MODE_NUNITS. 4194 * machmode.h (mode_mask_array): Use CONST_MODE_MASK. 4195 41962021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4197 4198 Backported from master: 4199 2020-12-31 Richard Sandiford <richard.sandiford@arm.com> 4200 4201 PR tree-optimization/98302 4202 * tree-vect-patterns.c (vect_determine_precisions_from_users): Make 4203 sure that the precision remains greater than the shift count. 4204 42052021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4206 4207 Backported from master: 4208 2021-01-05 Richard Sandiford <richard.sandiford@arm.com> 4209 4210 PR tree-optimization/98371 4211 * tree-vect-loop.c (vect_reanalyze_as_main_loop): New function. 4212 (vect_analyze_loop): If an epilogue loop appears to be cheaper 4213 than the main loop, re-analyze it as a main loop before adopting 4214 it as a main loop. 4215 42162021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4217 4218 Backported from master: 4219 2021-01-04 Richard Sandiford <richard.sandiford@arm.com> 4220 4221 PR target/89057 4222 * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Accept 4223 aarch64_simd_reg_or_zero for operand 2. Use the combinez patterns 4224 to handle zero operands. 4225 42262021-01-12 Richard Sandiford <richard.sandiford@arm.com> 4227 4228 Backported from master: 4229 2020-12-18 Richard Sandiford <richard.sandiford@arm.com> 4230 4231 * config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Use 4232 aarch64_full_sve_mode and aarch64_vq_mode directly, instead of 4233 going via aarch64_simd_container_mode. 4234 42352021-01-12 Andreas Krebbel <krebbel@gcc.gnu.org> 4236 4237 Backported from master: 4238 2021-01-11 Andreas Krebbel <krebbel@linux.ibm.com> 4239 4240 PR tree-optimization/98221 4241 * tree-ssa-forwprop.c (simplify_vector_constructor): For 4242 big-endian, use UNPACK[_FLOAT]_HI. 4243 42442021-01-11 Richard Biener <rguenther@suse.de> 4245 4246 Backported from master: 4247 2020-12-07 Richard Biener <rguenther@suse.de> 4248 4249 PR tree-optimization/98117 4250 * tree-vect-loop-manip.c (vect_gen_vector_loop_niters): 4251 Properly handle degenerate niter when setting the vector 4252 loop IV range. 4253 42542021-01-11 Richard Biener <rguenther@suse.de> 4255 4256 PR tree-optimization/97623 4257 * tree-ssa-pre.c (insert): Move hoist insertion after PRE 4258 insertion iteration and do not iterate it. 4259 (create_expression_by_pieces): Guard NEW_SETS access. 4260 (insert_into_preds_of_block): Likewise. 4261 42622021-01-11 Richard Biener <rguenther@suse.de> 4263 4264 Backported from master: 4265 2020-10-30 Richard Biener <rguenther@suse.de> 4266 4267 PR tree-optimization/97623 4268 * tree-ssa-pre.c (insert): First do hoist insertion in 4269 a backward walk. 4270 42712021-01-09 Jakub Jelinek <jakub@redhat.com> 4272 4273 Backported from master: 4274 2021-01-09 Jakub Jelinek <jakub@redhat.com> 4275 4276 PR c++/98556 4277 * tree-cfg.c (verify_gimple_assign_binary): Allow lhs of 4278 POINTER_DIFF_EXPR to be any integral type. 4279 42802021-01-07 Claudiu Zissulescu <claziss@synopsys.com> 4281 4282 Backported from master: 4283 2020-12-11 Claudiu Zissulescu <claziss@synopsys.com> 4284 4285 * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove 4286 it. 4287 (arc_sets_cc_p): Likewise. 4288 (arc_need_delay): Likewise. 4289 * config/arc/arc.c (arc_sets_cc_p): Likewise. 4290 (arc_need_delay): Likewise. 4291 (arc_scheduling_not_expected): Likewise. 4292 * config/arc/arc.md: Convert adc/sbc patterns to simple 4293 instruction definitions. 4294 42952021-01-06 Jakub Jelinek <jakub@redhat.com> 4296 4297 Backported from master: 4298 2021-01-05 Jakub Jelinek <jakub@redhat.com> 4299 4300 PR tree-optimization/98514 4301 * tree-ssa-reassoc.c (bb_rank): Change type from long * to 4302 int64_t *. 4303 (operand_rank): Change type from hash_map<tree, long> to 4304 hash_map<tree, int64_t>. 4305 (phi_rank): Change return type from long to int64_t. 4306 (loop_carried_phi): Change block_rank variable type from long to 4307 int64_t. 4308 (propagate_rank): Change return type, rank parameter type and 4309 op_rank variable type from long to int64_t. 4310 (find_operand_rank): Change return type from long to int64_t 4311 and change slot variable type from long * to int64_t *. 4312 (insert_operand_rank): Change rank parameter type from long to 4313 int64_t. 4314 (get_rank): Change return type and rank variable type from long to 4315 int64_t. Use PRId64 instead of ld to print the rank. 4316 (init_reassoc): Change rank variable type from long to int64_t 4317 and adjust correspondingly bb_rank and operand_rank initialization. 4318 43192021-01-06 Jakub Jelinek <jakub@redhat.com> 4320 4321 Backported from master: 4322 2020-12-31 Jakub Jelinek <jakub@redhat.com> 4323 4324 PR tree-optimization/98474 4325 * wide-int.cc (wi::to_mpz): If wide_int has MSB set, but type 4326 is unsigned and excess negative, append set bits after len until 4327 precision. 4328 43292021-01-06 Jakub Jelinek <jakub@redhat.com> 4330 4331 Backported from master: 4332 2020-12-21 Jakub Jelinek <jakub@redhat.com> 4333 4334 PR c++/98353 4335 * gimplify.c (gimplify_init_ctor_eval_range): Gimplify value before 4336 storing it into cref. 4337 43382021-01-06 Jakub Jelinek <jakub@redhat.com> 4339 4340 Backported from master: 4341 2020-12-21 Jakub Jelinek <jakub@redhat.com> 4342 4343 PR c++/98383 4344 * gimplify.c (struct gimplify_omp_ctx): Add in_for_exprs flag. 4345 (gimple_add_tmp_var): For addressable temporaries appearing in 4346 simd lb, b or incr expressions, don't add a private clause unless 4347 it is seen also outside of those expressions in the simd body. 4348 (omp_notice_variable): Likewise. 4349 (gimplify_omp_for): Set and reset in_for_exprs around gimplification 4350 of lb, b or incr expressions. 4351 43522021-01-06 Jakub Jelinek <jakub@redhat.com> 4353 4354 Backported from master: 4355 2020-12-18 Jakub Jelinek <jakub@redhat.com> 4356 4357 * gimplify.c (struct gimplify_omp_ctx): Add has_depend member. 4358 (gimplify_scan_omp_clauses): Set it to true if OMP_CLAUSE_DEPEND 4359 appears on OMP_TASK. 4360 (gimplify_adjust_omp_clauses_1, gimplify_adjust_omp_clauses): Force 4361 GOVD_WRITTEN on shared variables if task construct has depend clause. 4362 43632021-01-06 Jakub Jelinek <jakub@redhat.com> 4364 4365 Backported from master: 4366 2020-12-12 Jakub Jelinek <jakub@redhat.com> 4367 4368 PR middle-end/98183 4369 * omp-low.c (lower_omp_target): Don't add OMP_RETURN for 4370 data regions. 4371 * omp-expand.c (expand_omp_target): Don't try to remove 4372 OMP_RETURN for data regions. 4373 (build_omp_regions_1, omp_make_gimple_edges): Don't expect 4374 OMP_RETURN for data regions. 4375 43762021-01-06 Jakub Jelinek <jakub@redhat.com> 4377 4378 Backported from master: 4379 2020-12-10 Jakub Jelinek <jakub@redhat.com> 4380 4381 PR middle-end/98205 4382 * omp-expand.c (expand_omp_for_generic): Fix up broken_loop handling. 4383 43842021-01-06 Jakub Jelinek <jakub@redhat.com> 4385 4386 Backported from master: 4387 2020-12-08 Jakub Jelinek <jakub@redhat.com> 4388 4389 PR target/94440 4390 * config/i386/i386.opt (ix86_excess_precision, 4391 ix86_unsafe_math_optimizations): New TargetVariables. 4392 * config/i386/i386.h (X87_ENABLE_ARITH, X87_ENABLE_FLOAT): Use 4393 ix86_unsafe_math_optimizations instead of 4394 flag_unsafe_math_optimizations and ix86_excess_precision instead of 4395 flag_excess_precision. 4396 * config/i386/i386.c (ix86_excess_precision): Rename to ... 4397 (ix86_get_excess_precision): ... this. 4398 (TARGET_C_EXCESS_PRECISION): Define to ix86_get_excess_precision. 4399 * config/i386/i386-options.c (ix86_valid_target_attribute_tree, 4400 ix86_option_override_internal): Update ix86_unsafe_math_optimization 4401 from flag_unsafe_math_optimizations and ix86_excess_precision 4402 from flag_excess_precision when constructing target option nodes. 4403 (ix86_set_current_function): If flag_unsafe_math_optimizations 4404 or flag_excess_precision is different from the one recorded 4405 in TARGET_OPTION_NODE, create a new target option node for the 4406 current function and switch to that. 4407 44082021-01-06 Jakub Jelinek <jakub@redhat.com> 4409 4410 Backported from master: 4411 2020-12-04 Jakub Jelinek <jakub@redhat.com> 4412 4413 PR target/98100 4414 * cfgexpand.c (expand_gimple_basic_block): For vars with 4415 vector type, use TYPE_MODE rather than DECL_MODE. 4416 44172021-01-06 Jakub Jelinek <jakub@redhat.com> 4418 4419 Backported from master: 4420 2020-12-02 Jakub Jelinek <jakub@redhat.com> 4421 4422 * dwarf2out.c (add_scalar_info): Only use add_AT_wide for 128-bit 4423 constants and only in dwarf-5 or later, where DW_FORM_data16 is 4424 available. Otherwise use DW_FORM_block*/DW_FORM_exprloc with 4425 DW_OP_implicit_value to describe the constant. 4426 44272021-01-06 Scott Snyder <sss@li-snyder.org> 4428 4429 Backported from master: 4430 2020-12-02 Scott Snyder <sss@li-snyder.org> 4431 4432 PR plugins/98059 4433 * vec.h (auto_delete_vec): Use 4434 DISABLE_COPY_AND_ASSIGN(auto_delete_vec) instead of 4435 DISABLE_COPY_AND_ASSIGN(auto_delete_vec<T>) to make it valid C++20 4436 after DR2237. 4437 44382021-01-06 Jakub Jelinek <jakub@redhat.com> 4439 4440 Backported from master: 4441 2020-12-01 Jakub Jelinek <jakub@redhat.com> 4442 4443 PR target/98063 4444 * config/i386/i386-expand.c (ix86_expand_call): Handle non-plt 4445 CM_LARGE_PIC calls. 4446 44472021-01-05 Uroš Bizjak <ubizjak@gmail.com> 4448 4449 PR target/98522 4450 * config/i386/sse.md (sse_cvtps2pi): Redefine as define_insn_and_split. 4451 Clear the top 64 bytes of the input XMM register. 4452 (sse_cvttps2pi): Ditto. 4453 44542021-01-05 Uroš Bizjak <ubizjak@gmail.com> 4455 4456 PR target/98521 4457 * config/i386/xopintrin.h (_mm256_cmov_si256): New. 4458 44592021-01-03 Iain Sandoe <iain@sandoe.co.uk> 4460 Jakub Jelinek <jakub@redhat.com> 4461 4462 PR target/97865 4463 * configure: Regenerate. 4464 44652021-01-01 Iain Sandoe <iain@sandoe.co.uk> 4466 4467 * config/darwin-driver.c (validate_macosx_version_min): Allow 4468 MACOSX_DEPLOYMENT_TARGET=11. 4469 (darwin_default_min_version): Adjust warning spelling to avoid 4470 an apostrophe. 4471 44722021-01-01 Iain Sandoe <iain@sandoe.co.uk> 4473 4474 * config/darwin-driver.c (darwin_find_version_from_kernel): 4475 Compute the minor OS version from the minor kernel version. 4476 44772021-01-01 Iain Sandoe <iain@sandoe.co.uk> 4478 4479 Backported from master: 4480 2020-11-06 Iain Sandoe <iain@sandoe.co.uk> 4481 4482 * config/darwin-c.c: Allow for Darwin20 to correspond to macOS 11. 4483 * config/darwin-driver.c: Likewise. 4484 44852021-01-01 Iain Sandoe <iain@sandoe.co.uk> 4486 4487 Backported from master: 4488 2020-11-01 Iain Sandoe <iain@sandoe.co.uk> 4489 4490 * config/host-darwin.c: Align pch_address_space to 16384. 4491 44922021-01-01 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> 4493 4494 * config/aarch64/aarch64-builtins.c 4495 (aarch64_init_memtag_builtins): Manually initialize instead 4496 of using a C++11 brace-init-list. 4497 44982021-01-01 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> 4499 4500 * config/aarch64/driver-aarch64.c 4501 (aarch64_get_extension_string_for_isa_flags): Adjust signature. 4502 45032020-12-28 Uroš Bizjak <ubizjak@gmail.com> 4504 4505 PR target/96793 4506 * config/i386/i386-expand.c (ix86_expand_rint): 4507 Remove the sign of the intermediate value for flag_rounding_math. 4508 45092020-12-28 Piotr Kubaj <pkubaj@FreeBSD.org> 4510 4511 Backported from master: 4512 2020-12-16 Piotr Kubaj <pkubaj@FreeBSD.org> 4513 4514 * config.gcc (powerpc*le-*-freebsd*): Add. 4515 * configure.ac (powerpc*le-*-freebsd*): Ditto. 4516 * configure: Regenerate. 4517 * config/rs6000/freebsd64.h (ASM_SPEC_COMMON): Use ENDIAN_SELECT. 4518 (DEFAULT_ASM_ENDIAN): Add little endian support. 4519 (LINK_OS_FREEBSD_SPEC64): Ditto. 4520 45212020-12-24 Roman Zhuykov <zhroma@ispras.ru> 4522 4523 Backported from master: 4524 2020-12-05 Roman Zhuykov <zhroma@ispras.ru> 4525 4526 PR rtl-optimization/97421 4527 * modulo-sched.c (generate_prolog_epilog): Remove forward 4528 declaration, adjust last argument name and type. 4529 (const_iteration_count): Add bool pointer parameter to return 4530 whether count register is read in pre-header after its 4531 initialization. 4532 (sms_schedule): Fix count register initialization adjustment 4533 procedure according to what const_iteration_count said. 4534 45352020-12-23 Piotr Kubaj <pkubaj@FreeBSD.org> 4536 Gerald Pfeifer <gerald@pfeifer.com> 4537 4538 * config/rs6000/freebsd64.h (PROCESSOR_DEFAULT): Update 4539 to PROCESSOR_PPC7450. 4540 (PROCESSOR_DEFAULT64): Update to PROCESSOR_POWER8. 4541 45422020-12-23 Uroš Bizjak <ubizjak@gmail.com> 4543 4544 PR target/96793 4545 * config/i386/i386-expand.c (ix86_expand_truncdf_32): 4546 Remove the sign of the intermediate value for flag_rounding_math. 4547 45482020-12-22 Uroš Bizjak <ubizjak@gmail.com> 4549 4550 PR target/96793 4551 * config/i386/i386-expand.c (ix86_expand_floorceil): 4552 Remove the sign of the intermediate value for flag_rounding_math. 4553 (ix86_expand_floorceildf_32): Ditto. 4554 45552020-12-15 Andrea Corallo <andrea.corallo@arm.com> 4556 4557 PR rtl-optimization/97092 4558 * ira-color.c (update_costs_from_allocno): Do not carry over mode 4559 between subsequent iterations. 4560 45612020-12-14 Wilco Dijkstra <wdijkstr@arm.com> 4562 4563 * config.gcc (aarch64*-*-*): Add --with-tune. Support --with-cpu=native. 4564 * config/aarch64/aarch64.h (OPTION_DEFAULT_SPECS): Add --with-tune. 4565 45662020-12-14 Sebastian Pop <spop@amazon.com> 4567 4568 * config.gcc (aarch64*-*-*): Remove --with-{cpu,arch,tune}-32 flags. 4569 45702020-12-11 Dennis Zhang <dennis.zhang@arm.com> 4571 4572 Backported from master: 4573 2020-11-03 Dennis Zhang <dennis.zhang@arm.com> 4574 4575 * config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry. 4576 (vget_hi_half): Likewise. 4577 * config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry. 4578 (aarch64_vget_hi_halfv8bf): Likewise. 4579 * config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic. 4580 (vget_high_bf16): Likewise. 4581 45822020-12-11 Dennis Zhang <denzha01@e124712.cambridge.arm.com> 4583 4584 Backported from master: 4585 2020-11-03 Dennis Zhang <denzha01@e124712.cambridge.arm.com> 4586 4587 * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry. 4588 (vbfcvt_high, bfcvt): Likewise. 4589 * config/aarch64/aarch64-simd.md(aarch64_vbfcvt<mode>): New entry. 4590 (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise. 4591 * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic. 4592 * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise. 4593 (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise. 4594 45952020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4596 4597 * config/arm/arm_neon.h (vst2_lane_bf16, vst2q_lane_bf16) 4598 (vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16) 4599 (vst4q_lane_bf16): New intrinsics. 4600 * config/arm/arm_neon_builtins.def: Touch it for: 4601 __builtin_neon_vst2_lanev4bf, __builtin_neon_vst2_lanev8bf, 4602 __builtin_neon_vst3_lanev4bf, __builtin_neon_vst3_lanev8bf, 4603 __builtin_neon_vst4_lanev4bf,__builtin_neon_vst4_lanev8bf. 4604 46052020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4606 4607 * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16) 4608 (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16) 4609 (vld4q_lane_bf16): Add intrinsics. 4610 * config/arm/arm_neon_builtins.def: Touch for: 4611 __builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf, 4612 __builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf, 4613 __builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf. 4614 * config/arm/iterators.md (VQ_HS): Add V8BF to the iterator. 4615 46162020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4617 4618 * config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics. 4619 * config/arm/arm_neon_builtins.def : Touch for: 4620 __builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf. 4621 46222020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4623 4624 * config/arm/arm-builtins.c (VAR14): Define macro. 4625 * config/arm/arm_neon_builtins.def: Touch for: 4626 __builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf. 4627 * config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics. 4628 46292020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4630 4631 * config/arm/arm_neon.h (vst1_lane_bf16, vst1q_lane_bf16): Add 4632 intrinsics. 4633 * config/arm/arm_neon_builtins.def (STORE1LANE): Add v4bf, v8bf. 4634 46352020-12-11 Andrea Corallo <andrea.corallo@arm.com> 4636 4637 * config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf. 4638 * config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add 4639 intrinsics. 4640 46412020-12-09 Kewen Lin <linkw@linux.ibm.com> 4642 4643 Backported from master: 4644 2020-08-19 Kewen Lin <linkw@linux.ibm.com> 4645 4646 * opts-global.c (decode_options): Call target_option_override_hook 4647 before it prints for --help=*. 4648 46492020-12-08 Andrea Corallo <andrea.corallo@arm.com> 4650 4651 * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted 4652 fall-throughs. 4653 46542020-12-04 Hans-Peter Nilsson <hp@axis.com> 4655 4656 Backported from master: 4657 2020-12-04 Hans-Peter Nilsson <hp@axis.com> 4658 Martin Sebor <msebor@redhat.com> 4659 4660 PR middle-end/94600 4661 * doc/implement-c.texi (Qualifiers implementation): Add blurb 4662 about access to the whole of a volatile aggregate object, only for 4663 same-size as a scalar object. 4664 46652020-12-04 Eric Botcazou <ebotcazou@adacore.com> 4666 4667 * ipa-sra.c (verify_access_tree_1): Relax assertion on the size. 4668 46692020-12-03 Uros Bizjak <ubizjak@gmail.com> 4670 4671 Backported from master: 4672 2020-12-03 Uroš Bizjak <ubizjak@gmail.com> 4673 Jakub Jelinek <jakub@redhat.com> 4674 4675 PR target/98086 4676 * config/i386/i386.c (ix86_md_asm_adjustmd): Rewrite 4677 zero-extension part to use convert_to_mode. 4678 46792020-12-03 Sebastian Huber <sebastian.huber@embedded-brains.de> 4680 4681 Backported from master: 4682 2020-12-03 Sebastian Huber <sebastian.huber@embedded-brains.de> 4683 4684 * config/arm/t-rtems: Add "-mthumb -mcpu=cortex-r52 4685 -mfloat-abi=hard" multilib. 4686 46872020-12-03 Richard Sandiford <richard.sandiford@arm.com> 4688 4689 Backported from master: 4690 2020-07-08 Richard Sandiford <richard.sandiford@arm.com> 4691 4692 PR middle-end/95694 4693 * expr.c (expand_expr_real_2): Get the mode from the type rather 4694 than the rtx, and assert that it is consistent with the mode of 4695 the rtx (where known). Optimize all constant integers, not just 4696 those that can be represented in poly_int64. 4697 46982020-12-02 Richard Sandiford <richard.sandiford@arm.com> 4699 4700 Backported from master: 4701 2020-10-28 Richard Sandiford <richard.sandiford@arm.com> 4702 4703 PR tree-optimization/97457 4704 * value-range.cc (irange::set): Don't decay POLY_INT_CST ranges 4705 to integer ranges. 4706 47072020-12-02 Richard Sandiford <richard.sandiford@arm.com> 4708 4709 Backported from master: 4710 2020-10-02 Richard Sandiford <richard.sandiford@arm.com> 4711 4712 * config/aarch64/aarch64-protos.h (aarch64_sve_pred_dominates_p): 4713 Delete. 4714 * config/aarch64/aarch64.c (aarch64_sve_pred_dominates_p): Likewise. 4715 * config/aarch64/aarch64-sve.md: Add banner comment describing 4716 how merging predicated FP operations are represented. 4717 (*cond_<SVE_COND_FP_UNARY:optab><mode>_2): Split into... 4718 (*cond_<SVE_COND_FP_UNARY:optab><mode>_2_relaxed): ...this and... 4719 (*cond_<SVE_COND_FP_UNARY:optab><mode>_2_strict): ...this. 4720 (*cond_<SVE_COND_FP_UNARY:optab><mode>_any): Split into... 4721 (*cond_<SVE_COND_FP_UNARY:optab><mode>_any_relaxed): ...this and... 4722 (*cond_<SVE_COND_FP_UNARY:optab><mode>_any_strict): ...this. 4723 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_2): Split into... 4724 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_2_relaxed): ...this and... 4725 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_2_strict): ...this. 4726 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_any): Split into... 4727 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_any_relaxed): ...this 4728 and... 4729 (*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_any_strict): ...this. 4730 (*cond_<SVE_COND_FP_BINARY:optab><mode>_2): Split into... 4731 (*cond_<SVE_COND_FP_BINARY:optab><mode>_2_relaxed): ...this and... 4732 (*cond_<SVE_COND_FP_BINARY:optab><mode>_2_strict): ...this. 4733 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_2_const): Split into... 4734 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_2_const_relaxed): ...this 4735 and... 4736 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_2_const_strict): ...this. 4737 (*cond_<SVE_COND_FP_BINARY:optab><mode>_3): Split into... 4738 (*cond_<SVE_COND_FP_BINARY:optab><mode>_3_relaxed): ...this and... 4739 (*cond_<SVE_COND_FP_BINARY:optab><mode>_3_strict): ...this. 4740 (*cond_<SVE_COND_FP_BINARY:optab><mode>_any): Split into... 4741 (*cond_<SVE_COND_FP_BINARY:optab><mode>_any_relaxed): ...this and... 4742 (*cond_<SVE_COND_FP_BINARY:optab><mode>_any_strict): ...this. 4743 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_any_const): Split into... 4744 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_any_const_relaxed): ...this 4745 and... 4746 (*cond_<SVE_COND_FP_BINARY_I1:optab><mode>_any_const_strict): ...this. 4747 (*cond_add<mode>_2_const): Split into... 4748 (*cond_add<mode>_2_const_relaxed): ...this and... 4749 (*cond_add<mode>_2_const_strict): ...this. 4750 (*cond_add<mode>_any_const): Split into... 4751 (*cond_add<mode>_any_const_relaxed): ...this and... 4752 (*cond_add<mode>_any_const_strict): ...this. 4753 (*cond_<SVE_COND_FCADD:optab><mode>_2): Split into... 4754 (*cond_<SVE_COND_FCADD:optab><mode>_2_relaxed): ...this and... 4755 (*cond_<SVE_COND_FCADD:optab><mode>_2_strict): ...this. 4756 (*cond_<SVE_COND_FCADD:optab><mode>_any): Split into... 4757 (*cond_<SVE_COND_FCADD:optab><mode>_any_relaxed): ...this and... 4758 (*cond_<SVE_COND_FCADD:optab><mode>_any_strict): ...this. 4759 (*cond_sub<mode>_3_const): Split into... 4760 (*cond_sub<mode>_3_const_relaxed): ...this and... 4761 (*cond_sub<mode>_3_const_strict): ...this. 4762 (*aarch64_pred_abd<mode>): Split into... 4763 (*aarch64_pred_abd<mode>_relaxed): ...this and... 4764 (*aarch64_pred_abd<mode>_strict): ...this. 4765 (*aarch64_cond_abd<mode>_2): Split into... 4766 (*aarch64_cond_abd<mode>_2_relaxed): ...this and... 4767 (*aarch64_cond_abd<mode>_2_strict): ...this. 4768 (*aarch64_cond_abd<mode>_3): Split into... 4769 (*aarch64_cond_abd<mode>_3_relaxed): ...this and... 4770 (*aarch64_cond_abd<mode>_3_strict): ...this. 4771 (*aarch64_cond_abd<mode>_any): Split into... 4772 (*aarch64_cond_abd<mode>_any_relaxed): ...this and... 4773 (*aarch64_cond_abd<mode>_any_strict): ...this. 4774 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_2): Split into... 4775 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_2_relaxed): ...this and... 4776 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_2_strict): ...this. 4777 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_4): Split into... 4778 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_4_relaxed): ...this and... 4779 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_4_strict): ...this. 4780 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_any): Split into... 4781 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_any_relaxed): ...this and... 4782 (*cond_<SVE_COND_FP_TERNARY:optab><mode>_any_strict): ...this. 4783 (*cond_<SVE_COND_FCMLA:optab><mode>_4): Split into... 4784 (*cond_<SVE_COND_FCMLA:optab><mode>_4_relaxed): ...this and... 4785 (*cond_<SVE_COND_FCMLA:optab><mode>_4_strict): ...this. 4786 (*cond_<SVE_COND_FCMLA:optab><mode>_any): Split into... 4787 (*cond_<SVE_COND_FCMLA:optab><mode>_any_relaxed): ...this and... 4788 (*cond_<SVE_COND_FCMLA:optab><mode>_any_strict): ...this. 4789 (*aarch64_pred_fac<cmp_op><mode>): Split into... 4790 (*aarch64_pred_fac<cmp_op><mode>_relaxed): ...this and... 4791 (*aarch64_pred_fac<cmp_op><mode>_strict): ...this. 4792 (*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>): Split 4793 into... 4794 (*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_relaxed): 4795 ...this and... 4796 (*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_strict): 4797 ...this. 4798 (*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>): Split 4799 into... 4800 (*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_relaxed): 4801 ...this and... 4802 (*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_strict): 4803 ...this. 4804 * config/aarch64/aarch64-sve2.md 4805 (*cond_<SVE2_COND_FP_UNARY_LONG:optab><mode>): Split into... 4806 (*cond_<SVE2_COND_FP_UNARY_LONG:optab><mode>_relaxed): ...this and... 4807 (*cond_<SVE2_COND_FP_UNARY_LONG:optab><mode>_strict): ...this. 4808 (*cond_<SVE2_COND_FP_UNARY_NARROWB:optab><mode>_any): Split into... 4809 (*cond_<SVE2_COND_FP_UNARY_NARROWB:optab><mode>_any_relaxed): ...this 4810 and... 4811 (*cond_<SVE2_COND_FP_UNARY_NARROWB:optab><mode>_any_strict): ...this. 4812 (*cond_<SVE2_COND_INT_UNARY_FP:optab><mode>): Split into... 4813 (*cond_<SVE2_COND_INT_UNARY_FP:optab><mode>_relaxed): ...this and... 4814 (*cond_<SVE2_COND_INT_UNARY_FP:optab><mode>_strict): ...this. 4815 48162020-12-02 Richard Sandiford <richard.sandiford@arm.com> 4817 4818 Backported from master: 4819 2020-11-25 Richard Sandiford <richard.sandiford@arm.com> 4820 4821 * config/aarch64/aarch64.c (aarch64_maybe_expand_sve_subreg_move): 4822 Do not optimize LRA subregs. 4823 * config/aarch64/aarch64-sve.md 4824 (@aarch64_pred_<SVE_INT_UNARY:optab><mode>): Tie the input to the 4825 output. 4826 (@aarch64_sve_revbhw_<SVE_ALL:mode><PRED_HSD:mode>): Likewise. 4827 (*<ANY_EXTEND:optab><SVE_PARTIAL_I:mode><SVE_HSDI:mode>2): Likewise. 4828 (@aarch64_pred_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>): Likewise. 4829 (*cnot<mode>): Likewise. 4830 (@aarch64_pred_<SVE_COND_FP_UNARY:optab><mode>): Likewise. 4831 (@aarch64_sve_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>): 4832 Likewise. 4833 (@aarch64_sve_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>): 4834 Likewise. 4835 (@aarch64_sve_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>): 4836 Likewise. 4837 (@aarch64_sve_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>): 4838 Likewise. 4839 (@aarch64_sve_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>): 4840 Likewise. 4841 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): 4842 Likewise. 4843 (@aarch64_sve_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>): 4844 Likewise. 4845 * config/aarch64/aarch64-sve2.md 4846 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise. 4847 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise. 4848 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise. 4849 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise. 4850 48512020-12-02 Richard Sandiford <richard.sandiford@arm.com> 4852 4853 Backported from master: 4854 2020-11-30 Richard Sandiford <richard.sandiford@arm.com> 4855 4856 PR rtl-optimization/98037 4857 * dse.c (find_shift_sequence): Iterate over all integers and 4858 skip modes that are too small. 4859 48602020-12-02 Richard Biener <rguenther@suse.de> 4861 4862 Backported from master: 4863 2020-09-04 Richard Biener <rguenther@suse.de> 4864 4865 PR tree-optimization/96698 4866 PR tree-optimization/96920 4867 * tree-vectorizer.h (loop_vec_info::reduc_latch_defs): Remove. 4868 (loop_vec_info::reduc_latch_slp_defs): Likewise. 4869 * tree-vect-stmts.c (vect_transform_stmt): Remove vectorized 4870 cycle PHI latch code. 4871 * tree-vect-loop.c (maybe_set_vectorized_backedge_value): New 4872 helper to set vectorized cycle PHI latch values. 4873 (vect_transform_loop): Walk over all PHIs again after 4874 vectorizing them, calling maybe_set_vectorized_backedge_value. 4875 Call maybe_set_vectorized_backedge_value for each vectorized 4876 stmt. Remove delayed update code. 4877 * tree-vect-slp.c (vect_analyze_slp_instance): Initialize 4878 SLP instance reduc_phis member. 4879 (vect_schedule_slp): Set vectorized cycle PHI latch values. 4880 48812020-12-02 Richard Biener <rguenther@suse.de> 4882 4883 Backported from master: 4884 2020-08-26 Richard Biener <rguenther@suse.de> 4885 4886 PR tree-optimization/96698 4887 * tree-vectorizer.h (loop_vec_info::reduc_latch_defs): New. 4888 (loop_vec_info::reduc_latch_slp_defs): Likewise. 4889 * tree-vect-stmts.c (vect_transform_stmt): Only record 4890 stmts to update PHI latches from, perform the update ... 4891 * tree-vect-loop.c (vect_transform_loop): ... here after 4892 vectorizing those PHIs. 4893 (info_for_reduction): Properly handle non-reduction PHIs. 4894 48952020-12-01 Richard Biener <rguenther@suse.de> 4896 4897 Backported from master: 4898 2020-11-13 Richard Biener <rguenther@suse.de> 4899 4900 PR tree-optimization/97812 4901 * tree-vrp.c (register_edge_assert_for_2): Extend the range 4902 according to its sign before seeing whether it fits. 4903 49042020-12-01 Richard Biener <rguenther@suse.de> 4905 4906 Backported from master: 4907 2020-11-10 Richard Biener <rguenther@suse.de> 4908 4909 PR tree-optimization/97760 4910 * tree-vect-loop.c (check_reduction_path): Reject 4911 reduction paths we do not handle in epilogue generation. 4912 49132020-12-01 Richard Biener <rguenther@suse.de> 4914 4915 Backported from master: 4916 2020-10-26 Richard Biener <rguenther@suse.de> 4917 4918 PR tree-optimization/97539 4919 * tree-vect-loop-manip.c (vect_do_peeling): Reset out-of-loop 4920 debug uses before peeling. 4921 49222020-12-01 Richard Biener <rguenther@suse.de> 4923 4924 Backported from master: 4925 2020-05-18 Richard Biener <rguenther@suse.de> 4926 4927 PR middle-end/95171 4928 * tree-inline.c (remap_gimple_stmt): Split out trapping compares 4929 when inlining into a non-call EH function. 4930 49312020-12-01 Richard Biener <rguenther@suse.de> 4932 4933 Backported from master: 4934 2020-10-26 Richard Biener <rguenther@suse.de> 4935 4936 PR middle-end/97554 4937 * sbitmap.c (sbitmap_vector_alloc): Use size_t for byte 4938 quantities to avoid overflow. 4939 49402020-11-28 Eric Botcazou <ebotcazou@adacore.com> 4941 4942 PR target/97939 4943 * config/sparc/predicates.md (arith_double_add_operand): Comment. 4944 * config/sparc/sparc.md (uaddvdi4): Use arith_double_operand. 4945 (addvdi4): Use arith_double_add_operand. 4946 (addsi3): Remove useless attributes. 4947 (addvsi4): Use arith_add_operand. 4948 (*cmp_ccv_plus): Likewise and add second alternative accordingly. 4949 (*cmp_ccxv_plus): Likewise. 4950 (*cmp_ccv_plus_set): Likewise. 4951 (*cmp_ccxv_plus_set): Likewise. 4952 (*cmp_ccv_plus_sltu_set): Likewise. 4953 (usubvdi4): Use arith_double_operand. 4954 (subvdi4): Use arith_double_add_operand. 4955 (subsi3): Remove useless attributes. 4956 (subvsi4): Use arith_add_operand. 4957 (*cmp_ccv_minus): Likewise and add second alternative accordingly. 4958 (*cmp_ccxv_minus): Likewise. 4959 (*cmp_ccv_minus_set): Likewise. 4960 (*cmp_ccxv_minus_set): Likewise. 4961 (*cmp_ccv_minus_sltu_set): Likewise. 4962 (negsi2): Use register_operand. 4963 (unegvsi3): Likewise. 4964 (negvsi3) Likewise. 4965 (*cmp_ccnz_neg): Likewise. 4966 (*cmp_ccxnz_neg): Likewise. 4967 (*cmp_ccnz_neg_set): Likewise. 4968 (*cmp_ccxnz_neg_set): Likewise. 4969 (*cmp_ccc_neg_set): Likewise. 4970 (*cmp_ccxc_neg_set): Likewise. 4971 (*cmp_ccc_neg_sltu_set): Likewise. 4972 (*cmp_ccv_neg): Likewise. 4973 (*cmp_ccxv_neg): Likewise. 4974 (*cmp_ccv_neg_set): Likewise. 4975 (*cmp_ccxv_neg_set): Likewise. 4976 (*cmp_ccv_neg_sltu_set): Likewise. 4977 49782020-11-28 Eric Botcazou <ebotcazou@adacore.com> 4979 4980 PR target/96607 4981 * config/sparc/sparc-protos.h (eligible_for_call_delay): Delete. 4982 * config/sparc/sparc.c (eligible_for_call_delay): Likewise. 4983 * config/sparc/sparc.md (in_call_delay): Likewise. 4984 (tls_delay_slot): New attribute. 4985 (define_delay [call]): Use in_branch_delay. 4986 (tgd_call<P:mode>): Set type to call_no_delay_slot when 4987 tls_delay_slot is false. 4988 (tldm_call<P:mode>): Likewise. 4989 49902020-11-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 4991 4992 Backported from master: 4993 2020-11-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 4994 4995 * config/aarch64/aarch64.opt 4996 (-param=aarch64-autovec-preference): Define. 4997 * config/aarch64/aarch64.c (aarch64_override_options_internal): 4998 Set aarch64_sve_compare_costs to 0 when preferring only Advanced 4999 SIMD. 5000 (aarch64_cmp_autovec_modes): Define. 5001 (aarch64_preferred_simd_mode): Adjust to use the above. 5002 (aarch64_autovectorize_vector_modes): Likewise. 5003 * doc/invoke.texi: Document aarch64-autovec-preference param. 5004 50052020-11-25 Jakub Jelinek <jakub@redhat.com> 5006 5007 Backported from master: 5008 2020-11-20 Jakub Jelinek <jakub@redhat.com> 5009 5010 PR target/97528 5011 * config/arm/arm.c (neon_vector_mem_operand): For POST_MODIFY, require 5012 first POST_MODIFY operand is a REG and is equal to the first operand 5013 of PLUS. 5014 50152020-11-25 Jakub Jelinek <jakub@redhat.com> 5016 5017 Backported from master: 5018 2020-11-14 Jakub Jelinek <jakub@redhat.com> 5019 5020 PR debug/97599 5021 * dwarf2out.c (gen_subprogram_die): Call 5022 gen_unspecified_parameters_die even if not early dwarf, but only 5023 if subr_die is a newly created DIE. 5024 50252020-11-24 Jason Merrill <jason@redhat.com> 5026 5027 PR c++/97918 5028 * dwarf2out.c (dwarf2out_early_finish): flush_limbo_die_list 5029 after gen_scheduled_generic_parms_dies. 5030 50312020-11-24 Jason Merrill <jason@redhat.com> 5032 5033 PR debug/97060 5034 * dwarf2out.c (gen_subprogram_die): It's a declaration 5035 if DECL_INITIAL isn't set. 5036 50372020-11-24 Richard Earnshaw <rearnsha@arm.com> 5038 5039 PR target/97534 5040 * config/arm/arm.c (arm_split_atomic_op): Use gen_int_mode when 5041 negating a const_int. 5042 50432020-11-24 Thomas Schwinge <thomas@codesourcery.com> 5044 5045 Backported from master: 5046 2020-11-24 Thomas Schwinge <thomas@codesourcery.com> 5047 5048 * omp-expand.c (expand_oacc_for): More explicit checking of which 5049 OMP constructs we're expecting. 5050 50512020-11-23 Matthew Malcomson <matthew.malcomson@arm.com> 5052 5053 * doc/install.texi: Document bootstrap-asan option. 5054 50552020-11-19 Alex Coplan <alex.coplan@arm.com> 5056 5057 Backported from master: 5058 2020-11-12 Alex Coplan <alex.coplan@arm.com> 5059 5060 PR target/97730 5061 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_bcax<mode>): 5062 Change to define_expand, add missing (trivially-predicated) not 5063 rtx to fix wrong code bug. 5064 (*aarch64_sve2_bcax<mode>): New. 5065 50662020-11-19 Uroš Bizjak <ubizjak@gmail.com> 5067 5068 PR target/97887 5069 * config/i386/i386.md (*<absneg:code><mode>2_i387_1): 5070 Disable for TARGET_SSE_MATH modes. 5071 50722020-11-17 Sebastian Pop <spop@amazon.com> 5073 5074 Backported from master: 5075 2020-11-17 Sebastian Pop <spop@amazon.com> 5076 5077 * config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64} 5078 as alias flags for --with-{cpu,arch,tune} on AArch64. 5079 * doc/install.texi: Document new flags for aarch64. 5080 50812020-11-17 Sebastian Pop <spop@amazon.com> 5082 5083 Backported from master: 5084 2020-11-17 Sebastian Pop <spop@amazon.com> 5085 5086 * config.gcc: Add --with-tune to AArch64 configure flags. 5087 50882020-11-17 Tamar Christina <tamar.christina@arm.com> 5089 5090 PR target/97535 5091 * config/aarch64/aarch64.c (aarch64_expand_cpymem): Use unsigned 5092 arithmetic in check. 5093 50942020-11-17 Monk Chiang <monk.chiang@sifive.com> 5095 5096 Backported from master: 5097 2020-11-14 Monk Chiang <monk.chiang@sifive.com> 5098 5099 PR target/97682 5100 * config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change register 5101 to t0. 5102 (RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register. 5103 (RISCV_CALL_ADDRESS_TEMP): Use it for call instructions. 5104 * config/riscv/riscv.c (riscv_legitimize_call_address): Use 5105 RISCV_CALL_ADDRESS_TEMP. 5106 (riscv_compute_frame_info): Change temporary register to t0 form t1. 5107 (riscv_trampoline_init): Adjust comment. 5108 51092020-11-16 Cui,Lili <lili.cui@intel.com> 5110 5111 * config/i386/i386.h: Add PREFETCHW to march=broadwell. 5112 * doc/invoke.texi: Put PREFETCHW back to relation arch. 5113 51142020-11-13 Thomas Schwinge <thomas@codesourcery.com> 5115 5116 Backported from master: 5117 2020-11-13 Thomas Schwinge <thomas@codesourcery.com> 5118 5119 * omp-low.c (scan_sharing_clauses, scan_omp_for) 5120 (lower_oacc_reductions, lower_omp_target): More explicit checking 5121 of which OMP constructs we're expecting. 5122 51232020-11-13 Thomas Schwinge <thomas@codesourcery.com> 5124 5125 Backported from master: 5126 2020-11-13 Thomas Schwinge <thomas@codesourcery.com> 5127 5128 * omp-expand.c (expand_omp_target): Attach an attribute to all 5129 outlined OpenACC compute regions. 5130 * omp-offload.c (execute_oacc_device_lower): Adjust. 5131 51322020-11-12 Peter Bergner <bergner@linux.ibm.com> 5133 5134 Backported from master: 5135 2020-11-06 Peter Bergner <bergner@linux.ibm.com> 5136 5137 * config/rs6000/rs6000.h (BIGGEST_ALIGNMENT): Revert previous commit 5138 so as not to break the ABI. 5139 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Set the ABI 5140 mandated alignment for __vector_pair and __vector_quad types. 5141 51422020-11-11 liuhongt <hongtao.liu@intel.com> 5143 5144 * config/i386/i386-options.c (ix86_option_override_internal): 5145 Handle PTA_CLDEMOTE. 5146 * config/i386/i386.h (PTA_CLDEMOTE): Define. 5147 51482020-11-10 Jakub Jelinek <jakub@redhat.com> 5149 5150 PR tree-optimization/97764 5151 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): For 5152 little-endian stores with negative pd.offset, subtract 5153 BITS_PER_UNIT - amnt from size if amnt is non-zero. 5154 51552020-11-09 Sudakshina Das <sudi.das@arm.com> 5156 5157 Backported from master: 5158 2020-11-02 Sudakshina Das <sudi.das@arm.com> 5159 5160 PR target/97638 5161 * config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Update 5162 return value on INSN_P check. 5163 51642020-11-09 Lili Cui <lili.cui@intel.com> 5165 5166 PR target/97685 5167 * config/i386/i386.h: 5168 (PTA_BROADWELL): Delete PTA_PRFCHW. 5169 (PTA_SILVERMONT): Add PTA_PRFCHW. 5170 (PTA_KNL): Add PTA_PREFETCHWT1. 5171 (PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and PTA_WAITPKG. 5172 * doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl, knm, 5173 skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake, 5174 cooperlake, tigerlake and sapphirerapids. 5175 Add PREFETCHW for silvermont, goldmont, goldmont-plus and tremont. 5176 Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont. 5177 Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont. 5178 Add KEYLOCKER and HREST for alderlake. 5179 Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids. 5180 Add KEYLOCKER for tigerlake. 5181 51822020-11-07 Richard Biener <rguenther@suse.de> 5183 5184 Backported from master: 5185 2020-10-21 Richard Biener <rguenther@suse.de> 5186 Andrew MacLeod <amacleod@redhat.com> 5187 Martin Liska <mliska@suse.cz> 5188 5189 PR target/97360 5190 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Remove call to 5191 build_distinct_type_copy(). 5192 51932020-11-04 Andrea Corallo <andrea.corallo@arm.com> 5194 5195 * config/aarch64/arm_neon.h (__ST2_LANE_FUNC, __ST3_LANE_FUNC) 5196 (__ST4_LANE_FUNC): Rename the macro generating the 'q' variants 5197 into __ST2Q_LANE_FUNC, __ST2Q_LANE_FUNC, __ST2Q_LANE_FUNC so they 5198 all can be undefed at the and of the file. 5199 (vst2_lane_bf16, vst2q_lane_bf16, vst3_lane_bf16, vst3q_lane_bf16) 5200 (vst4_lane_bf16, vst4q_lane_bf16): Add new intrinsics. 5201 52022020-11-04 Andrea Corallo <andrea.corallo@arm.com> 5203 5204 * config/aarch64/arm_neon.h (__LD2_LANE_FUNC, __LD3_LANE_FUNC) 5205 (__LD4_LANE_FUNC): Rename the macro geneating the 'q' variants 5206 into __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC so they 5207 all can be undefed at the and of the file. 5208 (vld2_lane_bf16, vld2q_lane_bf16, vld3_lane_bf16, vld3q_lane_bf16) 5209 (vld4_lane_bf16, vld4q_lane_bf16): Add new intrinsics. 5210 52112020-11-04 Andrea Corallo <andrea.corallo@arm.com> 5212 5213 * config/aarch64/arm_neon.h (vcopy_lane_bf16, vcopyq_lane_bf16) 5214 (vcopyq_laneq_bf16, vcopy_laneq_bf16): New intrinsics. 5215 52162020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5217 5218 Backported from master: 5219 2020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5220 5221 * omp-low.c (scan_omp_for) <OpenACC>: Use proper location to 5222 'inform' of enclosing parent compute construct. 5223 52242020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5225 5226 Backported from master: 5227 2020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5228 5229 * omp-low.c (scan_omp_for) <OpenACC>: Move earlier inconsistent 5230 nested 'reduction' clauses checking. 5231 52322020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5233 5234 Backported from master: 5235 2020-11-03 Thomas Schwinge <thomas@codesourcery.com> 5236 5237 * omp-low.c (scan_omp_for) <OpenACC>: More precise diagnostics for 5238 'gang', 'worker', 'vector' clauses with arguments only allowed in 5239 'kernels' regions. 5240 52412020-11-02 Jakub Jelinek <jakub@redhat.com> 5242 5243 * wide-int.cc (wi::set_bit_large): Call canonize unless setting 5244 msb bit and clearing bits above it. 5245 52462020-10-29 Martin Liska <mliska@suse.cz> 5247 5248 Backported from master: 5249 2020-10-29 Martin Liska <mliska@suse.cz> 5250 5251 PR lto/97508 5252 * langhooks.c (lhd_begin_section): Call get_section with 5253 not_existing = true. 5254 * output.h (get_section): Add new argument. 5255 * varasm.c (get_section): Fail when NOT_EXISTING is true 5256 and a section already exists. 5257 * ipa-cp.c (ipcp_write_summary): Remove. 5258 (ipcp_read_summary): Likewise. 5259 * ipa-fnsummary.c (ipa_fn_summary_read): Always read jump 5260 functions summary. 5261 (ipa_fn_summary_write): Always stream it. 5262 52632020-10-28 Richard Biener <rguenther@suse.de> 5264 5265 Backported from master: 5266 2020-09-18 Richard Biener <rguenther@suse.de> 5267 5268 PR tree-optimization/97081 5269 * tree-vect-patterns.c (vect_recog_rotate_pattern): Use the 5270 precision of the shifted operand to determine the mask. 5271 52722020-10-26 Martin Jambor <mjambor@suse.cz> 5273 5274 Backported from master: 5275 2020-10-19 Martin Jambor <mjambor@suse.cz> 5276 5277 PR tree-optimization/97456 5278 * tree-complex.c (set_component_ssa_name): Do not replace ignored decl 5279 default definitions with new component vars. Reorder if conditions. 5280 52812020-10-22 Andreas Krebbel <krebbel@linux.ibm.com> 5282 5283 Backported from master: 5284 2020-10-22 Andreas Krebbel <krebbel@linux.ibm.com> 5285 5286 PR rtl-optimization/97439 5287 * dfp.c (decimal_real_maxval): Set the sign flag in the 5288 generated number. 5289 52902020-10-22 Kito Cheng <kito.cheng@sifive.com> 5291 5292 Backported from master: 5293 2020-10-14 Kito Cheng <kito.cheng@sifive.com> 5294 5295 PR target/96759 5296 * expr.c (expand_assignment): Handle misaligned stores with PARALLEL 5297 value. 5298 52992020-10-21 liuhongt <hongtao.liu@intel.com> 5300 5301 PR target/97506 5302 * config/i386/i386-expand.c (ix86_expand_sse_movcc): Move 5303 op_true to dest directly when op_true equals op_false. 5304 53052020-10-19 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5306 5307 Backported from master: 5308 2020-10-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5309 5310 PR target/97327 5311 * config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits array. 5312 53132020-10-16 Christophe Lyon <christophe.lyon@linaro.org> 5314 5315 Backported from master: 5316 2020-10-08 Christophe Lyon <christophe.lyon@linaro.org> 5317 5318 PR target/96914 5319 * config/arm/arm_mve.h (__arm_vcvtnq_u32_f32): New. 5320 53212020-10-16 Christophe Lyon <christophe.lyon@linaro.org> 5322 5323 Backported from master: 5324 2020-10-08 Christophe Lyon <christophe.lyon@linaro.org> 5325 5326 PR target/96914 5327 * config/arm/arm_mve.h (vqrdmlashq_n_u8, vqrdmlashq_n_u16) 5328 (vqrdmlashq_n_u32, vqrdmlahq_n_u8, vqrdmlahq_n_u16) 5329 (vqrdmlahq_n_u32, vqdmlahq_n_u8, vqdmlahq_n_u16, vqdmlahq_n_u32) 5330 (vmlaldavaxq_p_u16, vmlaldavaxq_p_u32): Remove. 5331 * config/arm/arm_mve_builtins.def (vqrdmlashq_n_u, vqrdmlahq_n_u) 5332 (vqdmlahq_n_u, vmlaldavaxq_p_u): Remove. 5333 * config/arm/unspecs.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) 5334 (VQRDMLASHQ_N_U) 5335 (VMLALDAVAXQ_P_U): Remove unspecs. 5336 * config/arm/iterators.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) 5337 (VQRDMLASHQ_N_U, VMLALDAVAXQ_P_U): Remove attributes. 5338 (VQDMLAHQ_N, VQRDMLAHQ_N, VQRDMLASHQ_N, VMLALDAVAXQ_P): Remove 5339 unsigned variants from iterators. 5340 * config/arm/mve.md (mve_vqdmlahq_n_<supf><mode>) 5341 (mve_vqrdmlahq_n_<supf><mode>) 5342 (mve_vqrdmlashq_n_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>): 5343 Update comment. 5344 53452020-10-16 Christophe Lyon <christophe.lyon@linaro.org> 5346 5347 Backported from master: 5348 2020-10-08 Christophe Lyon <christophe.lyon@linaro.org> 5349 5350 PR target/96914 5351 * config/arm/arm_mve.h (vqdmlashq, vqdmlashq_m): Define. 5352 * config/arm/arm_mve_builtins.def (vqdmlashq_n_s) 5353 (vqdmlashq_m_n_s,): New. 5354 * config/arm/unspecs.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New 5355 unspecs. 5356 * config/arm/iterators.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New 5357 attributes. 5358 (VQDMLASHQ_N): New iterator. 5359 * config/arm/mve.md (mve_vqdmlashq_n_, mve_vqdmlashq_m_n_s): New 5360 patterns. 5361 53622020-10-16 Jakub Jelinek <jakub@redhat.com> 5363 5364 Backported from master: 5365 2020-10-13 Jakub Jelinek <jakub@redhat.com> 5366 5367 PR rtl-optimization/97386 5368 * combine.c (simplify_shift_const_1): Don't optimize nested ROTATEs if 5369 they have different modes. 5370 53712020-10-16 Jakub Jelinek <jakub@redhat.com> 5372 5373 Backported from master: 5374 2020-10-08 Jakub Jelinek <jakub@redhat.com> 5375 5376 PR sanitizer/97294 5377 * tree-cfg.c (move_block_to_fn): Call notice_special_calls on 5378 call stmts being moved into dest_cfun. 5379 * omp-low.c (lower_rec_input_clauses): Set cfun->calls_alloca when 5380 adding __builtin_alloca_with_align call without gimplification. 5381 53822020-10-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5383 5384 Backported from master: 5385 2020-10-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5386 5387 PR target/97291 5388 * config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Modify array. 5389 (arm_strsbwbu_qualifiers): Likewise. 5390 (arm_strsbwbs_p_qualifiers): Likewise. 5391 (arm_strsbwbu_p_qualifiers): Likewise. 5392 * config/arm/arm_mve.h (__arm_vstrdq_scatter_base_wb_s64): Modify 5393 function definition. 5394 (__arm_vstrdq_scatter_base_wb_u64): Likewise. 5395 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. 5396 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. 5397 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. 5398 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. 5399 (__arm_vstrwq_scatter_base_wb_s32): Likewise. 5400 (__arm_vstrwq_scatter_base_wb_u32): Likewise. 5401 (__arm_vstrwq_scatter_base_wb_f32): Likewise. 5402 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. 5403 * config/arm/arm_mve_builtins.def (vstrwq_scatter_base_wb_add_u): Remove 5404 expansion for the builtin. 5405 (vstrwq_scatter_base_wb_add_s): Likewise. 5406 (vstrwq_scatter_base_wb_add_f): Likewise. 5407 (vstrdq_scatter_base_wb_add_u): Likewise. 5408 (vstrdq_scatter_base_wb_add_s): Likewise. 5409 (vstrwq_scatter_base_wb_p_add_u): Likewise. 5410 (vstrwq_scatter_base_wb_p_add_s): Likewise. 5411 (vstrwq_scatter_base_wb_p_add_f): Likewise. 5412 (vstrdq_scatter_base_wb_p_add_u): Likewise. 5413 (vstrdq_scatter_base_wb_p_add_s): Likewise. 5414 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Remove 5415 expand. 5416 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise. 5417 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Rename pattern to ... 5418 (mve_vstrwq_scatter_base_wb_<supf>v4si): This. 5419 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Remove expand. 5420 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise. 5421 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Rename pattern to ... 5422 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): This. 5423 (mve_vstrwq_scatter_base_wb_fv4sf): Remove expand. 5424 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. 5425 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Rename pattern to ... 5426 (mve_vstrwq_scatter_base_wb_fv4sf): This. 5427 (mve_vstrwq_scatter_base_wb_p_fv4sf): Remove expand. 5428 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. 5429 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Rename pattern to ... 5430 (mve_vstrwq_scatter_base_wb_p_fv4sf): This. 5431 (mve_vstrdq_scatter_base_wb_<supf>v2di): Remove expand. 5432 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise. 5433 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Rename pattern to ... 5434 (mve_vstrdq_scatter_base_wb_<supf>v2di): This. 5435 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Remove expand. 5436 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise. 5437 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Rename pattern to ... 5438 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): This. 5439 54402020-10-16 Joe Ramsay <Joe.Ramsay@arm.com> 5441 5442 Backported from master: 5443 2020-10-06 Joe Ramsay <joe.ramsay@arm.com> 5444 5445 * config/arm/arm-cpus.in: 5446 (ALL_FPU_INTERNAL): Remove vfp_base. 5447 (VFPv2): Remove vfp_base. 5448 (MVE): Remove vfp_base. 5449 (vfp_base): Redefine as implied bit dependent on MVE or FP 5450 (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. 5451 * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. 5452 * config/arm/parsecpu.awk: 5453 (gen_isa): Print implied bits and their dependencies to ISA header. 5454 (gen_data): Add parsing for implied feature bits. 5455 54562020-10-16 Martin Jambor <mjambor@suse.cz> 5457 5458 Backported from master: 5459 2020-10-07 Martin Jambor <mjambor@suse.cz> 5460 5461 PR ipa/96394 5462 * ipa-prop.c (update_indirect_edges_after_inlining): Do not add 5463 resolved speculation edges to vector of new direct edges even in 5464 presence of multiple speculative direct edges for a single call. 5465 54662020-10-16 Martin Liska <mliska@suse.cz> 5467 5468 Backported from master: 5469 2020-10-16 Martin Liska <mliska@suse.cz> 5470 5471 PR ipa/97404 5472 * ipa-prop.c (struct ipa_vr_ggc_hash_traits): 5473 Compare types of VRP as we can merge ranges of different types. 5474 54752020-10-15 Martin Liska <mliska@suse.cz> 5476 5477 Backported from master: 5478 2020-10-15 Martin Liska <mliska@suse.cz> 5479 5480 PR ipa/97295 5481 * profile-count.c (profile_count::to_frequency): Move part of 5482 gcc_assert to STATIC_ASSERT. 5483 * regs.h (REG_FREQ_FROM_BB): Do not use count.to_frequency for 5484 a function that does not have count_max initialized. 5485 54862020-10-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5487 5488 * config/aarch64/aarch64.c (neoversen2_tunings): Define. 5489 * config/aarch64/aarch64-cores.def (neoverse-n2): Use it. 5490 54912020-10-13 Alex Coplan <alex.coplan@arm.com> 5492 5493 Backported from master: 5494 2020-09-30 Alex Coplan <alex.coplan@arm.com> 5495 5496 PR target/97251 5497 * config/arm/arm.md (movsf): Relax TARGET_HARD_FLOAT to 5498 TARGET_VFP_BASE. 5499 (movdf): Likewise. 5500 * config/arm/vfp.md (no_literal_pool_df_immediate): Likewise. 5501 (no_literal_pool_sf_immediate): Likewise. 5502 55032020-10-13 Richard Sandiford <richard.sandiford@arm.com> 5504 5505 Backported from master: 5506 2020-09-25 Richard Sandiford <richard.sandiford@arm.com> 5507 5508 * config/arm/arm-protos.h (arm_mve_mode_and_operands_type_check): 5509 Delete. 5510 * config/arm/arm.c (arm_coproc_mem_operand_wb): Use a scale factor 5511 of 2 rather than 4 for 16-bit modes. 5512 (arm_mve_mode_and_operands_type_check): Delete. 5513 * config/arm/constraints.md (Uj): Allow writeback for Neon, 5514 but continue to disallow it for MVE. 5515 * config/arm/arm.md (*arm32_mov<HFBF:mode>): Add !TARGET_HAVE_MVE. 5516 * config/arm/vfp.md (*mov_load_vfp_hf16, *mov_store_vfp_hf16): Fold 5517 back into... 5518 (*mov<mode>_vfp_<mode>16): ...here but use Uj for the FPR memory 5519 constraints. Use for base MVE too. 5520 55212020-10-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5522 5523 Backported from master: 5524 2020-10-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5525 5526 PR target/97349 5527 * config/aarch64/arm_neon.h (vdupq_n_p8, vdupq_n_p16, 5528 vdupq_n_p64, vdupq_n_s8, vdupq_n_s16, vdupq_n_u8, vdupq_n_u16): 5529 Fix argument type. 5530 55312020-10-12 Richard Biener <rguenther@suse.de> 5532 5533 PR tree-optimization/97357 5534 * tree-ssa-loop-split.c (ssa_semi_invariant_p): Abnormal 5535 SSA names are not semi invariant. 5536 55372020-10-12 Richard Biener <rguenther@suse.de> 5538 5539 PR tree-optimization/97255 5540 * tree-vect-patterns.c (vect_recog_bool_pattern): Also handle 5541 VIEW_CONVERT_EXPR. 5542 55432020-10-09 Vladimir Makarov <vmakarov@redhat.com> 5544 5545 PR rtl-optimization/97313 5546 * lra-constraints.c (match_reload): Don't keep strict_low_part in 5547 reloads for non-registers. 5548 55492020-10-08 Martin Sebor <msebor@redhat.com> 5550 5551 PR middle-end/95189 5552 PR middle-end/95886 5553 * builtins.c (inline_expand_builtin_string_cmp): Rename... 5554 (inline_expand_builtin_bytecmp): ...to this. 5555 (builtin_memcpy_read_str): Don't expect data to be nul-terminated. 5556 (expand_builtin_memory_copy_args): Handle object representations 5557 with embedded nul bytes. 5558 (expand_builtin_memcmp): Same. 5559 (expand_builtin_strcmp): Adjust call to naming change. 5560 (expand_builtin_strncmp): Same. 5561 * expr.c (string_constant): Create empty strings with nonzero size. 5562 * fold-const.c (c_getstr): Rename locals and update comments. 5563 * tree.c (build_string): Accept null pointer argument. 5564 (build_string_literal): Same. 5565 * tree.h (build_string): Provide a default. 5566 (build_string_literal): Same. 5567 55682020-10-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5569 5570 Backported from master: 5571 2020-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5572 5573 PR target/97150 5574 * config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument 5575 signed. 5576 (vqrshlh_u16): Likewise. 5577 (vqrshls_u32): Likewise. 5578 (vqrshld_u64): Likewise. 5579 (vqshlb_u8): Likewise. 5580 (vqshlh_u16): Likewise. 5581 (vqshls_u32): Likewise. 5582 (vqshld_u64): Likewise. 5583 (vshld_u64): Likewise. 5584 55852020-10-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5586 5587 Backported from master: 5588 2020-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 5589 5590 PR target/96313 5591 * config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS 5592 qualifiers. 5593 * config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call. 5594 Remove unnecessary result cast. 5595 (vqmovun_s32): Likewise. 5596 (vqmovun_s64): Likewise. 5597 (vqmovunh_s16): Likewise. Fix return type. 5598 (vqmovuns_s32): Likewise. 5599 (vqmovund_s64): Likewise. 5600 56012020-10-08 Alan Modra <amodra@gmail.com> 5602 5603 Backported from master: 5604 2020-10-01 Alan Modra <amodra@gmail.com> 5605 5606 * config/rs6000/rs6000.c (rs6000_legitimize_address): Use 5607 gen_int_mode for high part of address constant. 5608 56092020-10-06 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5610 5611 Backported from master: 5612 2020-10-06 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 5613 5614 * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to 5615 iterators.md. 5616 (MVE_VLD_ST): Likewise. 5617 (MVE_0): Likewise. 5618 (MVE_1): Likewise. 5619 (MVE_3): Likewise. 5620 (MVE_2): Likewise. 5621 (MVE_5): Likewise. 5622 (MVE_6): Likewise. 5623 (MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md. 5624 (MVE_LANES): Likewise. 5625 (MVE_constraint): Likewise. 5626 (MVE_constraint1): Likewise. 5627 (MVE_constraint2): Likewise. 5628 (MVE_constraint3): Likewise. 5629 (MVE_pred): Likewise. 5630 (MVE_pred1): Likewise. 5631 (MVE_pred2): Likewise. 5632 (MVE_pred3): Likewise. 5633 (MVE_B_ELEM): Likewise. 5634 (MVE_H_ELEM): Likewise. 5635 (V_sz_elem1): Likewise. 5636 (V_extr_elem): Likewise. 5637 (earlyclobber_32): Likewise. 5638 (supf): Move int attribute from mve.md to iterators.md. 5639 (mode1): Likewise. 5640 (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md. 5641 (VMVNQ_N): Likewise. 5642 (VREV64Q): Likewise. 5643 (VCVTQ_FROM_F): Likewise. 5644 (VREV16Q): Likewise. 5645 (VCVTAQ): Likewise. 5646 (VMVNQ): Likewise. 5647 (VDUPQ_N): Likewise. 5648 (VCLZQ): Likewise. 5649 (VADDVQ): Likewise. 5650 (VREV32Q): Likewise. 5651 (VMOVLBQ): Likewise. 5652 (VMOVLTQ): Likewise. 5653 (VCVTPQ): Likewise. 5654 (VCVTNQ): Likewise. 5655 (VCVTMQ): Likewise. 5656 (VADDLVQ): Likewise. 5657 (VCTPQ): Likewise. 5658 (VCTPQ_M): Likewise. 5659 (VCVTQ_N_TO_F): Likewise. 5660 (VCREATEQ): Likewise. 5661 (VSHRQ_N): Likewise. 5662 (VCVTQ_N_FROM_F): Likewise. 5663 (VADDLVQ_P): Likewise. 5664 (VCMPNEQ): Likewise. 5665 (VSHLQ): Likewise. 5666 (VABDQ): Likewise. 5667 (VADDQ_N): Likewise. 5668 (VADDVAQ): Likewise. 5669 (VADDVQ_P): Likewise. 5670 (VANDQ): Likewise. 5671 (VBICQ): Likewise. 5672 (VBRSRQ_N): Likewise. 5673 (VCADDQ_ROT270): Likewise. 5674 (VCADDQ_ROT90): Likewise. 5675 (VCMPEQQ): Likewise. 5676 (VCMPEQQ_N): Likewise. 5677 (VCMPNEQ_N): Likewise. 5678 (VEORQ): Likewise. 5679 (VHADDQ): Likewise. 5680 (VHADDQ_N): Likewise. 5681 (VHSUBQ): Likewise. 5682 (VHSUBQ_N): Likewise. 5683 (VMAXQ): Likewise. 5684 (VMAXVQ): Likewise. 5685 (VMINQ): Likewise. 5686 (VMINVQ): Likewise. 5687 (VMLADAVQ): Likewise. 5688 (VMULHQ): Likewise. 5689 (VMULLBQ_INT): Likewise. 5690 (VMULLTQ_INT): Likewise. 5691 (VMULQ): Likewise. 5692 (VMULQ_N): Likewise. 5693 (VORNQ): Likewise. 5694 (VORRQ): Likewise. 5695 (VQADDQ): Likewise. 5696 (VQADDQ_N): Likewise. 5697 (VQRSHLQ): Likewise. 5698 (VQRSHLQ_N): Likewise. 5699 (VQSHLQ): Likewise. 5700 (VQSHLQ_N): Likewise. 5701 (VQSHLQ_R): Likewise. 5702 (VQSUBQ): Likewise. 5703 (VQSUBQ_N): Likewise. 5704 (VRHADDQ): Likewise. 5705 (VRMULHQ): Likewise. 5706 (VRSHLQ): Likewise. 5707 (VRSHLQ_N): Likewise. 5708 (VRSHRQ_N): Likewise. 5709 (VSHLQ_N): Likewise. 5710 (VSHLQ_R): Likewise. 5711 (VSUBQ): Likewise. 5712 (VSUBQ_N): Likewise. 5713 (VADDLVAQ): Likewise. 5714 (VBICQ_N): Likewise. 5715 (VMLALDAVQ): Likewise. 5716 (VMLALDAVXQ): Likewise. 5717 (VMOVNBQ): Likewise. 5718 (VMOVNTQ): Likewise. 5719 (VORRQ_N): Likewise. 5720 (VQMOVNBQ): Likewise. 5721 (VQMOVNTQ): Likewise. 5722 (VSHLLBQ_N): Likewise. 5723 (VSHLLTQ_N): Likewise. 5724 (VRMLALDAVHQ): Likewise. 5725 (VBICQ_M_N): Likewise. 5726 (VCVTAQ_M): Likewise. 5727 (VCVTQ_M_TO_F): Likewise. 5728 (VQRSHRNBQ_N): Likewise. 5729 (VABAVQ): Likewise. 5730 (VSHLCQ): Likewise. 5731 (VRMLALDAVHAQ): Likewise. 5732 (VADDVAQ_P): Likewise. 5733 (VCLZQ_M): Likewise. 5734 (VCMPEQQ_M_N): Likewise. 5735 (VCMPEQQ_M): Likewise. 5736 (VCMPNEQ_M_N): Likewise. 5737 (VCMPNEQ_M): Likewise. 5738 (VDUPQ_M_N): Likewise. 5739 (VMAXVQ_P): Likewise. 5740 (VMINVQ_P): Likewise. 5741 (VMLADAVAQ): Likewise. 5742 (VMLADAVQ_P): Likewise. 5743 (VMLAQ_N): Likewise. 5744 (VMLASQ_N): Likewise. 5745 (VMVNQ_M): Likewise. 5746 (VPSELQ): Likewise. 5747 (VQDMLAHQ_N): Likewise. 5748 (VQRDMLAHQ_N): Likewise. 5749 (VQRDMLASHQ_N): Likewise. 5750 (VQRSHLQ_M_N): Likewise. 5751 (VQSHLQ_M_R): Likewise. 5752 (VREV64Q_M): Likewise. 5753 (VRSHLQ_M_N): Likewise. 5754 (VSHLQ_M_R): Likewise. 5755 (VSLIQ_N): Likewise. 5756 (VSRIQ_N): Likewise. 5757 (VMLALDAVQ_P): Likewise. 5758 (VQMOVNBQ_M): Likewise. 5759 (VMOVLTQ_M): Likewise. 5760 (VMOVNBQ_M): Likewise. 5761 (VRSHRNTQ_N): Likewise. 5762 (VORRQ_M_N): Likewise. 5763 (VREV32Q_M): Likewise. 5764 (VREV16Q_M): Likewise. 5765 (VQRSHRNTQ_N): Likewise. 5766 (VMOVNTQ_M): Likewise. 5767 (VMOVLBQ_M): Likewise. 5768 (VMLALDAVAQ): Likewise. 5769 (VQSHRNBQ_N): Likewise. 5770 (VSHRNBQ_N): Likewise. 5771 (VRSHRNBQ_N): Likewise. 5772 (VMLALDAVXQ_P): Likewise. 5773 (VQMOVNTQ_M): Likewise. 5774 (VMVNQ_M_N): Likewise. 5775 (VQSHRNTQ_N): Likewise. 5776 (VMLALDAVAXQ): Likewise. 5777 (VSHRNTQ_N): Likewise. 5778 (VCVTMQ_M): Likewise. 5779 (VCVTNQ_M): Likewise. 5780 (VCVTPQ_M): Likewise. 5781 (VCVTQ_M_N_FROM_F): Likewise. 5782 (VCVTQ_M_FROM_F): Likewise. 5783 (VRMLALDAVHQ_P): Likewise. 5784 (VADDLVAQ_P): Likewise. 5785 (VABAVQ_P): Likewise. 5786 (VSHLQ_M): Likewise. 5787 (VSRIQ_M_N): Likewise. 5788 (VSUBQ_M): Likewise. 5789 (VCVTQ_M_N_TO_F): Likewise. 5790 (VHSUBQ_M): Likewise. 5791 (VSLIQ_M_N): Likewise. 5792 (VRSHLQ_M): Likewise. 5793 (VMINQ_M): Likewise. 5794 (VMULLBQ_INT_M): Likewise. 5795 (VMULHQ_M): Likewise. 5796 (VMULQ_M): Likewise. 5797 (VHSUBQ_M_N): Likewise. 5798 (VHADDQ_M_N): Likewise. 5799 (VORRQ_M): Likewise. 5800 (VRMULHQ_M): Likewise. 5801 (VQADDQ_M): Likewise. 5802 (VRSHRQ_M_N): Likewise. 5803 (VQSUBQ_M_N): Likewise. 5804 (VADDQ_M): Likewise. 5805 (VORNQ_M): Likewise. 5806 (VRHADDQ_M): Likewise. 5807 (VQSHLQ_M): Likewise. 5808 (VANDQ_M): Likewise. 5809 (VBICQ_M): Likewise. 5810 (VSHLQ_M_N): Likewise. 5811 (VCADDQ_ROT270_M): Likewise. 5812 (VQRSHLQ_M): Likewise. 5813 (VQADDQ_M_N): Likewise. 5814 (VADDQ_M_N): Likewise. 5815 (VMAXQ_M): Likewise. 5816 (VQSUBQ_M): Likewise. 5817 (VMLASQ_M_N): Likewise. 5818 (VMLADAVAQ_P): Likewise. 5819 (VBRSRQ_M_N): Likewise. 5820 (VMULQ_M_N): Likewise. 5821 (VCADDQ_ROT90_M): Likewise. 5822 (VMULLTQ_INT_M): Likewise. 5823 (VEORQ_M): Likewise. 5824 (VSHRQ_M_N): Likewise. 5825 (VSUBQ_M_N): Likewise. 5826 (VHADDQ_M): Likewise. 5827 (VABDQ_M): Likewise. 5828 (VMLAQ_M_N): Likewise. 5829 (VQSHLQ_M_N): Likewise. 5830 (VMLALDAVAQ_P): Likewise. 5831 (VMLALDAVAXQ_P): Likewise. 5832 (VQRSHRNBQ_M_N): Likewise. 5833 (VQRSHRNTQ_M_N): Likewise. 5834 (VQSHRNBQ_M_N): Likewise. 5835 (VQSHRNTQ_M_N): Likewise. 5836 (VRSHRNBQ_M_N): Likewise. 5837 (VRSHRNTQ_M_N): Likewise. 5838 (VSHLLBQ_M_N): Likewise. 5839 (VSHLLTQ_M_N): Likewise. 5840 (VSHRNBQ_M_N): Likewise. 5841 (VSHRNTQ_M_N): Likewise. 5842 (VSTRWSBQ): Likewise. 5843 (VSTRBSOQ): Likewise. 5844 (VSTRBQ): Likewise. 5845 (VLDRBGOQ): Likewise. 5846 (VLDRBQ): Likewise. 5847 (VLDRWGBQ): Likewise. 5848 (VLD1Q): Likewise. 5849 (VLDRHGOQ): Likewise. 5850 (VLDRHGSOQ): Likewise. 5851 (VLDRHQ): Likewise. 5852 (VLDRWQ): Likewise. 5853 (VLDRDGBQ): Likewise. 5854 (VLDRDGOQ): Likewise. 5855 (VLDRDGSOQ): Likewise. 5856 (VLDRWGOQ): Likewise. 5857 (VLDRWGSOQ): Likewise. 5858 (VST1Q): Likewise. 5859 (VSTRHSOQ): Likewise. 5860 (VSTRHSSOQ): Likewise. 5861 (VSTRHQ): Likewise. 5862 (VSTRWQ): Likewise. 5863 (VSTRDSBQ): Likewise. 5864 (VSTRDSOQ): Likewise. 5865 (VSTRDSSOQ): Likewise. 5866 (VSTRWSOQ): Likewise. 5867 (VSTRWSSOQ): Likewise. 5868 (VSTRWSBWBQ): Likewise. 5869 (VLDRWGBWBQ): Likewise. 5870 (VSTRDSBWBQ): Likewise. 5871 (VLDRDGBWBQ): Likewise. 5872 (VADCIQ): Likewise. 5873 (VADCIQ_M): Likewise. 5874 (VSBCQ): Likewise. 5875 (VSBCQ_M): Likewise. 5876 (VSBCIQ): Likewise. 5877 (VSBCIQ_M): Likewise. 5878 (VADCQ): Likewise. 5879 (VADCQ_M): Likewise. 5880 (UQRSHLLQ): Likewise. 5881 (SQRSHRLQ): Likewise. 5882 (VSHLCQ_M): Likewise. 5883 * config/arm/mve.md (MVE_types): Move mode iterator to iterators.md from mve.md. 5884 (MVE_VLD_ST): Likewise. 5885 (MVE_0): Likewise. 5886 (MVE_1): Likewise. 5887 (MVE_3): Likewise. 5888 (MVE_2): Likewise. 5889 (MVE_5): Likewise. 5890 (MVE_6): Likewise. 5891 (MVE_CNVT): Move mode attribute iterator to iterators.md from mve.md. 5892 (MVE_LANES): Likewise. 5893 (MVE_constraint): Likewise. 5894 (MVE_constraint1): Likewise. 5895 (MVE_constraint2): Likewise. 5896 (MVE_constraint3): Likewise. 5897 (MVE_pred): Likewise. 5898 (MVE_pred1): Likewise. 5899 (MVE_pred2): Likewise. 5900 (MVE_pred3): Likewise. 5901 (MVE_B_ELEM): Likewise. 5902 (MVE_H_ELEM): Likewise. 5903 (V_sz_elem1): Likewise. 5904 (V_extr_elem): Likewise. 5905 (earlyclobber_32): Likewise. 5906 (supf): Move int attribute to iterators.md from mve.md. 5907 (mode1): Likewise. 5908 (VCVTQ_TO_F): Move int iterator to iterators.md from mve.md. 5909 (VMVNQ_N): Likewise. 5910 (VREV64Q): Likewise. 5911 (VCVTQ_FROM_F): Likewise. 5912 (VREV16Q): Likewise. 5913 (VCVTAQ): Likewise. 5914 (VMVNQ): Likewise. 5915 (VDUPQ_N): Likewise. 5916 (VCLZQ): Likewise. 5917 (VADDVQ): Likewise. 5918 (VREV32Q): Likewise. 5919 (VMOVLBQ): Likewise. 5920 (VMOVLTQ): Likewise. 5921 (VCVTPQ): Likewise. 5922 (VCVTNQ): Likewise. 5923 (VCVTMQ): Likewise. 5924 (VADDLVQ): Likewise. 5925 (VCTPQ): Likewise. 5926 (VCTPQ_M): Likewise. 5927 (VCVTQ_N_TO_F): Likewise. 5928 (VCREATEQ): Likewise. 5929 (VSHRQ_N): Likewise. 5930 (VCVTQ_N_FROM_F): Likewise. 5931 (VADDLVQ_P): Likewise. 5932 (VCMPNEQ): Likewise. 5933 (VSHLQ): Likewise. 5934 (VABDQ): Likewise. 5935 (VADDQ_N): Likewise. 5936 (VADDVAQ): Likewise. 5937 (VADDVQ_P): Likewise. 5938 (VANDQ): Likewise. 5939 (VBICQ): Likewise. 5940 (VBRSRQ_N): Likewise. 5941 (VCADDQ_ROT270): Likewise. 5942 (VCADDQ_ROT90): Likewise. 5943 (VCMPEQQ): Likewise. 5944 (VCMPEQQ_N): Likewise. 5945 (VCMPNEQ_N): Likewise. 5946 (VEORQ): Likewise. 5947 (VHADDQ): Likewise. 5948 (VHADDQ_N): Likewise. 5949 (VHSUBQ): Likewise. 5950 (VHSUBQ_N): Likewise. 5951 (VMAXQ): Likewise. 5952 (VMAXVQ): Likewise. 5953 (VMINQ): Likewise. 5954 (VMINVQ): Likewise. 5955 (VMLADAVQ): Likewise. 5956 (VMULHQ): Likewise. 5957 (VMULLBQ_INT): Likewise. 5958 (VMULLTQ_INT): Likewise. 5959 (VMULQ): Likewise. 5960 (VMULQ_N): Likewise. 5961 (VORNQ): Likewise. 5962 (VORRQ): Likewise. 5963 (VQADDQ): Likewise. 5964 (VQADDQ_N): Likewise. 5965 (VQRSHLQ): Likewise. 5966 (VQRSHLQ_N): Likewise. 5967 (VQSHLQ): Likewise. 5968 (VQSHLQ_N): Likewise. 5969 (VQSHLQ_R): Likewise. 5970 (VQSUBQ): Likewise. 5971 (VQSUBQ_N): Likewise. 5972 (VRHADDQ): Likewise. 5973 (VRMULHQ): Likewise. 5974 (VRSHLQ): Likewise. 5975 (VRSHLQ_N): Likewise. 5976 (VRSHRQ_N): Likewise. 5977 (VSHLQ_N): Likewise. 5978 (VSHLQ_R): Likewise. 5979 (VSUBQ): Likewise. 5980 (VSUBQ_N): Likewise. 5981 (VADDLVAQ): Likewise. 5982 (VBICQ_N): Likewise. 5983 (VMLALDAVQ): Likewise. 5984 (VMLALDAVXQ): Likewise. 5985 (VMOVNBQ): Likewise. 5986 (VMOVNTQ): Likewise. 5987 (VORRQ_N): Likewise. 5988 (VQMOVNBQ): Likewise. 5989 (VQMOVNTQ): Likewise. 5990 (VSHLLBQ_N): Likewise. 5991 (VSHLLTQ_N): Likewise. 5992 (VRMLALDAVHQ): Likewise. 5993 (VBICQ_M_N): Likewise. 5994 (VCVTAQ_M): Likewise. 5995 (VCVTQ_M_TO_F): Likewise. 5996 (VQRSHRNBQ_N): Likewise. 5997 (VABAVQ): Likewise. 5998 (VSHLCQ): Likewise. 5999 (VRMLALDAVHAQ): Likewise. 6000 (VADDVAQ_P): Likewise. 6001 (VCLZQ_M): Likewise. 6002 (VCMPEQQ_M_N): Likewise. 6003 (VCMPEQQ_M): Likewise. 6004 (VCMPNEQ_M_N): Likewise. 6005 (VCMPNEQ_M): Likewise. 6006 (VDUPQ_M_N): Likewise. 6007 (VMAXVQ_P): Likewise. 6008 (VMINVQ_P): Likewise. 6009 (VMLADAVAQ): Likewise. 6010 (VMLADAVQ_P): Likewise. 6011 (VMLAQ_N): Likewise. 6012 (VMLASQ_N): Likewise. 6013 (VMVNQ_M): Likewise. 6014 (VPSELQ): Likewise. 6015 (VQDMLAHQ_N): Likewise. 6016 (VQRDMLAHQ_N): Likewise. 6017 (VQRDMLASHQ_N): Likewise. 6018 (VQRSHLQ_M_N): Likewise. 6019 (VQSHLQ_M_R): Likewise. 6020 (VREV64Q_M): Likewise. 6021 (VRSHLQ_M_N): Likewise. 6022 (VSHLQ_M_R): Likewise. 6023 (VSLIQ_N): Likewise. 6024 (VSRIQ_N): Likewise. 6025 (VMLALDAVQ_P): Likewise. 6026 (VQMOVNBQ_M): Likewise. 6027 (VMOVLTQ_M): Likewise. 6028 (VMOVNBQ_M): Likewise. 6029 (VRSHRNTQ_N): Likewise. 6030 (VORRQ_M_N): Likewise. 6031 (VREV32Q_M): Likewise. 6032 (VREV16Q_M): Likewise. 6033 (VQRSHRNTQ_N): Likewise. 6034 (VMOVNTQ_M): Likewise. 6035 (VMOVLBQ_M): Likewise. 6036 (VMLALDAVAQ): Likewise. 6037 (VQSHRNBQ_N): Likewise. 6038 (VSHRNBQ_N): Likewise. 6039 (VRSHRNBQ_N): Likewise. 6040 (VMLALDAVXQ_P): Likewise. 6041 (VQMOVNTQ_M): Likewise. 6042 (VMVNQ_M_N): Likewise. 6043 (VQSHRNTQ_N): Likewise. 6044 (VMLALDAVAXQ): Likewise. 6045 (VSHRNTQ_N): Likewise. 6046 (VCVTMQ_M): Likewise. 6047 (VCVTNQ_M): Likewise. 6048 (VCVTPQ_M): Likewise. 6049 (VCVTQ_M_N_FROM_F): Likewise. 6050 (VCVTQ_M_FROM_F): Likewise. 6051 (VRMLALDAVHQ_P): Likewise. 6052 (VADDLVAQ_P): Likewise. 6053 (VABAVQ_P): Likewise. 6054 (VSHLQ_M): Likewise. 6055 (VSRIQ_M_N): Likewise. 6056 (VSUBQ_M): Likewise. 6057 (VCVTQ_M_N_TO_F): Likewise. 6058 (VHSUBQ_M): Likewise. 6059 (VSLIQ_M_N): Likewise. 6060 (VRSHLQ_M): Likewise. 6061 (VMINQ_M): Likewise. 6062 (VMULLBQ_INT_M): Likewise. 6063 (VMULHQ_M): Likewise. 6064 (VMULQ_M): Likewise. 6065 (VHSUBQ_M_N): Likewise. 6066 (VHADDQ_M_N): Likewise. 6067 (VORRQ_M): Likewise. 6068 (VRMULHQ_M): Likewise. 6069 (VQADDQ_M): Likewise. 6070 (VRSHRQ_M_N): Likewise. 6071 (VQSUBQ_M_N): Likewise. 6072 (VADDQ_M): Likewise. 6073 (VORNQ_M): Likewise. 6074 (VRHADDQ_M): Likewise. 6075 (VQSHLQ_M): Likewise. 6076 (VANDQ_M): Likewise. 6077 (VBICQ_M): Likewise. 6078 (VSHLQ_M_N): Likewise. 6079 (VCADDQ_ROT270_M): Likewise. 6080 (VQRSHLQ_M): Likewise. 6081 (VQADDQ_M_N): Likewise. 6082 (VADDQ_M_N): Likewise. 6083 (VMAXQ_M): Likewise. 6084 (VQSUBQ_M): Likewise. 6085 (VMLASQ_M_N): Likewise. 6086 (VMLADAVAQ_P): Likewise. 6087 (VBRSRQ_M_N): Likewise. 6088 (VMULQ_M_N): Likewise. 6089 (VCADDQ_ROT90_M): Likewise. 6090 (VMULLTQ_INT_M): Likewise. 6091 (VEORQ_M): Likewise. 6092 (VSHRQ_M_N): Likewise. 6093 (VSUBQ_M_N): Likewise. 6094 (VHADDQ_M): Likewise. 6095 (VABDQ_M): Likewise. 6096 (VMLAQ_M_N): Likewise. 6097 (VQSHLQ_M_N): Likewise. 6098 (VMLALDAVAQ_P): Likewise. 6099 (VMLALDAVAXQ_P): Likewise. 6100 (VQRSHRNBQ_M_N): Likewise. 6101 (VQRSHRNTQ_M_N): Likewise. 6102 (VQSHRNBQ_M_N): Likewise. 6103 (VQSHRNTQ_M_N): Likewise. 6104 (VRSHRNBQ_M_N): Likewise. 6105 (VRSHRNTQ_M_N): Likewise. 6106 (VSHLLBQ_M_N): Likewise. 6107 (VSHLLTQ_M_N): Likewise. 6108 (VSHRNBQ_M_N): Likewise. 6109 (VSHRNTQ_M_N): Likewise. 6110 (VSTRWSBQ): Likewise. 6111 (VSTRBSOQ): Likewise. 6112 (VSTRBQ): Likewise. 6113 (VLDRBGOQ): Likewise. 6114 (VLDRBQ): Likewise. 6115 (VLDRWGBQ): Likewise. 6116 (VLD1Q): Likewise. 6117 (VLDRHGOQ): Likewise. 6118 (VLDRHGSOQ): Likewise. 6119 (VLDRHQ): Likewise. 6120 (VLDRWQ): Likewise. 6121 (VLDRDGBQ): Likewise. 6122 (VLDRDGOQ): Likewise. 6123 (VLDRDGSOQ): Likewise. 6124 (VLDRWGOQ): Likewise. 6125 (VLDRWGSOQ): Likewise. 6126 (VST1Q): Likewise. 6127 (VSTRHSOQ): Likewise. 6128 (VSTRHSSOQ): Likewise. 6129 (VSTRHQ): Likewise. 6130 (VSTRWQ): Likewise. 6131 (VSTRDSBQ): Likewise. 6132 (VSTRDSOQ): Likewise. 6133 (VSTRDSSOQ): Likewise. 6134 (VSTRWSOQ): Likewise. 6135 (VSTRWSSOQ): Likewise. 6136 (VSTRWSBWBQ): Likewise. 6137 (VLDRWGBWBQ): Likewise. 6138 (VSTRDSBWBQ): Likewise. 6139 (VLDRDGBWBQ): Likewise. 6140 (VADCIQ): Likewise. 6141 (VADCIQ_M): Likewise. 6142 (VSBCQ): Likewise. 6143 (VSBCQ_M): Likewise. 6144 (VSBCIQ): Likewise. 6145 (VSBCIQ_M): Likewise. 6146 (VADCQ): Likewise. 6147 (VADCQ_M): Likewise. 6148 (UQRSHLLQ): Likewise. 6149 (SQRSHRLQ): Likewise. 6150 (VSHLCQ_M): Likewise. 6151 (define_c_enum "unspec"): Move MVE enumerator to unspecs.md from mve.md. 6152 * config/arm/unspecs.md (define_c_enum "unspec"): Move MVE enumerator from 6153 mve.md to unspecs.md. 6154 61552020-10-06 Joe Ramsay <Joe.Ramsay@arm.com> 6156 6157 Backported from master: 6158 2020-10-02 Joe Ramsay <joe.ramsay@arm.com> 6159 6160 * config/arm/arm_mve.h (__arm_vmaxnmavq): Remove coercion of scalar 6161 argument. 6162 (__arm_vmaxnmvq): Likewise. 6163 (__arm_vminnmavq): Likewise. 6164 (__arm_vminnmvq): Likewise. 6165 (__arm_vmaxnmavq_p): Likewise. 6166 (__arm_vmaxnmvq_p): Likewise (and delete duplicate definition). 6167 (__arm_vminnmavq_p): Likewise. 6168 (__arm_vminnmvq_p): Likewise. 6169 (__arm_vmaxavq): Likewise. 6170 (__arm_vmaxavq_p): Likewise. 6171 (__arm_vmaxvq): Likewise. 6172 (__arm_vmaxvq_p): Likewise. 6173 (__arm_vminavq): Likewise. 6174 (__arm_vminavq_p): Likewise. 6175 (__arm_vminvq): Likewise. 6176 (__arm_vminvq_p): Likewise. 6177 61782020-10-06 Richard Biener <rguenther@suse.de> 6179 6180 PR tree-optimization/97236 6181 * tree-vect-stmts.c (get_group_load_store_type): Keep 6182 VMAT_ELEMENTWISE for single-element vectors. 6183 61842020-10-06 Andreas Krebbel <krebbel@linux.ibm.com> 6185 6186 Backported from master: 6187 2020-10-06 Andreas Krebbel <krebbel@linux.ibm.com> 6188 6189 * doc/invoke.texi: Add z15/arch13 to the list of documented 6190 -march/-mtune options. 6191 61922020-10-06 Andreas Krebbel <krebbel@linux.ibm.com> 6193 6194 Backported from master: 6195 2020-08-12 Andreas Krebbel <krebbel@linux.ibm.com> 6196 6197 PR target/96456 6198 * config/s390/s390.h (TARGET_NONSIGNALING_VECTOR_COMPARE_OK): New 6199 macro. 6200 * config/s390/vector.md (vcond_comparison_operator): Use new macro 6201 for the check. 6202 62032020-10-05 Alex Coplan <alex.coplan@arm.com> 6204 6205 * config/arm/arm-cpus.in (neoverse-v1): Add missing vendor and 6206 part numbers. 6207 62082020-10-02 Alex Coplan <alex.coplan@arm.com> 6209 6210 * config/arm/arm-cpus.in (neoverse-n2): New. 6211 * config/arm/arm-tables.opt: Regenerate. 6212 * config/arm/arm-tune.md: Regenerate. 6213 * doc/invoke.texi: Document support for Neoverse N2. 6214 62152020-10-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6216 6217 Backported from master: 6218 2020-10-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6219 6220 * config/aarch64/aarch64.c (neoversev1_tunings): Define. 6221 * config/aarch64/aarch64-cores.def (zeus): Use it. 6222 (neoverse-v1): Likewise. 6223 62242020-10-02 Martin Liska <mliska@suse.cz> 6225 6226 Backported from master: 6227 2020-10-02 Martin Liska <mliska@suse.cz> 6228 6229 PR gcov-profile/97193 6230 * coverage.c (coverage_init): GCDA note files should not be 6231 mangled and should end in output directory. 6232 62332020-10-01 Martin Liska <mliska@suse.cz> 6234 6235 Backported from master: 6236 2020-09-25 Martin Liska <mliska@suse.cz> 6237 6238 PR gcov-profile/64636 6239 * value-prof.c (stream_out_histogram_value): Allow negative 6240 values for HIST_TYPE_IOR. 6241 62422020-10-01 Martin Liska <mliska@suse.cz> 6243 6244 Backported from master: 6245 2020-09-29 Martin Liska <mliska@suse.cz> 6246 6247 PR tree-optimization/96979 6248 * tree-switch-conversion.c (jump_table_cluster::can_be_handled): 6249 Make a fast bail out. 6250 (bit_test_cluster::can_be_handled): Likewise here. 6251 * tree-switch-conversion.h (get_range): Use wi::to_wide instead 6252 of a folding. 6253 62542020-10-01 Martin Liska <mliska@suse.cz> 6255 6256 Backported from master: 6257 2020-09-23 Martin Liska <mliska@suse.cz> 6258 6259 PR gcov-profile/97069 6260 * profile.c (branch_prob): Line number must be at least 1. 6261 62622020-10-01 Michael Davidsaver <mdavidsaver@gmail.com> 6263 6264 * config/i386/t-rtems: Change from mtune to march when building 6265 multilibs. The mtune argument tunes or optimizes for a specific 6266 CPU model but does not ensure the generated code is appropriate 6267 for the CPU model. Prior to this patch, i386 compatible code 6268 was always generated but tuned for later models. 6269 62702020-10-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6271 6272 Backported from master: 6273 2020-09-30 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 6274 6275 PR target/96795 6276 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. 6277 (__arm_vaddq): Correct the scalar argument. 6278 (__arm_vaddq_m): Likewise. 6279 (__arm_vaddq_x): Likewise. 6280 (__arm_vcmpeqq_m): Likewise. 6281 (__arm_vcmpeqq): Likewise. 6282 (__arm_vcmpgeq_m): Likewise. 6283 (__arm_vcmpgeq): Likewise. 6284 (__arm_vcmpgtq_m): Likewise. 6285 (__arm_vcmpgtq): Likewise. 6286 (__arm_vcmpleq_m): Likewise. 6287 (__arm_vcmpleq): Likewise. 6288 (__arm_vcmpltq_m): Likewise. 6289 (__arm_vcmpltq): Likewise. 6290 (__arm_vcmpneq_m): Likewise. 6291 (__arm_vcmpneq): Likewise. 6292 (__arm_vfmaq_m): Likewise. 6293 (__arm_vfmaq): Likewise. 6294 (__arm_vfmasq_m): Likewise. 6295 (__arm_vfmasq): Likewise. 6296 (__arm_vmaxnmavq): Likewise. 6297 (__arm_vmaxnmavq_p): Likewise. 6298 (__arm_vmaxnmvq): Likewise. 6299 (__arm_vmaxnmvq_p): Likewise. 6300 (__arm_vminnmavq): Likewise. 6301 (__arm_vminnmavq_p): Likewise. 6302 (__arm_vminnmvq): Likewise. 6303 (__arm_vminnmvq_p): Likewise. 6304 (__arm_vmulq_m): Likewise. 6305 (__arm_vmulq): Likewise. 6306 (__arm_vmulq_x): Likewise. 6307 (__arm_vsetq_lane): Likewise. 6308 (__arm_vsubq_m): Likewise. 6309 (__arm_vsubq): Likewise. 6310 (__arm_vsubq_x): Likewise. 6311 63122020-10-01 Jakub Jelinek <jakub@redhat.com> 6313 6314 Backported from master: 6315 2020-10-01 Jakub Jelinek <jakub@redhat.com> 6316 6317 * config/s390/s390.c (s390_atomic_assign_expand_fenv): Use 6318 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to 6319 fenv_var and old_fpc. Formatting fixes. 6320 63212020-10-01 Joel Hutton <joel.hutton@arm.com> 6322 6323 Backported from master: 6324 2020-09-30 Joel Hutton <joel.hutton@arm.com> 6325 6326 PR target/96827 6327 * tree-vect-slp.c (vect_analyze_slp): Do not call 6328 vect_attempt_slp_rearrange_stmts for vector constructors. 6329 63302020-09-30 Jim Wilson <jimw@sifive.com> 6331 6332 PR bootstrap/97183 6333 * configure.ac (gcc_cv_header_zstd_h): Check ZSTD_VERISON_NUMBER. 6334 * configure: Regenerated. 6335 63362020-09-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6337 6338 Backported from master: 6339 2020-09-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6340 6341 * config/aarch64/aarch64-option-extensions.def (rng): Add 6342 cpuinfo string. 6343 63442020-09-30 H.J. Lu <hjl.tools@gmail.com> 6345 6346 Backported from master: 6347 2020-09-30 H.J. Lu <hjl.tools@gmail.com> 6348 6349 PR target/97184 6350 * config/i386/i386.md (UNSPECV_MOVDIRI): Renamed to ... 6351 (UNSPEC_MOVDIRI): This. 6352 (UNSPECV_MOVDIR64B): Renamed to ... 6353 (UNSPEC_MOVDIR64B): This. 6354 (movdiri<mode>): Use SET operation. 6355 (@movdir64b_<mode>): Likewise. 6356 63572020-09-29 H.J. Lu <hjl.tools@gmail.com> 6358 6359 Backported from master: 6360 2020-09-29 H.J. Lu <hjl.tools@gmail.com> 6361 6362 PR target/97247 6363 * config/i386/enqcmdintrin.h: Replace <enqcmdntrin.h> with 6364 <enqcmdintrin.h>. Replace _ENQCMDNTRIN_H_INCLUDED with 6365 _ENQCMDINTRIN_H_INCLUDED. 6366 63672020-09-29 Hongyu Wang <hongyu.wang@intel.com> 6368 6369 Backported from master: 6370 2020-09-29 Hongyu Wang <hongyu.wang@intel.com> 6371 6372 PR target/97231 6373 * config/i386/avx512vp2intersectintrin.h: Add FSF copyright notes. 6374 * config/i386/avx512vp2intersectvlintrin.h: Ditto. 6375 * config/i386/pconfigintrin.h: Ditto. 6376 * config/i386/wbnoinvdintrin.h: Ditto. 6377 63782020-09-29 Alex Coplan <alex.coplan@arm.com> 6379 6380 * config/aarch64/aarch64-cores.def: Add Neoverse N2. 6381 * config/aarch64/aarch64-tune.md: Regenerate. 6382 * doc/invoke.texi: Document AArch64 support for Neoverse N2. 6383 63842020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6385 6386 Backported from master: 6387 2020-09-18 Richard Sandiford <richard.sandiford@arm.com> 6388 6389 PR middle-end/97054 6390 * ira.c (ira_setup_eliminable_regset): Skip the special elimination 6391 handling of the hard frame pointer if the hard frame pointer is fixed. 6392 63932020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6394 6395 Backported from master: 6396 2020-09-24 Richard Sandiford <richard.sandiford@arm.com> 6397 6398 * config/arm/arm.md (*stack_protect_combined_set_insn): For non-PIC, 6399 load the address of the canary rather than the address of the 6400 constant pool entry that points to it. 6401 (*stack_protect_combined_test_insn): Likewise. 6402 64032020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6404 6405 Backported from master: 6406 2020-09-23 Richard Sandiford <richard.sandiford@arm.com> 6407 6408 * config/aarch64/aarch64-protos.h (aarch64_salt_type): New enum. 6409 (aarch64_stack_protect_canary_mem): Declare. 6410 * config/aarch64/aarch64.md (UNSPEC_SALT_ADDR): New unspec. 6411 (stack_protect_set): Forward to stack_protect_combined_set. 6412 (stack_protect_combined_set): New pattern. Use 6413 aarch64_stack_protect_canary_mem. 6414 (reg_stack_protect_address_<mode>): Add a salt operand. 6415 (stack_protect_test): Forward to stack_protect_combined_test. 6416 (stack_protect_combined_test): New pattern. Use 6417 aarch64_stack_protect_canary_mem. 6418 * config/aarch64/aarch64.c (strip_salt): New function. 6419 (strip_offset_and_salt): Likewise. 6420 (tls_symbolic_operand_type): Use strip_offset_and_salt. 6421 (aarch64_stack_protect_canary_mem): New function. 6422 (aarch64_cannot_force_const_mem): Use strip_offset_and_salt. 6423 (aarch64_classify_address): Likewise. 6424 (aarch64_symbolic_address_p): Likewise. 6425 (aarch64_print_operand): Likewise. 6426 (aarch64_output_addr_const_extra): New function. 6427 (aarch64_tls_symbol_p): Use strip_salt. 6428 (aarch64_classify_symbol): Likewise. 6429 (aarch64_legitimate_pic_operand_p): Use strip_offset_and_salt. 6430 (aarch64_legitimate_constant_p): Likewise. 6431 (aarch64_mov_operand_p): Use strip_salt. 6432 (TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Override. 6433 64342020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6435 6436 Backported from master: 6437 2020-08-25 Richard Sandiford <richard.sandiford@arm.com> 6438 6439 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Rename 6440 __ARM_FEATURE_SVE_VECTOR_OPERATIONS to 6441 __ARM_FEATURE_SVE_VECTOR_OPERATORS. 6442 64432020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6444 6445 Backported from master: 6446 2020-08-25 Richard Sandiford <richard.sandiford@arm.com> 6447 6448 * config/aarch64/aarch64-sve-builtins.cc (add_sve_type_attribute): 6449 Take the ACLE name of the type as a parameter and add it as fourth 6450 argument to the "SVE type" attribute. 6451 (register_builtin_types): Update call accordingly. 6452 (register_tuple_type): Likewise. Construct the name of the type 6453 earlier in order to do this. 6454 (get_arm_sve_vector_bits_attributes): New function. 6455 (handle_arm_sve_vector_bits_attribute): Report a more sensible 6456 error message if the attribute is applied to an SVE tuple type. 6457 Don't allow the attribute to be applied to an existing fixed-length 6458 SVE type. Mangle the new type as __SVE_VLS<type, vector-bits>. 6459 Add a dummy TYPE_DECL to the new type. 6460 64612020-09-29 Richard Sandiford <richard.sandiford@arm.com> 6462 6463 Backported from master: 6464 2020-08-25 Richard Sandiford <richard.sandiford@arm.com> 6465 6466 * config/aarch64/aarch64-sve-builtins.cc (DEF_SVE_TYPE): Add a 6467 leading "u" to each mangled name. 6468 64692020-09-29 Alex Coplan <alex.coplan@arm.com> 6470 6471 * config/arm/arm-cpus.in (neoverse-v1): New. 6472 * config/arm/arm-tables.opt: Regenerate. 6473 * config/arm/arm-tune.md: Regenerate. 6474 * doc/invoke.texi: Document AArch32 support for Neoverse V1. 6475 64762020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6477 6478 Backported from master: 6479 2020-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6480 6481 PR target/71233 6482 * config/aarch64/arm_neon.h (vreinterpretq_f64_p128, 6483 vreinterpretq_p128_f64): Define. 6484 64852020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6486 6487 Backported from master: 6488 2020-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6489 6490 PR target/71233 6491 * config/aarch64/aarch64-simd-builtins.def (frintn): Use BUILTIN_VHSDF_HSDF 6492 for modes. Remove explicit hf instantiation. 6493 * config/aarch64/arm_neon.h (vrndns_f32): Define. 6494 64952020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6496 6497 Backported from master: 6498 2020-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6499 6500 PR target/71233 6501 * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64, 6502 vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define. 6503 65042020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6505 6506 Backported from master: 6507 2020-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6508 6509 PR target/71233 6510 * config/aarch64/arm_neon.h (vldrq_p128): Define. 6511 65122020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6513 6514 Backported from master: 6515 2020-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6516 6517 PR target/71233 6518 * config/aarch64/arm_neon.h (vstrq_p128): Define. 6519 65202020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6521 6522 Backported from master: 6523 2020-09-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6524 6525 PR target/71233 6526 * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32, 6527 vclsq_u8, vclsq_u16, vclsq_u32): Define. 6528 65292020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6530 6531 Backported from master: 6532 2020-09-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6533 6534 PR target/71233 6535 * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64): Define. 6536 65372020-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6538 6539 Backported from master: 6540 2020-09-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 6541 6542 PR target/71233 6543 * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8, 6544 vaddq_p16, vaddq_p64, vaddq_p128): Define. 6545 65462020-09-27 Jakub Jelinek <jakub@redhat.com> 6547 6548 Backported from master: 6549 2020-09-27 Jakub Jelinek <jakub@redhat.com> 6550 6551 PR middle-end/97073 6552 * optabs.c (expand_binop, expand_absneg_bit, expand_unop, 6553 expand_copysign_bit): Check reg_overlap_mentioned_p between target 6554 and operand(s) and if it returns true, force a pseudo as target. 6555 65562020-09-25 Vladimir N. Makarov <vmakarov@redhat.com> 6557 6558 Backported from master: 6559 2020-06-04 Vladimir Makarov <vmakarov@redhat.com> 6560 6561 PR middle-end/95464 6562 * lra.c (lra_emit_move): Add processing STRICT_LOW_PART. 6563 * lra-constraints.c (match_reload): Use STRICT_LOW_PART in output 6564 reload if the original insn has it too. 6565 65662020-09-25 Joe Ramsay <Joe.Ramsay@arm.com> 6567 6568 Backported from master: 6569 2020-08-20 Joe Ramsay <Joe.Ramsay@arm.com> 6570 6571 PR target/96683 6572 * config/arm/mve.md (mve_vst1q_f<mode>): Require MVE memory operand for 6573 destination. 6574 (mve_vst1q_<supf><mode>): Likewise. 6575 65762020-09-24 H.J. Lu <hjl.tools@gmail.com> 6577 6578 Backported from master: 6579 2020-09-16 H.J. Lu <hjl.tools@gmail.com> 6580 6581 PR target/97032 6582 * cfgexpand.c (asm_clobber_reg_kind): Set sp_is_clobbered_by_asm 6583 to true if the stack pointer is clobbered by asm statement. 6584 * emit-rtl.h (rtl_data): Add sp_is_clobbered_by_asm. 6585 * config/i386/i386.c (ix86_get_drap_rtx): Set need_drap to true 6586 if the stack pointer is clobbered by asm statement. 6587 65882020-09-24 Alan Modra <amodra@gmail.com> 6589 6590 Backported from master: 6591 2020-09-24 Alan Modra <amodra@gmail.com> 6592 6593 PR target/97166 6594 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): 6595 Conditionally define __PCREL__. 6596 65972020-09-24 Andrea Corallo <andrea.corallo@arm.com> 6598 6599 Backported from master: 6600 2020-09-21 Andrea Corallo <andrea.corallo@arm.com> 6601 6602 * config/aarch64/aarch64-builtins.c 6603 (aarch64_general_expand_builtin): Use expand machinery not to 6604 alter the value of an rtx returned by force_reg. 6605 66062020-09-24 Alex Coplan <alex.coplan@arm.com> 6607 6608 * config/aarch64/aarch64-cores.def: Add Neoverse V1. 6609 * config/aarch64/aarch64-tune.md: Regenerate. 6610 * doc/invoke.texi: Document support for Neoverse V1. 6611 66122020-09-22 David Faust <david.faust@oracle.com> 6613 6614 Backported from master: 6615 2020-09-22 David Faust <david.faust@oracle.com> 6616 6617 * config/bpf/bpf.md: Add defines for signed div and mod operators. 6618 66192020-09-20 John David Anglin < danglin@gcc.gnu.org> 6620 6621 * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Delete. 6622 * config/pa/pa64-hpux.h (LINK_GCC_C_SEQUENCE_SPEC): Likewise. 6623 (ENDFILE_SPEC): Link with libgcc_stub.a and mill.a. 6624 * config/pa/pa32-linux.h (ENDFILE_SPEC): Link with libgcc.a. 6625 66262020-09-17 Marek Polacek <polacek@redhat.com> 6627 6628 Backported from master: 6629 2020-09-16 Marek Polacek <polacek@redhat.com> 6630 6631 PR preprocessor/96935 6632 * input.c (get_substring_ranges_for_loc): Return if start.column 6633 is less than 1. 6634 66352020-09-17 liuhongt <hongtao.liu@intel.com> 6636 6637 * common/config/i386/i386-common.c 6638 (OPTION_MASK_ISA_AVX_UNSET): Remove OPTION_MASK_ISA_XSAVE_UNSET. 6639 (OPTION_MASK_ISA_XSAVE_UNSET): Add OPTION_MASK_ISA_AVX_UNSET. 6640 66412020-09-16 Jakub Jelinek <jakub@redhat.com> 6642 6643 Backported from master: 6644 2020-09-16 Jakub Jelinek <jakub@redhat.com> 6645 6646 PR tree-optimization/97053 6647 * gimple-ssa-store-merging.c (check_no_overlap): Add FIRST_ORDER, 6648 START, FIRST_EARLIER and LAST_EARLIER arguments. Return false if 6649 any stores between FIRST_EARLIER inclusive and LAST_EARLIER exclusive 6650 has order in between FIRST_ORDER and LAST_ORDER and overlaps the to 6651 be merged store. 6652 (imm_store_chain_info::try_coalesce_bswap): Add FIRST_EARLIER argument. 6653 Adjust check_no_overlap caller. 6654 (imm_store_chain_info::coalesce_immediate_stores): Add first_earlier 6655 and last_earlier variables, adjust them during iterations. Adjust 6656 check_no_overlap callers, call check_no_overlap even when extending 6657 overlapping stores by extra INTEGER_CST stores. 6658 66592020-09-15 Will Schmidt <will_schmidt@vnet.ibm.com> 6660 6661 Backported from master: 6662 2020-09-03 Will Schmidt <will_schmidt@vnet.ibm.com> 6663 6664 * config/rs6000/rs6000-call.c (rs6000_init_builtin): Update V2DI_type_node 6665 and unsigned_V2DI_type_node definitions. 6666 66672020-09-15 Jakub Jelinek <jakub@redhat.com> 6668 6669 Backported from master: 6670 2020-09-15 Jakub Jelinek <jakub@redhat.com> 6671 6672 PR target/97028 6673 * config/i386/sse.md (mul<mode>3<mask_name>_bcs, 6674 <avx512>_div<mode>3<mask_name>_bcst): Use <avx512bcst> instead of 6675 <<avx512bcst>>. 6676 66772020-09-15 Richard Biener <rguenther@suse.de> 6678 6679 Backported from master: 6680 2020-08-25 Richard Biener <rguenther@suse.de> 6681 6682 PR debug/96690 6683 * dwarf2out.c (reference_to_unused): Make FUNCTION_DECL 6684 processing more consistent with respect to 6685 symtab->global_info_ready. 6686 (tree_add_const_value_attribute): Unconditionally call 6687 rtl_for_decl_init to do all mangling early but throw 6688 away the result if early_dwarf. 6689 66902020-09-14 Sergei Trofimovich <siarheit@google.com> 6691 6692 Backported from master: 6693 2020-09-14 Sergei Trofimovich <siarheit@google.com> 6694 6695 * doc/invoke.texi: fix '-fprofile-reproducibility' option 6696 spelling in manual. 6697 66982020-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> 6699 6700 Backported from master: 6701 2020-09-14 Jose E. Marchesi <jose.marchesi@oracle.com> 6702 6703 * config/bpf/bpf.md ("nop"): Re-define as `ja 0'. 6704 67052020-09-14 Richard Biener <rguenther@suse.de> 6706 6707 Backported from master: 6708 2020-08-27 Richard Biener <rguenther@suse.de> 6709 6710 PR tree-optimization/96522 6711 * tree-ssa-address.c (copy_ref_info): Reset flow-sensitive 6712 info of the copied points-to. Transfer bigger alignment 6713 via the access type. 6714 * tree-ssa-sccvn.c (eliminate_dom_walker::eliminate_stmt): 6715 Reset all flow-sensitive info. 6716 67172020-09-14 Richard Biener <rguenther@suse.de> 6718 6719 PR tree-optimization/97043 6720 * tree-vect-slp.c (vect_analyze_slp_instance): Do not 6721 elide a load permutation if the current vectorization 6722 factor is one. 6723 67242020-09-14 Nathan Sidwell <nathan@acm.org> 6725 6726 * config/i386/sse.md (mov<mode>): Fix operand indices. 6727 67282020-09-13 Roger Sayle <roger@nextmovesoftware.com> 6729 6730 * config/pa/pa.c (hppa_rtx_costs) [ASHIFT, ASHIFTRT, LSHIFTRT]: 6731 Provide accurate costs for DImode shifts of integer constants. 6732 67332020-09-12 Roger Sayle <roger@nextmovesoftware.com> 6734 John David Anglin <danglin@gcc.gnu.org> 6735 6736 * config/pa/pa.md (shrpsi4_1, shrpsi4_2): New define_insns split 6737 out from previous shrpsi4 providing two commutitive variants using 6738 plus_xor_ior_operator as a predicate. 6739 (shrpdi4_1, shrpdi4_2, shrpdi_3, shrpdi_4): Likewise DImode versions 6740 where _1 and _2 take register shifts, and _3 and _4 for integers. 6741 (rotlsi3_internal): Name this anonymous instruction. 6742 (rotrdi3): New DImode insn copied from rotrsi3. 6743 (rotldi3): New DImode expander copied from rotlsi3. 6744 (rotldi4_internal): New DImode insn copied from rotsi3_internal. 6745 67462020-09-11 Andrew Stubbs <ams@codesourcery.com> 6747 6748 Backported from master: 6749 2020-09-11 Andrew Stubbs <ams@codesourcery.com> 6750 6751 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align TImode registers. 6752 * config/gcn/gcn.md: Assert that TImode registers do not early clobber. 6753 67542020-09-11 Richard Biener <rguenther@suse.de> 6755 6756 Backported from master: 6757 2020-08-27 Richard Biener <rguenther@suse.de> 6758 6759 PR tree-optimization/96579 6760 * tree-ssa-reassoc.c (linearize_expr_tree): If we expand 6761 rhs via special ops make sure to swap operands. 6762 67632020-09-11 Richard Biener <rguenther@suse.de> 6764 6765 Backported from master: 6766 2020-07-30 Richard Biener <rguenther@suse.de> 6767 6768 PR tree-optimization/96370 6769 * tree-ssa-reassoc.c (rewrite_expr_tree): Add operation 6770 code parameter and use it instead of picking it up from 6771 the stmt that is being rewritten. 6772 (reassociate_bb): Pass down the operation code. 6773 67742020-09-11 Richard Biener <rguenther@suse.de> 6775 6776 Backported from master: 6777 2020-08-07 Richard Biener <rguenther@suse.de> 6778 6779 PR tree-optimization/96514 6780 * tree-if-conv.c (if_convertible_bb_p): If the last stmt 6781 is a call that is control-altering, fail. 6782 67832020-09-11 Richard Biener <rguenther@suse.de> 6784 6785 Backported from master: 6786 2020-07-31 Richard Biener <rguenther@suse.de> 6787 6788 PR middle-end/96369 6789 * fold-const.c (fold_range_test): Special-case constant 6790 LHS for short-circuiting operations. 6791 67922020-09-11 Richard Biener <rguenther@suse.de> 6793 6794 Backported from master: 6795 2020-07-29 Richard Biener <rguenther@suse.de> 6796 6797 PR tree-optimization/96349 6798 * tree-ssa-loop-split.c (stmt_semi_invariant_p_1): When the 6799 condition runs into a loop PHI with an abnormal entry value give up. 6800 68012020-09-11 Matthias Klose <doko@ubuntu.com> 6802 6803 Backported from master: 6804 2020-07-27 Matthias Klose <doko@ubuntu.com> 6805 6806 PR bootstrap/96203 6807 * common.opt: Add -fcf-protection=check. 6808 * flag-types.h (cf_protection_level): Add CF_CHECK. 6809 * lto-wrapper.c (merge_and_complain): Issue an error for 6810 mismatching -fcf-protection values with -fcf-protection=check. 6811 Otherwise, merge -fcf-protection values. 6812 * doc/invoke.texi: Document -fcf-protection=check. 6813 68142020-09-11 Matthias Klose <doko@ubuntu.com> 6815 6816 Backported from master: 6817 2020-07-14 Matthias Klose <doko@ubuntu.com> 6818 6819 PR lto/95604 6820 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, 6821 error on different values for -fcf-protection. 6822 (append_compiler_options): Pass -fcf-protection option. 6823 (find_and_merge_options): Add decoded options as parameter, 6824 pass decoded_options to merge_and_complain. 6825 (run_gcc): Pass decoded options to find_and_merge_options. 6826 * lto-opts.c (lto_write_options): Pass -fcf-protection option. 6827 68282020-09-11 Jakub Jelinek <jakub@redhat.com> 6829 6830 Backported from master: 6831 2020-09-10 Jakub Jelinek <jakub@redhat.com> 6832 6833 * lto-streamer-out.c (collect_block_tree_leafs): Recurse on 6834 root rather than BLOCK_SUBBLOCKS (root). 6835 68362020-09-11 Jakub Jelinek <jakub@redhat.com> 6837 6838 * lto-streamer.h (LTO_minor_version): Bump. 6839 68402020-09-11 Jakub Jelinek <jakub@redhat.com> 6841 6842 Backported from master: 6843 2020-09-10 Jakub Jelinek <jakub@redhat.com> 6844 6845 PR debug/93865 6846 * lto-streamer.h (struct output_block): Add emit_pwd member. 6847 * lto-streamer-out.c: Include toplev.h. 6848 (clear_line_info): Set emit_pwd. 6849 (lto_output_location_1): Encode the ob->current_file != xloc.file 6850 bit directly into the location number. If changing file, emit 6851 additionally a bit whether pwd is emitted and emit it before the 6852 first relative pathname since clear_line_info. 6853 (output_function, output_constructor): Don't call clear_line_info 6854 here. 6855 * lto-streamer-in.c (struct string_pair_map): New type. 6856 (struct string_pair_map_hasher): New type. 6857 (string_pair_map_hasher::hash): New method. 6858 (string_pair_map_hasher::equal): New method. 6859 (path_name_pair_hash_table, string_pair_map_allocator): New variables. 6860 (relative_path_prefix, canon_relative_path_prefix, 6861 canon_relative_file_name): New functions. 6862 (canon_file_name): Add relative_prefix argument, if non-NULL 6863 and string is a relative path, return canon_relative_file_name. 6864 (lto_location_cache::input_location_and_block): Decode file change 6865 bit from the location number. If changing file, unpack bit whether 6866 pwd is streamed and stream in pwd. Adjust canon_file_name caller. 6867 (lto_free_file_name_hash): Delete path_name_pair_hash_table 6868 and string_pair_map_allocator. 6869 68702020-09-11 Jakub Jelinek <jakub@redhat.com> 6871 6872 Backported from master: 6873 2020-09-07 Jakub Jelinek <jakub@redhat.com> 6874 6875 PR debug/94235 6876 * lto-streamer-out.c (output_cfg): Also stream goto_locus for edges. 6877 Use bp_pack_var_len_unsigned instead of streamer_write_uhwi to stream 6878 e->dest->index and e->flags. 6879 (output_function): Call output_cfg before output_ssa_name, rather than 6880 after streaming all bbs. 6881 * lto-streamer-in.c (input_cfg): Stream in goto_locus for edges. 6882 Use bp_unpack_var_len_unsigned instead of streamer_read_uhwi to stream 6883 in dest_index and edge_flags. 6884 68852020-09-11 Jakub Jelinek <jakub@redhat.com> 6886 6887 Backported from master: 6888 2020-09-04 Jakub Jelinek <jakub@redhat.com> 6889 6890 * lto-streamer.h (stream_input_location_now): Remove declaration. 6891 * lto-streamer-in.c (stream_input_location_now): Remove. 6892 (input_eh_region, input_struct_function_base): Use 6893 stream_input_location instead of stream_input_location_now. 6894 68952020-09-11 Jakub Jelinek <jakub@redhat.com> 6896 6897 Backported from master: 6898 2020-09-04 Jakub Jelinek <jakub@redhat.com> 6899 6900 * lto-streamer.h (struct output_block): Add reset_locus member. 6901 * lto-streamer-out.c (clear_line_info): Set reset_locus to true. 6902 (lto_output_location_1): If reset_locus, clear it and ensure 6903 current_{file,line,col} is different from xloc members. 6904 69052020-09-11 Jakub Jelinek <jakub@redhat.com> 6906 6907 Backported from master: 6908 2020-09-03 Jakub Jelinek <jakub@redhat.com> 6909 6910 PR c++/96901 6911 * tree.h (struct decl_tree_traits): New type. 6912 (decl_tree_map): New typedef. 6913 69142020-09-11 Jakub Jelinek <jakub@redhat.com> 6915 6916 Backported from master: 6917 2020-09-03 Jakub Jelinek <jakub@redhat.com> 6918 6919 PR lto/94311 6920 * gimple.h (gimple_location_ptr, gimple_phi_arg_location_ptr): New 6921 functions. 6922 * streamer-hooks.h (struct streamer_hooks): Add 6923 output_location_and_block callback. Fix up formatting for 6924 output_location. 6925 (stream_output_location_and_block): Define. 6926 * lto-streamer.h (class lto_location_cache): Fix comment typo. Add 6927 current_block member. 6928 (lto_location_cache::input_location_and_block): New method. 6929 (lto_location_cache::lto_location_cache): Initialize current_block. 6930 (lto_location_cache::cached_location): Add block member. 6931 (struct output_block): Add current_block member. 6932 (lto_output_location): Formatting fix. 6933 (lto_output_location_and_block): Declare. 6934 * lto-streamer.c (lto_streamer_hooks_init): Initialize 6935 streamer_hooks.output_location_and_block. 6936 * lto-streamer-in.c (lto_location_cache::cmp_loc): Also compare 6937 block members. 6938 (lto_location_cache::apply_location_cache): Handle blocks. 6939 (lto_location_cache::accept_location_cache, 6940 lto_location_cache::revert_location_cache): Fix up function comments. 6941 (lto_location_cache::input_location_and_block): New method. 6942 (lto_location_cache::input_location): Implement using 6943 input_location_and_block. 6944 (input_function): Invoke apply_location_cache after streaming in all 6945 bbs. 6946 * lto-streamer-out.c (clear_line_info): Set current_block. 6947 (lto_output_location_1): New function, moved from lto_output_location, 6948 added block handling. 6949 (lto_output_location): Implement using lto_output_location_1. 6950 (lto_output_location_and_block): New function. 6951 * gimple-streamer-in.c (input_phi): Use input_location_and_block 6952 to input and cache both location and block. 6953 (input_gimple_stmt): Likewise. 6954 * gimple-streamer-out.c (output_phi): Use 6955 stream_output_location_and_block. 6956 (output_gimple_stmt): Likewise. 6957 69582020-09-11 Jakub Jelinek <jakub@redhat.com> 6959 6960 Backported from master: 6961 2020-08-26 Jakub Jelinek <jakub@redhat.com> 6962 6963 PR debug/96729 6964 * dwarf2out.c (dwarf2out_next_real_insn): Adjust function comment. 6965 (dwarf2out_var_location): Look for next_note only if next_real is 6966 non-NULL, in that case look for the first non-deleted 6967 NOTE_INSN_VAR_LOCATION between loc_note and next_real, if any. 6968 69692020-09-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 6970 6971 PR target/96357 6972 * config/aarch64/aarch64-sve.md 6973 (cond_sub<mode>_relaxed_const): Updated and renamed from 6974 cond_sub<mode>_any_const pattern. 6975 (cond_sub<mode>_strict_const): New pattern. 6976 69772020-09-04 Carl Love <cel@us.ibm.com> 6978 6979 PR target/85830 6980 * config/rs6000/altivec.h (vec_popcntb, vec_popcnth, vec_popcntw, 6981 vec_popcntd): Remove defines. 6982 69832020-09-04 Martin Jambor <mjambor@suse.cz> 6984 6985 Backported from master: 6986 2020-09-03 Martin Jambor <mjambor@suse.cz> 6987 6988 PR tree-optimization/96820 6989 * tree-sra.c (create_access): Disqualify candidates with accesses 6990 beyond the end of the original aggregate. 6991 (maybe_add_sra_candidate): Check that candidate type size fits 6992 signed uhwi for the sake of consistency. 6993 69942020-09-04 David Faust <david.faust@oracle.com> 6995 6996 Backported from master: 6997 2020-09-04 David Faust <david.faust@oracle.com> 6998 6999 * config/bpf/bpf.h (ASM_SPEC): Pass -mxbpf to gas, if specified. 7000 * config/bpf/bpf.c (bpf_output_call): Support indirect calls in xBPF. 7001 70022020-09-03 Peter Bergner <bergner@linux.ibm.com> 7003 7004 Backported from master: 7005 2020-09-01 Peter Bergner <bergner@linux.ibm.com> 7006 7007 PR target/96808 7008 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Do not 7009 reuse accumulator memory reference for source and destination accesses. 7010 70112020-09-02 Jose E. Marchesi <jose.marchesi@oracle.com> 7012 7013 Backported from master: 7014 2020-09-02 Jose E. Marchesi <jose.marchesi@oracle.com> 7015 7016 * config/bpf/bpf.c (bpf_asm_named_section): Delete. 7017 (TARGET_ASM_NAMED_SECTION): Likewise. 7018 70192020-09-02 Jose E. Marchesi <jose.marchesi@oracle.com> 7020 7021 Backported from master: 7022 2020-09-02 Jose E. Marchesi <jemarch@gnu.org> 7023 7024 * config.gcc: Use elfos.h in bpf-*-* targets. 7025 * config/bpf/bpf.h (MAX_OFILE_ALIGNMENT): Remove definition. 7026 (COMMON_ASM_OP): Likewise. 7027 (INIT_SECTION_ASM_OP): Likewise. 7028 (FINI_SECTION_ASM_OP): Likewise. 7029 (ASM_OUTPUT_SKIP): Likewise. 7030 (ASM_OUTPUT_ALIGNED_COMMON): Likewise. 7031 (ASM_OUTPUT_ALIGNED_LOCAL): Likewise. 7032 70332020-09-01 Martin Liska <mliska@suse.cz> 7034 7035 Backported from master: 7036 2020-08-24 Martin Liska <mliska@suse.cz> 7037 7038 PR tree-optimization/96597 7039 * tree-ssa-sccvn.c (vn_reference_lookup_call): Add missing 7040 initialization of ::punned. 7041 (vn_reference_insert): Use consistently false instead of 0. 7042 (vn_reference_insert_pieces): Likewise. 7043 70442020-09-01 Richard Biener <rguenther@suse.de> 7045 7046 Backported from master: 7047 2020-08-04 Richard Biener <rguenther@suse.de> 7048 7049 PR tree-optimization/88240 7050 * tree-ssa-sccvn.h (vn_reference_s::punned): New flag. 7051 * tree-ssa-sccvn.c (vn_reference_insert): Initialize punned. 7052 (vn_reference_insert_pieces): Likewise. 7053 (visit_reference_op_call): Likewise. 7054 (visit_reference_op_load): Track whether a ref was punned. 7055 * tree-ssa-pre.c (do_hoist_insertion): Refuse to perform hoist 7056 insertion on punned floating point loads. 7057 70582020-08-31 Richard Biener <rguenther@suse.de> 7059 7060 PR tree-optimization/96854 7061 * tree-vect-loop.c (vectorizable_live_operation): Disallow 7062 SLP_TREE_TWO_OPERATORS nodes. 7063 70642020-08-31 liuhongt <hongtao.liu@intel.com> 7065 7066 PR target/96551 7067 * config/i386/sse.md (vec_unpacku_float_hi_v16si): For vector 7068 compare to integer mask, don't use gen_rtx_LT, use 7069 ix86_expand_mask_vec_cmp instead. 7070 (vec_unpacku_float_hi_v16si): Ditto. 7071 70722020-08-28 Uros Bizjak <ubizjak@gmail.com> 7073 7074 PR target/96744 7075 * config/i386/i386-expand.c (split_double_mode): Also handle 7076 E_P2HImode and E_P2QImode. 7077 * config/i386/sse.md (MASK_DWI): New define_mode_iterator. 7078 (mov<mode>): New expander for P2HI,P2QI. 7079 (*mov<mode>_internal): New define_insn_and_split to split 7080 movement of P2QI/P2HI to 2 movqi/movhi patterns after reload. 7081 70822020-08-28 liuhongt <hongtao.liu@intel.com> 7083 7084 * common/config/i386/i386-common.c (ix86_handle_option): Set 7085 AVX512DQ when AVX512VP2INTERSECT exists. 7086 70872020-08-27 Carl Love <cel@us.ibm.com> 7088 7089 * config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin 7090 macro expansion. 7091 (XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with 7092 BU_P10V_VSX_1. 7093 * config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, 7094 VSX_BUILTIN_XVCVBF16SPN): Replace with P10V_BUILTIN_XVCVSPBF16, 7095 P10V_BUILTIN_XVCVBF16SPN respectively. 7096 70972020-08-27 Christophe Lyon <christophe.lyon@linaro.org> 7098 7099 Backported from master: 7100 2020-08-24 Christophe Lyon <christophe.lyon@linaro.org> 7101 7102 PR target/94538 7103 PR target/94538 7104 * config/arm/thumb1.md: Disable set-constant splitter when 7105 TARGET_HAVE_MOVT. 7106 (thumb1_movsi_insn): Fix -mpure-code 7107 alternative. 7108 71092020-08-26 Roger Sayle <roger@nextmovesoftware.com> 7110 7111 PR middle-end/87256 7112 * config/pa/pa.c (hppa_rtx_costs_shadd_p): New helper function 7113 to check for coefficients supported by shNadd and shladd,l. 7114 (hppa_rtx_costs): Rewrite to avoid using estimates based upon 7115 FACTOR and enable recursing deeper into RTL expressions. 7116 * config/pa/pa.md (shd_internal): Fix define_expand to provide 7117 gen_shd_internal. 7118 71192020-08-26 Roger Sayle <roger@nextmovesoftware.com> 7120 7121 * config/pa/pa.md (ashldi3): Additionally, on !TARGET_64BIT 7122 generate a two instruction shd/zdep sequence when shifting 7123 registers by suitable constants. 7124 (shd_internal): New define_expand to provide gen_shd_internal. 7125 71262020-08-25 Jakub Jelinek <jakub@redhat.com> 7127 7128 Backported from master: 7129 2020-08-25 Jakub Jelinek <jakub@redhat.com> 7130 7131 PR tree-optimization/96722 7132 * gimple.c (infer_nonnull_range): Formatting fix. 7133 (infer_nonnull_range_by_dereference): Return false for clobber stmts. 7134 71352020-08-25 Jakub Jelinek <jakub@redhat.com> 7136 7137 Backported from master: 7138 2020-08-25 Jakub Jelinek <jakub@redhat.com> 7139 7140 PR tree-optimization/96758 7141 * tree-ssa-strlen.c (handle_builtin_string_cmp): If both cstlen1 7142 and cstlen2 are set, set cmpsiz to their minimum, otherwise use the 7143 one that is set. If bound is used and smaller than cmpsiz, set cmpsiz 7144 to bound. If both cstlen1 and cstlen2 are set, perform the optimization. 7145 71462020-08-25 Jakub Jelinek <jakub@redhat.com> 7147 7148 Backported from master: 7149 2020-08-25 Jakub Jelinek <jakub@redhat.com> 7150 7151 PR target/95450 7152 * fold-const.c (native_interpret_real): For MODE_COMPOSITE_P modes 7153 punt if the to be returned REAL_CST does not encode to the bitwise 7154 same representation. 7155 71562020-08-25 Jakub Jelinek <jakub@redhat.com> 7157 7158 Backported from master: 7159 2020-08-12 Jakub Jelinek <jakub@redhat.com> 7160 7161 PR tree-optimization/96535 7162 * toplev.c (process_options): Move flag_unroll_loops and 7163 flag_cunroll_grow_size handling from here to ... 7164 * opts.c (finish_options): ... here. For flag_cunroll_grow_size, 7165 don't check for AUTODETECT_VALUE, but instead check 7166 opts_set->x_flag_cunroll_grow_size. 7167 * common.opt (funroll-completely-grow-size): Default to 0. 7168 * config/rs6000/rs6000.c (TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): 7169 Redefine. 7170 (rs6000_override_options_after_change): New function. 7171 (rs6000_option_override_internal): Call it. Move there the 7172 flag_cunroll_grow_size, unroll_only_small_loops and 7173 flag_rename_registers handling. 7174 71752020-08-25 Jakub Jelinek <jakub@redhat.com> 7176 7177 Backported from master: 7178 2020-08-11 Jakub Jelinek <jakub@redhat.com> 7179 7180 PR c/96549 7181 * tree.c (get_narrower): Use TREE_TYPE (ret) instead of 7182 TREE_TYPE (win) for COMPOUND_EXPRs. 7183 71842020-08-25 Jakub Jelinek <jakub@redhat.com> 7185 7186 Backported from master: 7187 2020-08-08 Jakub Jelinek <jakub@redhat.com> 7188 7189 PR fortran/93553 7190 * tree-nested.c (convert_nonlocal_omp_clauses): For 7191 OMP_CLAUSE_REDUCTION, OMP_CLAUSE_LASTPRIVATE and OMP_CLAUSE_LINEAR 7192 save info->new_local_var_chain around walks of the clause gimple 7193 sequences and declare_vars if needed into the sequence. 7194 71952020-08-25 Jakub Jelinek <jakub@redhat.com> 7196 7197 Backported from master: 7198 2020-08-05 Jakub Jelinek <jakub@redhat.com> 7199 7200 PR middle-end/96459 7201 * omp-low.c (lower_omp_taskreg): Call lower_reduction_clauses even in 7202 for host teams. 7203 72042020-08-25 Martin Jambor <mjambor@suse.cz> 7205 7206 Backported from master: 7207 2020-08-25 Martin Jambor <mjambor@suse.cz> 7208 7209 PR tree-optimization/96730 7210 * tree-sra.c (create_access): Disqualify any aggregate with negative 7211 offset access. 7212 (build_ref_for_model): Add assert that offset is non-negative. 7213 72142020-08-21 Richard Sandiford <richard.sandiford@arm.com> 7215 7216 Backported from master: 7217 2020-08-21 Richard Sandiford <richard.sandiford@arm.com> 7218 7219 * doc/extend.texi: Update links to Arm docs. 7220 * doc/invoke.texi: Likewise. 7221 72222020-08-21 Tobias Burnus <tobias@codesourcery.com> 7223 7224 Backported from master: 7225 2020-05-26 Tobias Burnus <tobias@codesourcery.com> 7226 7227 PR ipa/95320 7228 * ipa-utils.h (odr_type_p): Also permit calls with 7229 only flag_generate_offload set. 7230 72312020-08-19 Joe Ramsay <joe.ramsay@arm.com> 7232 7233 Backported from master: 7234 2020-07-29 Joe Ramsay <joe.ramsay@arm.com> 7235 7236 PR target/96682 7237 * config/arm/arm-protos.h (arm_coproc_mem_operand_no_writeback): 7238 Declare prototype. 7239 (arm_mve_mode_and_operands_type_check): Declare prototype. 7240 * config/arm/arm.c (arm_coproc_mem_operand): Refactor to use 7241 _arm_coproc_mem_operand. 7242 (arm_coproc_mem_operand_wb): New function to cover full, limited 7243 and no writeback. 7244 (arm_coproc_mem_operand_no_writeback): New constraint for memory 7245 operand with no writeback. 7246 (arm_print_operand): Extend 'E' specifier for memory operand 7247 that does not support writeback. 7248 (arm_mve_mode_and_operands_type_check): New constraint check for 7249 MVE memory operands. 7250 * config/arm/constraints.md: Add Uj constraint for VFP vldr.16 7251 and vstr.16. 7252 * config/arm/vfp.md (*mov_load_vfp_hf16): New pattern for 7253 vldr.16. 7254 (*mov_store_vfp_hf16): New pattern for vstr.16. 7255 (*mov<mode>_vfp_<mode>16): Remove MVE moves. 7256 72572020-08-19 Peter Bergner <bergner@linux.ibm.com> 7258 7259 Backported from master: 7260 2020-08-18 Peter Bergner <bergner@linux.ibm.com> 7261 7262 * config/rs6000/rs6000-builtin.def (BU_VSX_1): Rename xvcvbf16sp to 7263 xvcvbf16spn. 7264 * config/rs6000/rs6000-call.c (builtin_function_type): Likewise. 7265 * config/rs6000/vsx.md: Likewise. 7266 * doc/extend.texi: Likewise. 7267 72682020-08-19 Peter Bergner <bergner@linux.ibm.com> 7269 7270 Backported from master: 7271 2020-08-13 Peter Bergner <bergner@linux.ibm.com> 7272 7273 PR target/96506 7274 * config/rs6000/rs6000-call.c (rs6000_promote_function_mode): Disallow 7275 MMA types as return values. 7276 (rs6000_function_arg): Disallow MMA types as function arguments. 7277 72782020-08-18 Uroš Bizjak <ubizjak@gmail.com> 7279 7280 PR target/96536 7281 * config/i386/i386.md (restore_stack_nonlocal): 7282 Add missing compare RTX. 7283 72842020-08-18 liuhongt <hongtao.liu@intel.com> 7285 7286 PR target/96562 7287 PR target/93897 7288 * config/i386/i386-expand.c (ix86_expand_pinsr): Don't use 7289 pinsr for TImode. 7290 (ix86_expand_pextr): Don't use pextr for TImode. 7291 72922020-08-14 Jan Hubicka <jh@suse.cz> 7293 7294 Backported from master: 7295 2020-05-29 Jan Hubicka <hubicka@ucw.cz> 7296 7297 PR lto/95362 7298 * lto-streamer-out.c (lto_output_tree): Disable redundant streaming. 7299 73002020-08-13 Jan Hubicka <jh@suse.cz> 7301 7302 * lto-streamer.h (LTO_minor_version): Bump version. 7303 73042020-08-13 Jan Hubicka <jh@suse.cz> 7305 7306 Backported from master: 7307 2020-06-06 Jan Hubicka <hubicka@ucw.cz> 7308 7309 PR lto/95548 7310 * ipa-devirt.c (struct odr_enum_val): Turn values to wide_int. 7311 (ipa_odr_summary_write): Update streaming. 7312 (ipa_odr_read_section): Update streaming. 7313 73142020-08-13 Jan Hubicka <jh@suse.cz> 7315 7316 Backported from master: 7317 2020-06-03 Jan Hubicka <hubicka@ucw.cz> 7318 7319 * ipa-devirt.c: Include data-streamer.h, lto-streamer.h and 7320 streamer-hooks.h. 7321 (odr_enums): New static var. 7322 (struct odr_enum_val): New struct. 7323 (class odr_enum): New struct. 7324 (odr_enum_map): New hashtable. 7325 (odr_types_equivalent_p): Drop code testing TYPE_VALUES. 7326 (add_type_duplicate): Likewise. 7327 (free_odr_warning_data): Do not free TYPE_VALUES. 7328 (register_odr_enum): New function. 7329 (ipa_odr_summary_write): New function. 7330 (ipa_odr_read_section): New function. 7331 (ipa_odr_summary_read): New function. 7332 (class pass_ipa_odr): New pass. 7333 (make_pass_ipa_odr): New function. 7334 * ipa-utils.h (register_odr_enum): Declare. 7335 * lto-section-in.c: (lto_section_name): Add odr_types section. 7336 * lto-streamer.h (enum lto_section_type): Add odr_types section. 7337 * passes.def: Add odr_types pass. 7338 * lto-streamer-out.c (DFS::DFS_write_tree_body): Do not stream 7339 TYPE_VALUES. 7340 (hash_tree): Likewise. 7341 * tree-streamer-in.c (lto_input_ts_type_non_common_tree_pointers): 7342 Likewise. 7343 * tree-streamer-out.c (write_ts_type_non_common_tree_pointers): 7344 Likewise. 7345 * timevar.def (TV_IPA_ODR): New timervar. 7346 * tree-pass.h (make_pass_ipa_odr): Declare. 7347 * tree.c (free_lang_data_in_type): Regiser ODR types. 7348 73492020-08-13 Jan Hubicka <jh@suse.cz> 7350 7351 Backported from master: 7352 2020-08-13 Jan Hubicka <jh@suse.cz> 7353 7354 * lto-streamer-out.c (lto_output_tree): Add streamer_debugging check. 7355 * lto-streamer.h (streamer_debugging): New constant 7356 * tree-streamer-in.c (streamer_read_tree_bitfields): Add 7357 streamer_debugging check. 7358 (streamer_get_pickled_tree): Likewise. 7359 * tree-streamer-out.c (pack_ts_base_value_fields): Likewise. 7360 73612020-08-13 Jan Hubicka <jh@suse.cz> 7362 7363 Backported from master: 7364 2020-08-13 Jan Hubicka <hubicka@ucw.cz> 7365 7366 * lto-streamer-out.c (lto_output_tree): Do not stream final ref if 7367 it is not needed. 7368 73692020-08-13 Jan Hubicka <jh@suse.cz> 7370 7371 Backported from master: 7372 2020-08-13 Jan Hubicka <jh@suse.cz> 7373 7374 * tree-streamer.c (record_common_node): Fix hash value of pre-streamed 7375 nodes. 7376 73772020-08-13 Jan Hubicka <jh@suse.cz> 7378 7379 Backported from master: 7380 2020-08-13 Jan Hubicka <hubicka@ucw.cz> 7381 7382 * lto-streamer-in.c (lto_read_tree): Do not stream end markers. 7383 (lto_input_scc): Optimize streaming of entry lengths. 7384 * lto-streamer-out.c (lto_write_tree): Do not stream end markers 7385 (DFS::DFS): Optimize stremaing of entry lengths 7386 73872020-08-13 Jan Hubicka <jh@suse.cz> 7388 7389 Backported from master: 7390 2020-08-13 Jan Hubicka <hubicka@ucw.cz> 7391 7392 * lto-streamer-in.c (lto_input_scc): Add SHARED_SCC parameter. 7393 (lto_input_tree_1): Strenghten sanity check. 7394 (lto_input_tree): Update call of lto_input_scc. 7395 * lto-streamer-out.c: Include ipa-utils.h 7396 (create_output_block): Initialize local_trees if merigng is going 7397 to happen. 7398 (destroy_output_block): Destroy local_trees. 7399 (DFS): Add max_local_entry. 7400 (local_tree_p): New function. 7401 (DFS::DFS): Initialize and maintain it. 7402 (DFS::DFS_write_tree): Decide on streaming format. 7403 (lto_output_tree): Stream inline singleton SCCs 7404 * lto-streamer.h (enum LTO_tags): Add LTO_trees. 7405 (struct output_block): Add local_trees. 7406 (lto_input_scc): Update prototype. 7407 74082020-08-13 Martin Liska <mliska@suse.cz> 7409 7410 Backported from master: 7411 2020-08-13 Martin Liska <mliska@suse.cz> 7412 7413 PR ipa/96482 7414 * ipa-cp.c (ipcp_bits_lattice::meet_with_1): Mask m_value 7415 with m_mask. 7416 74172020-08-12 Alan Modra <amodra@gmail.com> 7418 7419 Backported from master: 7420 2020-08-07 Alan Modra <amodra@gmail.com> 7421 7422 PR target/96493 7423 * config/rs6000/predicates.md (current_file_function_operand): Don't 7424 accept functions that differ in r2 usage. 7425 74262020-08-12 Martin Liska <mliska@suse.cz> 7427 7428 Backported from master: 7429 2020-08-12 Martin Liska <mliska@suse.cz> 7430 7431 PR ipa/96482 7432 * ipa-cp.c (ipcp_bits_lattice::meet_with_1): Drop value bits 7433 for bits that are unknown. 7434 (ipcp_bits_lattice::set_to_constant): Likewise. 7435 * tree-ssa-ccp.c (get_default_value): Add sanity check that 7436 IPA CP bit info has all bits set to zero in bits that 7437 are unknown. 7438 74392020-08-12 Sergei Trofimovich <siarheit@google.com> 7440 7441 Backported from master: 7442 2020-07-28 Sergei Trofimovich <siarheit@google.com> 7443 7444 PR ipa/96291 7445 * ipa-cp.c (has_undead_caller_from_outside_scc_p): Consider 7446 unoptimized callers as undead. 7447 74482020-08-12 Jose E. Marchesi <jose.marchesi@oracle.com> 7449 7450 * config/bpf/bpf.md: Remove trailing whitespaces. 7451 * config/bpf/constraints.md: Likewise. 7452 * config/bpf/predicates.md: Likewise. 7453 74542020-08-12 Jose E. Marchesi <jose.marchesi@oracle.com> 7455 7456 * config/bpf/bpf-helpers.h (KERNEL_HELPER): Define. 7457 (KERNEL_VERSION): Remove. 7458 * config/bpf/bpf-helpers.def: Delete. 7459 * config/bpf/bpf.c (bpf_handle_fndecl_attribute): New function. 7460 (bpf_attribute_table): Define. 7461 (bpf_helper_names): Delete. 7462 (bpf_helper_code): Likewise. 7463 (enum bpf_builtins): Adjust to new helpers mechanism. 7464 (bpf_output_call): Likewise. 7465 (bpf_init_builtins): Likewise. 7466 (bpf_init_builtins): Likewise. 7467 * doc/extend.texi (BPF Function Attributes): New section. 7468 (BPF Kernel Helpers): Delete section. 7469 74702020-08-12 Jose E. Marchesi <jose.marchesi@oracle.com> 7471 7472 * config/bpf/bpf.c (bpf_compute_frame_layout): Include space for 7473 callee saved registers only in xBPF. 7474 (bpf_expand_prologue): Save callee saved registers only in xBPF. 7475 (bpf_expand_epilogue): Likewise for restoring. 7476 * doc/invoke.texi (eBPF Options): Document this is activated by 7477 -mxbpf. 7478 74792020-08-12 Jose E. Marchesi <jose.marchesi@oracle.com> 7480 7481 * config/bpf/bpf.opt (mxbpf): New option. 7482 * doc/invoke.texi (Option Summary): Add -mxbpf. 7483 (eBPF Options): Document -mxbbpf. 7484 74852020-08-10 Hongtao Liu <hongtao.liu@intel.com> 7486 7487 PR target/96243 7488 * config/i386/i386-expand.c (ix86_expand_sse_cmp): Refine for 7489 maskcmp. 7490 (ix86_expand_mask_vec_cmp): Change prototype. 7491 * config/i386/i386-protos.h (ix86_expand_mask_vec_cmp): Change prototype. 7492 * config/i386/i386.c (ix86_print_operand): Remove operand 7493 modifier 'I'. 7494 * config/i386/sse.md 7495 (*<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>): Deleted. 7496 (*<avx512>_cmp<mode>3<mask_scalar_merge_name>): Ditto. 7497 (*<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Ditto. 7498 (*<avx512>_ucmp<mode>3<mask_scalar_merge_name>, 7499 avx512f_maskcmp<mode>3): Ditto. 7500 75012020-08-10 Martin Liska <mliska@suse.cz> 7502 7503 Backported from master: 7504 2020-05-20 Martin Liska <mliska@suse.cz> 7505 7506 * lto-compress.c (lto_compression_zstd): Fill up 7507 num_compressed_il_bytes. 7508 (lto_uncompression_zstd): Likewise for num_uncompressed_il_bytes here. 7509 75102020-08-10 Peter Bergner <bergner@linux.ibm.com> 7511 7512 Backported from master: 7513 2020-08-08 Peter Bergner <bergner@linux.ibm.com> 7514 7515 PR target/96530 7516 * config/rs6000/rs6000.c (rs6000_invalid_conversion): Use canonical 7517 types for type comparisons. Refactor code to simplify it. 7518 75192020-08-08 Peter Bergner <bergner@linux.ibm.com> 7520 7521 Backported from master: 7522 2020-08-06 Peter Bergner <bergner@linux.ibm.com> 7523 7524 PR target/96446 7525 * config/rs6000/mma.md (*movpxi): Add xxsetaccz generation. 7526 Disable split for zero constant source operand. 7527 (mma_xxsetaccz): Change to define_expand. Call gen_movpxi. 7528 75292020-08-07 Tamar Christina <tamar.christina@arm.com> 7530 7531 Backported from master: 7532 2020-08-03 Tamar Christina <tamar.christina@arm.com> 7533 7534 * config/aarch64/driver-aarch64.c (readline): Check return value fgets. 7535 75362020-08-07 Tamar Christina <tamar.christina@arm.com> 7537 7538 Backported from master: 7539 2020-07-17 Tamar Christina <tamar.christina@arm.com> 7540 7541 * doc/sourcebuild.texi (dg-set-compiler-env-var, 7542 dg-set-target-env-var): Document. 7543 75442020-08-07 Tamar Christina <tamar.christina@arm.com> 7545 7546 Backported from master: 7547 2020-07-17 Tamar Christina <tamar.christina@arm.com> 7548 7549 * config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO. 7550 75512020-08-07 Tamar Christina <tamar.christina@arm.com> 7552 7553 Backported from master: 7554 2020-07-17 Tamar Christina <tamar.christina@arm.com> 7555 7556 * config/aarch64/driver-aarch64.c (host_detect_local_cpu): 7557 Add GCC_CPUINFO. 7558 75592020-08-07 Tamar Christina <tamar.christina@arm.com> 7560 7561 Backported from master: 7562 2020-07-17 Tamar Christina <tamar.christina@arm.com> 7563 7564 * config/aarch64/driver-aarch64.c (INCLUDE_SET): New. 7565 (parse_field): Use std::string. 7566 (split_words, readline, find_field): New. 7567 (host_detect_local_cpu): Fix truncation issues. 7568 75692020-08-07 Richard Sandiford <richard.sandiford@arm.com> 7570 7571 Backported from master: 7572 2020-08-06 Richard Sandiford <richard.sandiford@arm.com> 7573 7574 PR target/96191 7575 * config/arm/arm.md (arm_stack_protect_test_insn): Zero out 7576 operand 2 after use. 7577 * config/arm/thumb1.md (thumb1_stack_protect_test_insn): Likewise. 7578 75792020-08-07 Richard Sandiford <richard.sandiford@arm.com> 7580 7581 Backported from master: 7582 2020-08-05 Richard Sandiford <richard.sandiford@arm.com> 7583 7584 PR target/96191 7585 * config/aarch64/aarch64.md (stack_protect_test_<mode>): Set the 7586 CC register directly, instead of a GPR. Replace the original GPR 7587 destination with an extra scratch register. Zero out operand 3 7588 after use. 7589 (stack_protect_test): Update accordingly. 7590 75912020-08-06 Richard Biener <rguenther@suse.de> 7592 7593 Backported from master: 7594 2020-08-06 Richard Biener <rguenther@suse.de> 7595 7596 PR tree-optimization/96483 7597 * tree-ssa-pre.c (create_component_ref_by_pieces_1): Handle 7598 POLY_INT_CST. 7599 76002020-08-04 Jakub Jelinek <jakub@redhat.com> 7601 7602 Backported from master: 7603 2020-08-04 Jakub Jelinek <jakub@redhat.com> 7604 7605 * doc/extend.texi (symver): Add @cindex for symver function attribute. 7606 76072020-08-04 Matthew Malcomson <matthew.malcomson@arm.com> 7608 7609 * config/aarch64/aarch64-protos.h (aarch64_indirect_call_asm): 7610 New declaration. 7611 * config/aarch64/aarch64.c (aarch64_regno_regclass): Handle new 7612 stub registers class. 7613 (aarch64_class_max_nregs): Likewise. 7614 (aarch64_register_move_cost): Likewise. 7615 (aarch64_sls_shared_thunks): Global array to store stub labels. 7616 (aarch64_sls_emit_function_stub): New. 7617 (aarch64_create_blr_label): New. 7618 (aarch64_sls_emit_blr_function_thunks): New. 7619 (aarch64_sls_emit_shared_blr_thunks): New. 7620 (aarch64_asm_file_end): New. 7621 (aarch64_indirect_call_asm): New. 7622 (TARGET_ASM_FILE_END): Use aarch64_asm_file_end. 7623 (TARGET_ASM_FUNCTION_EPILOGUE): Use 7624 aarch64_sls_emit_blr_function_thunks. 7625 * config/aarch64/aarch64.h (STB_REGNUM_P): New. 7626 (enum reg_class): Add STUB_REGS class. 7627 (machine_function): Introduce `call_via` array for 7628 function-local stub labels. 7629 * config/aarch64/aarch64.md (*call_insn, *call_value_insn): Use 7630 aarch64_indirect_call_asm to emit code when hardening BLR 7631 instructions. 7632 * config/aarch64/constraints.md (Ucr): New constraint 7633 representing registers for indirect calls. Is GENERAL_REGS 7634 usually, and STUB_REGS when hardening BLR instruction against 7635 SLS. 7636 * config/aarch64/predicates.md (aarch64_general_reg): STUB_REGS class 7637 is also a general register. 7638 76392020-08-04 Matthew Malcomson <matthew.malcomson@arm.com> 7640 7641 * config/aarch64/aarch64-protos.h (aarch64_sls_barrier): New. 7642 * config/aarch64/aarch64.c (aarch64_output_casesi): Emit 7643 speculation barrier after BR instruction if needs be. 7644 (aarch64_trampoline_init): Handle ptr_mode value & adjust size 7645 of code copied. 7646 (aarch64_sls_barrier): New. 7647 (aarch64_asm_trampoline_template): Add needed barriers. 7648 * config/aarch64/aarch64.h (AARCH64_ISA_SB): New. 7649 (TARGET_SB): New. 7650 (TRAMPOLINE_SIZE): Account for barrier. 7651 * config/aarch64/aarch64.md (indirect_jump, *casesi_dispatch, 7652 simple_return, *do_return, *sibcall_insn, *sibcall_value_insn): 7653 Emit barrier if needs be, also account for possible barrier using 7654 "sls_length" attribute. 7655 (sls_length): New attribute. 7656 (length): Determine default using any non-default sls_length 7657 value. 7658 76592020-08-04 Matthew Malcomson <matthew.malcomson@arm.com> 7660 7661 * config/aarch64/aarch64-protos.h (aarch64_harden_sls_retbr_p): 7662 New. 7663 (aarch64_harden_sls_blr_p): New. 7664 * config/aarch64/aarch64.c (enum aarch64_sls_hardening_type): 7665 New. 7666 (aarch64_harden_sls_retbr_p): New. 7667 (aarch64_harden_sls_blr_p): New. 7668 (aarch64_validate_sls_mitigation): New. 7669 (aarch64_override_options): Parse options for SLS mitigation. 7670 * config/aarch64/aarch64.opt (-mharden-sls): New option. 7671 * doc/invoke.texi: Document new option. 7672 76732020-08-04 Andrea Corallo <andrea.corallo@arm.com> 7674 7675 Backported from master: 7676 2020-08-04 Andrea Corallo <andrea.corallo@arm.com> 7677 7678 * config/aarch64/aarch64.md (aarch64_fjcvtzs): Add missing 7679 clobber. 7680 * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new 7681 target supports option. 7682 76832020-08-04 Jakub Jelinek <jakub@redhat.com> 7684 7685 Backported from master: 7686 2020-08-04 Jakub Jelinek <jakub@redhat.com> 7687 7688 PR middle-end/96426 7689 * tree-vect-generic.c (expand_vector_conversion): Replace .VEC_CONVERT 7690 call with GIMPLE_NOP if there is no lhs. 7691 76922020-08-04 Jakub Jelinek <jakub@redhat.com> 7693 7694 Backported from master: 7695 2020-08-04 Jakub Jelinek <jakub@redhat.com> 7696 7697 PR debug/96354 7698 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Add IS_DEBUG 7699 argument. Return false instead of gcc_unreachable if it is true and 7700 get_addr_base_and_unit_offset returns NULL. 7701 (fold_stmt_1) <case GIMPLE_DEBUG>: Adjust caller. 7702 77032020-08-03 Jonathan Wakely <jwakely@redhat.com> 7704 7705 Backported from master: 7706 2020-08-03 Jonathan Wakely <jwakely@redhat.com> 7707 7708 * doc/cpp.texi (Variadic Macros): Use the exact ... token in 7709 code examples. 7710 77112020-08-03 Richard Sandiford <richard.sandiford@arm.com> 7712 7713 Backported from master: 7714 2020-08-03 Richard Sandiford <richard.sandiford@arm.com> 7715 7716 * doc/invoke.texi: Add missing comma after octeontx2f95mm entry. 7717 77182020-08-03 Qian Jianhua <qianjh@cn.fujitsu.com> 7719 7720 Backported from master: 7721 2020-08-03 Qian jianhua <qianjh@cn.fujitsu.com> 7722 7723 * config/aarch64/aarch64-cores.def (a64fx): New core. 7724 * config/aarch64/aarch64-tune.md: Regenerated. 7725 * config/aarch64/aarch64.c (a64fx_prefetch_tune, a64fx_tunings): New. 7726 * doc/invoke.texi: Add a64fx to the list. 7727 77282020-07-31 Martin Liska <mliska@suse.cz> 7729 7730 Backported from master: 7731 2020-07-31 Martin Liska <mliska@suse.cz> 7732 7733 * cgraph.h: Remove leading empty lines. 7734 * cgraphunit.c (enum cgraph_order_sort_kind): Remove 7735 ORDER_UNDEFINED. 7736 (struct cgraph_order_sort): Add constructors. 7737 (cgraph_order_sort::process): New. 7738 (cgraph_order_cmp): New. 7739 (output_in_order): Simplify and push nodes to vector. 7740 77412020-07-30 Martin Liska <mliska@suse.cz> 7742 7743 Backported from master: 7744 2020-07-30 Martin Liska <mliska@suse.cz> 7745 7746 PR target/95435 7747 * config/i386/x86-tune-costs.h: Use libcall for large sizes for 7748 -m32. Start using libcall from 128+ bytes. 7749 77502020-07-30 Martin Liska <mliska@suse.cz> 7751 7752 Backported from master: 7753 2020-07-30 Martin Liska <mliska@suse.cz> 7754 7755 * config/i386/x86-tune-costs.h: Change code formatting. 7756 77572020-07-28 Martin Liska <mliska@suse.cz> 7758 7759 Backported from master: 7760 2020-07-27 Martin Liska <mliska@suse.cz> 7761 7762 PR tree-optimization/96058 7763 * expr.c (string_constant): Build string_constant only 7764 for a type that has same precision as char_type_node 7765 and is an integral type. 7766 77672020-07-28 Jakub Jelinek <jakub@redhat.com> 7768 7769 Backported from master: 7770 2020-07-28 Jakub Jelinek <jakub@redhat.com> 7771 7772 PR middle-end/96335 7773 * calls.c (maybe_warn_rdwr_sizes): Add FNDECL and FNTYPE arguments, 7774 instead of trying to rediscover them in the body. 7775 (initialize_argument_information): Adjust caller. 7776 77772020-07-27 Aaron Sawdey <acsawdey@linux.ibm.com> 7778 7779 Backported from master: 7780 2020-06-23 Aaron Sawdey <acsawdey@linux.ibm.com> 7781 7782 * config.gcc: Identify power10 as a 64-bit processor and as valid 7783 for --with-cpu and --with-tune. 7784 77852020-07-27 Martin Liska <mliska@suse.cz> 7786 7787 Backported from master: 7788 2020-07-27 Martin Liska <mliska@suse.cz> 7789 7790 PR lto/45375 7791 * symbol-summary.h: Call vec_safe_reserve before grow is called 7792 in order to grow to a reasonable size. 7793 * vec.h (vec_safe_reserve): Add missing function for vl_ptr 7794 type. 7795 77962020-07-23 Sergei Trofimovich <siarheit@google.com> 7797 7798 Backported from master: 7799 2020-07-20 Sergei Trofimovich <siarheit@google.com> 7800 7801 PR target/96190 7802 * config/sparc/linux.h (ENDFILE_SPEC): Use GNU_USER_TARGET_ENDFILE_SPEC 7803 to get crtendS.o for !no-pie mode. 7804 * config/sparc/linux64.h (ENDFILE_SPEC): Ditto. 7805 78062020-07-23 Peter Bergner <bergner@linux.ibm.com> 7807 7808 Backported from master: 7809 2020-07-22 Peter Bergner <bergner@linux.ibm.com> 7810 7811 PR target/96236 7812 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Handle 7813 little-endian memory ordering. 7814 78152020-07-23 Kito Cheng <kito.cheng@sifive.com> 7816 7817 Backported from master: 7818 2020-07-23 Kito Cheng <kito.cheng@sifive.com> 7819 7820 PR target/96260 7821 * asan.c (asan_shadow_offset_set_p): New. 7822 * asan.h (asan_shadow_offset_set_p): Ditto. 7823 * toplev.c (process_options): Allow -fsanitize=kernel-address 7824 even TARGET_ASAN_SHADOW_OFFSET not implemented, only check when 7825 asan stack protection is enabled. 7826 78272020-07-23 Release Manager 7828 7829 * GCC 10.2.0 released. 7830 78312020-07-21 Uroš Bizjak <ubizjak@gmail.com> 7832 7833 * config/i386/i386.h (TARGET_AVOID_MFENCE): 7834 Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE. 7835 * config/i386/sync.md (atomic_store<mode>): Update for rename. 7836 * config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE): 7837 Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE. 7838 78392020-07-17 Romain Naour <romain.naour@gmail.com> 7840 7841 Backported from master: 7842 2020-06-03 Romain Naour <romain.naour@gmail.com> 7843 7844 * Makefile.in (SELFTEST_DEPS): Move before including language makefile 7845 fragments. 7846 78472020-07-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 7848 7849 Backported from master: 7850 2020-06-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 7851 7852 * config.in: Regenerate. 7853 * config/s390/s390.c (print_operand): Emit vector alignment hints 7854 for target z13, if AS accepts them. For other targets the logic 7855 stays the same. 7856 * config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define 7857 macro. 7858 * configure: Regenerate. 7859 * configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13. 7860 78612020-07-15 Richard Sandiford <richard.sandiford@arm.com> 7862 7863 PR target/95726 7864 * config/aarch64/aarch64.c (aarch64_attribute_table): Add 7865 "Advanced SIMD type". 7866 * config/aarch64/aarch64-builtins.c: Include stringpool.h and 7867 attribs.h. 7868 (aarch64_init_simd_builtin_types): Add an "Advanced SIMD type" 7869 attribute to each Advanced SIMD type. 7870 * config/arm/arm.c (arm_attribute_table): Add "Advanced SIMD type". 7871 * config/arm/arm-builtins.c: Include stringpool.h and attribs.h. 7872 (arm_init_simd_builtin_types): Add an "Advanced SIMD type" 7873 attribute to each Advanced SIMD type. 7874 78752020-07-15 Jakub Jelinek <jakub@redhat.com> 7876 7877 Backported from master: 7878 2020-07-15 Jakub Jelinek <jakub@redhat.com> 7879 7880 PR target/96174 7881 * config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask, 7882 _mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask, 7883 _mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask, 7884 _mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask, 7885 _mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask, 7886 _mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask, 7887 _mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask, 7888 _mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask, 7889 _mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask, 7890 _mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask, 7891 _mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask, 7892 _mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask, 7893 _mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask, 7894 _mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask, 7895 _mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask, 7896 _mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask, 7897 _mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded 7898 section. 7899 79002020-07-15 Richard Biener <rguenther@suse.de> 7901 7902 Revert: 7903 2020-07-14 Matthias Klose <doko@ubuntu.com> 7904 7905 PR lto/95604 7906 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, 7907 error on different values for -fcf-protection. 7908 (append_compiler_options): Pass -fcf-protection option. 7909 (find_and_merge_options): Add decoded options as parameter, 7910 pass decoded_options to merge_and_complain. 7911 (run_gcc): Pass decoded options to find_and_merge_options. 7912 * lto-opts.c (lto_write_options): Pass -fcf-protection option. 7913 79142020-07-14 Richard Sandiford <richard.sandiford@arm.com> 7915 7916 PR middle-end/95114 7917 * tree.h (virtual_method_call_p): Add a default-false parameter 7918 that indicates whether the function is being called from dump 7919 routines. 7920 (obj_type_ref_class): Likewise. 7921 * tree.c (virtual_method_call_p): Likewise. 7922 * ipa-devirt.c (obj_type_ref_class): Likewise. Lazily add ODR 7923 type information for the type when the parameter is false. 7924 * tree-pretty-print.c (dump_generic_node): Update calls to 7925 virtual_method_call_p and obj_type_ref_class accordingly. 7926 79272020-07-14 Richard Sandiford <richard.sandiford@arm.com> 7928 7929 PR tree-optimization/96146 7930 * value-range.cc (value_range::set): Only decompose POLY_INT_CST 7931 bounds to integers for VR_RANGE. Decay to VR_VARYING for anti-ranges 7932 involving POLY_INT_CSTs. 7933 79342020-07-14 Jakub Jelinek <jakub@redhat.com> 7935 7936 Backported from master: 7937 2020-07-14 Jakub Jelinek <jakub@redhat.com> 7938 7939 PR middle-end/96194 7940 * expr.c (expand_constructor): Don't create temporary for store to 7941 volatile MEM if exp has an addressable type. 7942 79432020-07-14 Matthias Klose <doko@ubuntu.com> 7944 7945 Backported from master: 7946 2020-07-14 Matthias Klose <doko@ubuntu.com> 7947 7948 PR lto/95604 7949 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, 7950 error on different values for -fcf-protection. 7951 (append_compiler_options): Pass -fcf-protection option. 7952 (find_and_merge_options): Add decoded options as parameter, 7953 pass decoded_options to merge_and_complain. 7954 (run_gcc): Pass decoded options to find_and_merge_options. 7955 * lto-opts.c (lto_write_options): Pass -fcf-protection option. 7956 79572020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7958 7959 Backported from master: 7960 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7961 7962 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add 7963 __ARM_FEATURE_PAC_DEFAULT support. 7964 79652020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7966 7967 Backported from master: 7968 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7969 7970 PR target/94891 7971 * doc/extend.texi: Update the text for __builtin_return_address. 7972 79732020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7974 7975 Backported from master: 7976 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7977 7978 PR target/94891 7979 * config/aarch64/aarch64.c (aarch64_return_address_signing_enabled): 7980 Disable return address signing if __builtin_eh_return is used. 7981 79822020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7983 7984 Backported from master: 7985 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7986 7987 PR target/94891 7988 PR target/94791 7989 * config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare. 7990 * config/aarch64/aarch64.c (aarch64_return_addr_rtx): New. 7991 (aarch64_return_addr): Use aarch64_return_addr_rtx. 7992 * config/aarch64/aarch64.h (PROFILE_HOOK): Likewise. 7993 79942020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> 7995 7996 Backported from master: 7997 2020-07-09 Szabolcs Nagy <szabolcs.nagy@arm.com> 7998 7999 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add 8000 __ARM_FEATURE_BTI_DEFAULT support. 8001 80022020-07-13 Julian Brown <julian@codesourcery.com> 8003 8004 Backported from master: 8005 2020-07-13 Julian Brown <julian@codesourcery.com> 8006 Thomas Schwinge <thomas@codesourcery.com> 8007 8008 * gimplify.c (gimplify_scan_omp_clauses): Do not strip 8009 GOMP_MAP_TO_PSET/GOMP_MAP_POINTER for OpenACC enter/exit data 8010 directives (see also PR92929). 8011 80122020-07-13 Jakub Jelinek <jakub@redhat.com> 8013 8014 Backported from master: 8015 2020-07-13 Jakub Jelinek <jakub@redhat.com> 8016 8017 PR ipa/96130 8018 * ipa-fnsummary.c (analyze_function_body): Treat NULL bb->aux 8019 as false predicate. 8020 80212020-07-13 Hans-Peter Nilsson <hp@axis.com> 8022 8023 Backported from master: 8024 2020-07-13 Richard Biener <rguenther@suse.de> 8025 8026 PR middle-end/94600 8027 * expr.c (expand_constructor): Make a temporary also if we're 8028 storing to volatile memory. 8029 80302020-07-12 Jakub Jelinek <jakub@redhat.com> 8031 8032 Backported from master: 8033 2020-07-02 Jakub Jelinek <jakub@redhat.com> 8034 8035 PR tree-optimization/95857 8036 * tree-cfg.c (group_case_labels_stmt): When removing an unreachable 8037 base_bb, remember all forced and non-local labels on it and later 8038 treat those as if they have NULL label_to_block. Formatting fix. 8039 Fix a comment typo. 8040 80412020-07-10 Bill Seurer <seurer@linux.vnet.ibm.com> 8042 8043 Backported from master: 8044 2020-07-10 Bill Seurer <seurer@linux.vnet.ibm.com> 8045 8046 PR target/95581 8047 * config/rs6000/rs6000-call.c: Add new type v16qi_ftype_pcvoid. 8048 (altivec_init_builtins) Change __builtin_altivec_mask_for_load to use 8049 v16qi_ftype_pcvoid with correct number of parameters. 8050 80512020-07-10 Anton Youdkevitch <anton.youdkevitch@bell-sw.com> 8052 8053 * config/aarch64/aarch64.c (thunderx2t99_regmove_cost, 8054 thunderx2t99_vector_cost): Likewise. 8055 80562020-07-10 Peter Bergner <bergner@linux.ibm.com> 8057 8058 Backported from master: 8059 2020-07-09 Peter Bergner <bergner@linux.ibm.com> 8060 8061 PR target/96125 8062 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Define the MMA 8063 specific types __vector_quad and __vector_pair, and initialize the 8064 MMA built-ins if TARGET_EXTRA_BUILTINS is set. 8065 (mma_init_builtins): Don't test for mask set in rs6000_builtin_mask. 8066 Remove now unneeded mask variable. 8067 * config/rs6000/rs6000.c (rs6000_option_override_internal): Add the 8068 OPTION_MASK_MMA flag for power10 if not already set. 8069 80702020-07-10 Will Schmidt <will_schmidt@vnet.ibm.com> 8071 8072 Backported from master: 8073 2020-07-08 Will Schmidt <will_schmidt@vnet.ibm.com> 8074 8075 * config/rs6000/altivec.h (vec_vmsumudm): New define. 8076 * config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec. 8077 (altivec_vmsumudm): New define_insn. 8078 * config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New BU_ALTIVEC_3 8079 entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3 entry. 8080 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add entries for 8081 ALTIVEC_BUILTIN_VMSUMUDM variants of vec_msum. 8082 * doc/extend.texi: Add document for vmsumudm behind vmsum. 8083 80842020-07-10 Richard Biener <rguenther@suse.de> 8085 8086 Backported from master: 8087 2020-07-10 Richard Biener <rguenther@suse.de> 8088 8089 PR tree-optimization/96133 8090 * gimple-fold.c (fold_array_ctor_reference): Do not 8091 recurse to folding a CTOR that does not fully cover the 8092 asked for object. 8093 80942020-07-10 Bin Cheng <bin.cheng@linux.alibaba.com> 8095 8096 Backported from master: 8097 2020-07-09 Bin Cheng <bin.cheng@linux.alibaba.com> 8098 8099 PR tree-optimization/95804 8100 * tree-loop-distribution.c (break_alias_scc_partitions): Force 8101 negative post order to reduction partition. 8102 81032020-07-10 Bin Cheng <bin.cheng@linux.alibaba.com> 8104 8105 Backported from master: 8106 2020-06-20 Bin Cheng <bin.cheng@linux.alibaba.com> 8107 8108 PR tree-optimization/95638 8109 * tree-loop-distribution.c (pg_edge_callback_data): New field. 8110 (loop_distribution::break_alias_scc_partitions): Record and restore 8111 postorder information. Fix memory leak. 8112 81132020-07-09 Kito Cheng <kito.cheng@sifive.com> 8114 8115 Backported from master: 8116 2020-07-09 Kito Cheng <kito.cheng@sifive.com> 8117 8118 * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): 8119 Abort if any arguments on stack. 8120 81212020-07-09 Kito Cheng <kito.cheng@sifive.com> 8122 8123 Backported from master: 8124 2020-06-22 Kito Cheng <kito.cheng@sifive.com> 8125 8126 * config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New. 8127 (RISCV_FTYPE_ATYPES0): New. 8128 (riscv_builtins): Using RISCV_USI_FTYPE for frflags. 8129 * config/riscv/riscv-ftypes.def: Remove VOID argument. 8130 81312020-07-09 Kito Cheng <kito.cheng@sifive.com> 8132 8133 Backported from master: 8134 2020-06-16 Kito Cheng <kito.cheng@sifive.com> 8135 8136 PR target/95683 8137 * config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove 8138 assertion and turn it into a early exit check. 8139 81402020-07-09 Kito Cheng <kito.cheng@sifive.com> 8141 8142 Backported from master: 8143 2020-06-15 Kito Cheng <kito.cheng@sifive.com> 8144 8145 * config/riscv/riscv.c (riscv_gen_gpr_save_insn): Change type to 8146 unsigned for i. 8147 (riscv_gpr_save_operation_p): Change type to unsigned for i and 8148 len. 8149 81502020-07-09 Kito Cheng <kito.cheng@sifive.com> 8151 8152 Backported from master: 8153 2020-06-11 Kito Cheng <kito.cheng@sifive.com> 8154 8155 * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove. 8156 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update 8157 value. 8158 * config/riscv/riscv.c (riscv_output_gpr_save): Remove. 8159 * config/riscv/riscv.md (gpr_save): Update output asm pattern. 8160 81612020-07-09 Kito Cheng <kito.cheng@sifive.com> 8162 8163 Backported from master: 8164 2020-06-11 Kito Cheng <kito.cheng@sifive.com> 8165 8166 * config/riscv/predicates.md (gpr_save_operation): New. 8167 * config/riscv/riscv-protos.h (riscv_gen_gpr_save_insn): New. 8168 (riscv_gpr_save_operation_p): Ditto. 8169 * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): 8170 Ignore USEs for gpr_save patter. 8171 * config/riscv/riscv.c (gpr_save_reg_order): New. 8172 (riscv_expand_prologue): Use riscv_gen_gpr_save_insn to gen gpr_save. 8173 (riscv_gen_gpr_save_insn): New. 8174 (riscv_gpr_save_operation_p): Ditto. 8175 * config/riscv/riscv.md (S3_REGNUM): New. 8176 (S4_REGNUM): Ditto. 8177 (S5_REGNUM): Ditto. 8178 (S6_REGNUM): Ditto. 8179 (S7_REGNUM): Ditto. 8180 (S8_REGNUM): Ditto. 8181 (S9_REGNUM): Ditto. 8182 (S10_REGNUM): Ditto. 8183 (S11_REGNUM): Ditto. 8184 (gpr_save): Model USEs correctly. 8185 81862020-07-09 Keith Packard <keithp@keithp.com> 8187 8188 Backported from master: 8189 2020-05-12 Keith Packard <keithp@keithp.com> 8190 8191 * config/riscv/riscv.c (riscv_unique_section): New. 8192 (TARGET_ASM_UNIQUE_SECTION): New. 8193 81942020-07-08 Richard Sandiford <richard.sandiford@arm.com> 8195 8196 PR target/95105 8197 * config/aarch64/aarch64-sve-builtins.cc 8198 (handle_arm_sve_vector_bits_attribute): Create a copy of the 8199 original type's TYPE_MAIN_VARIANT, then reapply all the differences 8200 between the original type and its main variant. 8201 82022020-07-07 Richard Biener <rguenther@suse.de> 8203 8204 Backported from master: 8205 2020-07-06 Richard Biener <rguenther@suse.de> 8206 8207 PR tree-optimization/96075 8208 * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Use 8209 TYPE_SIZE_UNIT of the vector component type instead of DR_STEP 8210 for the misalignment calculation for negative step. 8211 82122020-07-07 Richard Biener <rguenther@suse.de> 8213 8214 Backported from master: 8215 2020-07-07 Richard Biener <rguenther@suse.de> 8216 8217 * lto-streamer-out.c (cmp_symbol_files): Use the computed 8218 order map to sort symbols from the same sub-file together. 8219 (lto_output): Compute a map of sub-file to an order number 8220 it appears in the symbol output array. 8221 82222020-07-06 Will Schmidt <will_schmidt@vnet.ibm.com> 8223 8224 * config/rs6000/altivec.h (vec_pack_to_short_fp32): Update. 8225 * config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec. 8226 (convert_4f32_8f16): New define_expand 8227 * config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define 8228 and overload. 8229 * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New 8230 overloaded builtin entry. 8231 * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec. 8232 (vsx_xvcvsphp): New define_insn. 8233 82342020-07-04 Martin Jambor <mjambor@suse.cz> 8235 8236 Backported from master: 8237 2020-07-03 Martin Jambor <mjambor@suse.cz> 8238 8239 PR ipa/96040 8240 * ipa-sra.c (all_callee_accesses_present_p): Do not accept type 8241 mismatched accesses. 8242 82432020-07-03 Martin Jambor <mjambor@suse.cz> 8244 8245 Backported from master: 8246 2020-07-02 Martin Jambor <mjambor@suse.cz> 8247 8248 PR debug/95343 8249 * ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Adjust 8250 argument index if necessary. 8251 82522020-07-02 Segher Boessenkool <segher@kernel.crashing.org> 8253 8254 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define 8255 _ARCH_PWR10 when appropriate. 8256 82572020-07-02 Peter Bergner <bergner@linux.ibm.com> 8258 8259 Backported from master: 8260 2020-06-26 Peter Bergner <bergner@linux.ibm.com> 8261 8262 * config/rs6000/rs6000-call.c (cpu_is_info) <power10>: New. 8263 * doc/extend.texi (PowerPC Built-in Functions): Document power10, 8264 arch_3_1 and mma. 8265 82662020-07-02 Michael Meissner <meissner@linux.ibm.com> 8267 8268 Backported from master: 8269 2020-06-09 Michael Meissner <meissner@linux.ibm.com> 8270 8271 * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Allocate 8272 'power10' PowerPC platform. 8273 (PPC_FEATURE2_ARCH_3_1): New HWCAP2 bit for ARCH 3.1. 8274 (PPC_FEATURE2_MMA): New HWCAP2 bit for MMA. 8275 * config/rs6000/rs6000-call.c (cpu_supports_info): Add ARCH 3.1 and 8276 MMA HWCAP2 bits. 8277 82782020-07-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8279 8280 Backported from master: 8281 2020-06-22 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8282 8283 * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. 8284 (arm_mve_hw): Likewise. 8285 82862020-06-30 Segher Boessenkool <segher@kernel.crashing.org> 8287 8288 * config/rs6000/rs6000.md (isa): Rename "fut" to "p10". 8289 82902020-06-30 Segher Boessenkool <segher@kernel.crashing.org> 8291 8292 * config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10 8293 on AIX, and -mpower10 elsewhere. 8294 * config/rs6000/future.md: Delete. 8295 * config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not 8296 TARGET_FUTURE. 8297 * config/rs6000/power10.md: New file. 8298 * config/rs6000/rs6000-builtin.def: Update comments. 8299 * config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*. 8300 Update compiler messages. 8301 * config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not 8302 ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. 8303 * config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not 8304 PROCESSOR_FUTURE. 8305 * config/rs6000/rs6000-string.c: Ditto. 8306 * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10" 8307 instead of "future", reorder it to right after "power9". 8308 * config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10, 8309 not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use 8310 RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages. 8311 Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER, 8312 not ISA_FUTURE_MASKS_SERVER. 8313 (rs6000_opt_masks): Use "power10" instead of "future". 8314 (rs6000_builtin_mask_names): Ditto. 8315 (rs6000_disable_incompatible_switches): Ditto. 8316 * config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use 8317 -mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE. 8318 Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10, 8319 not RS6000_BTM_FUTURE. 8320 * config/rs6000/rs6000.md: Use "power10", not "future". Use 8321 TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not 8322 "future.md". 8323 * config/rs6000/rs6000.opt (mfuture): Delete. 8324 (mpower10): New. 8325 * config/rs6000/t-rs6000: Use "power10.md", not "future.md". 8326 * config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE. 8327 83282020-06-30 Alex Coplan <alex.coplan@arm.com> 8329 8330 Backported from master: 8331 2020-05-18 Alex Coplan <alex.coplan@arm.com> 8332 8333 * config/arm/arm.c (output_move_double): Fix codegen when loading into 8334 a register pair with an odd base register. 8335 83362020-06-29 Jakub Jelinek <jakub@redhat.com> 8337 8338 Backported from master: 8339 2020-06-24 Jakub Jelinek <jakub@redhat.com> 8340 8341 PR middle-end/95810 8342 * fold-const.c (fold_cond_expr_with_comparison): Optimize 8343 A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A). 8344 83452020-06-25 H.J. Lu <hjl.tools@gmail.com> 8346 8347 Backported from master: 8348 2020-06-25 H.J. Lu <hjl.tools@gmail.com> 8349 8350 PR target/95874 8351 * config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB. 8352 (PTA_ICELAKE_SERVER): Add PTA_CLWB. 8353 (PTA_TIGERLAKE): Add PTA_CLWB. 8354 83552020-06-24 Peter Bergner <bergner@linux.ibm.com> 8356 8357 Backported from master: 8358 2020-06-21 Peter Bergner <bergner@linux.ibm.com> 8359 8360 * config/rs6000/predicates.md (mma_assemble_input_operand): New. 8361 * config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3, 8362 BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA 8363 built-in functions. 8364 (ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR, 8365 PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, 8366 PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP, 8367 PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN, 8368 PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN, 8369 PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP, 8370 PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4, 8371 PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP, 8372 XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2, 8373 XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER, 8374 XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN, 8375 XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S, 8376 XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP, 8377 XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins. 8378 * config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P. 8379 Allow zero constants. 8380 (print_operand) <case 'A'>: New output modifier. 8381 (rs6000_split_multireg_move): Add support for inserting accumulator 8382 priming and depriming instructions. Add support for splitting an 8383 assemble accumulator pattern. 8384 * config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin, 8385 rs6000_gimple_fold_mma_builtin): New functions. 8386 (RS6000_BUILTIN_M): New macro. 8387 (def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes. 8388 (bdesc_mma): Add new MMA built-in support. 8389 (htm_expand_builtin): Use RS6000_BTC_OPND_MASK. 8390 (rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and 8391 RS6000_BTM_MMA. 8392 (rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute. 8393 (rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p 8394 and rs6000_gimple_fold_mma_builtin. 8395 (rs6000_expand_builtin): Call mma_expand_builtin. 8396 Use RS6000_BTC_OPND_MASK. 8397 (rs6000_init_builtins): Adjust comment. Call mma_init_builtins. 8398 (htm_init_builtins): Use RS6000_BTC_OPND_MASK. 8399 (builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and 8400 VSX_BUILTIN_XVCVBF16SP. 8401 * config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY, 8402 RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR, 8403 RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines. 8404 (RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST, 8405 RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values. 8406 * config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant. 8407 (UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2, 8408 UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP, 8409 UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP, 8410 UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN, 8411 UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN, 8412 UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER, 8413 UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP, 8414 UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP, 8415 UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN, 8416 UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN, 8417 UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2, 8418 UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S, 8419 UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8, 8420 UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4, 8421 UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP, 8422 UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN, 8423 UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN, 8424 UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN, 8425 UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP, 8426 UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP, 8427 UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER, 8428 UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN, 8429 UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP, 8430 UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8, 8431 UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP, 8432 UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New. 8433 (MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8, 8434 MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4, 8435 MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4, 8436 MMA_AVVI4I4I4): New define_int_iterator. 8437 (acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2, 8438 avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4, 8439 avvi4i4i4): New define_int_attr. 8440 (*movpxi): Add zero constant alternative. 8441 (mma_assemble_pair, mma_assemble_acc): New define_expand. 8442 (*mma_assemble_acc): New define_insn_and_split. 8443 (mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>, 8444 mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>, 8445 mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>, 8446 mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn. 8447 * config/rs6000/rs6000.md (define_attr "type"): New type mma. 8448 * config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New. 8449 (UNSPEC_VSX_XVCVSPBF16): Likewise. 8450 (XVCVBF16): New define_int_iterator. 8451 (xvcvbf16): New define_int_attr. 8452 (vsx_<xvcvbf16>): New define_insn. 8453 * doc/extend.texi: Document the mma built-ins. 8454 84552020-06-24 Kelvin Nilsen <wschmidt@linux.ibm.com> 8456 8457 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate. 8458 84592020-06-24 Peter Bergner <bergner@linux.ibm.com> 8460 8461 Backported from master: 8462 2020-06-21 Peter Bergner <bergner@linux.ibm.com> 8463 Michael Meissner <meissner@linux.ibm.com> 8464 8465 * config/rs6000/mma.md: New file. 8466 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define 8467 __MMA__ for mma. 8468 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support 8469 for __vector_pair and __vector_quad types. 8470 * config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add 8471 OPTION_MASK_MMA. 8472 (POWERPC_MASKS): Likewise. 8473 * config/rs6000/rs6000-modes.def (OI, XI): New integer modes. 8474 (POI, PXI): New partial integer modes. 8475 * config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define. 8476 (rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P. 8477 (rs6000_hard_regno_mode_ok_uncached): Likewise. 8478 Add support for POImode being allowed in VSX registers and PXImode 8479 being allowed in FP registers. 8480 (rs6000_modes_tieable_p): Adjust comment. 8481 Add support for POImode and PXImode. 8482 (rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode 8483 XImode, PXImode, V2SImode, V2SFmode and CCFPmode.. 8484 (rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P. 8485 Set up appropriate addr_masks for vector pair and vector quad addresses. 8486 (rs6000_init_hard_regno_mode_ok): Add support for vector pair and 8487 vector quad registers. Setup reload handlers for POImode and PXImode. 8488 (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA. 8489 (rs6000_option_override_internal): Error if -mmma is specified 8490 without -mcpu=future. 8491 (rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P. 8492 (quad_address_p): Change size test to less than 16 bytes. 8493 (reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair 8494 and vector quad instructions. 8495 (avoiding_indexed_address_p): Likewise. 8496 (rs6000_emit_move): Disallow POImode and PXImode moves involving 8497 constants. 8498 (rs6000_preferred_reload_class): Prefer VSX registers for POImode 8499 and FP registers for PXImode. 8500 (rs6000_split_multireg_move): Support splitting POImode and PXImode 8501 move instructions. 8502 (rs6000_mangle_type): Adjust comment. Add support for mangling 8503 __vector_pair and __vector_quad types. 8504 (rs6000_opt_masks): Add entry for mma. 8505 (rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. 8506 (rs6000_function_value): Use VECTOR_ALIGNMENT_P. 8507 (address_to_insn_form): Likewise. 8508 (reg_to_non_prefixed): Likewise. 8509 (rs6000_invalid_conversion): New function. 8510 * config/rs6000/rs6000.h (MASK_MMA): Define. 8511 (BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled. 8512 (VECTOR_ALIGNMENT_P): New helper macro. 8513 (ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P. 8514 (RS6000_BTM_MMA): Define. 8515 (RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. 8516 (rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and 8517 RS6000_BTI_vector_quad. 8518 (vector_pair_type_node): New. 8519 (vector_quad_type_node): New. 8520 * config/rs6000/rs6000.md: Include mma.md. 8521 (define_mode_iterator RELOAD): Add POI and PXI. 8522 * config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md. 8523 * config/rs6000/rs6000.opt (-mmma): New. 8524 * doc/invoke.texi: Document -mmma. 8525 85262020-06-24 Richard Biener <rguenther@suse.de> 8527 8528 Backported from master: 8529 2020-06-17 Richard Biener <rguenther@suse.de> 8530 8531 PR tree-optimization/95717 8532 * tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg): 8533 Move BB SSA updating before exit/latch PHI current def copying. 8534 85352020-06-23 Richard Biener <rguenther@suse.de> 8536 8537 PR middle-end/95493 8538 PR middle-end/95690 8539 * cfgexpand.c (expand_debug_expr): Avoid calling 8540 set_mem_attributes_minus_bitpos when we were expanding 8541 an SSA name. 8542 * emit-rtl.c (set_mem_attributes_minus_bitpos): Remove 8543 ARRAY_REF special-casing, add CONSTRUCTOR to the set of 8544 special-cases we do not want MEM_EXPRs for. Assert 8545 we end up with reasonable MEM_EXPRs. 8546 * varasm.c (build_constant_desc): Remove set_mem_attributes call. 8547 85482020-06-23 Richard Biener <rguenther@suse.de> 8549 8550 PR tree-optimization/95487 8551 * tree-vect-stmts.c (vectorizable_store): Use a truth type 8552 for the scatter mask. 8553 85542020-06-23 Richard Biener <rguenther@suse.de> 8555 8556 PR tree-optimization/95308 8557 * tree-ssa-forwprop.c (pass_forwprop::execute): Generalize 8558 test for TARGET_MEM_REFs. 8559 85602020-06-23 Richard Biener <rguenther@suse.de> 8561 8562 PR tree-optimization/95133 8563 * gimple-ssa-split-paths.c 8564 (find_block_to_duplicate_for_splitting_paths): Check for 8565 normal edges. 8566 85672020-06-23 Richard Biener <rguenther@suse.de> 8568 8569 PR middle-end/95118 8570 * real.c (real_to_decimal_for_mode): Make sure we handle 8571 a zero with nonzero exponent. 8572 85732020-06-23 Richard Biener <rguenther@suse.de> 8574 8575 PR tree-optimization/95049 8576 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition 8577 between different constants. 8578 85792020-06-23 Richard Biener <rguenther@suse.de> 8580 8581 PR middle-end/94964 8582 * cfgloopmanip.c (create_preheader): Require non-complex 8583 preheader edge for CP_SIMPLE_PREHEADERS. 8584 85852020-06-20 Bin Cheng <bin.cheng@linux.alibaba.com> 8586 8587 PR tree-optimization/94969 8588 * tree-data-ref.c (constant_access_functions): Rename to... 8589 (invariant_access_functions): ...this. Add parameter. Check for 8590 invariant access function, rather than constant. 8591 (build_classic_dist_vector): Call above function. 8592 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment. 8593 85942020-06-19 Jiufu Guo <guojiufu@linux.ibm.com> 8595 8596 PR target/95018 8597 * common.opt (flag_cunroll_grow_size): New flag. 8598 * toplev.c (process_options): Set flag_cunroll_grow_size. 8599 * tree-ssa-loop-ivcanon.c (pass_complete_unroll::execute): 8600 Use flag_cunroll_grow_size. 8601 * config/rs6000/rs6000.c (rs6000_option_override_internal): 8602 Override flag_cunroll_grow_size. 8603 86042020-06-18 Aaron Sawdey <acsawdey@linux.ibm.com> 8605 8606 PR target/95347 8607 * config/rs6000/rs6000.c (is_stfs_insn): Rename to 8608 is_lfs_stfs_insn and make it recognize lfs as well. 8609 (prefixed_store_p): Use is_lfs_stfs_insn(). 8610 (prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs. 8611 86122020-06-18 Aaron Sawdey <acsawdey@linux.ibm.com> 8613 8614 PR target/95347 8615 * config/rs6000/rs6000.c (prefixed_store_p): Add special case 8616 for stfs. 8617 (is_stfs_insn): New helper function. 8618 86192020-06-18 Jakub Jelinek <jakub@redhat.com> 8620 8621 Backported from master: 8622 2020-06-18 Jakub Jelinek <jakub@redhat.com> 8623 8624 PR target/95713 8625 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow 8626 scalar mode halfvectype other than vector boolean for 8627 VEC_PACK_TRUNC_EXPR. 8628 86292020-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8630 8631 Backported from master: 8632 2020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8633 8634 * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic 8635 arguments. 8636 (__arm_vaddq_m_n_s32): Likewise. 8637 (__arm_vaddq_m_n_s16): Likewise. 8638 (__arm_vaddq_m_n_u8): Likewise. 8639 (__arm_vaddq_m_n_u32): Likewise. 8640 (__arm_vaddq_m_n_u16): Likewise. 8641 (__arm_vaddq_m): Modify polymorphic variant. 8642 86432020-06-18 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8644 8645 Backported from master: 8646 2020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8647 8648 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate 8649 and constraint of all the operands. 8650 (mve_sqrshrl_sat<supf>_di): Likewise. 8651 (mve_uqrshl_si): Likewise. 8652 (mve_sqrshr_si): Likewise. 8653 (mve_uqshll_di): Likewise. 8654 (mve_urshrl_di): Likewise. 8655 (mve_uqshl_si): Likewise. 8656 (mve_urshr_si): Likewise. 8657 (mve_sqshl_si): Likewise. 8658 (mve_srshr_si): Likewise. 8659 (mve_srshrl_di): Likewise. 8660 (mve_sqshll_di): Likewise. 8661 * config/arm/predicates.md (arm_low_register_operand): Define. 8662 86632020-06-17 Thomas Schwinge <thomas@codesourcery.com> 8664 8665 Backported from master: 8666 2020-06-17 Thomas Schwinge <thomas@codesourcery.com> 8667 8668 * hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl == 8669 NULL_TREE' check earlier. 8670 86712020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8672 8673 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic 8674 arguments. 8675 (__arm_vbicq_n_s16): Likewise. 8676 (__arm_vbicq_n_u32): Likewise. 8677 (__arm_vbicq_n_s32): Likewise. 8678 (__arm_vbicq): Modify polymorphic variant. 8679 86802020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8681 8682 PR target/94735 8683 * config/arm/predicates.md (mve_scatter_memory): Define to 8684 match (mem (reg)) for scatter store memory. 8685 * config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>): Modify 8686 define_insn to define_expand. 8687 (mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise. 8688 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise. 8689 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise. 8690 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise. 8691 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise. 8692 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise. 8693 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise. 8694 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise. 8695 (mve_vstrhq_scatter_offset_fv8hf): Likewise. 8696 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. 8697 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. 8698 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. 8699 (mve_vstrwq_scatter_offset_fv4sf): Likewise. 8700 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. 8701 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise. 8702 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise. 8703 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. 8704 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. 8705 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise. 8706 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise. 8707 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for scatter 8708 stores. 8709 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise. 8710 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise. 8711 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise. 8712 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise. 8713 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise. 8714 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise. 8715 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise. 8716 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise. 8717 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. 8718 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. 8719 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. 8720 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. 8721 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. 8722 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. 8723 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise. 8724 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise. 8725 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. 8726 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. 8727 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise. 8728 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise. 8729 87302020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8731 8732 * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted 8733 fall-throughs. 8734 87352020-06-16 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 8736 Andre Vieira <andre.simoesdiasvieira@arm.com> 8737 8738 PR target/94959 8739 * config/arm/arm-protos.h (arm_mode_base_reg_class): Function 8740 declaration. 8741 (mve_vector_mem_operand): Likewise. 8742 * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check 8743 the load from memory to a core register is legitimate for give mode. 8744 (mve_vector_mem_operand): Define function. 8745 (arm_print_operand): Modify comment. 8746 (arm_mode_base_reg_class): Define. 8747 * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for 8748 TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE. 8749 * config/arm/constraints.md (Ux): Likewise. 8750 (Ul): Likewise. 8751 * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also 8752 add support for missing Vector Store Register and Vector Load Register. 8753 Add a new alternative to support load from memory to PC (or label) in 8754 vector store/load. 8755 (mve_vstrbq_<supf><mode>): Modify constraint Us to Ux. 8756 (mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to 8757 mve_memory_operand and also modify the MVE instructions to emit. 8758 (mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux. 8759 (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to 8760 mve_memory_operand and also modify the MVE instructions to emit. 8761 (mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to 8762 mve_memory_operand and also modify the MVE instructions to emit. 8763 (mve_vldrhq_z_fv8hf): Likewise. 8764 (mve_vldrhq_z_<supf><mode>): Likewise. 8765 (mve_vldrwq_fv4sf): Likewise. 8766 (mve_vldrwq_<supf>v4si): Likewise. 8767 (mve_vldrwq_z_fv4sf): Likewise. 8768 (mve_vldrwq_z_<supf>v4si): Likewise. 8769 (mve_vld1q_f<mode>): Modify constriant Us to Ux. 8770 (mve_vld1q_<supf><mode>): Likewise. 8771 (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to 8772 mve_memory_operand. 8773 (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to 8774 mve_memory_operand and also modify the MVE instructions to emit. 8775 (mve_vstrhq_p_<supf><mode>): Likewise. 8776 (mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to 8777 mve_memory_operand. 8778 (mve_vstrwq_fv4sf): Modify constriant Us to Ux. 8779 (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE 8780 instructions to emit. 8781 (mve_vstrwq_p_<supf>v4si): Likewise. 8782 (mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux. 8783 * config/arm/predicates.md (mve_memory_operand): Define. 8784 87852020-06-15 Andrew Stubbs <ams@codesourcery.com> 8786 8787 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp. 8788 87892020-06-15 Tobias Burnus <tobias@codesourcery.com> 8790 8791 * omp-offload.c (add_decls_addresses_to_decl_constructor, 8792 omp_finish_file): With in_lto_p, stream out all offload-table 8793 items even if the symtab_node does not exist. 8794 87952020-06-15 Tobias Burnus <tobias@codesourcery.com> 8796 8797 PR lto/94848 8798 PR middle-end/95551 8799 * omp-offload.c (add_decls_addresses_to_decl_constructor, 8800 omp_finish_file): Skip removed items. 8801 * lto-cgraph.c (output_offload_tables): Likewise; set force_output 8802 to this node for variables and functions. 8803 88042020-06-14 Jakub Jelinek <jakub@redhat.com> 8805 8806 PR target/95528 8807 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't use 8808 VEC_UNPACK*_EXPR or VEC_PACK_TRUNC_EXPR with scalar modes unless the 8809 type is vector boolean. 8810 88112020-06-14 Jakub Jelinek <jakub@redhat.com> 8812 8813 PR c++/95197 8814 * gimplify.c (find_combined_omp_for): Move to omp-general.c. 8815 * omp-general.h (find_combined_omp_for): Declare. 8816 * omp-general.c: Include tree-iterator.h. 8817 (find_combined_omp_for): New function, moved from gimplify.c. 8818 88192020-06-14 Jakub Jelinek <jakub@redhat.com> 8820 8821 PR middle-end/95108 8822 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member. 8823 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in 8824 entry block if info->after_stmt is NULL, otherwise add after that stmt 8825 and update it after adding each stmt. 8826 (ipa_simd_modify_function_body): Initialize info.after_stmt. 8827 88282020-06-14 Jakub Jelinek <jakub@redhat.com> 8829 8830 PR debug/95080 8831 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even 8832 if the last insn is a note. 8833 88342020-06-12 Martin Liska <mliska@suse.cz> 8835 Jakub Jelinek <jakub@redhat.com> 8836 8837 PR sanitizer/95634 8838 * asan.c (asan_emit_stack_protection): Fix emission for ilp32 8839 by using Pmode instead of ptr_mode. 8840 88412020-06-12 Martin Liska <mliska@suse.cz> 8842 8843 PR sanitizer/94910 8844 * asan.c (asan_emit_stack_protection): Emit 8845 also **SavedFlagPtr(FakeStack, class_id) = 0 in order to release 8846 a stack frame. 8847 88482020-06-08 Martin Jambor <mjambor@suse.cz> 8849 8850 PR ipa/95113 8851 * tree-ssa-dce.c (mark_stmt_if_obviously_necessary): Move non-call 8852 exceptions check to... 8853 * tree-eh.c (stmt_unremovable_because_of_non_call_eh_p): ...this 8854 new function. 8855 * tree-eh.h (stmt_unremovable_because_of_non_call_eh_p): Declare it. 8856 * ipa-sra.c (isra_track_scalar_value_uses): Use it. New parameter 8857 fun. 8858 88592020-06-05 Thomas Schwinge <thomas@codesourcery.com> 8860 Julian Brown <julian@codesourcery.com> 8861 8862 * gimplify.c (gimplify_adjust_omp_clauses): Remove 8863 'GOMP_MAP_STRUCT' mapping from OpenACC 'exit data' directives. 8864 88652020-06-05 H.J. Lu <hjl.tools@gmail.com> 8866 8867 * config/i386/driver-i386.c (host_detect_local_cpu): Support 8868 Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake 8869 processor families. 8870 88712020-06-05 Lili Cui <lili.cui@intel.com> 8872 8873 PR target/95525 8874 * config/i386/i386.h (PTA_WAITPKG): Change bitmask value. 8875 88762020-06-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 8877 8878 * config/aarch64/aarch64-cores.def (zeus): Define. 8879 * config/aarch64/aarch64-tune.md: Regenerate. 8880 * doc/invoke.texi (AArch64 Options): Document zeus -mcpu option. 8881 88822020-06-02 Iain Buclaw <ibuclaw@gdcproject.org> 8883 8884 PR target/95420 8885 * config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a. 8886 88872020-05-29 Alex Coplan <alex.coplan@arm.com> 8888 8889 PR target/94591 8890 * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match 8891 identity permutation. 8892 88932020-05-29 Andrew Stubbs <ams@codesourcery.com> 8894 8895 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a 8896 define_expand, and rename the original to ... 8897 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand. 8898 (add<mode>3_zext_dup_exec): Likewise, with ... 8899 (add<mode>3_vcc_zext_dup_exec): ... this. 8900 (add<mode>3_zext_dup2): Likewise, with ... 8901 (add<mode>3_zext_dup_exec): ... this. 8902 (add<mode>3_zext_dup2_exec): Likewise, with ... 8903 (add<mode>3_zext_dup2): ... this. 8904 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch 8905 addv64di3_zext* calls to use addv64di3_vcc_zext*. 8906 89072020-05-29 Dong JianQiang <dongjianqiang2@huawei.com> 8908 8909 PR gcov-profile/95332 8910 * gcov-io.c (gcov_var::endian): Move field. 8911 (from_file): Add IN_GCOV_TOOL check. 8912 * gcov-io.h (gcov_magic): Ditto. 8913 89142020-05-28 Richard Sandiford <richard.sandiford@arm.com> 8915 8916 PR testsuite/95361 8917 * config/aarch64/aarch64.c (aarch64_expand_epilogue): Only 8918 redefine the CFA if we have CFI operations. 8919 89202020-05-28 Uroš Bizjak <ubizjak@gmail.com> 8921 8922 * config/i386/mmx.md (mmx_haddsubv2sf3): Correct 8923 RTL template to model horizontal subtraction and addition. 8924 89252020-05-28 Uroš Bizjak <ubizjak@gmail.com> 8926 8927 PR target/95355 8928 * config/i386/sse.md 8929 (<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): 8930 Remove %q operand modifier from insn template. 8931 (avx512f_<code>v8hiv8di2<mask_name>): Ditto. 8932 89332020-05-28 Martin Liska <mliska@suse.cz> 8934 8935 PR web/95380 8936 * doc/invoke.texi: Add missing params, remove max-once-peeled-insns and 8937 rename ipcp-unit-growth to ipa-cp-unit-growth. 8938 89392020-05-24 Uroš Bizjak <ubizjak@gmail.com> 8940 8941 PR target/95255 8942 * config/i386/i386.md (<rounding_insn><mode>2): Do not try to 8943 expand non-sse4 ROUND_ROUNDEVEN rounding via SSE support routines. 8944 89452020-05-24 Iain Sandoe <iain@sandoe.co.uk> 8946 8947 Backported from master. 8948 2020-05-22 Iain Sandoe <iain@sandoe.co.uk> 8949 8950 * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): 8951 Make ubsan_{data,type},ASAN linker-visible. 8952 89532020-05-24 H.J. Lu <hongjiu.lu@intel.com> 8954 8955 PR target/95258 8956 * config/i386/driver-i386.c (host_detect_local_cpu): Detect 8957 AVX512VPOPCNTDQ. 8958 89592020-05-22 Richard Biener <rguenther@suse.de> 8960 8961 PR lto/95190 8962 * doc/invoke.texi (flto): Document behavior of diagnostic 8963 options. 8964 89652020-05-21 Uroš Bizjak <ubizjak@gmail.com> 8966 8967 PR target/95169 8968 * config/i386/i386-expand.c (ix86_expand_int_movcc): 8969 Avoid reversing a non-trapping comparison to a trapping one. 8970 89712020-05-21 Martin Liska <mliska@suse.cz> 8972 8973 * common/config/aarch64/aarch64-common.c (aarch64_handle_option): 8974 Handle OPT_moutline_atomics. 8975 * config/aarch64/aarch64.c: Add outline-atomics to 8976 aarch64_attributes. 8977 * doc/extend.texi: Document the newly added target attribute. 8978 89792020-05-21 H.J. Lu <hongjiu.lu@intel.com> 8980 8981 Backport from master 8982 2020-05-21 H.J. Lu <hongjiu.lu@intel.com> 8983 8984 PR target/95212 8985 * config/i386/i386-builtins.c (processor_features): Move 8986 F_AVX512VP2INTERSECT after F_AVX512BF16. 8987 (isa_names_table): Likewise. 8988 89892020-05-19 Gerald Pfeifer <gerald@pfeifer.com> 8990 8991 Backport from mainline 8992 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com> 8993 8994 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and 8995 __ILP32__ for 32-bit targets. 8996 89972020-05-19 Tobias Burnus <tobias@codesourcery.com> 8998 8999 Backport from mainline 9000 2020-05-15 Tobias Burnus <tobias@codesourcery.com> 9001 9002 PR middle-end/94635 9003 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with 9004 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated 9005 item is 'delete:'. 9006 90072020-05-18 Martin Sebor <msebor@redhat.com> 9008 9009 PR middle-end/94940 9010 * tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code. 9011 * tree.c (component_ref_size): Correct the handling or array members 9012 of unions. 9013 Drop a pointless test. 9014 Rename a local variable. 9015 90162020-05-12 Richard Biener <rguenther@suse.de> 9017 9018 Backport from mainline 9019 2020-05-07 Richard Biener <rguenther@suse.de> 9020 9021 PR ipa/94947 9022 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use 9023 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible. 9024 (refered_from_nonlocal_var): Likewise. 9025 (ipa_pta_execute): Likewise. 9026 9027 2020-05-05 Richard Biener <rguenther@suse.de> 9028 9029 PR ipa/94947 9030 * tree-ssa-structalias.c (ipa_pta_execute): Use 9031 varpool_node::externally_visible_p (). 9032 (refered_from_nonlocal_var): Likewise. 9033 90342020-05-12 David Edelsohn <dje.gcc@gmail.com> 9035 9036 Backport from mainline 9037 2020-05-04 Clement Chigot <clement.chigot@atos.net> 9038 David Edelsohn <dje.gcc@gmail.com> 9039 9040 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit 9041 for fmodl, frexpl, ldexpl and modfl builtins. 9042 90432020-05-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 9044 9045 Backport from mainline 9046 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de> 9047 9048 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined. 9049 (RTEMS_ENDFILE_SPEC): Likewise. 9050 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC. 9051 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC. 9052 (LIB_SPECS): Support -nodefaultlibs option. 9053 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define. 9054 (RTEMS_ENDFILE_SPEC): Likewise. 9055 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. 9056 (RTEMS_ENDFILE_SPEC): Likewise. 9057 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. 9058 (RTEMS_ENDFILE_SPEC): Likewise. 9059 90602020-05-11 Martin Liska <mliska@suse.cz> 9061 9062 Backport from mainline 9063 2020-05-11 Martin Liska <mliska@suse.cz> 9064 9065 PR c/95040 9066 * common.opt: Fix typo in option description. 9067 90682020-05-08 Jakub Jelinek <jakub@redhat.com> 9069 9070 PR middle-end/94724 9071 * tree.c (get_narrower): Reuse the op temporary instead of 9072 shadowing it. 9073 90742020-05-07 Uroš Bizjak <ubizjak@gmail.com> 9075 9076 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use 9077 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to 9078 fenv_var and new_fenv_var. 9079 90802020-05-07 Martin Liska <mliska@suse.cz> 9081 9082 Backport from mainline 9083 2020-05-07 Martin Liska <mliska@suse.cz> 9084 9085 * doc/invoke.texi: Fix 2 optindex entries. 9086 90872020-05-07 Jakub Jelinek <jakub@redhat.com> 9088 9089 Backported from mainline 9090 2020-05-06 Jakub Jelinek <jakub@redhat.com> 9091 9092 PR target/94950 9093 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use 9094 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags. 9095 9096 PR rtl-optimization/94873 9097 * combine.c (combine_instructions): Don't optimize using REG_EQUAL 9098 note if SET_SRC (set) has side-effects. 9099 9100 2020-05-05 Jakub Jelinek <jakub@redhat.com> 9101 9102 PR target/94942 9103 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv. 9104 9105 2020-05-04 Jakub Jelinek <jakub@redhat.com> 9106 9107 * opts.c (get_option_html_page): Instead of hardcoding a list of 9108 options common between C/C++ and Fortran only use gfortran/ 9109 documentation for warnings that have CL_Fortran set but not 9110 CL_C or CL_CXX. 9111 91122020-05-07 Jakub Jelinek <jakub@redhat.com> 9113 9114 * BASE-VER: Set to 10.1.1. 9115 91162020-05-07 Release Manager 9117 9118 * GCC 10.1.0 released. 9119 91202020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 9121 9122 * doc/install.texi: Replace Sun with Solaris as appropriate. 9123 (Tools/packages necessary for building GCC, Perl version between 9124 5.6.1 and 5.6.24): Remove Solaris 8 reference. 9125 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove 9126 TGCware reference. 9127 (Specific, i?86-*-solaris2*): Update version references for 9128 Solaris 11.3 and later. Remove gas 2.26 caveat. 9129 (Specific, *-*-solaris2*): Update version references for 9130 Solaris 11.3 and later. Remove boehm-gc reference. 9131 Document GMP, MPFR caveats on Solaris 11.3. 9132 (Specific, sparc-sun-solaris2*): Update Solaris 9 references. 9133 (Specific, sparc64-*-solaris2*): Likewise. 9134 Document --build requirement. 9135 91362020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 9137 9138 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris. 9139 * configure: Regenerate. 9140 91412020-05-04 Richard Sandiford <richard.sandiford@arm.com> 9142 9143 PR middle-end/94941 9144 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the 9145 chosen lhs is different from the gcall lhs. 9146 (expand_mask_load_optab_fn): Likewise. 9147 (expand_gather_load_optab_fn): Likewise. 9148 91492020-05-04 Marek Polacek <polacek@redhat.com> 9150 9151 Revert: 9152 2020-04-30 Marek Polacek <polacek@redhat.com> 9153 9154 PR c++/94775 9155 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. 9156 (check_aligned_type): Check if TYPE_USER_ALIGN match. 9157 91582020-05-02 Jakub Jelinek <jakub@redhat.com> 9159 9160 * config/tilegx/tilegx.md 9161 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n> 9162 rather than just <n>. 9163 91642020-04-30 Alexandre Oliva <oliva@adacore.com> 9165 9166 * doc/sourcebuild.texi (Effective-Target Keywords): Document 9167 the newly-introduced fileio effective target. 9168 91692020-04-30 Richard Sandiford <richard.sandiford@arm.com> 9170 9171 PR rtl-optimization/94740 9172 * cse.c (cse_process_notes_1): Replace with... 9173 (cse_process_note_1): ...this new function, acting as a 9174 simplify_replace_fn_rtx callback to process_note. Handle only 9175 REGs and MEMs directly. Validate the MEM if cse_process_note 9176 changes its address. 9177 (cse_process_notes): Replace with... 9178 (cse_process_note): ...this new function. 9179 (cse_extended_basic_block): Update accordingly, iterating over 9180 the register notes and passing individual notes to cse_process_note. 9181 91822020-04-30 Martin Jambor <mjambor@suse.cz> 9183 9184 PR ipa/94856 9185 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies 9186 saved by the inliner and thunks which had their call inlined. 9187 * ipa-inline-transform.c (save_inline_function_body): Fill in 9188 former_clone_of of new body holders. 9189 91902020-04-30 Jakub Jelinek <jakub@redhat.com> 9191 9192 * DEV-PHASE: Set to prerelease. 9193 91942020-04-30 Jonathan Wakely <jwakely@redhat.com> 9195 9196 * pretty-print.c (pp_take_prefix): Fix spelling in comment. 9197 91982020-04-30 Marek Polacek <polacek@redhat.com> 9199 9200 PR c++/94775 9201 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. 9202 (check_aligned_type): Check if TYPE_USER_ALIGN match. 9203 92042020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 9205 9206 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define. 9207 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable. 9208 * doc/invoke.texi (moutline-atomics): Document as on by default. 9209 92102020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com> 9211 9212 PR target/94748 9213 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove 9214 the check for NOTE_INSN_DELETED_LABEL. 9215 92162020-04-30 Jakub Jelinek <jakub@redhat.com> 9217 9218 * configure.ac (--with-documentation-root-url, 9219 --with-changes-root-url): Diagnose URL not ending with /, 9220 use AC_DEFINE_UNQUOTED instead of AC_SUBST. 9221 * opts.h (get_changes_url): Remove. 9222 * opts.c (get_changes_url): Remove. 9223 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL 9224 or -DCHANGES_ROOT_URL. 9225 * doc/install.texi (--with-documentation-root-url, 9226 --with-changes-root-url): Document. 9227 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call 9228 get_changes_url and free, change url variable type to const char * and 9229 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base". 9230 * config/s390/s390.c (s390_function_arg_vector, 9231 s390_function_arg_float): Likewise. 9232 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): 9233 Likewise. 9234 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): 9235 Likewise. 9236 * config.in: Regenerate. 9237 * configure: Regenerate. 9238 92392020-04-30 Christophe Lyon <christophe.lyon@linaro.org> 9240 9241 PR target/57002 9242 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries. 9243 92442020-04-30 Andreas Krebbel <krebbel@linux.ibm.com> 9245 9246 * config/s390/constraints.md ("j>f", "jb4"): New constraints. 9247 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix 9248 macro definitions. 9249 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a 9250 separate expander. 9251 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst. 9252 Change constraint for vlrl/vstrl to jb4. 9253 92542020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 9255 9256 * var-tracking.c (vt_initialize): Move variables pre and post 9257 into inner block and initialize both in order to fix warning 9258 about uninitialized use. Remove unnecessary checks for 9259 frame_pointer_needed. 9260 92612020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 9262 9263 * toplev.c (output_stack_usage_1): Ensure that first 9264 argument to fprintf is not null. 9265 92662020-04-29 Jakub Jelinek <jakub@redhat.com> 9267 9268 * configure.ac (-with-changes-root-url): New configure option, 9269 defaulting to https://gcc.gnu.org/. 9270 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for 9271 opts.c. 9272 * pretty-print.c (get_end_url_string): New function. 9273 (pp_format): Handle %{ and %} for URLs. 9274 (pp_begin_url): Use pp_string instead of pp_printf. 9275 (pp_end_url): Use get_end_url_string. 9276 * opts.h (get_changes_url): Declare. 9277 * opts.c (get_changes_url): New function. 9278 * config/rs6000/rs6000-call.c: Include opts.h. 9279 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead 9280 of just in GCC 10.1 in diagnostics and add URL. 9281 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise. 9282 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): 9283 Likewise. 9284 * config/s390/s390.c (s390_function_arg_vector, 9285 s390_function_arg_float): Likewise. 9286 * configure: Regenerated. 9287 9288 PR target/94704 9289 * config/s390/s390.c (s390_function_arg_vector, 9290 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of 9291 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type 9292 passed to the function rather than the type of the single element. 9293 Rename cxx17_empty_base_seen variable to empty_base_seen, change 9294 type to int, and adjust diagnostics depending on if the field 9295 has [[no_unique_attribute]] or not. 9296 9297 PR target/94832 9298 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8, 9299 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands 9300 used in casts into parens. 9301 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph, 9302 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph, 9303 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph, 9304 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask, 9305 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask, 9306 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask, 9307 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise. 9308 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8, 9309 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8, 9310 _mm256_mask_cmp_epu8_mask): Likewise. 9311 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph, 9312 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise. 9313 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise. 9314 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise. 9315 9316 PR target/94832 9317 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd, 9318 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd, 9319 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps, 9320 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps, 9321 _mm256_mask_i64gather_ps, _mm_i32gather_epi64, 9322 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64, 9323 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64, 9324 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64, 9325 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32, 9326 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32, 9327 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32, 9328 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32, 9329 _mm256_mask_i64gather_epi32): Surround macro parameter uses with 9330 parens. 9331 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd, 9332 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps, 9333 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use 9334 as mask vector containing -1.0 or -1.0f elts, but instead vector 9335 with all bits set using _mm*_cmpeq_p? with zero operands. 9336 * config/i386/avx512fintrin.h (_mm512_i32gather_ps, 9337 _mm512_mask_i32gather_ps, _mm512_i32gather_pd, 9338 _mm512_mask_i32gather_pd, _mm512_i64gather_ps, 9339 _mm512_mask_i64gather_ps, _mm512_i64gather_pd, 9340 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32, 9341 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64, 9342 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32, 9343 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64, 9344 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps, 9345 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd, 9346 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps, 9347 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd, 9348 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32, 9349 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64, 9350 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32, 9351 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64, 9352 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with 9353 parens. 9354 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd, 9355 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd, 9356 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd, 9357 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd, 9358 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd, 9359 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd, 9360 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd, 9361 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd, 9362 _mm512_mask_prefetch_i64scatter_ps): Likewise. 9363 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps, 9364 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd, 9365 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps, 9366 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd, 9367 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32, 9368 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64, 9369 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32, 9370 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64, 9371 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps, 9372 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps, 9373 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd, 9374 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps, 9375 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps, 9376 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd, 9377 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32, 9378 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32, 9379 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64, 9380 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64, 9381 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32, 9382 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32, 9383 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64, 9384 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64, 9385 _mm_mask_i64scatter_epi64): Likewise. 9386 93872020-04-29 Jeff Law <law@redhat.com> 9388 9389 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific 9390 division instructions are 4 bytes long. 9391 93922020-04-29 Jakub Jelinek <jakub@redhat.com> 9393 9394 PR target/94826 9395 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use 9396 TARGET_EXPR instead of MODIFY_EXPR for first assignment to 9397 fenv_var, fenv_clear and old_fenv variables. For fenv_addr 9398 take address of TARGET_EXPR of fenv_var with void_node initializer. 9399 Formatting fixes. 9400 94012020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> 9402 9403 PR tree-optimization/94774 9404 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize 9405 variable retval. 9406 94072020-04-29 Richard Sandiford <richard.sandiford@arm.com> 9408 9409 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration. 9410 * calls.c (cxx17_empty_base_field_p): New function. Check 9411 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the 9412 previous checks. 9413 94142020-04-29 H.J. Lu <hongjiu.lu@intel.com> 9415 9416 PR target/93654 9417 * config/i386/i386-options.c (ix86_set_indirect_branch_type): 9418 Allow -fcf-protection with -mindirect-branch=thunk-extern and 9419 -mfunction-return=thunk-extern. 9420 * doc/invoke.texi: Update notes for -fcf-protection=branch with 9421 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern. 9422 94232020-04-29 Richard Sandiford <richard.sandiford@arm.com> 9424 9425 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor. 9426 94272020-04-29 Richard Sandiford <richard.sandiford@arm.com> 9428 9429 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use 9430 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to 9431 fenv_var and new_fenv_var. 9432 94332020-04-29 Richard Sandiford <richard.sandiford@arm.com> 9434 9435 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new 9436 effective-target keyword. 9437 (arm_arch_v8a_hard_multilib): Likewise. 9438 (arm_arch_v8a_hard): Document new dg-add-options keyword. 9439 * config/arm/arm.c (arm_return_in_memory): Note that the APCS 9440 code is deprecated and has not been updated to handle 9441 DECL_FIELD_ABI_IGNORED. 9442 (WARN_PSABI_EMPTY_CXX17_BASE): New constant. 9443 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. 9444 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter 9445 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields 9446 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether 9447 something actually is a HFA or HVA. Record whether we see a 9448 [[no_unique_address]] field that previous GCCs would not have 9449 ignored in this way. 9450 (aapcs_vfp_is_call_or_return_candidate): Update the calls to 9451 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the 9452 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the 9453 diagnostic messages. 9454 (arm_needs_doubleword_align): Add a comment explaining why we 9455 consider even zero-sized fields. 9456 94572020-04-29 Richard Biener <rguenther@suse.de> 9458 Li Zekun <lizekun1@huawei.com> 9459 9460 PR lto/94822 9461 * tree.c (component_ref_size): Guard against error_mark_node 9462 DECL_INITIAL as it happens with LTO. 9463 94642020-04-29 Richard Sandiford <richard.sandiford@arm.com> 9465 9466 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a 9467 comment explaining why we consider even zero-sized fields. 9468 (WARN_PSABI_EMPTY_CXX17_BASE): New constant. 9469 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. 9470 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter 9471 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields 9472 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether 9473 something actually is a HFA or HVA. Record whether we see a 9474 [[no_unique_address]] field that previous GCCs would not have 9475 ignored in this way. 9476 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say 9477 whether diagnostics should be suppressed. Update the calls to 9478 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the 9479 [[no_unique_address]] case. 9480 (aarch64_return_in_msb): Update call accordingly, never silencing 9481 diagnostics. 9482 (aarch64_function_value): Likewise. 9483 (aarch64_return_in_memory_1): Likewise. 9484 (aarch64_init_cumulative_args): Likewise. 9485 (aarch64_gimplify_va_arg_expr): Likewise. 9486 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and 9487 use it to decide whether arch64_vfp_is_call_or_return_candidate 9488 should be silent. 9489 (aarch64_pass_by_reference): Update calls accordingly. 9490 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument 9491 to decide whether arch64_vfp_is_call_or_return_candidate should be 9492 silent. 9493 94942020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com> 9495 9496 PR target/94820 9497 * config/aarch64/aarch64-builtins.c 9498 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of 9499 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and 9500 new_fenv_var. 9501 95022020-04-29 Thomas Schwinge <thomas@codesourcery.com> 9503 9504 * configure.ac <$enable_offload_targets>: Do parsing as done 9505 elsewhere. 9506 * configure: Regenerate. 9507 9508 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'. 9509 * configure: Regenerate. 9510 9511 PR target/94279 9512 * rtlanal.c (set_noop_p): Handle non-constant selectors. 9513 9514 PR target/94282 9515 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New 9516 function. 9517 (TARGET_EXCEPT_UNWIND_INFO): Define. 9518 95192020-04-29 Jakub Jelinek <jakub@redhat.com> 9520 9521 PR target/94248 9522 * config/gcn/gcn.md (*mov<mode>_insn): Use 9523 'reg_overlap_mentioned_p' to check for overlap. 9524 9525 PR target/94706 9526 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED 9527 instead of cxx17_empty_base_field_p. 9528 9529 PR target/94707 9530 * tree-core.h (tree_decl_common): Note decl_flag_0 used for 9531 DECL_FIELD_ABI_IGNORED. 9532 * tree.h (DECL_FIELD_ABI_IGNORED): Define. 9533 * calls.h (cxx17_empty_base_field_p): Change into a temporary 9534 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address" 9535 attribute. 9536 * calls.c (cxx17_empty_base_field_p): Remove. 9537 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle 9538 DECL_FIELD_ABI_IGNORED. 9539 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise. 9540 * lto-streamer-out.c (hash_tree): Likewise. 9541 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename 9542 cxx17_empty_base_seen to empty_base_seen, change type to int *, 9543 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of 9544 cxx17_empty_base_field_p, if "no_unique_address" attribute is 9545 present, propagate that to the caller too. 9546 (rs6000_discover_homogeneous_aggregate): Adjust 9547 rs6000_aggregate_candidate caller, emit different diagnostics 9548 when c++17 empty base fields are present and when empty 9549 [[no_unique_address]] fields are present. 9550 * config/rs6000/rs6000.c (rs6000_special_round_type_align, 9551 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED 9552 fields. 9553 95542020-04-29 Richard Biener <rguenther@suse.de> 9555 9556 * tree-ssa-loop-im.c (ref_always_accessed::operator ()): 9557 Just check whether the stmt stores. 9558 95592020-04-28 Alexandre Oliva <oliva@adacore.com> 9560 9561 PR target/94812 9562 * gcc/config/rs6000/rs6000.md (rs6000_mffsl): Copy result to 9563 output operand in emulation. Don't overwrite pseudos. 9564 95652020-04-28 Jeff Law <law@redhat.com> 9566 9567 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific 9568 multiply patterns are 4 bytes long. 9569 95702020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 9571 9572 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option. 9573 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option. 9574 95752020-04-28 Matthew Malcomson <matthew.malcomson@arm.com> 9576 Jakub Jelinek <jakub@redhat.com> 9577 9578 PR target/94711 9579 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty 9580 base class artificial fields. 9581 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI 9582 decision is different after this fix. 9583 95842020-04-28 David Malcolm <dmalcolm@redhat.com> 9585 9586 PR analyzer/94447 9587 PR analyzer/94639 9588 PR analyzer/94732 9589 PR analyzer/94754 9590 * doc/invoke.texi (Static Analyzer Options): Remove 9591 -Wanalyzer-use-of-uninitialized-value. 9592 (-Wno-analyzer-use-of-uninitialized-value): Remove item. 9593 95942020-04-28 Jakub Jelinek <jakub@redhat.com> 9595 9596 PR tree-optimization/94809 9597 * tree.c (build_call_expr_internal_loc_array): Call 9598 process_call_operands. 9599 96002020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com> 9601 9602 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name. 9603 * config/aarch64/aarch64-tune.md: Regenerate. 9604 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define. 9605 (thunderx3t110_regmove_cost): Likewise. 9606 (thunderx3t110_vector_cost): Likewise. 9607 (thunderx3t110_prefetch_tune): Likewise. 9608 (thunderx3t110_tunings): Likewise. 9609 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs): 9610 Define. 9611 * config/aarch64/thunderx3t110.md: New file. 9612 * config/aarch64/aarch64.md: Include thunderx3t110.md. 9613 * doc/invoke.texi (AArch64 options): Add thunderx3t110. 9614 96152020-04-28 Jakub Jelinek <jakub@redhat.com> 9616 9617 PR target/94704 9618 * config/s390/s390.c (s390_function_arg_vector, 9619 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed. 9620 96212020-04-28 Richard Sandiford <richard.sandiford@arm.com> 9622 9623 PR tree-optimization/94727 9624 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison 9625 operands are invariant booleans, use the mask type associated with the 9626 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP. 9627 (vectorizable_condition): Pass vectype unconditionally to 9628 vect_is_simple_cond. 9629 96302020-04-27 Jakub Jelinek <jakub@redhat.com> 9631 9632 PR target/94780 9633 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use 9634 TARGET_EXPR instead of MODIFY_EXPR for first assignment to 9635 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var. 9636 96372020-04-27 David Malcolm <dmalcolm@redhat.com> 9638 9639 PR 92830 9640 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from 9641 default value, so that it can by supplied by get_option_html_page. 9642 * configure: Regenerate. 9643 * opts.c: Include "selftest.h". 9644 (get_option_html_page): New function. 9645 (get_option_url): Use it. Reformat to place comments next to the 9646 expressions they refer to. 9647 (selftest::test_get_option_html_page): New. 9648 (selftest::opts_c_tests): New. 9649 * selftest-run-tests.c (selftest::run_tests): Call 9650 selftest::opts_c_tests. 9651 * selftest.h (selftest::opts_c_tests): New decl. 9652 96532020-04-27 Richard Sandiford <richard.sandiford@arm.com> 9654 9655 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply 9656 UINTVAL to CONST_INTs. 9657 96582020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 9659 9660 * config/arm/constraints.md (e): Remove constraint. 9661 (Te): Define constraint. 9662 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in 9663 operand 0 from "e" to "Te". 9664 (vaddvaq_<supf><mode>): Likewise. 9665 (vaddvq_p_<supf><mode>): Likewise. 9666 (vmladavq_<supf><mode>): Likewise. 9667 (vmladavxq_s<mode>): Likewise. 9668 (vmlsdavq_s<mode>): Likewise. 9669 (vmlsdavxq_s<mode>): Likewise. 9670 (vaddvaq_p_<supf><mode>): Likewise. 9671 (vmladavaq_<supf><mode>): Likewise. 9672 (vmladavq_p_<supf><mode>): Likewise. 9673 (vmladavxq_p_s<mode>): Likewise. 9674 (vmlsdavq_p_s<mode>): Likewise. 9675 (vmlsdavxq_p_s<mode>): Likewise. 9676 (vmlsdavaxq_s<mode>): Likewise. 9677 (vmlsdavaq_s<mode>): Likewise. 9678 (vmladavaxq_s<mode>): Likewise. 9679 (vmladavaq_p_<supf><mode>): Likewise. 9680 (vmladavaxq_p_s<mode>): Likewise. 9681 (vmlsdavaq_p_s<mode>): Likewise. 9682 (vmlsdavaxq_p_s<mode>): Likewise. 9683 96842020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com> 9685 9686 * config/arm/arm.c (output_move_neon): Only get the first operand if 9687 addr is PLUS. 9688 96892020-04-27 Felix Yang <felix.yang@huawei.com> 9690 9691 PR tree-optimization/94784 9692 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the 9693 assert around so that it checks that the two vectors have equal 9694 TYPE_VECTOR_SUBPARTS and that converting the corresponding element 9695 types is a useless_type_conversion_p. 9696 96972020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com> 9698 9699 PR target/94515 9700 * dwarf2cfi.c (struct GTY): Add ra_mangled. 9701 (cfi_row_equal_p): Check ra_mangled. 9702 (dwarf2out_frame_debug_cfa_window_save): Remove the argument, 9703 this only handles the sparc logic now. 9704 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for 9705 the aarch64 specific logic. 9706 (dwarf2out_frame_debug): Update to use the new subroutines. 9707 (change_cfi_row): Check ra_mangled. 9708 97092020-04-27 Jakub Jelinek <jakub@redhat.com> 9710 9711 PR target/94704 9712 * config/s390/s390.c (s390_function_arg_vector, 9713 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields. 9714 97152020-04-27 Jiufu Guo <guojiufu@cn.ibm.com> 9716 9717 * common/config/rs6000/rs6000-common.c 9718 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off 9719 -fweb. 9720 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to 9721 set flag_web. 9722 97232020-04-27 Martin Liska <mliska@suse.cz> 9724 9725 PR lto/94659 9726 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p): 9727 Do not remove ifunc_resolvers in remove unreachable nodes in LTO. 9728 97292020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com> 9730 9731 PR target/91518 9732 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed): 9733 New variable. 9734 (rs6000_emit_prologue_components): 9735 Check with frame_pointer_needed_indeed. 9736 (rs6000_emit_epilogue_components): Likewise. 9737 (rs6000_emit_prologue): Likewise. 9738 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed. 9739 97402020-04-25 David Edelsohn <dje.gcc@gmail.com> 9741 9742 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a 9743 stack frame when debugging and flag_compare_debug is enabled. 9744 97452020-04-25 Michael Meissner <meissner@linux.ibm.com> 9746 9747 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to 9748 enable PC-relative addressing for -mcpu=future. 9749 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move 9750 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS. 9751 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined, 9752 suppress PC-relative addressing. 9753 (rs6000_option_override_internal): Split up error messages 9754 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target 9755 system supports it. 9756 97572020-04-25 Jakub Jelinek <jakub@redhat.com> 9758 Richard Biener <rguenther@suse.de> 9759 9760 PR tree-optimization/94734 9761 PR tree-optimization/89430 9762 * tree-ssa-phiopt.c: Include tree-eh.h. 9763 (cond_store_replacement): Return false if an automatic variable 9764 access could trap. If -fstore-data-races, don't return false 9765 just because an automatic variable is addressable. 9766 97672020-04-24 Andrew Stubbs <ams@codesourcery.com> 9768 9769 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge 9770 of high-part. 9771 (add<mode>_sext_dup2_exec): Likewise. 9772 97732020-04-24 Segher Boessenkool <segher@kernel.crashing.org> 9774 9775 PR target/94710 9776 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little 9777 endian byteshift_val calculation. 9778 97792020-04-24 Andrew Stubbs <ams@codesourcery.com> 9780 9781 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload. 9782 97832020-04-24 Richard Sandiford <richard.sandiford@arm.com> 9784 9785 * config/aarch64/arm_sve.h: Add a comment. 9786 97872020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com> 9788 9789 PR rtl-optimization/94708 9790 * combine.c (simplify_if_then_else): Add check for 9791 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode). 9792 97932020-04-23 Martin Sebor <msebor@redhat.com> 9794 9795 PR driver/90983 9796 * common.opt (-Wno-frame-larger-than): New option. 9797 (-Wno-larger-than, -Wno-stack-usage): Same. 9798 97992020-04-23 Andrew Stubbs <ams@codesourcery.com> 9800 9801 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands 9802 2 and 3. 9803 (mov<mode>_exec): Likewise. 9804 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec. 9805 (<convop><mode><vndi>2_exec): Likewise. 9806 98072019-04-23 Eric Botcazou <ebotcazou@adacore.com> 9808 9809 PR tree-optimization/94717 9810 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one 9811 of the stores doesn't have the same landing pad number as the first. 9812 (coalesce_immediate_stores): Do not try to coalesce the store using 9813 bswap if it doesn't have the same landing pad number as the first. 9814 98152020-04-23 Bill Schmidt <wschmidt@linux.ibm.com> 9816 9817 * gcc/doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): 9818 Replace outdated link to ELFv2 ABI. 9819 98202020-04-23 Jakub Jelinek <jakub@redhat.com> 9821 9822 PR target/94710 9823 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx 9824 just return v2. 9825 9826 PR middle-end/94724 9827 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs 9828 temporarily with non-final second operand and updating it later, 9829 push COMPOUND_EXPRs into a vector and process it in reverse, 9830 creating COMPOUND_EXPRs with the final operands. 9831 98322020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com> 9833 9834 PR target/94697 9835 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap 9836 bti c and bti j handling. 9837 98382020-04-23 Andrew Stubbs <ams@codesourcery.com> 9839 Thomas Schwinge <thomas@codesourcery.com> 9840 9841 PR middle-end/93488 9842 9843 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on 9844 t_async and the wait arguments. 9845 98462020-04-23 Richard Sandiford <richard.sandiford@arm.com> 9847 9848 PR tree-optimization/94727 9849 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when 9850 comparing invariant scalar booleans. 9851 98522020-04-23 Matthew Malcomson <matthew.malcomson@arm.com> 9853 Jakub Jelinek <jakub@redhat.com> 9854 9855 PR target/94383 9856 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17 9857 empty base class artificial fields. 9858 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is 9859 different after this fix. 9860 98612020-04-23 Jakub Jelinek <jakub@redhat.com> 9862 9863 PR target/94707 9864 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): 9865 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check 9866 if the same type has been diagnosed most recently already. 9867 98682020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 9869 9870 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's 9871 datatype. 9872 (__arm_vbicq_n_s16): Likewise. 9873 (__arm_vbicq_n_u32): Likewise. 9874 (__arm_vbicq_n_s32): Likewise. 9875 (__arm_vbicq): Likewise. 9876 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype. 9877 (__arm_vbicq_n_s32): Likewise. 9878 (__arm_vbicq_n_u16): Likewise. 9879 (__arm_vbicq_n_u32): Likewise. 9880 (__arm_vdupq_m_n_s8): Likewise. 9881 (__arm_vdupq_m_n_s16): Likewise. 9882 (__arm_vdupq_m_n_s32): Likewise. 9883 (__arm_vdupq_m_n_u8): Likewise. 9884 (__arm_vdupq_m_n_u16): Likewise. 9885 (__arm_vdupq_m_n_u32): Likewise. 9886 (__arm_vdupq_m_n_f16): Likewise. 9887 (__arm_vdupq_m_n_f32): Likewise. 9888 (__arm_vldrhq_gather_offset_s16): Likewise. 9889 (__arm_vldrhq_gather_offset_s32): Likewise. 9890 (__arm_vldrhq_gather_offset_u16): Likewise. 9891 (__arm_vldrhq_gather_offset_u32): Likewise. 9892 (__arm_vldrhq_gather_offset_f16): Likewise. 9893 (__arm_vldrhq_gather_offset_z_s16): Likewise. 9894 (__arm_vldrhq_gather_offset_z_s32): Likewise. 9895 (__arm_vldrhq_gather_offset_z_u16): Likewise. 9896 (__arm_vldrhq_gather_offset_z_u32): Likewise. 9897 (__arm_vldrhq_gather_offset_z_f16): Likewise. 9898 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 9899 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 9900 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 9901 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 9902 (__arm_vldrhq_gather_shifted_offset_f16): Likewise. 9903 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 9904 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 9905 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 9906 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 9907 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise. 9908 (__arm_vldrwq_gather_offset_s32): Likewise. 9909 (__arm_vldrwq_gather_offset_u32): Likewise. 9910 (__arm_vldrwq_gather_offset_f32): Likewise. 9911 (__arm_vldrwq_gather_offset_z_s32): Likewise. 9912 (__arm_vldrwq_gather_offset_z_u32): Likewise. 9913 (__arm_vldrwq_gather_offset_z_f32): Likewise. 9914 (__arm_vldrwq_gather_shifted_offset_s32): Likewise. 9915 (__arm_vldrwq_gather_shifted_offset_u32): Likewise. 9916 (__arm_vldrwq_gather_shifted_offset_f32): Likewise. 9917 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise. 9918 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise. 9919 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise. 9920 (__arm_vdwdupq_x_n_u8): Likewise. 9921 (__arm_vdwdupq_x_n_u16): Likewise. 9922 (__arm_vdwdupq_x_n_u32): Likewise. 9923 (__arm_viwdupq_x_n_u8): Likewise. 9924 (__arm_viwdupq_x_n_u16): Likewise. 9925 (__arm_viwdupq_x_n_u32): Likewise. 9926 (__arm_vidupq_x_n_u8): Likewise. 9927 (__arm_vddupq_x_n_u8): Likewise. 9928 (__arm_vidupq_x_n_u16): Likewise. 9929 (__arm_vddupq_x_n_u16): Likewise. 9930 (__arm_vidupq_x_n_u32): Likewise. 9931 (__arm_vddupq_x_n_u32): Likewise. 9932 (__arm_vldrdq_gather_offset_s64): Likewise. 9933 (__arm_vldrdq_gather_offset_u64): Likewise. 9934 (__arm_vldrdq_gather_offset_z_s64): Likewise. 9935 (__arm_vldrdq_gather_offset_z_u64): Likewise. 9936 (__arm_vldrdq_gather_shifted_offset_s64): Likewise. 9937 (__arm_vldrdq_gather_shifted_offset_u64): Likewise. 9938 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise. 9939 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise. 9940 (__arm_vidupq_m_n_u8): Likewise. 9941 (__arm_vidupq_m_n_u16): Likewise. 9942 (__arm_vidupq_m_n_u32): Likewise. 9943 (__arm_vddupq_m_n_u8): Likewise. 9944 (__arm_vddupq_m_n_u16): Likewise. 9945 (__arm_vddupq_m_n_u32): Likewise. 9946 (__arm_vidupq_n_u16): Likewise. 9947 (__arm_vidupq_n_u32): Likewise. 9948 (__arm_vidupq_n_u8): Likewise. 9949 (__arm_vddupq_n_u16): Likewise. 9950 (__arm_vddupq_n_u32): Likewise. 9951 (__arm_vddupq_n_u8): Likewise. 9952 99532020-04-23 Iain Buclaw <ibuclaw@gdcproject.org> 9954 9955 * doc/install.texi (D-Specific Options): Document 9956 --enable-libphobos-checking and --with-libphobos-druntime-only. 9957 99582020-04-23 Jakub Jelinek <jakub@redhat.com> 9959 9960 PR target/94707 9961 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add 9962 cxx17_empty_base_seen argument. Pass it to recursive calls. 9963 Ignore cxx17_empty_base_field_p fields after setting 9964 *cxx17_empty_base_seen to true. 9965 (rs6000_discover_homogeneous_aggregate): Adjust 9966 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous 9967 aggregates with C++17 empty base fields. 9968 9969 PR c/94705 9970 * attribs.c (decl_attribute): Don't diagnose attribute exclusions 9971 if last_decl is error_mark_node or has such a TREE_TYPE. 9972 9973 PR c/94705 9974 * attribs.c (decl_attribute): Don't diagnose attribute exclusions 9975 if last_decl is error_mark_node or has such a TREE_TYPE. 9976 99772020-04-22 Felix Yang <felix.yang@huawei.com> 9978 9979 PR target/94678 9980 * config/aarch64/aarch64.h (TARGET_SVE): 9981 Add && !TARGET_GENERAL_REGS_ONLY. 9982 (TARGET_SVE2): Add && TARGET_SVE. 9983 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3, 9984 TARGET_SVE2_SM4): Add && TARGET_SVE2. 9985 * config/aarch64/aarch64-sve-builtins.h 9986 (sve_switcher::m_old_general_regs_only): New member. 9987 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers): 9988 New function. 9989 (reported_missing_registers_p): New variable. 9990 (check_required_extensions): Call check_required_registers before 9991 return if all required extenstions are present. 9992 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in 9993 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in 9994 global_options.x_target_flags. 9995 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in 9996 global_options.x_target_flags if m_old_general_regs_only is true. 9997 99982020-04-22 Zackery Spytz <zspytz@gmail.com> 9999 10000 * doc/extend.exi: Add "free" to list of other builtin functions 10001 supported by GCC. 10002 100032020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com> 10004 10005 PR target/94622 10006 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed" 10007 if TARGET_PREFIXED. 10008 (store_quadpti): Ditto. 10009 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as 10010 plq will be used and doesn't need it. 10011 (atomic_store<mode>): Ditto, for pstq. 10012 100132020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com> 10014 10015 * doc/invoke.texi: Update flags turned on by -O3. 10016 100172020-04-22 Jakub Jelinek <jakub@redhat.com> 10018 10019 PR target/94706 10020 * config/ia64/ia64.c (hfa_element_mode): Ignore 10021 cxx17_empty_base_field_p fields. 10022 10023 PR target/94383 10024 * calls.h (cxx17_empty_base_field_p): Declare. 10025 * calls.c (cxx17_empty_base_field_p): Define. 10026 100272020-04-22 Christophe Lyon <christophe.lyon@linaro.org> 10028 10029 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document. 10030 100312020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 10032 Andre Vieira <andre.simoesdiasvieira@arm.com> 10033 Mihail Ionescu <mihail.ionescu@arm.com> 10034 10035 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu. 10036 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define. 10037 (ALL_QUIRKS): Add quirk_no_asmcpu. 10038 (cortex-m55): Define new cpu. 10039 * config/arm/arm-tables.opt: Regenerate. 10040 * config/arm/arm-tune.md: Likewise. 10041 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55. 10042 100432020-04-22 Richard Sandiford <richard.sandiford@arm.com> 10044 10045 PR tree-optimization/94700 10046 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing 10047 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures 10048 of similarly-structured but distinct vector types. 10049 100502020-04-21 Martin Sebor <msebor@redhat.com> 10051 10052 PR middle-end/94647 10053 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct 10054 the computation of the lower bound of the source access size. 10055 (builtin_access::generic_overlap): Remove a hack for setting ranges 10056 of overlap offsets. 10057 100582020-04-21 John David Anglin <danglin@gcc.gnu.org> 10059 10060 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete. 10061 (ASM_WEAKEN_DECL): New define. 10062 (HAVE_GAS_WEAKREF): Undefine. 10063 100642020-04-21 Richard Sandiford <richard.sandiford@arm.com> 10065 10066 PR tree-optimization/94683 10067 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a 10068 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured 10069 but distinct vector types. 10070 100712020-04-21 Jakub Jelinek <jakub@redhat.com> 10072 10073 PR c/94641 10074 * stor-layout.c (place_field, finalize_record_size): Don't emit 10075 -Wpadded warning on TYPE_ARTIFICIAL rli->t. 10076 * ubsan.c (ubsan_get_type_descriptor_type, 10077 ubsan_get_source_location_type, ubsan_create_data): Set 10078 TYPE_ARTIFICIAL. 10079 * asan.c (asan_global_struct): Likewise. 10080 100812020-04-21 Duan bo <duanbo3@huawei.com> 10082 10083 PR target/94577 10084 * config/aarch64/aarch64.c: Add an error message for option conflict. 10085 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is 10086 incompatible with -fpic, -fPIC and -mabi=ilp32. 10087 100882020-04-21 Frederik Harwath <frederik@codesourcery.com> 10089 10090 PR other/94629 10091 * omp-low.c (new_omp_context): Remove assignments to 10092 ctx->outer_reduction_clauses and ctx->local_reduction_clauses. 10093 100942020-04-20 Andreas Krebbel <krebbel@linux.ibm.com> 10095 10096 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx") 10097 ("popcountv2di2_vx"): Use simplify_gen_subreg. 10098 100992020-04-20 Andreas Krebbel <krebbel@linux.ibm.com> 10100 10101 PR target/94613 10102 * config/s390/s390-builtin-types.def: Add 3 new function modes. 10103 * config/s390/s390-builtins.def: Add mode dependent low-level 10104 builtin and map the overloaded builtins to these. 10105 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ... 10106 ("vsel<V_HW"): ... this and rewrite the pattern with bitops. 10107 101082020-04-20 Richard Sandiford <richard.sandiford@arm.com> 10109 10110 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo 10111 has a variable VF, prefer new_loop_vinfo if it is cheaper for the 10112 estimated VF and is no worse at double the estimated VF. 10113 101142020-04-20 Richard Sandiford <richard.sandiford@arm.com> 10115 10116 PR target/94668 10117 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix 10118 order of arguments to rtx_vector_builder. 10119 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise. 10120 When extending the trailing constants to a full vector, replace any 10121 variables with zeros. 10122 101232020-04-20 Jan Hubicka <hubicka@ucw.cz> 10124 10125 PR ipa/94582 10126 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local 10127 flag. 10128 101292020-04-20 Martin Liska <mliska@suse.cz> 10130 10131 * symtab.c (symtab_node::dump_references): Add space after 10132 one entry. 10133 (symtab_node::dump_referring): Likewise. 10134 101352020-04-18 Jeff Law <law@redhat.com> 10136 10137 PR debug/94439 10138 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking 10139 the chain. 10140 101412020-04-18 Iain Buclaw <ibuclaw@gdcproject.org> 10142 10143 * doc/sourcebuild.texi (Effective-Target Keywords, Environment 10144 attributes): Document d_runtime_has_std_library. 10145 101462020-04-17 Jeff Law <law@redhat.com> 10147 10148 PR rtl-optimization/90275 10149 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels 10150 when the destination has a REG_UNUSED note. 10151 101522020-04-17 Tobias Burnus <tobias@codesourcery.com> 10153 10154 PR middle-end/94635 10155 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to 10156 MAP_DELETE. 10157 101582020-04-17 Richard Sandiford <richard.sandiford@arm.com> 10159 10160 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function. 10161 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the 10162 cost of load and store insns if one loop iteration has enough scalar 10163 elements to use an Advanced SIMD LDP or STP. 10164 (aarch64_add_stmt_cost): Update call accordingly. 10165 101662020-04-17 Jakub Jelinek <jakub@redhat.com> 10167 Jeff Law <law@redhat.com> 10168 10169 PR target/94567 10170 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than 10171 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision, 10172 or pos + len >= 32, or pos + len is equal to operands[2] precision 10173 and operands[2] is not a register operand. During splitting perform 10174 SImode AND if operands[0] doesn't have CCZmode and pos + len is 10175 equal to mode precision. 10176 101772020-04-17 Richard Biener <rguenther@suse.de> 10178 10179 PR other/94629 10180 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate 10181 initialization. 10182 * dwarf2out.c (dw_val_equal_p): Fix pasto in 10183 dw_val_class_vms_delta comparison. 10184 * optabs.c (expand_binop_directly): Fix pasto in commutation 10185 check. 10186 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in 10187 initialization. 10188 101892020-04-17 Jakub Jelinek <jakub@redhat.com> 10190 10191 PR rtl-optimization/94618 10192 * cfgrtl.c (delete_insn_and_edges): Set purge not just when 10193 insn is the BB_END of its block, but also when it is only followed 10194 by DEBUG_INSNs in its block. 10195 10196 PR tree-optimization/94621 10197 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN. 10198 Move id->adjust_array_error_bounds check first in the condition. 10199 102002020-04-17 Martin Liska <mliska@suse.cz> 10201 Jonathan Yong <10walls@gmail.com> 10202 10203 PR gcov-profile/94570 10204 * coverage.c (coverage_init): Use separator properly. 10205 102062020-04-16 Peter Bergner <bergner@linux.ibm.com> 10207 10208 PR rtl-optimization/93974 10209 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define. 10210 (rs6000_cannot_substitute_mem_equiv_p): New function. 10211 102122020-04-16 Martin Jambor <mjambor@suse.cz> 10213 10214 PR ipa/93621 10215 * ipa-inline.h (ipa_saved_clone_sources): Declare. 10216 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable. 10217 (save_inline_function_body): Link the new body holder with the 10218 previous one. 10219 * cgraph.c: Include ipa-inline.h. 10220 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from 10221 the statement in ipa_saved_clone_sources. 10222 * cgraphunit.c: Include ipa-inline.h. 10223 (expand_all_functions): Free ipa_saved_clone_sources. 10224 102252020-04-16 Richard Sandiford <richard.sandiford@arm.com> 10226 10227 PR target/94606 10228 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take 10229 the VNx16BI lowpart of the recursively-generated constant. 10230 102312020-04-16 Martin Liska <mliska@suse.cz> 10232 Jakub Jelinek <jakub@redhat.com> 10233 10234 PR c++/94314 10235 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop 10236 DECL_IS_REPLACEABLE_OPERATOR during cloning. 10237 * tree-ssa-dce.c (valid_new_delete_pair_p): New function. 10238 (propagate_necessity): Check operator names. 10239 102402020-04-16 Richard Sandiford <richard.sandiford@arm.com> 10241 10242 PR rtl-optimization/94605 10243 * early-remat.c (early_remat::process_block): Handle insns that 10244 set multiple candidate registers. 102452020-04-16 Jan Hubicka <hubicka@ucw.cz> 10246 10247 PR gcov-profile/93401 10248 * common.opt (profile-prefix-path): New option. 10249 * coverae.c: Include diagnostics.h. 10250 (coverage_init): Strip profile prefix path. 10251 * doc/invoke.texi (-fprofile-prefix-path): Document. 10252 102532020-04-16 Richard Biener <rguenther@suse.de> 10254 10255 PR middle-end/94614 10256 * expr.c (emit_move_multi_word): Do not generate code when 10257 the destination part is undefined_operand_subword_p. 10258 * lower-subreg.c (resolve_clobber): Look through a paradoxica 10259 subreg. 10260 102612020-04-16 Martin Jambor <mjambor@suse.cz> 10262 10263 PR tree-optimization/94598 10264 * tree-sra.c (verify_sra_access_forest): Fix verification of total 10265 scalarization accesses under access to one-element arrays. 10266 102672020-04-16 Jakub Jelinek <jakub@redhat.com> 10268 10269 PR bootstrap/89494 10270 * function.c (assign_parm_find_data_types): Add workaround for 10271 BROKEN_VALUE_INITIALIZATION compilers. 10272 102732020-04-16 Richard Biener <rguenther@suse.de> 10274 10275 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME 10276 nodes. 10277 102782020-04-15 Uroš Bizjak <ubizjak@gmail.com> 10279 10280 PR target/94603 10281 * config/i386/i386-builtin.def (__builtin_ia32_movq128): 10282 Require OPTION_MASK_ISA_SSE2. 10283 102842020-04-15 Gustavo Romero <gromero@linux.ibm.com> 10285 10286 PR bootstrap/89494 10287 * dumpfile.c (selftest::temp_dump_context::temp_dump_context): 10288 Don't construct a dump_context temporary to call static method. 10289 102902020-04-15 Andrea Corallo <andrea.corallo@arm.com> 10291 10292 * config/aarch64/falkor-tag-collision-avoidance.c 10293 (valid_src_p): Check for aarch64_address_info type before 10294 accessing base field. 10295 102962020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> 10297 10298 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern. 10299 (V_sz_elem2): Remove unused mode attribute. 10300 103012020-04-15 Matthew Malcomson <matthew.malcomson@arm.com> 10302 10303 * config/arm/arm.md (arm_movdi): Disallow for MVE. 10304 103052020-04-15 Richard Biener <rguenther@suse.de> 10306 10307 PR middle-end/94539 10308 * tree-ssa-alias.c (same_type_for_tbaa): Defer to 10309 alias_sets_conflict_p for pointers. 10310 103112020-04-14 Max Filippov <jcmvbkbc@gmail.com> 10312 10313 PR target/94584 10314 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) 10315 (extendhisi2_internal): Add %v1 before the load instructions. 10316 103172020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com> 10318 10319 PR target/94542 10320 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to 10321 use PC-relative addressing for TLS references. 10322 103232020-04-14 Martin Jambor <mjambor@suse.cz> 10324 10325 PR ipa/94434 10326 * ipa-sra.c: Include internal-fn.h. 10327 (enum isra_scan_context): Update comment. 10328 (scan_function): Treat calls to internal_functions like loads or stores. 10329 103302020-04-14 Yang Yang <yangyang305@huawei.com> 10331 10332 PR tree-optimization/94574 10333 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing 10334 whether a vector-insert is rewritable using a BIT_INSERT_EXPR. 10335 103362020-04-14 H.J. Lu <hongjiu.lu@intel.com> 10337 10338 PR target/94561 10339 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check. 10340 103412020-04-13 Martin Sebor <msebor@redhat.com> 10342 10343 * doc/extend.texi (-Wall): Mention -Wformat-overflow and 10344 -Wformat-truncation. Move -Wzero-length-bounds last. 10345 (-Wrestrict): Document positive form of option enabled by -Wall. 10346 103472020-04-13 Zachary Spytz <zspytz@gmail.com> 10348 10349 * doc/extend.texi: Add realloc to list of built-in functions 10350 are recognized by the compiler. 10351 103522020-04-13 H.J. Lu <hongjiu.lu@intel.com> 10353 10354 PR target/94556 10355 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame 10356 pointer in word_mode for eh_return epilogues. 10357 103582020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com> 10359 10360 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to 10361 memory references in %B, %C and %D operand selectors when the inner 10362 operand is a post increment address. 10363 103642020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com> 10365 10366 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory 10367 reference by 4 bytes, and %D memory reference by 6 bytes. 10368 103692020-04-11 Uroš Bizjak <ubizjak@gmail.com> 10370 10371 PR target/94494 10372 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2 10373 condition for V4SI, V8HI and V16QI modes. 10374 103752020-04-11 Jakub Jelinek <jakub@redhat.com> 10376 10377 PR debug/94495 10378 PR target/94551 10379 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on 10380 val->val_rtx. 10381 103822020-04-10 Thomas Schwinge <thomas@codesourcery.com> 10383 10384 PR middle-end/89433 10385 PR middle-end/93465 10386 * omp-general.c (oacc_verify_routine_clauses): Diagnose if 10387 "#pragma omp declare target" has also been applied. 10388 103892020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com> 10390 10391 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn 10392 when to emit the epilogue_helper insn. 10393 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the 10394 RTL pattern. 10395 103962020-04-09 Jakub Jelinek <jakub@redhat.com> 10397 10398 PR debug/94495 10399 * cselib.h (cselib_record_sp_cfa_base_equiv, 10400 cselib_sp_derived_value_p): Declare. 10401 * cselib.c (cselib_record_sp_cfa_base_equiv, 10402 cselib_sp_derived_value_p): New functions. 10403 * var-tracking.c (add_stores): Don't record MO_VAL_SET for 10404 cselib_sp_derived_value_p values. 10405 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the 10406 start of extended basic blocks other than the first one 10407 for !frame_pointer_needed functions. 10408 104092020-04-09 Richard Sandiford <richard.sandiford@arm.com> 10410 10411 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw) 10412 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw) 10413 (aarch64_sve2048_hw): Document. 10414 * config/aarch64/aarch64-protos.h 10415 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare. 10416 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define 10417 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled. 10418 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New 10419 function. 10420 (find_type_suffix_for_scalar_type): Use it instead of comparing 10421 TYPE_MAIN_VARIANTs. 10422 (function_resolver::infer_vector_or_tuple_type): Likewise. 10423 (function_resolver::require_vector_type): Likewise. 10424 (handle_arm_sve_vector_bits_attribute): New function. 10425 * config/aarch64/aarch64.c (pure_scalable_type_info): New class. 10426 (aarch64_attribute_table): Add arm_sve_vector_bits. 10427 (aarch64_return_in_memory_1): 10428 (pure_scalable_type_info::piece::get_rtx): New function. 10429 (pure_scalable_type_info::num_zr): Likewise. 10430 (pure_scalable_type_info::num_pr): Likewise. 10431 (pure_scalable_type_info::get_rtx): Likewise. 10432 (pure_scalable_type_info::analyze): Likewise. 10433 (pure_scalable_type_info::analyze_registers): Likewise. 10434 (pure_scalable_type_info::analyze_array): Likewise. 10435 (pure_scalable_type_info::analyze_record): Likewise. 10436 (pure_scalable_type_info::add_piece): Likewise. 10437 (aarch64_some_values_include_pst_objects_p): Likewise. 10438 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info 10439 to analyze whether the type is returned in SVE registers. 10440 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type 10441 is passed in SVE registers. 10442 (aarch64_pass_by_reference_1): New function, extracted from... 10443 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info 10444 to analyze whether the type is a pure scalable type and, if so, 10445 whether it should be passed by reference. 10446 (aarch64_return_in_msb): Return false for pure scalable types. 10447 (aarch64_function_value_1): Fold back into... 10448 (aarch64_function_value): ...this function. Use 10449 pure_scalable_type_info to analyze whether the type is a pure 10450 scalable type and, if so, which registers it should use. Handle 10451 types that include pure scalable types but are not themselves 10452 pure scalable types. 10453 (aarch64_return_in_memory_1): New function, split out from... 10454 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info 10455 to analyze whether the type is a pure scalable type and, if so, 10456 whether it should be returned by reference. 10457 (aarch64_layout_arg): Remove orig_mode argument. Use 10458 pure_scalable_type_info to analyze whether the type is a pure 10459 scalable type and, if so, which registers it should use. Handle 10460 types that include pure scalable types but are not themselves 10461 pure scalable types. 10462 (aarch64_function_arg): Update call accordingly. 10463 (aarch64_function_arg_advance): Likewise. 10464 (aarch64_pad_reg_upward): On big-endian targets, return false for 10465 pure scalable types that are smaller than 16 bytes. 10466 (aarch64_member_type_forces_blk): New function. 10467 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types. 10468 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that 10469 correspond to built-in SVE types. Do not rely on a vector mode 10470 if the type includes an pure scalable type. When returning true, 10471 assert that the mode is not an SVE mode. 10472 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE 10473 built-in types here. When returning true, assert that the type 10474 does not have an SVE mode. 10475 (aarch64_can_change_mode_class): Don't allow anything to change 10476 between a predicate mode and a non-predicate mode. Also don't 10477 allow changes between SVE vector modes and other modes that 10478 might be bigger than 128 bits. 10479 (aarch64_invalid_binary_op): Reject binary operations that mix 10480 SVE and GNU vector types. 10481 (TARGET_MEMBER_TYPE_FORCES_BLK): Define. 10482 104832020-04-09 Richard Sandiford <richard.sandiford@arm.com> 10484 10485 * config/aarch64/aarch64.c (aarch64_attribute_table): Add 10486 "SVE sizeless type". 10487 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless) 10488 (sizeless_type_p): New functions. 10489 (register_builtin_types): Apply make_type_sizeless to the type. 10490 (register_tuple_type): Likewise. 10491 (verify_type_context): Use sizeless_type_p instead of builin_type_p. 10492 104932020-04-09 Matthew Malcomson <matthew.malcomson@arm.com> 10494 10495 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for 10496 C++. 10497 104982020-04-09 Martin Jambor <mjambor@suse.cz> 10499 Richard Biener <rguenther@suse.de> 10500 10501 PR tree-optimization/94482 10502 * tree-sra.c (create_access_replacement): Dump new replacement with 10503 TDF_UID. 10504 (sra_modify_expr): Fix handling of cases when the original EXPR writes 10505 to only part of the replacement. 10506 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify 10507 the first operand of combinations into REAL/IMAGPART_EXPR and 10508 BIT_FIELD_REF. 10509 105102020-04-09 Richard Sandiford <richard.sandiford@arm.com> 10511 10512 * doc/sourcebuild.texi (check-function-bodies): Treat the third 10513 parameter as a list of option regexps and require each regexp 10514 to match. 10515 105162020-04-09 Andrea Corallo <andrea.corallo@arm.com> 10517 10518 PR target/94530 10519 * config/aarch64/falkor-tag-collision-avoidance.c 10520 (valid_src_p): Fix missing rtx type check. 10521 105222020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com> 10523 Richard Biener <rguenther@suse.de> 10524 10525 PR tree-optimization/93674 10526 * tree-ssa-loop-ivopts.c (langhooks.h): New include. 10527 (add_iv_candidate_for_use): For iv_use of non integer or pointer type, 10528 or non-mode precision type, add candidate in unsigned type with the 10529 same precision. 10530 105312020-04-08 Clement Chigot <clement.chigot@atos.net> 10532 10533 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128. 10534 * config/rs6000/aix71.h (LIB_SPEC): Likewise. 10535 * config/rs6000/aix72.h (LIB_SPEC): Likewise. 10536 105372020-04-08 Jakub Jelinek <jakub@redhat.com> 10538 10539 PR middle-end/94526 10540 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P 10541 with zero offset. 10542 * reload1.c (eliminate_regs_1): Avoid creating 10543 (plus (reg) (const_int 0)) in DEBUG_INSNs. 10544 10545 PR tree-optimization/94524 10546 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is 10547 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of 10548 op1 rather than op1 itself at the end. Punt for signed modulo by 10549 most negative constant. 10550 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed 10551 modulo by most negative constant. 10552 105532020-04-08 Richard Biener <rguenther@suse.de> 10554 10555 PR rtl-optimization/93946 10556 * cse.c (cse_insn): Record the tabled expression in 10557 src_related. Verify a redundant store removal is valid. 10558 105592020-04-08 H.J. Lu <hongjiu.lu@intel.com> 10560 10561 PR target/94417 10562 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert 10563 ENDBR at function entry if function will be called indirectly. 10564 105652020-04-08 Jakub Jelinek <jakub@redhat.com> 10566 10567 PR target/94438 10568 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size 10569 1, 2, 4 and 8. 10570 105712020-04-08 Martin Liska <mliska@suse.cz> 10572 10573 PR c++/94314 10574 * gimple.c (gimple_call_operator_delete_p): Rename to... 10575 (gimple_call_replaceable_operator_delete_p): ... this. 10576 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. 10577 * gimple.h (gimple_call_operator_delete_p): Rename to ... 10578 (gimple_call_replaceable_operator_delete_p): ... this. 10579 * tree-core.h (tree_function_decl): Add replaceable_operator 10580 flag. 10581 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1): 10582 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. 10583 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p. 10584 (eliminate_unnecessary_stmts): Likewise. 10585 * tree-streamer-in.c (unpack_ts_function_decl_value_fields): 10586 Pack DECL_IS_REPLACEABLE_OPERATOR. 10587 * tree-streamer-out.c (pack_ts_function_decl_value_fields): 10588 Unpack the field here. 10589 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New. 10590 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New. 10591 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New. 10592 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable. 10593 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare 10594 replaceable operator flags. 10595 105962020-04-08 Dennis Zhang <dennis.zhang@arm.com> 10597 Matthew Malcomson <matthew.malcomson@arm.com> 10598 10599 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro. 10600 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise. 10601 (CX_TERNARY_QUALIFIERS): Likewise. 10602 (ARM_BUILTIN_CDE_PATTERN_START): Likewise. 10603 (ARM_BUILTIN_CDE_PATTERN_END): Likewise. 10604 (arm_init_acle_builtins): Initialize CDE builtins. 10605 (arm_expand_acle_builtin): Check CDE constant operands. 10606 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range 10607 of CDE constant operand. 10608 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for 10609 TARGET_VFP_BASE. 10610 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise. 10611 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface. 10612 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise. 10613 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise. 10614 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise. 10615 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise. 10616 * config/arm/arm_cde_builtins.def: New file. 10617 * config/arm/iterators.md (V_reg): New attribute of SI. 10618 * config/arm/predicates.md (const_int_coproc_operand): New. 10619 (const_int_vcde1_operand, const_int_vcde2_operand): New. 10620 (const_int_vcde3_operand): New. 10621 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New. 10622 * config/arm/vfp.md (arm_vcx1<mode>): New entry. 10623 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise. 10624 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise. 10625 106262020-04-08 Dennis Zhang <dennis.zhang@arm.com> 10627 10628 * config.gcc: Add arm_cde.h. 10629 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine 10630 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC. 10631 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options. 10632 * config/arm/arm.c (arm_option_reconfigure_globals): Configure 10633 arm_arch_cde and arm_arch_cde_coproc to store the feature bits. 10634 * config/arm/arm.h (TARGET_CDE): New macro. 10635 * config/arm/arm_cde.h: New file. 10636 * doc/invoke.texi: Document CDE options +cdecp[0-7]. 10637 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target 10638 supports option. 10639 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise. 10640 106412020-04-08 Jakub Jelinek <jakub@redhat.com> 10642 10643 PR rtl-optimization/94516 10644 * postreload.c: Include rtl-iter.h. 10645 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR 10646 looking for all MEMs with RTX_AUTOINC operand. 10647 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling. 10648 106492020-04-08 Tobias Burnus <tobias@codesourcery.com> 10650 10651 * omp-grid.c (grid_eliminate_combined_simd_part): Use 10652 OMP_CLAUSE_CODE to access the omp clause code. 10653 106542020-04-07 Jeff Law <law@redhat.com> 10655 10656 PR rtl-optimization/92264 10657 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when 10658 the destination is the stack pointer. 10659 106602020-04-07 Jakub Jelinek <jakub@redhat.com> 10661 10662 PR rtl-optimization/94291 10663 PR rtl-optimization/84169 10664 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST 10665 must be a REG or SUBREG of REG; if it is not one of these, don't 10666 update LOG_LINKs. 10667 106682020-04-07 Richard Biener <rguenther@suse.de> 10669 10670 PR middle-end/94479 10671 * gimplify.c (gimplify_addr_expr): Also consider generated 10672 MEM_REFs. 10673 106742020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10675 10676 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs. 10677 106782020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10679 10680 * config/arm/arm_mve.h: Cast some pointers to expected types. 10681 106822020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10683 10684 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the 10685 same with '__arm_' prefix. 10686 106872020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10688 10689 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set. 10690 106912020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10692 10693 * config/arm/arm.c (arm_mve_immediate_check): Removed. 10694 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types. 10695 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*, 10696 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*, 10697 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*, 10698 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*, 10699 mve_vqshruntq_m_n_s*): Fixed immediate constraints. 10700 107012020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10702 10703 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts. 10704 107052020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10706 10707 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics. 10708 * config/arm/mve/md: Fix v[id]wdup patterns. 10709 107102020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10711 10712 * config/arm/arm.c (output_move_neon): Deal with label + offset cases. 10713 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors. 10714 107152020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10716 10717 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters 10718 and remove const_ptr enums. 10719 107202020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 10721 10722 * config/arm/arm_mve.h (vsubq_n): Merge with... 10723 (vsubq): ... this. 10724 (vmulq_n): Merge with... 10725 (vmulq): ... this. 10726 (__ARM_mve_typeid): Simplify scalar and constant detection. 10727 107282020-04-07 Jakub Jelinek <jakub@redhat.com> 10729 10730 PR target/94509 10731 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check 10732 for inter-lane permutation for 64-byte modes. 10733 10734 PR target/94488 10735 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3, 10736 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT. 10737 Assume it is a REG after that instead of testing it and doing FAIL 10738 otherwise. Formatting fix. 10739 107402020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de> 10741 10742 * config/rs6000/t-rtems: Delete mcpu=8540 multilib. 10743 107442020-04-07 Jakub Jelinek <jakub@redhat.com> 10745 10746 PR target/94500 10747 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode 10748 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes. 10749 107502020-04-06 Jakub Jelinek <jakub@redhat.com> 10751 10752 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P 10753 + const0_rtx return the SP_DERIVED_VALUE_P. 10754 107552020-04-06 Richard Sandiford <richard.sandiford@arm.com> 10756 10757 PR rtl-optimization/92989 10758 * lra-lives.c (process_bb_lives): Do not treat eh_return data 10759 registers as being live at the beginning of the EH receiver. 10760 107612020-04-05 Zachary Spytz <zspytz@gmail.com> 10762 10763 * extend.texi: Add free to list of ISO C90 functions that 10764 are recognized by the compiler. 10765 107662020-04-05 Nagaraju Mekala <nmekala@xilix.com> 10767 10768 * config/microblaze/microblaze.c (microblaze_must_save_register): Check 10769 for fast_interrupt. 10770 10771 * config/microblaze/microblaze.md (trap): Update output pattern. 10772 107732020-04-04 Hannes Domani <ssbssa@yahoo.de> 10774 Jakub Jelinek <jakub@redhat.com> 10775 10776 PR debug/94459 10777 * dwarf2out.c (gen_subprogram_die): Look through references, pointers, 10778 arrays, pointer-to-members, function types and qualifiers when 10779 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type 10780 to emit type again on definition. 10781 107822020-04-04 Jan Hubicka <hubicka@ucw.cz> 10783 10784 PR ipa/93940 10785 * ipa-fnsummary.c (vrp_will_run_p): New function. 10786 (fre_will_run_p): New function. 10787 (evaluate_properties_for_edge): Use it. 10788 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline 10789 !optimize_debug to optimize_debug. 10790 107912020-04-04 Jakub Jelinek <jakub@redhat.com> 10792 10793 PR rtl-optimization/94468 10794 * cselib.c (references_value_p): Formatting fix. 10795 (cselib_useless_value_p): New function. 10796 (discard_useless_locs, discard_useless_values, 10797 cselib_invalidate_regno_val, cselib_invalidate_mem, 10798 cselib_record_set): Use it instead of 10799 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx). 10800 10801 PR debug/94441 10802 * tree-iterator.h (expr_single): Declare. 10803 * tree-iterator.c (expr_single): New function. 10804 * tree.h (protected_set_expr_location_if_unset): Declare. 10805 * tree.c (protected_set_expr_location): Use expr_single. 10806 (protected_set_expr_location_if_unset): New function. 10807 108082020-04-03 Jeff Law <law@redhat.com> 10809 10810 PR rtl-optimization/92264 10811 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle 10812 reloading of auto-increment addressing modes. 10813 108142020-04-03 H.J. Lu <hongjiu.lu@intel.com> 10815 10816 PR target/94467 10817 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand 10818 as earlyclobber. 10819 108202020-04-03 Jeff Law <law@redhat.com> 10821 10822 PR rtl-optimization/92264 10823 * config/m32r/m32r.c (m32r_output_block_move): Properly account for 10824 post-increment addressing of source operands as well as residuals 10825 when computing any adjustments to the input pointer. 10826 108272020-04-03 Jakub Jelinek <jakub@redhat.com> 10828 10829 PR target/94460 10830 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3, 10831 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do 10832 second half of first lane from first lane of second operand and 10833 first half of second lane from second lane of first operand. 10834 108352020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com> 10836 10837 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE. 10838 108392020-04-03 Tamar Christina <tamar.christina@arm.com> 10840 10841 PR target/94396 10842 * common/config/aarch64/aarch64-common.c 10843 (aarch64_get_extension_string_for_isa_flags): Handle default flags. 10844 108452020-04-03 Richard Biener <rguenther@suse.de> 10846 10847 PR middle-end/94465 10848 * tree.c (array_ref_low_bound): Deal with released SSA names 10849 in index position. 10850 108512020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com> 10852 10853 * config/gcn/gcn.c (print_operand): Handle unordered comparison 10854 operators. 10855 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered 10856 comparison operators. 10857 108582020-04-03 Kewen Lin <linkw@gcc.gnu.org> 10859 10860 PR tree-optimization/94443 10861 * tree-vect-loop.c (vectorizable_live_operation): Use 10862 gsi_insert_seq_before to replace gsi_insert_before. 10863 108642020-04-03 Martin Liska <mliska@suse.cz> 10865 10866 PR ipa/94445 10867 * ipa-icf-gimple.c (func_checker::compare_gimple_call): 10868 Compare type attributes for gimple_call_fntypes. 10869 108702020-04-02 Sandra Loosemore <sandra@codesourcery.com> 10871 10872 * alias.c (get_alias_set): Fix comment typos. 10873 108742020-04-02 Fritz Reese <foreese@gcc.gnu.org> 10875 10876 PR fortran/85982 10877 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into 10878 attribute checking used by TYPE. 10879 108802020-04-02 Martin Jambor <mjambor@suse.cz> 10881 10882 PR ipa/92676 10883 * ipa-sra.c (struct caller_issues): New fields candidate and 10884 call_from_outside_comdat. 10885 (check_for_caller_issues): Check for calls from outsied of 10886 candidate's same_comdat_group. 10887 (check_all_callers_for_issues): Set up issues.candidate, check result 10888 of the new check. 10889 (mark_callers_calls_comdat_local): New function. 10890 (process_isra_node_results): Set calls_comdat_local of callers if 10891 appropriate. 10892 108932020-04-02 Richard Biener <rguenther@suse.de> 10894 10895 PR c/94392 10896 * common.opt (ffinite-loops): Initialize to zero. 10897 * opts.c (default_options_table): Remove OPT_ffinite_loops 10898 entry. 10899 * cfgloop.h (loop::finite_p): New member. 10900 * cfgloopmanip.c (copy_loop_info): Copy finite_p. 10901 * ipa-icf-gimple.c (func_checker::compare_loops): Compare 10902 finite_p. 10903 * lto-streamer-in.c (input_cfg): Stream finite_p. 10904 * lto-streamer-out.c (output_cfg): Likewise. 10905 * tree-cfg.c (replace_loop_annotate): Initialize finite_p 10906 from flag_finite_loops at CFG build time. 10907 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops 10908 finite_p flag instead of flag_finite_loops. 10909 * doc/invoke.texi (ffinite-loops): Adjust documentation of 10910 default setting. 10911 109122020-04-02 Richard Biener <rguenther@suse.de> 10913 10914 PR debug/94450 10915 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting 10916 DW_TAG_imported_unit. 10917 109182020-04-02 Maciej W. Rozycki <macro@wdc.com> 10919 10920 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux> 10921 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to 10922 2.30. 10923 109242020-04-02 Kewen Lin <linkw@gcc.gnu.org> 10925 10926 PR tree-optimization/94401 10927 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE 10928 access type when loading halves of vector to avoid peeling for gaps. 10929 109302020-04-02 Jakub Jelinek <jakub@redhat.com> 10931 10932 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in 10933 between a string literal and MIPS_SYSVERSION_SPEC macro. 10934 109352020-04-02 Martin Jambor <mjambor@suse.cz> 10936 10937 * doc/invoke.texi (Optimize Options): Document sra-max-propagations. 10938 109392020-04-02 Jakub Jelinek <jakub@redhat.com> 10940 10941 PR rtl-optimization/92264 10942 * params.opt (-param=max-find-base-term-values=): Decrease default 10943 from 2000 to 200. 10944 10945 PR rtl-optimization/92264 10946 * rtl.h (struct rtx_def): Mention that call bit is used as 10947 SP_DERIVED_VALUE_P in cselib.c. 10948 * cselib.c (SP_DERIVED_VALUE_P): Define. 10949 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier. 10950 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P 10951 val_rtx and sp based expression where offsets cancel each other. 10952 (preserve_constants_and_equivs): Formatting fix. 10953 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P 10954 locs list for cfa_base_preserved_val if needed. Formatting fix. 10955 (autoinc_split): If the to be returned value is a REG, MEM or 10956 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its 10957 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off. 10958 (rtx_equal_for_cselib_1): Call autoinc_split even if both 10959 expressions are PLUS in Pmode with CONST_INT second operands. 10960 Handle SP_DERIVED_VALUE_P cases. 10961 (cselib_hash_plus_const_int): New function. 10962 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT 10963 second operand, as well as for PRE_DEC etc. that ought to be 10964 hashed the same way. 10965 (cselib_subst_to_values): Substitute PLUS with Pmode and 10966 CONST_INT operand if the first operand is a VALUE which has 10967 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the 10968 SP_DERIVED_VALUE_P + adjusted offset. 10969 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx, 10970 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding 10971 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location. 10972 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv 10973 on the sp value before calling cselib_add_permanent_equiv on the 10974 cfa_base value. 10975 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC 10976 in the insn without REG_INC note. 10977 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced. 10978 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes. 10979 10980 PR target/94435 10981 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For 10982 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. 10983 109842020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 10985 10986 PR target/94317 10987 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define. 10988 (LDRGBWBXU_Z_QUALIFIERS): Likewise. 10989 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify 10990 intrinsic defintion by adding a new builtin call to writeback into base 10991 address. 10992 (__arm_vldrdq_gather_base_wb_u64): Likewise. 10993 (__arm_vldrdq_gather_base_wb_z_s64): Likewise. 10994 (__arm_vldrdq_gather_base_wb_z_u64): Likewise. 10995 (__arm_vldrwq_gather_base_wb_s32): Likewise. 10996 (__arm_vldrwq_gather_base_wb_u32): Likewise. 10997 (__arm_vldrwq_gather_base_wb_z_s32): Likewise. 10998 (__arm_vldrwq_gather_base_wb_z_u32): Likewise. 10999 (__arm_vldrwq_gather_base_wb_f32): Likewise. 11000 (__arm_vldrwq_gather_base_wb_z_f32): Likewise. 11001 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify 11002 builtin's qualifier. 11003 (vldrdq_gather_base_wb_z_u): Likewise. 11004 (vldrwq_gather_base_wb_u): Likewise. 11005 (vldrdq_gather_base_wb_u): Likewise. 11006 (vldrwq_gather_base_wb_z_s): Likewise. 11007 (vldrwq_gather_base_wb_z_f): Likewise. 11008 (vldrdq_gather_base_wb_z_s): Likewise. 11009 (vldrwq_gather_base_wb_s): Likewise. 11010 (vldrwq_gather_base_wb_f): Likewise. 11011 (vldrdq_gather_base_wb_s): Likewise. 11012 (vldrwq_gather_base_nowb_z_u): Define builtin. 11013 (vldrdq_gather_base_nowb_z_u): Likewise. 11014 (vldrwq_gather_base_nowb_u): Likewise. 11015 (vldrdq_gather_base_nowb_u): Likewise. 11016 (vldrwq_gather_base_nowb_z_s): Likewise. 11017 (vldrwq_gather_base_nowb_z_f): Likewise. 11018 (vldrdq_gather_base_nowb_z_s): Likewise. 11019 (vldrwq_gather_base_nowb_s): Likewise. 11020 (vldrwq_gather_base_nowb_f): Likewise. 11021 (vldrdq_gather_base_nowb_s): Likewise. 11022 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL 11023 pattern. 11024 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern. 11025 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern. 11026 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern. 11027 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern. 11028 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern. 11029 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern. 11030 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern. 11031 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern. 11032 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern. 11033 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern. 11034 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern. 11035 110362020-04-02 Andreas Krebbel <krebbel@linux.ibm.com> 11037 11038 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3") 11039 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3") 11040 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3") 11041 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>") 11042 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>") 11043 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3") 11044 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4") 11045 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx") 11046 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint 11047 modifier. 11048 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>") 11049 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"): 11050 Remove constraints from expander. 11051 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq") 11052 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>") 11053 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>") 11054 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>") 11055 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3") 11056 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier. 11057 110582020-04-01 Peter Bergner <bergner@linux.ibm.com> 11059 11060 PR rtl-optimization/94123 11061 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for 11062 flag_split_wide_types_early. 11063 110642020-04-01 Joerg Sonnenberger <joerg@bec.de> 11065 11066 * doc/extend.texi (Common Function Attributes): Fix typo. 11067 110682020-04-01 Segher Boessenkool <segher@kernel.crashing.org> 11069 11070 PR target/94420 11071 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition 11072 on operands[1]. 11073 110742020-04-01 Zackery Spytz <zspytz@gmail.com> 11075 11076 * doc/extend.texi: Fix a typo in the documentation of the 11077 copy function attribute. 11078 110792020-04-01 Jakub Jelinek <jakub@redhat.com> 11080 11081 PR middle-end/94423 11082 * tree-object-size.c (pass_object_sizes::execute): Don't call 11083 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead 11084 call replace_call_with_value. 11085 110862020-04-01 Kewen Lin <linkw@gcc.gnu.org> 11087 11088 PR tree-optimization/94043 11089 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed 11090 phi for vec_lhs and use it for lane extraction. 11091 110922020-03-31 Felix Yang <felix.yang@huawei.com> 11093 11094 PR tree-optimization/94398 11095 * tree-vect-stmts.c (vectorizable_store): Instead of calling 11096 vect_supportable_dr_alignment, set alignment_support_scheme to 11097 dr_unaligned_supported for gather-scatter accesses. 11098 (vectorizable_load): Likewise. 11099 111002020-03-31 Andrew Stubbs <ams@codesourcery.com> 11101 11102 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF): 11103 New mode iterators. 11104 (vnsi, VnSI, vndi, VnDI): New mode attributes. 11105 (mov<mode>): Use <VnDI> in place of V64DI. 11106 (mov<mode>_exec): Likewise. 11107 (mov<mode>_sgprbase): Likewise. 11108 (reload_out<mode>): Likewise. 11109 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64. 11110 (gather_load<mode>v64si): Rename to ... 11111 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI, 11112 and <VnDI> in place of V64DI. 11113 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI. 11114 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI. 11115 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>. 11116 (scatter_store<mode>v64si): Rename to ... 11117 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 11118 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>. 11119 (scatter<mode>_insn_1offset<exec_scatter>): Likewise. 11120 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise. 11121 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. 11122 (ds_bpermute<mode>): Use <VnSI>. 11123 (addv64si3_vcc<exec_vcc>): Rename to ... 11124 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI. 11125 (addv64si3_vcc_dup<exec_vcc>): Rename to ... 11126 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI. 11127 (addcv64si3<exec_vcc>): Rename to ... 11128 (addc<mode>3<exec_vcc>): ... this, and use V_SI. 11129 (subv64si3_vcc<exec_vcc>): Rename to ... 11130 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI. 11131 (subcv64si3<exec_vcc>): Rename to ... 11132 (subc<mode>3<exec_vcc>): ... this, and use V_SI. 11133 (addv64di3): Rename to ... 11134 (add<mode>3): ... this, and use V_DI. 11135 (addv64di3_exec): Rename to ... 11136 (add<mode>3_exec): ... this, and use V_DI. 11137 (subv64di3): Rename to ... 11138 (sub<mode>3): ... this, and use V_DI. 11139 (subv64di3_exec): Rename to ... 11140 (sub<mode>3_exec): ... this, and use V_DI. 11141 (addv64di3_zext): Rename to ... 11142 (add<mode>3_zext): ... this, and use V_DI and <VnSI>. 11143 (addv64di3_zext_exec): Rename to ... 11144 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. 11145 (addv64di3_zext_dup): Rename to ... 11146 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>. 11147 (addv64di3_zext_dup_exec): Rename to ... 11148 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>. 11149 (addv64di3_zext_dup2): Rename to ... 11150 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. 11151 (addv64di3_zext_dup2_exec): Rename to ... 11152 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. 11153 (addv64di3_sext_dup2): Rename to ... 11154 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>. 11155 (addv64di3_sext_dup2_exec): Rename to ... 11156 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>. 11157 (<su>mulv64si3_highpart<exec>): Rename to ... 11158 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>. 11159 (mulv64di3): Rename to ... 11160 (mul<mode>3): ... this, and use V_DI and <VnSI>. 11161 (mulv64di3_exec): Rename to ... 11162 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>. 11163 (mulv64di3_zext): Rename to ... 11164 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>. 11165 (mulv64di3_zext_exec): Rename to ... 11166 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. 11167 (mulv64di3_zext_dup2): Rename to ... 11168 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. 11169 (mulv64di3_zext_dup2_exec): Rename to ... 11170 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. 11171 (<expander>v64di3): Rename to ... 11172 (<expander><mode>3): ... this, and use V_DI and <VnSI>. 11173 (<expander>v64di3_exec): Rename to ... 11174 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>. 11175 (<expander>v64si3<exec>): Rename to ... 11176 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. 11177 (v<expander>v64si3<exec>): Rename to ... 11178 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. 11179 (<expander>v64si3<exec>): Rename to ... 11180 (<expander><vnsi>3<exec>): ... this, and use V_SI. 11181 (subv64df3<exec>): Rename to ... 11182 (sub<mode>3<exec>): ... this, and use V_DF. 11183 (truncv64di<mode>2): Rename to ... 11184 (trunc<vndi><mode>2): ... this, and use <VnDI>. 11185 (truncv64di<mode>2_exec): Rename to ... 11186 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>. 11187 (<convop><mode>v64di2): Rename to ... 11188 (<convop><mode><vndi>2): ... this, and use <VnDI>. 11189 (<convop><mode>v64di2_exec): Rename to ... 11190 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>. 11191 (vec_cmp<u>v64qidi): Rename to ... 11192 (vec_cmp<u><mode>di): ... this, and use <VnSI>. 11193 (vec_cmp<u>v64qidi_exec): Rename to ... 11194 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>. 11195 (vcond_mask_<mode>di): Use <VnDI>. 11196 (maskload<mode>di): Likewise. 11197 (maskstore<mode>di): Likewise. 11198 (mask_gather_load<mode>v64si): Rename to ... 11199 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 11200 (mask_scatter_store<mode>v64si): Rename to ... 11201 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. 11202 (*<reduc_op>_dpp_shr_v64di): Rename to ... 11203 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. 11204 (*plus_carry_in_dpp_shr_v64si): Rename to ... 11205 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI. 11206 (*plus_carry_dpp_shr_v64di): Rename to ... 11207 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. 11208 (vec_seriesv64si): Rename to ... 11209 (vec_series<mode>): ... this, and use V_SI. 11210 (vec_seriesv64di): Rename to ... 11211 (vec_series<mode>): ... this, and use V_DI. 11212 112132020-03-31 Claudiu Zissulescu <claziss@synopsys.com> 11214 11215 * config/arc/arc.c (arc_print_operand): Use 11216 HOST_WIDE_INT_PRINT_DEC macro. 11217 112182020-03-31 Claudiu Zissulescu <claziss@synopsys.com> 11219 11220 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it. 11221 112222020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11223 11224 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic 11225 variant. 11226 (__arm_vbicq): Likewise. 11227 112282020-03-31 Vineet Gupta <vgupta@synopsys.com> 11229 11230 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700. 11231 112322020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11233 11234 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the 11235 common section of both MVE Integer and MVE Floating Point. 11236 (vaddvq): Likewise. 11237 (vaddlvq_p): Likewise. 11238 (vaddvaq): Likewise. 11239 (vaddvq_p): Likewise. 11240 (vcmpcsq): Likewise. 11241 (vmlsdavxq): Likewise. 11242 (vmlsdavq): Likewise. 11243 (vmladavxq): Likewise. 11244 (vmladavq): Likewise. 11245 (vminvq): Likewise. 11246 (vminavq): Likewise. 11247 (vmaxvq): Likewise. 11248 (vmaxavq): Likewise. 11249 (vmlaldavq): Likewise. 11250 (vcmphiq): Likewise. 11251 (vaddlvaq): Likewise. 11252 (vrmlaldavhq): Likewise. 11253 (vrmlaldavhxq): Likewise. 11254 (vrmlsldavhq): Likewise. 11255 (vrmlsldavhxq): Likewise. 11256 (vmlsldavxq): Likewise. 11257 (vmlsldavq): Likewise. 11258 (vabavq): Likewise. 11259 (vrmlaldavhaq): Likewise. 11260 (vcmpgeq_m_n): Likewise. 11261 (vmlsdavxq_p): Likewise. 11262 (vmlsdavq_p): Likewise. 11263 (vmlsdavaxq): Likewise. 11264 (vmlsdavaq): Likewise. 11265 (vaddvaq_p): Likewise. 11266 (vcmpcsq_m_n): Likewise. 11267 (vcmpcsq_m): Likewise. 11268 (vmladavxq_p): Likewise. 11269 (vmladavq_p): Likewise. 11270 (vmladavaxq): Likewise. 11271 (vmladavaq): Likewise. 11272 (vminvq_p): Likewise. 11273 (vminavq_p): Likewise. 11274 (vmaxvq_p): Likewise. 11275 (vmaxavq_p): Likewise. 11276 (vcmphiq_m): Likewise. 11277 (vaddlvaq_p): Likewise. 11278 (vmlaldavaq): Likewise. 11279 (vmlaldavaxq): Likewise. 11280 (vmlaldavq_p): Likewise. 11281 (vmlaldavxq_p): Likewise. 11282 (vmlsldavaq): Likewise. 11283 (vmlsldavaxq): Likewise. 11284 (vmlsldavq_p): Likewise. 11285 (vmlsldavxq_p): Likewise. 11286 (vrmlaldavhaxq): Likewise. 11287 (vrmlaldavhq_p): Likewise. 11288 (vrmlaldavhxq_p): Likewise. 11289 (vrmlsldavhaq): Likewise. 11290 (vrmlsldavhaxq): Likewise. 11291 (vrmlsldavhq_p): Likewise. 11292 (vrmlsldavhxq_p): Likewise. 11293 (vabavq_p): Likewise. 11294 (vmladavaq_p): Likewise. 11295 (vstrbq_scatter_offset): Likewise. 11296 (vstrbq_p): Likewise. 11297 (vstrbq_scatter_offset_p): Likewise. 11298 (vstrdq_scatter_base_p): Likewise. 11299 (vstrdq_scatter_base): Likewise. 11300 (vstrdq_scatter_offset_p): Likewise. 11301 (vstrdq_scatter_offset): Likewise. 11302 (vstrdq_scatter_shifted_offset_p): Likewise. 11303 (vstrdq_scatter_shifted_offset): Likewise. 11304 (vmaxq_x): Likewise. 11305 (vminq_x): Likewise. 11306 (vmovlbq_x): Likewise. 11307 (vmovltq_x): Likewise. 11308 (vmulhq_x): Likewise. 11309 (vmullbq_int_x): Likewise. 11310 (vmullbq_poly_x): Likewise. 11311 (vmulltq_int_x): Likewise. 11312 (vmulltq_poly_x): Likewise. 11313 (vstrbq): Likewise. 11314 113152020-03-31 Jakub Jelinek <jakub@redhat.com> 11316 11317 PR target/94368 11318 * config/aarch64/constraints.md (Uph): New constraint. 11319 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr. 11320 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's 11321 constraint. 11322 113232020-03-31 Marc Glisse <marc.glisse@inria.fr> 11324 Jakub Jelinek <jakub@redhat.com> 11325 11326 PR middle-end/94412 11327 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use 11328 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P. 11329 113302020-03-31 Jakub Jelinek <jakub@redhat.com> 11331 11332 PR tree-optimization/94403 11333 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also 11334 ENUMERAL_TYPE lhs_type. 11335 11336 PR rtl-optimization/94344 11337 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision 11338 conversions, either on both operands of |^+ or just one. Handle 11339 also extra same precision conversion on RSHIFT_EXPR first operand 11340 provided RSHIFT_EXPR is performed in unsigned type. 11341 113422020-03-30 David Malcolm <dmalcolm@redhat.com> 11343 11344 * lra.c (finish_insn_code_data_once): Set the array elements 11345 to NULL after freeing them. 11346 113472020-03-30 Andreas Schwab <schwab@suse.de> 11348 11349 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]: 11350 Define. 11351 113522020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com> 11353 11354 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code 11355 to skip defining builtins based on builtin_mask. 11356 113572020-03-30 Jakub Jelinek <jakub@redhat.com> 11358 11359 PR target/94343 11360 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If 11361 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input 11362 operand is a register. Don't enable masked variants for V*[QH]Imode. 11363 11364 PR target/93069 11365 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use 11366 <store_mask_constraint> instead of m in output operand constraint. 11367 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of 11368 %{%3%}. 11369 113702020-03-30 Alan Modra <amodra@gmail.com> 11371 11372 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern. 11373 (rs6000_indirect_call_template_1): Adjust to suit. 11374 * config/rs6000/rs6000.md (call_local): Merge call_local32, 11375 call_local64, and call_local_aix. 11376 (call_value_local): Simlarly. 11377 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit, 11378 and disable pattern when CALL_LONG. 11379 (call_indirect_aix, call_value_indirect_aix): Adjust rtl. 11380 (call_indirect_elfv2, call_indirect_pcrel): Likewise. 11381 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise. 11382 113832020-03-29 H.J. Lu <hongjiu.lu@intel.com> 11384 11385 PR driver/94381 11386 * doc/invoke.texi: Update -falign-functions, -falign-loops and 11387 -falign-jumps documentation. 11388 113892020-03-29 Martin Liska <mliska@suse.cz> 11390 11391 PR ipa/94363 11392 * cgraphunit.c (process_function_and_variable_attributes): Remove 11393 double 'attribute' words. 11394 113952020-03-29 John David Anglin <dave.anglin@bell.net> 11396 11397 * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate 11398 .align output. 11399 114002020-03-28 Jakub Jelinek <jakub@redhat.com> 11401 11402 PR c/93573 11403 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const 11404 to true after setting size to integer_one_node. 11405 11406 PR tree-optimization/94329 11407 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt 11408 on the last stmt in a bb, make sure gsi_prev isn't done immediately 11409 after gsi_last_bb. 11410 114112020-03-27 Alan Modra <amodra@gmail.com> 11412 11413 PR target/94145 11414 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile 11415 for PLT16_LO and PLT_PCREL. 11416 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove. 11417 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define. 11418 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile. 11419 114202020-03-27 Martin Sebor <msebor@redhat.com> 11421 11422 PR c++/94098 11423 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes. 11424 114252020-03-27 Andrew Stubbs <ams@codesourcery.com> 11426 11427 * config/gcn/gcn-valu.md: 11428 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout. 11429 (VEC_1REG_MODE): Delete. 11430 (VEC_1REG_ALT): Delete. 11431 (VEC_ALL1REG_MODE): Rename to V_1REG throughout. 11432 (VEC_1REG_INT_MODE): Delete. 11433 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout. 11434 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout. 11435 (VEC_2REG_MODE): Rename to V_2REG throughout. 11436 (VEC_REG_MODE): Rename to V_noHI throughout. 11437 (VEC_ALLREG_MODE): Rename to V_ALL throughout. 11438 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout. 11439 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout. 11440 (VEC_INT_MODE): Delete. 11441 (VEC_FP_MODE): Rename to V_FP throughout and move to top. 11442 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top. 11443 (FP_MODE): Delete and replace with FP throughout. 11444 (FP_1REG_MODE): Delete and replace with FP_1REG throughout. 11445 (VCMP_MODE): Rename to V_noQI throughout and move to top. 11446 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top. 11447 * config/gcn/gcn.md (FP): New mode iterator. 11448 (FP_1REG): New mode iterator. 11449 114502020-03-27 David Malcolm <dmalcolm@redhat.com> 11451 11452 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this 11453 now emits two .dot files. 11454 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD. 11455 (graphviz_out::end_tr): Only close a TR, not a TD. 11456 (graphviz_out::begin_td): New. 11457 (graphviz_out::end_td): New. 11458 (graphviz_out::begin_trtd): New, replacing the old implementation 11459 of graphviz_out::begin_tr. 11460 (graphviz_out::end_tdtr): New, replacing the old implementation 11461 of graphviz_out::end_tr. 11462 * graphviz.h (graphviz_out::begin_td): New decl. 11463 (graphviz_out::end_td): New decl. 11464 (graphviz_out::begin_trtd): New decl. 11465 (graphviz_out::end_tdtr): New decl. 11466 114672020-03-27 Richard Biener <rguenther@suse.de> 11468 11469 PR debug/94273 11470 * dwarf2out.c (should_emit_struct_debug): Return false for 11471 DINFO_LEVEL_TERSE. 11472 114732020-03-27 Richard Biener <rguenther@suse.de> 11474 11475 PR tree-optimization/94352 11476 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the 11477 worklist ... 11478 (ssa_propagation_engine::ssa_propagate): ... here after 11479 initializing curr_order. 11480 114812020-03-27 Kewen Lin <linkw@gcc.gnu.org> 11482 11483 PR tree-optimization/90332 11484 * tree-vect-stmts.c (vector_vector_composition_type): New function. 11485 (get_group_load_store_type): Adjust to call 11486 vector_vector_composition_type, extend it to construct with scalar 11487 types. 11488 (vectorizable_load): Likewise. 11489 114902020-03-27 Roman Zhuykov <zhroma@ispras.ru> 11491 11492 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions. 11493 (create_ddg_dep_no_link): Likewise. 11494 (add_cross_iteration_register_deps): Move debug instruction check. 11495 Other minor refactoring. 11496 (add_intra_loop_mem_dep): Do not check for debug instructions. 11497 (add_inter_loop_mem_dep): Likewise. 11498 (build_intra_loop_deps): Likewise. 11499 (create_ddg): Do not include debug insns into the graph. 11500 * ddg.h (struct ddg): Remove num_debug field. 11501 * modulo-sched.c (doloop_register_get): Adjust condition. 11502 (res_MII): Remove DDG num_debug field usage. 11503 (sms_schedule_by_order): Use assertion against debug insns. 11504 (ps_has_conflicts): Drop debug insn check. 11505 115062020-03-26 Jakub Jelinek <jakub@redhat.com> 11507 11508 PR debug/94323 11509 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST 11510 that contains exactly one non-DEBUG_BEGIN_STMT statement. 11511 11512 PR debug/94281 11513 * gimple.h (gimple_seq_first_nondebug_stmt): New function. 11514 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains 11515 a single non-debug stmt followed by one or more debug stmts. 11516 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt 11517 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt 11518 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and 11519 gimple_seq_last to check if outer_stmt gbind could be reused and 11520 if yes and it is surrounded by any debug stmts, move them into the 11521 gbind body. 11522 11523 PR rtl-optimization/92264 11524 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even 11525 for sp based values in !frame_pointer_needed 11526 && !ACCUMULATE_OUTGOING_ARGS functions. 11527 115282020-03-26 Felix Yang <felix.yang@huawei.com> 11529 11530 PR tree-optimization/94269 11531 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict 11532 this 11533 operation to single basic block. 11534 115352020-03-25 Jeff Law <law@redhat.com> 11536 11537 PR rtl-optimization/90275 11538 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the 11539 pattern. 11540 115412020-03-25 Jakub Jelinek <jakub@redhat.com> 11542 11543 PR target/94292 11544 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to 11545 mode rather than VOIDmode. 11546 115472020-03-25 Martin Sebor <msebor@redhat.com> 11548 11549 PR middle-end/94004 11550 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings 11551 even for alloca calls resulting from system macro expansion. 11552 Include inlining context in all warnings. 11553 115542020-03-25 Richard Sandiford <richard.sandiford@arm.com> 11555 11556 PR target/94254 11557 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow 11558 FPRs to change between SDmode and DDmode. 11559 115602020-03-25 Martin Sebor <msebor@redhat.com> 11561 11562 PR tree-optimization/94131 11563 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length 11564 types and decls. 11565 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming 11566 types have constant sizes. 11567 115682020-03-25 Martin Liska <mliska@suse.cz> 11569 11570 PR lto/94259 11571 * configure.ac: Report error only when --with-zstd 11572 is used. 11573 * configure: Regenerate. 11574 115752020-03-25 Jakub Jelinek <jakub@redhat.com> 11576 11577 PR target/94308 11578 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set 11579 INSN_CODE (insn) to -1 when changing the pattern. 11580 115812020-03-25 Martin Liska <mliska@suse.cz> 11582 11583 PR target/93274 11584 PR ipa/94271 11585 * config/i386/i386-features.c (make_resolver_func): Drop 11586 public flag for resolver. 11587 * config/rs6000/rs6000.c (make_resolver_func): Add comdat 11588 group for resolver and drop public flag if possible. 11589 * multiple_target.c (create_dispatcher_calls): Drop unique_name 11590 and resolution as we want to enable LTO privatization of the default 11591 symbol. 11592 115932020-03-25 Martin Liska <mliska@suse.cz> 11594 11595 PR lto/94259 11596 * configure.ac: Respect --without-zstd and report 11597 error when we can't find header file with --with-zstd. 11598 * configure: Regenerate. 11599 116002020-03-25 Jakub Jelinek <jakub@redhat.com> 11601 11602 PR middle-end/94303 11603 * varasm.c (output_constructor_array_range): If local->index 11604 RANGE_EXPR doesn't start at the current location in the constructor, 11605 skip needed number of bytes using assemble_zeros or assert we don't 11606 go backwards. 11607 11608 PR c++/94223 11609 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong 11610 counter instead of DECL_UID. 11611 11612 PR tree-optimization/94300 11613 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset 11614 is positive, make sure that off + size isn't larger than needed_len. 11615 116162020-03-25 Richard Biener <rguenther@suse.de> 11617 Jakub Jelinek <jakub@redhat.com> 11618 11619 PR debug/94283 11620 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards. 11621 116222020-03-24 Christophe Lyon <christophe.lyon@linaro.org> 11623 11624 * doc/sourcebuild.texi (ARM-specific attributes): Add 11625 arm_fp_dp_ok. 11626 (Features for dg-add-options): Add arm_fp_dp. 11627 116282020-03-24 John David Anglin <danglin@gcc.gnu.org> 11629 11630 PR lto/94249 11631 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__. 11632 116332020-03-24 Tobias Burnus <tobias@codesourcery.com> 11634 11635 PR libgomp/81689 11636 * omp-offload.c (omp_finish_file): Fix target-link handling if 11637 targetm_common.have_named_sections is false. 11638 116392020-03-24 Jakub Jelinek <jakub@redhat.com> 11640 11641 PR target/94286 11642 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode 11643 instead of GEN_INT. 11644 11645 PR debug/94285 11646 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to 11647 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts. 11648 If not after and at *incr_pos is a debug stmt, set stmt location to 11649 location of next non-debug stmt after it if any. 11650 11651 PR debug/94283 11652 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set 11653 GF_PLF_2, but don't add them to worklist. Don't add an assigment to 11654 worklist or set GF_PLF_2 just because it is used in a debug stmt in 11655 another bb. Formatting improvements. 11656 11657 PR debug/94277 11658 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and 11659 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC 11660 regardless of whether TREE_NO_WARNING is set on it or whether 11661 warn_unused_function is true or not. 11662 116632020-03-23 Jeff Law <law@redhat.com> 11664 11665 PR rtl-optimization/90275 11666 PR target/94238 11667 PR target/94144 11668 * simplify-rtx.c (comparison_code_valid_for_mode): New function. 11669 (simplify_logical_relational_operation): Use it. 11670 116712020-03-23 Jakub Jelinek <jakub@redhat.com> 11672 11673 PR c++/91993 11674 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on 11675 ultimate rhs and if returned something different, reconstructing 11676 the COMPOUND_EXPRs. 11677 116782020-03-23 Lewis Hyatt <lhyatt@gmail.com> 11679 11680 * opts.c (print_filtered_help): Improve the help text for alias options. 11681 116822020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11683 Andre Vieira <andre.simoesdiasvieira@arm.com> 11684 Mihail Ionescu <mihail.ionescu@arm.com> 11685 11686 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro. 11687 (vshlcq_m_u8): Likewise. 11688 (vshlcq_m_s16): Likewise. 11689 (vshlcq_m_u16): Likewise. 11690 (vshlcq_m_s32): Likewise. 11691 (vshlcq_m_u32): Likewise. 11692 (__arm_vshlcq_m_s8): Define intrinsic. 11693 (__arm_vshlcq_m_u8): Likewise. 11694 (__arm_vshlcq_m_s16): Likewise. 11695 (__arm_vshlcq_m_u16): Likewise. 11696 (__arm_vshlcq_m_s32): Likewise. 11697 (__arm_vshlcq_m_u32): Likewise. 11698 (vshlcq_m): Define polymorphic variant. 11699 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE): 11700 Use builtin qualifier. 11701 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 11702 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern. 11703 (mve_vshlcq_m_carry_<supf><mode>): Likewise. 11704 (mve_vshlcq_m_<supf><mode>): Likewise. 11705 117062020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11707 11708 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier. 11709 (UQSHL_QUALIFIERS): Likewise. 11710 (ASRL_QUALIFIERS): Likewise. 11711 (SQSHL_QUALIFIERS): Likewise. 11712 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in 11713 Big-Endian Mode. 11714 (sqrshr): Define macro. 11715 (sqrshrl): Likewise. 11716 (sqrshrl_sat48): Likewise. 11717 (sqshl): Likewise. 11718 (sqshll): Likewise. 11719 (srshr): Likewise. 11720 (srshrl): Likewise. 11721 (uqrshl): Likewise. 11722 (uqrshll): Likewise. 11723 (uqrshll_sat48): Likewise. 11724 (uqshl): Likewise. 11725 (uqshll): Likewise. 11726 (urshr): Likewise. 11727 (urshrl): Likewise. 11728 (lsll): Likewise. 11729 (asrl): Likewise. 11730 (__arm_lsll): Define intrinsic. 11731 (__arm_asrl): Likewise. 11732 (__arm_uqrshll): Likewise. 11733 (__arm_uqrshll_sat48): Likewise. 11734 (__arm_sqrshrl): Likewise. 11735 (__arm_sqrshrl_sat48): Likewise. 11736 (__arm_uqshll): Likewise. 11737 (__arm_urshrl): Likewise. 11738 (__arm_srshrl): Likewise. 11739 (__arm_sqshll): Likewise. 11740 (__arm_uqrshl): Likewise. 11741 (__arm_sqrshr): Likewise. 11742 (__arm_uqshl): Likewise. 11743 (__arm_urshr): Likewise. 11744 (__arm_sqshl): Likewise. 11745 (__arm_srshr): Likewise. 11746 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin 11747 qualifier. 11748 (UQSHL_QUALIFIERS): Likewise. 11749 (ASRL_QUALIFIERS): Likewise. 11750 (SQSHL_QUALIFIERS): Likewise. 11751 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern. 11752 (mve_sqrshrl_sat<supf>_di): Likewise. 11753 (mve_uqrshl_si): Likewise. 11754 (mve_sqrshr_si): Likewise. 11755 (mve_uqshll_di): Likewise. 11756 (mve_urshrl_di): Likewise. 11757 (mve_uqshl_si): Likewise. 11758 (mve_urshr_si): Likewise. 11759 (mve_sqshl_si): Likewise. 11760 (mve_srshr_si): Likewise. 11761 (mve_srshrl_di): Likewise. 11762 (mve_sqshll_di): Likewise. 11763 117642020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11765 Andre Vieira <andre.simoesdiasvieira@arm.com> 11766 Mihail Ionescu <mihail.ionescu@arm.com> 11767 11768 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro. 11769 (vsetq_lane_f32): Likewise. 11770 (vsetq_lane_s16): Likewise. 11771 (vsetq_lane_s32): Likewise. 11772 (vsetq_lane_s8): Likewise. 11773 (vsetq_lane_s64): Likewise. 11774 (vsetq_lane_u8): Likewise. 11775 (vsetq_lane_u16): Likewise. 11776 (vsetq_lane_u32): Likewise. 11777 (vsetq_lane_u64): Likewise. 11778 (vgetq_lane_f16): Likewise. 11779 (vgetq_lane_f32): Likewise. 11780 (vgetq_lane_s16): Likewise. 11781 (vgetq_lane_s32): Likewise. 11782 (vgetq_lane_s8): Likewise. 11783 (vgetq_lane_s64): Likewise. 11784 (vgetq_lane_u8): Likewise. 11785 (vgetq_lane_u16): Likewise. 11786 (vgetq_lane_u32): Likewise. 11787 (vgetq_lane_u64): Likewise. 11788 (__ARM_NUM_LANES): Likewise. 11789 (__ARM_LANEQ): Likewise. 11790 (__ARM_CHECK_LANEQ): Likewise. 11791 (__arm_vsetq_lane_s16): Define intrinsic. 11792 (__arm_vsetq_lane_s32): Likewise. 11793 (__arm_vsetq_lane_s8): Likewise. 11794 (__arm_vsetq_lane_s64): Likewise. 11795 (__arm_vsetq_lane_u8): Likewise. 11796 (__arm_vsetq_lane_u16): Likewise. 11797 (__arm_vsetq_lane_u32): Likewise. 11798 (__arm_vsetq_lane_u64): Likewise. 11799 (__arm_vgetq_lane_s16): Likewise. 11800 (__arm_vgetq_lane_s32): Likewise. 11801 (__arm_vgetq_lane_s8): Likewise. 11802 (__arm_vgetq_lane_s64): Likewise. 11803 (__arm_vgetq_lane_u8): Likewise. 11804 (__arm_vgetq_lane_u16): Likewise. 11805 (__arm_vgetq_lane_u32): Likewise. 11806 (__arm_vgetq_lane_u64): Likewise. 11807 (__arm_vsetq_lane_f16): Likewise. 11808 (__arm_vsetq_lane_f32): Likewise. 11809 (__arm_vgetq_lane_f16): Likewise. 11810 (__arm_vgetq_lane_f32): Likewise. 11811 (vgetq_lane): Define polymorphic variant. 11812 (vsetq_lane): Likewise. 11813 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL 11814 pattern. 11815 (mve_vec_extractv2didi): Likewise. 11816 (mve_vec_extract_sext_internal<mode>): Likewise. 11817 (mve_vec_extract_zext_internal<mode>): Likewise. 11818 (mve_vec_set<mode>_internal): Likewise. 11819 (mve_vec_setv2di_internal): Likewise. 11820 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md 11821 file. 11822 (vec_extract<mode><V_elem_l>): Rename to 11823 "neon_vec_extract<mode><V_elem_l>". 11824 (vec_extractv2didi): Rename to "neon_vec_extractv2didi". 11825 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL 11826 pattern common for MVE and NEON. 11827 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both 11828 MVE and NEON. 11829 118302020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com> 11831 11832 * config/arm/mve.md (earlyclobber_32): New mode attribute. 11833 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*, 11834 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers. 11835 118362020-03-23 Richard Biener <rguenther@suse.de> 11837 11838 PR tree-optimization/94261 11839 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove 11840 IL operand swapping code. 11841 (vect_slp_rearrange_stmts): Do not arrange isomorphic 11842 nodes that would need operation code adjustments. 11843 118442020-03-23 Tobias Burnus <tobias@codesourcery.com> 11845 11846 * doc/install.texi (amdgcn-*-amdhsa): Renamed 11847 from amdgcn-unknown-amdhsa; change 11848 amdgcn-unknown-amdhsa to amdgcn-amdhsa. 11849 118502020-03-23 Richard Biener <rguenther@suse.de> 11851 11852 PR ipa/94245 11853 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP 11854 directly rather than also folding it via build_fold_addr_expr. 11855 118562020-03-23 Richard Biener <rguenther@suse.de> 11857 11858 PR tree-optimization/94266 11859 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate 11860 addresses of TARGET_MEM_REFs. 11861 118622020-03-23 Martin Liska <mliska@suse.cz> 11863 11864 PR ipa/94250 11865 * symtab.c (symtab_node::clone_references): Save speculative_id 11866 as ref may be overwritten by create_reference. 11867 (symtab_node::clone_referring): Likewise. 11868 (symtab_node::clone_reference): Likewise. 11869 118702020-03-22 Iain Sandoe <iain@sandoe.co.uk> 11871 11872 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove 11873 references to Darwin. 11874 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this 11875 unconditionally and comment on why. 11876 118772020-03-21 Iain Sandoe <iain@sandoe.co.uk> 11878 11879 * config/darwin.c (darwin_mergeable_constant_section): Collect 11880 section anchor checks into the caller. 11881 (machopic_select_section): Collect section anchor checks into 11882 the determination of 'effective zero-size' objects. When the 11883 size is unknown, assume it is non-zero, and thus return the 11884 'generic' section for the DECL. 11885 118862020-03-21 Iain Sandoe <iain@sandoe.co.uk> 11887 11888 PR target/93694 11889 * gcc/config/darwin.opt: Amend options descriptions. 11890 118912020-03-21 Richard Sandiford <richard.sandiford@arm.com> 11892 11893 PR rtl-optimization/94052 11894 * lra-constraints.c (simplify_operand_subreg): Reload the inner 11895 register of a paradoxical subreg if simplify_subreg_regno fails 11896 to give a valid hard register for the outer mode. 11897 118982020-03-20 Martin Jambor <mjambor@suse.cz> 11899 11900 PR tree-optimization/93435 11901 * params.opt (sra-max-propagations): New parameter. 11902 * tree-sra.c (propagation_budget): New variable. 11903 (budget_for_propagation_access): New function. 11904 (propagate_subaccesses_from_rhs): Use it. 11905 (propagate_subaccesses_from_lhs): Likewise. 11906 (propagate_all_subaccesses): Set up and destroy propagation_budget. 11907 119082020-03-20 Carl Love <cel@us.ibm.com> 11909 11910 PR/target 87583 11911 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): 11912 Add check for TARGET_FPRND for Power 7 or newer. 11913 119142020-03-20 Jan Hubicka <hubicka@ucw.cz> 11915 11916 PR ipa/93347 11917 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag. 11918 (cgraph_edge::redirect_callee): Move here; likewise. 11919 (cgraph_node::remove_callees): Update calls_comdat_local flag. 11920 (cgraph_node::verify_node): Verify that calls_comdat_local flag match 11921 reality. 11922 (cgraph_node::check_calls_comdat_local_p): New member function. 11923 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare. 11924 (cgraph_edge::redirect_callee): Move offline. 11925 * ipa-fnsummary.c (compute_fn_summary): Do not compute 11926 calls_comdat_local flag here. 11927 * ipa-inline-transform.c (inline_call): Fix updating of 11928 calls_comdat_local flag. 11929 * ipa-split.c (split_function): Use true instead of 1 to set the flag. 11930 * symtab.c (symtab_node::add_to_same_comdat_group): Update 11931 calls_comdat_local flag. 11932 119332020-03-20 Richard Biener <rguenther@suse.de> 11934 11935 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree 11936 from the possibly modified root. 11937 119382020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 11939 Andre Vieira <andre.simoesdiasvieira@arm.com> 11940 Mihail Ionescu <mihail.ionescu@arm.com> 11941 11942 * config/arm/arm_mve.h (vst1q_p_u8): Define macro. 11943 (vst1q_p_s8): Likewise. 11944 (vst2q_s8): Likewise. 11945 (vst2q_u8): Likewise. 11946 (vld1q_z_u8): Likewise. 11947 (vld1q_z_s8): Likewise. 11948 (vld2q_s8): Likewise. 11949 (vld2q_u8): Likewise. 11950 (vld4q_s8): Likewise. 11951 (vld4q_u8): Likewise. 11952 (vst1q_p_u16): Likewise. 11953 (vst1q_p_s16): Likewise. 11954 (vst2q_s16): Likewise. 11955 (vst2q_u16): Likewise. 11956 (vld1q_z_u16): Likewise. 11957 (vld1q_z_s16): Likewise. 11958 (vld2q_s16): Likewise. 11959 (vld2q_u16): Likewise. 11960 (vld4q_s16): Likewise. 11961 (vld4q_u16): Likewise. 11962 (vst1q_p_u32): Likewise. 11963 (vst1q_p_s32): Likewise. 11964 (vst2q_s32): Likewise. 11965 (vst2q_u32): Likewise. 11966 (vld1q_z_u32): Likewise. 11967 (vld1q_z_s32): Likewise. 11968 (vld2q_s32): Likewise. 11969 (vld2q_u32): Likewise. 11970 (vld4q_s32): Likewise. 11971 (vld4q_u32): Likewise. 11972 (vld4q_f16): Likewise. 11973 (vld2q_f16): Likewise. 11974 (vld1q_z_f16): Likewise. 11975 (vst2q_f16): Likewise. 11976 (vst1q_p_f16): Likewise. 11977 (vld4q_f32): Likewise. 11978 (vld2q_f32): Likewise. 11979 (vld1q_z_f32): Likewise. 11980 (vst2q_f32): Likewise. 11981 (vst1q_p_f32): Likewise. 11982 (__arm_vst1q_p_u8): Define intrinsic. 11983 (__arm_vst1q_p_s8): Likewise. 11984 (__arm_vst2q_s8): Likewise. 11985 (__arm_vst2q_u8): Likewise. 11986 (__arm_vld1q_z_u8): Likewise. 11987 (__arm_vld1q_z_s8): Likewise. 11988 (__arm_vld2q_s8): Likewise. 11989 (__arm_vld2q_u8): Likewise. 11990 (__arm_vld4q_s8): Likewise. 11991 (__arm_vld4q_u8): Likewise. 11992 (__arm_vst1q_p_u16): Likewise. 11993 (__arm_vst1q_p_s16): Likewise. 11994 (__arm_vst2q_s16): Likewise. 11995 (__arm_vst2q_u16): Likewise. 11996 (__arm_vld1q_z_u16): Likewise. 11997 (__arm_vld1q_z_s16): Likewise. 11998 (__arm_vld2q_s16): Likewise. 11999 (__arm_vld2q_u16): Likewise. 12000 (__arm_vld4q_s16): Likewise. 12001 (__arm_vld4q_u16): Likewise. 12002 (__arm_vst1q_p_u32): Likewise. 12003 (__arm_vst1q_p_s32): Likewise. 12004 (__arm_vst2q_s32): Likewise. 12005 (__arm_vst2q_u32): Likewise. 12006 (__arm_vld1q_z_u32): Likewise. 12007 (__arm_vld1q_z_s32): Likewise. 12008 (__arm_vld2q_s32): Likewise. 12009 (__arm_vld2q_u32): Likewise. 12010 (__arm_vld4q_s32): Likewise. 12011 (__arm_vld4q_u32): Likewise. 12012 (__arm_vld4q_f16): Likewise. 12013 (__arm_vld2q_f16): Likewise. 12014 (__arm_vld1q_z_f16): Likewise. 12015 (__arm_vst2q_f16): Likewise. 12016 (__arm_vst1q_p_f16): Likewise. 12017 (__arm_vld4q_f32): Likewise. 12018 (__arm_vld2q_f32): Likewise. 12019 (__arm_vld1q_z_f32): Likewise. 12020 (__arm_vst2q_f32): Likewise. 12021 (__arm_vst1q_p_f32): Likewise. 12022 (vld1q_z): Define polymorphic variant. 12023 (vld2q): Likewise. 12024 (vld4q): Likewise. 12025 (vst1q_p): Likewise. 12026 (vst2q): Likewise. 12027 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. 12028 (LOAD1): Likewise. 12029 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern. 12030 (mve_vld2q<mode>): Likewise. 12031 (mve_vld4q<mode>): Likewise. 12032 120332020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 12034 Andre Vieira <andre.simoesdiasvieira@arm.com> 12035 Mihail Ionescu <mihail.ionescu@arm.com> 12036 12037 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. 12038 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. 12039 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and 12040 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array. 12041 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC 12042 and ARM_BUILTIN_SET_FPSCR_NZCVQC. 12043 * config/arm/arm_mve.h (vadciq_s32): Define macro. 12044 (vadciq_u32): Likewise. 12045 (vadciq_m_s32): Likewise. 12046 (vadciq_m_u32): Likewise. 12047 (vadcq_s32): Likewise. 12048 (vadcq_u32): Likewise. 12049 (vadcq_m_s32): Likewise. 12050 (vadcq_m_u32): Likewise. 12051 (vsbciq_s32): Likewise. 12052 (vsbciq_u32): Likewise. 12053 (vsbciq_m_s32): Likewise. 12054 (vsbciq_m_u32): Likewise. 12055 (vsbcq_s32): Likewise. 12056 (vsbcq_u32): Likewise. 12057 (vsbcq_m_s32): Likewise. 12058 (vsbcq_m_u32): Likewise. 12059 (__arm_vadciq_s32): Define intrinsic. 12060 (__arm_vadciq_u32): Likewise. 12061 (__arm_vadciq_m_s32): Likewise. 12062 (__arm_vadciq_m_u32): Likewise. 12063 (__arm_vadcq_s32): Likewise. 12064 (__arm_vadcq_u32): Likewise. 12065 (__arm_vadcq_m_s32): Likewise. 12066 (__arm_vadcq_m_u32): Likewise. 12067 (__arm_vsbciq_s32): Likewise. 12068 (__arm_vsbciq_u32): Likewise. 12069 (__arm_vsbciq_m_s32): Likewise. 12070 (__arm_vsbciq_m_u32): Likewise. 12071 (__arm_vsbcq_s32): Likewise. 12072 (__arm_vsbcq_u32): Likewise. 12073 (__arm_vsbcq_m_s32): Likewise. 12074 (__arm_vsbcq_m_u32): Likewise. 12075 (vadciq_m): Define polymorphic variant. 12076 (vadciq): Likewise. 12077 (vadcq_m): Likewise. 12078 (vadcq): Likewise. 12079 (vsbciq_m): Likewise. 12080 (vsbciq): Likewise. 12081 (vsbcq_m): Likewise. 12082 (vsbcq): Likewise. 12083 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin 12084 qualifier. 12085 (BINOP_UNONE_UNONE_UNONE): Likewise. 12086 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 12087 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 12088 * config/arm/mve.md (VADCIQ): Define iterator. 12089 (VADCIQ_M): Likewise. 12090 (VSBCQ): Likewise. 12091 (VSBCQ_M): Likewise. 12092 (VSBCIQ): Likewise. 12093 (VSBCIQ_M): Likewise. 12094 (VADCQ): Likewise. 12095 (VADCQ_M): Likewise. 12096 (mve_vadciq_m_<supf>v4si): Define RTL pattern. 12097 (mve_vadciq_<supf>v4si): Likewise. 12098 (mve_vadcq_m_<supf>v4si): Likewise. 12099 (mve_vadcq_<supf>v4si): Likewise. 12100 (mve_vsbciq_m_<supf>v4si): Likewise. 12101 (mve_vsbciq_<supf>v4si): Likewise. 12102 (mve_vsbcq_m_<supf>v4si): Likewise. 12103 (mve_vsbcq_<supf>v4si): Likewise. 12104 (get_fpscr_nzcvqc): Define isns. 12105 (set_fpscr_nzcvqc): Define isns. 12106 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define. 12107 (UNSPEC_SET_FPSCR_NZCVQC): Define. 12108 121092020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 12110 12111 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. 12112 (vddupq_x_n_u16): Likewise. 12113 (vddupq_x_n_u32): Likewise. 12114 (vddupq_x_wb_u8): Likewise. 12115 (vddupq_x_wb_u16): Likewise. 12116 (vddupq_x_wb_u32): Likewise. 12117 (vdwdupq_x_n_u8): Likewise. 12118 (vdwdupq_x_n_u16): Likewise. 12119 (vdwdupq_x_n_u32): Likewise. 12120 (vdwdupq_x_wb_u8): Likewise. 12121 (vdwdupq_x_wb_u16): Likewise. 12122 (vdwdupq_x_wb_u32): Likewise. 12123 (vidupq_x_n_u8): Likewise. 12124 (vidupq_x_n_u16): Likewise. 12125 (vidupq_x_n_u32): Likewise. 12126 (vidupq_x_wb_u8): Likewise. 12127 (vidupq_x_wb_u16): Likewise. 12128 (vidupq_x_wb_u32): Likewise. 12129 (viwdupq_x_n_u8): Likewise. 12130 (viwdupq_x_n_u16): Likewise. 12131 (viwdupq_x_n_u32): Likewise. 12132 (viwdupq_x_wb_u8): Likewise. 12133 (viwdupq_x_wb_u16): Likewise. 12134 (viwdupq_x_wb_u32): Likewise. 12135 (vdupq_x_n_s8): Likewise. 12136 (vdupq_x_n_s16): Likewise. 12137 (vdupq_x_n_s32): Likewise. 12138 (vdupq_x_n_u8): Likewise. 12139 (vdupq_x_n_u16): Likewise. 12140 (vdupq_x_n_u32): Likewise. 12141 (vminq_x_s8): Likewise. 12142 (vminq_x_s16): Likewise. 12143 (vminq_x_s32): Likewise. 12144 (vminq_x_u8): Likewise. 12145 (vminq_x_u16): Likewise. 12146 (vminq_x_u32): Likewise. 12147 (vmaxq_x_s8): Likewise. 12148 (vmaxq_x_s16): Likewise. 12149 (vmaxq_x_s32): Likewise. 12150 (vmaxq_x_u8): Likewise. 12151 (vmaxq_x_u16): Likewise. 12152 (vmaxq_x_u32): Likewise. 12153 (vabdq_x_s8): Likewise. 12154 (vabdq_x_s16): Likewise. 12155 (vabdq_x_s32): Likewise. 12156 (vabdq_x_u8): Likewise. 12157 (vabdq_x_u16): Likewise. 12158 (vabdq_x_u32): Likewise. 12159 (vabsq_x_s8): Likewise. 12160 (vabsq_x_s16): Likewise. 12161 (vabsq_x_s32): Likewise. 12162 (vaddq_x_s8): Likewise. 12163 (vaddq_x_s16): Likewise. 12164 (vaddq_x_s32): Likewise. 12165 (vaddq_x_n_s8): Likewise. 12166 (vaddq_x_n_s16): Likewise. 12167 (vaddq_x_n_s32): Likewise. 12168 (vaddq_x_u8): Likewise. 12169 (vaddq_x_u16): Likewise. 12170 (vaddq_x_u32): Likewise. 12171 (vaddq_x_n_u8): Likewise. 12172 (vaddq_x_n_u16): Likewise. 12173 (vaddq_x_n_u32): Likewise. 12174 (vclsq_x_s8): Likewise. 12175 (vclsq_x_s16): Likewise. 12176 (vclsq_x_s32): Likewise. 12177 (vclzq_x_s8): Likewise. 12178 (vclzq_x_s16): Likewise. 12179 (vclzq_x_s32): Likewise. 12180 (vclzq_x_u8): Likewise. 12181 (vclzq_x_u16): Likewise. 12182 (vclzq_x_u32): Likewise. 12183 (vnegq_x_s8): Likewise. 12184 (vnegq_x_s16): Likewise. 12185 (vnegq_x_s32): Likewise. 12186 (vmulhq_x_s8): Likewise. 12187 (vmulhq_x_s16): Likewise. 12188 (vmulhq_x_s32): Likewise. 12189 (vmulhq_x_u8): Likewise. 12190 (vmulhq_x_u16): Likewise. 12191 (vmulhq_x_u32): Likewise. 12192 (vmullbq_poly_x_p8): Likewise. 12193 (vmullbq_poly_x_p16): Likewise. 12194 (vmullbq_int_x_s8): Likewise. 12195 (vmullbq_int_x_s16): Likewise. 12196 (vmullbq_int_x_s32): Likewise. 12197 (vmullbq_int_x_u8): Likewise. 12198 (vmullbq_int_x_u16): Likewise. 12199 (vmullbq_int_x_u32): Likewise. 12200 (vmulltq_poly_x_p8): Likewise. 12201 (vmulltq_poly_x_p16): Likewise. 12202 (vmulltq_int_x_s8): Likewise. 12203 (vmulltq_int_x_s16): Likewise. 12204 (vmulltq_int_x_s32): Likewise. 12205 (vmulltq_int_x_u8): Likewise. 12206 (vmulltq_int_x_u16): Likewise. 12207 (vmulltq_int_x_u32): Likewise. 12208 (vmulq_x_s8): Likewise. 12209 (vmulq_x_s16): Likewise. 12210 (vmulq_x_s32): Likewise. 12211 (vmulq_x_n_s8): Likewise. 12212 (vmulq_x_n_s16): Likewise. 12213 (vmulq_x_n_s32): Likewise. 12214 (vmulq_x_u8): Likewise. 12215 (vmulq_x_u16): Likewise. 12216 (vmulq_x_u32): Likewise. 12217 (vmulq_x_n_u8): Likewise. 12218 (vmulq_x_n_u16): Likewise. 12219 (vmulq_x_n_u32): Likewise. 12220 (vsubq_x_s8): Likewise. 12221 (vsubq_x_s16): Likewise. 12222 (vsubq_x_s32): Likewise. 12223 (vsubq_x_n_s8): Likewise. 12224 (vsubq_x_n_s16): Likewise. 12225 (vsubq_x_n_s32): Likewise. 12226 (vsubq_x_u8): Likewise. 12227 (vsubq_x_u16): Likewise. 12228 (vsubq_x_u32): Likewise. 12229 (vsubq_x_n_u8): Likewise. 12230 (vsubq_x_n_u16): Likewise. 12231 (vsubq_x_n_u32): Likewise. 12232 (vcaddq_rot90_x_s8): Likewise. 12233 (vcaddq_rot90_x_s16): Likewise. 12234 (vcaddq_rot90_x_s32): Likewise. 12235 (vcaddq_rot90_x_u8): Likewise. 12236 (vcaddq_rot90_x_u16): Likewise. 12237 (vcaddq_rot90_x_u32): Likewise. 12238 (vcaddq_rot270_x_s8): Likewise. 12239 (vcaddq_rot270_x_s16): Likewise. 12240 (vcaddq_rot270_x_s32): Likewise. 12241 (vcaddq_rot270_x_u8): Likewise. 12242 (vcaddq_rot270_x_u16): Likewise. 12243 (vcaddq_rot270_x_u32): Likewise. 12244 (vhaddq_x_n_s8): Likewise. 12245 (vhaddq_x_n_s16): Likewise. 12246 (vhaddq_x_n_s32): Likewise. 12247 (vhaddq_x_n_u8): Likewise. 12248 (vhaddq_x_n_u16): Likewise. 12249 (vhaddq_x_n_u32): Likewise. 12250 (vhaddq_x_s8): Likewise. 12251 (vhaddq_x_s16): Likewise. 12252 (vhaddq_x_s32): Likewise. 12253 (vhaddq_x_u8): Likewise. 12254 (vhaddq_x_u16): Likewise. 12255 (vhaddq_x_u32): Likewise. 12256 (vhcaddq_rot90_x_s8): Likewise. 12257 (vhcaddq_rot90_x_s16): Likewise. 12258 (vhcaddq_rot90_x_s32): Likewise. 12259 (vhcaddq_rot270_x_s8): Likewise. 12260 (vhcaddq_rot270_x_s16): Likewise. 12261 (vhcaddq_rot270_x_s32): Likewise. 12262 (vhsubq_x_n_s8): Likewise. 12263 (vhsubq_x_n_s16): Likewise. 12264 (vhsubq_x_n_s32): Likewise. 12265 (vhsubq_x_n_u8): Likewise. 12266 (vhsubq_x_n_u16): Likewise. 12267 (vhsubq_x_n_u32): Likewise. 12268 (vhsubq_x_s8): Likewise. 12269 (vhsubq_x_s16): Likewise. 12270 (vhsubq_x_s32): Likewise. 12271 (vhsubq_x_u8): Likewise. 12272 (vhsubq_x_u16): Likewise. 12273 (vhsubq_x_u32): Likewise. 12274 (vrhaddq_x_s8): Likewise. 12275 (vrhaddq_x_s16): Likewise. 12276 (vrhaddq_x_s32): Likewise. 12277 (vrhaddq_x_u8): Likewise. 12278 (vrhaddq_x_u16): Likewise. 12279 (vrhaddq_x_u32): Likewise. 12280 (vrmulhq_x_s8): Likewise. 12281 (vrmulhq_x_s16): Likewise. 12282 (vrmulhq_x_s32): Likewise. 12283 (vrmulhq_x_u8): Likewise. 12284 (vrmulhq_x_u16): Likewise. 12285 (vrmulhq_x_u32): Likewise. 12286 (vandq_x_s8): Likewise. 12287 (vandq_x_s16): Likewise. 12288 (vandq_x_s32): Likewise. 12289 (vandq_x_u8): Likewise. 12290 (vandq_x_u16): Likewise. 12291 (vandq_x_u32): Likewise. 12292 (vbicq_x_s8): Likewise. 12293 (vbicq_x_s16): Likewise. 12294 (vbicq_x_s32): Likewise. 12295 (vbicq_x_u8): Likewise. 12296 (vbicq_x_u16): Likewise. 12297 (vbicq_x_u32): Likewise. 12298 (vbrsrq_x_n_s8): Likewise. 12299 (vbrsrq_x_n_s16): Likewise. 12300 (vbrsrq_x_n_s32): Likewise. 12301 (vbrsrq_x_n_u8): Likewise. 12302 (vbrsrq_x_n_u16): Likewise. 12303 (vbrsrq_x_n_u32): Likewise. 12304 (veorq_x_s8): Likewise. 12305 (veorq_x_s16): Likewise. 12306 (veorq_x_s32): Likewise. 12307 (veorq_x_u8): Likewise. 12308 (veorq_x_u16): Likewise. 12309 (veorq_x_u32): Likewise. 12310 (vmovlbq_x_s8): Likewise. 12311 (vmovlbq_x_s16): Likewise. 12312 (vmovlbq_x_u8): Likewise. 12313 (vmovlbq_x_u16): Likewise. 12314 (vmovltq_x_s8): Likewise. 12315 (vmovltq_x_s16): Likewise. 12316 (vmovltq_x_u8): Likewise. 12317 (vmovltq_x_u16): Likewise. 12318 (vmvnq_x_s8): Likewise. 12319 (vmvnq_x_s16): Likewise. 12320 (vmvnq_x_s32): Likewise. 12321 (vmvnq_x_u8): Likewise. 12322 (vmvnq_x_u16): Likewise. 12323 (vmvnq_x_u32): Likewise. 12324 (vmvnq_x_n_s16): Likewise. 12325 (vmvnq_x_n_s32): Likewise. 12326 (vmvnq_x_n_u16): Likewise. 12327 (vmvnq_x_n_u32): Likewise. 12328 (vornq_x_s8): Likewise. 12329 (vornq_x_s16): Likewise. 12330 (vornq_x_s32): Likewise. 12331 (vornq_x_u8): Likewise. 12332 (vornq_x_u16): Likewise. 12333 (vornq_x_u32): Likewise. 12334 (vorrq_x_s8): Likewise. 12335 (vorrq_x_s16): Likewise. 12336 (vorrq_x_s32): Likewise. 12337 (vorrq_x_u8): Likewise. 12338 (vorrq_x_u16): Likewise. 12339 (vorrq_x_u32): Likewise. 12340 (vrev16q_x_s8): Likewise. 12341 (vrev16q_x_u8): Likewise. 12342 (vrev32q_x_s8): Likewise. 12343 (vrev32q_x_s16): Likewise. 12344 (vrev32q_x_u8): Likewise. 12345 (vrev32q_x_u16): Likewise. 12346 (vrev64q_x_s8): Likewise. 12347 (vrev64q_x_s16): Likewise. 12348 (vrev64q_x_s32): Likewise. 12349 (vrev64q_x_u8): Likewise. 12350 (vrev64q_x_u16): Likewise. 12351 (vrev64q_x_u32): Likewise. 12352 (vrshlq_x_s8): Likewise. 12353 (vrshlq_x_s16): Likewise. 12354 (vrshlq_x_s32): Likewise. 12355 (vrshlq_x_u8): Likewise. 12356 (vrshlq_x_u16): Likewise. 12357 (vrshlq_x_u32): Likewise. 12358 (vshllbq_x_n_s8): Likewise. 12359 (vshllbq_x_n_s16): Likewise. 12360 (vshllbq_x_n_u8): Likewise. 12361 (vshllbq_x_n_u16): Likewise. 12362 (vshlltq_x_n_s8): Likewise. 12363 (vshlltq_x_n_s16): Likewise. 12364 (vshlltq_x_n_u8): Likewise. 12365 (vshlltq_x_n_u16): Likewise. 12366 (vshlq_x_s8): Likewise. 12367 (vshlq_x_s16): Likewise. 12368 (vshlq_x_s32): Likewise. 12369 (vshlq_x_u8): Likewise. 12370 (vshlq_x_u16): Likewise. 12371 (vshlq_x_u32): Likewise. 12372 (vshlq_x_n_s8): Likewise. 12373 (vshlq_x_n_s16): Likewise. 12374 (vshlq_x_n_s32): Likewise. 12375 (vshlq_x_n_u8): Likewise. 12376 (vshlq_x_n_u16): Likewise. 12377 (vshlq_x_n_u32): Likewise. 12378 (vrshrq_x_n_s8): Likewise. 12379 (vrshrq_x_n_s16): Likewise. 12380 (vrshrq_x_n_s32): Likewise. 12381 (vrshrq_x_n_u8): Likewise. 12382 (vrshrq_x_n_u16): Likewise. 12383 (vrshrq_x_n_u32): Likewise. 12384 (vshrq_x_n_s8): Likewise. 12385 (vshrq_x_n_s16): Likewise. 12386 (vshrq_x_n_s32): Likewise. 12387 (vshrq_x_n_u8): Likewise. 12388 (vshrq_x_n_u16): Likewise. 12389 (vshrq_x_n_u32): Likewise. 12390 (vdupq_x_n_f16): Likewise. 12391 (vdupq_x_n_f32): Likewise. 12392 (vminnmq_x_f16): Likewise. 12393 (vminnmq_x_f32): Likewise. 12394 (vmaxnmq_x_f16): Likewise. 12395 (vmaxnmq_x_f32): Likewise. 12396 (vabdq_x_f16): Likewise. 12397 (vabdq_x_f32): Likewise. 12398 (vabsq_x_f16): Likewise. 12399 (vabsq_x_f32): Likewise. 12400 (vaddq_x_f16): Likewise. 12401 (vaddq_x_f32): Likewise. 12402 (vaddq_x_n_f16): Likewise. 12403 (vaddq_x_n_f32): Likewise. 12404 (vnegq_x_f16): Likewise. 12405 (vnegq_x_f32): Likewise. 12406 (vmulq_x_f16): Likewise. 12407 (vmulq_x_f32): Likewise. 12408 (vmulq_x_n_f16): Likewise. 12409 (vmulq_x_n_f32): Likewise. 12410 (vsubq_x_f16): Likewise. 12411 (vsubq_x_f32): Likewise. 12412 (vsubq_x_n_f16): Likewise. 12413 (vsubq_x_n_f32): Likewise. 12414 (vcaddq_rot90_x_f16): Likewise. 12415 (vcaddq_rot90_x_f32): Likewise. 12416 (vcaddq_rot270_x_f16): Likewise. 12417 (vcaddq_rot270_x_f32): Likewise. 12418 (vcmulq_x_f16): Likewise. 12419 (vcmulq_x_f32): Likewise. 12420 (vcmulq_rot90_x_f16): Likewise. 12421 (vcmulq_rot90_x_f32): Likewise. 12422 (vcmulq_rot180_x_f16): Likewise. 12423 (vcmulq_rot180_x_f32): Likewise. 12424 (vcmulq_rot270_x_f16): Likewise. 12425 (vcmulq_rot270_x_f32): Likewise. 12426 (vcvtaq_x_s16_f16): Likewise. 12427 (vcvtaq_x_s32_f32): Likewise. 12428 (vcvtaq_x_u16_f16): Likewise. 12429 (vcvtaq_x_u32_f32): Likewise. 12430 (vcvtnq_x_s16_f16): Likewise. 12431 (vcvtnq_x_s32_f32): Likewise. 12432 (vcvtnq_x_u16_f16): Likewise. 12433 (vcvtnq_x_u32_f32): Likewise. 12434 (vcvtpq_x_s16_f16): Likewise. 12435 (vcvtpq_x_s32_f32): Likewise. 12436 (vcvtpq_x_u16_f16): Likewise. 12437 (vcvtpq_x_u32_f32): Likewise. 12438 (vcvtmq_x_s16_f16): Likewise. 12439 (vcvtmq_x_s32_f32): Likewise. 12440 (vcvtmq_x_u16_f16): Likewise. 12441 (vcvtmq_x_u32_f32): Likewise. 12442 (vcvtbq_x_f32_f16): Likewise. 12443 (vcvttq_x_f32_f16): Likewise. 12444 (vcvtq_x_f16_u16): Likewise. 12445 (vcvtq_x_f16_s16): Likewise. 12446 (vcvtq_x_f32_s32): Likewise. 12447 (vcvtq_x_f32_u32): Likewise. 12448 (vcvtq_x_n_f16_s16): Likewise. 12449 (vcvtq_x_n_f16_u16): Likewise. 12450 (vcvtq_x_n_f32_s32): Likewise. 12451 (vcvtq_x_n_f32_u32): Likewise. 12452 (vcvtq_x_s16_f16): Likewise. 12453 (vcvtq_x_s32_f32): Likewise. 12454 (vcvtq_x_u16_f16): Likewise. 12455 (vcvtq_x_u32_f32): Likewise. 12456 (vcvtq_x_n_s16_f16): Likewise. 12457 (vcvtq_x_n_s32_f32): Likewise. 12458 (vcvtq_x_n_u16_f16): Likewise. 12459 (vcvtq_x_n_u32_f32): Likewise. 12460 (vrndq_x_f16): Likewise. 12461 (vrndq_x_f32): Likewise. 12462 (vrndnq_x_f16): Likewise. 12463 (vrndnq_x_f32): Likewise. 12464 (vrndmq_x_f16): Likewise. 12465 (vrndmq_x_f32): Likewise. 12466 (vrndpq_x_f16): Likewise. 12467 (vrndpq_x_f32): Likewise. 12468 (vrndaq_x_f16): Likewise. 12469 (vrndaq_x_f32): Likewise. 12470 (vrndxq_x_f16): Likewise. 12471 (vrndxq_x_f32): Likewise. 12472 (vandq_x_f16): Likewise. 12473 (vandq_x_f32): Likewise. 12474 (vbicq_x_f16): Likewise. 12475 (vbicq_x_f32): Likewise. 12476 (vbrsrq_x_n_f16): Likewise. 12477 (vbrsrq_x_n_f32): Likewise. 12478 (veorq_x_f16): Likewise. 12479 (veorq_x_f32): Likewise. 12480 (vornq_x_f16): Likewise. 12481 (vornq_x_f32): Likewise. 12482 (vorrq_x_f16): Likewise. 12483 (vorrq_x_f32): Likewise. 12484 (vrev32q_x_f16): Likewise. 12485 (vrev64q_x_f16): Likewise. 12486 (vrev64q_x_f32): Likewise. 12487 (__arm_vddupq_x_n_u8): Define intrinsic. 12488 (__arm_vddupq_x_n_u16): Likewise. 12489 (__arm_vddupq_x_n_u32): Likewise. 12490 (__arm_vddupq_x_wb_u8): Likewise. 12491 (__arm_vddupq_x_wb_u16): Likewise. 12492 (__arm_vddupq_x_wb_u32): Likewise. 12493 (__arm_vdwdupq_x_n_u8): Likewise. 12494 (__arm_vdwdupq_x_n_u16): Likewise. 12495 (__arm_vdwdupq_x_n_u32): Likewise. 12496 (__arm_vdwdupq_x_wb_u8): Likewise. 12497 (__arm_vdwdupq_x_wb_u16): Likewise. 12498 (__arm_vdwdupq_x_wb_u32): Likewise. 12499 (__arm_vidupq_x_n_u8): Likewise. 12500 (__arm_vidupq_x_n_u16): Likewise. 12501 (__arm_vidupq_x_n_u32): Likewise. 12502 (__arm_vidupq_x_wb_u8): Likewise. 12503 (__arm_vidupq_x_wb_u16): Likewise. 12504 (__arm_vidupq_x_wb_u32): Likewise. 12505 (__arm_viwdupq_x_n_u8): Likewise. 12506 (__arm_viwdupq_x_n_u16): Likewise. 12507 (__arm_viwdupq_x_n_u32): Likewise. 12508 (__arm_viwdupq_x_wb_u8): Likewise. 12509 (__arm_viwdupq_x_wb_u16): Likewise. 12510 (__arm_viwdupq_x_wb_u32): Likewise. 12511 (__arm_vdupq_x_n_s8): Likewise. 12512 (__arm_vdupq_x_n_s16): Likewise. 12513 (__arm_vdupq_x_n_s32): Likewise. 12514 (__arm_vdupq_x_n_u8): Likewise. 12515 (__arm_vdupq_x_n_u16): Likewise. 12516 (__arm_vdupq_x_n_u32): Likewise. 12517 (__arm_vminq_x_s8): Likewise. 12518 (__arm_vminq_x_s16): Likewise. 12519 (__arm_vminq_x_s32): Likewise. 12520 (__arm_vminq_x_u8): Likewise. 12521 (__arm_vminq_x_u16): Likewise. 12522 (__arm_vminq_x_u32): Likewise. 12523 (__arm_vmaxq_x_s8): Likewise. 12524 (__arm_vmaxq_x_s16): Likewise. 12525 (__arm_vmaxq_x_s32): Likewise. 12526 (__arm_vmaxq_x_u8): Likewise. 12527 (__arm_vmaxq_x_u16): Likewise. 12528 (__arm_vmaxq_x_u32): Likewise. 12529 (__arm_vabdq_x_s8): Likewise. 12530 (__arm_vabdq_x_s16): Likewise. 12531 (__arm_vabdq_x_s32): Likewise. 12532 (__arm_vabdq_x_u8): Likewise. 12533 (__arm_vabdq_x_u16): Likewise. 12534 (__arm_vabdq_x_u32): Likewise. 12535 (__arm_vabsq_x_s8): Likewise. 12536 (__arm_vabsq_x_s16): Likewise. 12537 (__arm_vabsq_x_s32): Likewise. 12538 (__arm_vaddq_x_s8): Likewise. 12539 (__arm_vaddq_x_s16): Likewise. 12540 (__arm_vaddq_x_s32): Likewise. 12541 (__arm_vaddq_x_n_s8): Likewise. 12542 (__arm_vaddq_x_n_s16): Likewise. 12543 (__arm_vaddq_x_n_s32): Likewise. 12544 (__arm_vaddq_x_u8): Likewise. 12545 (__arm_vaddq_x_u16): Likewise. 12546 (__arm_vaddq_x_u32): Likewise. 12547 (__arm_vaddq_x_n_u8): Likewise. 12548 (__arm_vaddq_x_n_u16): Likewise. 12549 (__arm_vaddq_x_n_u32): Likewise. 12550 (__arm_vclsq_x_s8): Likewise. 12551 (__arm_vclsq_x_s16): Likewise. 12552 (__arm_vclsq_x_s32): Likewise. 12553 (__arm_vclzq_x_s8): Likewise. 12554 (__arm_vclzq_x_s16): Likewise. 12555 (__arm_vclzq_x_s32): Likewise. 12556 (__arm_vclzq_x_u8): Likewise. 12557 (__arm_vclzq_x_u16): Likewise. 12558 (__arm_vclzq_x_u32): Likewise. 12559 (__arm_vnegq_x_s8): Likewise. 12560 (__arm_vnegq_x_s16): Likewise. 12561 (__arm_vnegq_x_s32): Likewise. 12562 (__arm_vmulhq_x_s8): Likewise. 12563 (__arm_vmulhq_x_s16): Likewise. 12564 (__arm_vmulhq_x_s32): Likewise. 12565 (__arm_vmulhq_x_u8): Likewise. 12566 (__arm_vmulhq_x_u16): Likewise. 12567 (__arm_vmulhq_x_u32): Likewise. 12568 (__arm_vmullbq_poly_x_p8): Likewise. 12569 (__arm_vmullbq_poly_x_p16): Likewise. 12570 (__arm_vmullbq_int_x_s8): Likewise. 12571 (__arm_vmullbq_int_x_s16): Likewise. 12572 (__arm_vmullbq_int_x_s32): Likewise. 12573 (__arm_vmullbq_int_x_u8): Likewise. 12574 (__arm_vmullbq_int_x_u16): Likewise. 12575 (__arm_vmullbq_int_x_u32): Likewise. 12576 (__arm_vmulltq_poly_x_p8): Likewise. 12577 (__arm_vmulltq_poly_x_p16): Likewise. 12578 (__arm_vmulltq_int_x_s8): Likewise. 12579 (__arm_vmulltq_int_x_s16): Likewise. 12580 (__arm_vmulltq_int_x_s32): Likewise. 12581 (__arm_vmulltq_int_x_u8): Likewise. 12582 (__arm_vmulltq_int_x_u16): Likewise. 12583 (__arm_vmulltq_int_x_u32): Likewise. 12584 (__arm_vmulq_x_s8): Likewise. 12585 (__arm_vmulq_x_s16): Likewise. 12586 (__arm_vmulq_x_s32): Likewise. 12587 (__arm_vmulq_x_n_s8): Likewise. 12588 (__arm_vmulq_x_n_s16): Likewise. 12589 (__arm_vmulq_x_n_s32): Likewise. 12590 (__arm_vmulq_x_u8): Likewise. 12591 (__arm_vmulq_x_u16): Likewise. 12592 (__arm_vmulq_x_u32): Likewise. 12593 (__arm_vmulq_x_n_u8): Likewise. 12594 (__arm_vmulq_x_n_u16): Likewise. 12595 (__arm_vmulq_x_n_u32): Likewise. 12596 (__arm_vsubq_x_s8): Likewise. 12597 (__arm_vsubq_x_s16): Likewise. 12598 (__arm_vsubq_x_s32): Likewise. 12599 (__arm_vsubq_x_n_s8): Likewise. 12600 (__arm_vsubq_x_n_s16): Likewise. 12601 (__arm_vsubq_x_n_s32): Likewise. 12602 (__arm_vsubq_x_u8): Likewise. 12603 (__arm_vsubq_x_u16): Likewise. 12604 (__arm_vsubq_x_u32): Likewise. 12605 (__arm_vsubq_x_n_u8): Likewise. 12606 (__arm_vsubq_x_n_u16): Likewise. 12607 (__arm_vsubq_x_n_u32): Likewise. 12608 (__arm_vcaddq_rot90_x_s8): Likewise. 12609 (__arm_vcaddq_rot90_x_s16): Likewise. 12610 (__arm_vcaddq_rot90_x_s32): Likewise. 12611 (__arm_vcaddq_rot90_x_u8): Likewise. 12612 (__arm_vcaddq_rot90_x_u16): Likewise. 12613 (__arm_vcaddq_rot90_x_u32): Likewise. 12614 (__arm_vcaddq_rot270_x_s8): Likewise. 12615 (__arm_vcaddq_rot270_x_s16): Likewise. 12616 (__arm_vcaddq_rot270_x_s32): Likewise. 12617 (__arm_vcaddq_rot270_x_u8): Likewise. 12618 (__arm_vcaddq_rot270_x_u16): Likewise. 12619 (__arm_vcaddq_rot270_x_u32): Likewise. 12620 (__arm_vhaddq_x_n_s8): Likewise. 12621 (__arm_vhaddq_x_n_s16): Likewise. 12622 (__arm_vhaddq_x_n_s32): Likewise. 12623 (__arm_vhaddq_x_n_u8): Likewise. 12624 (__arm_vhaddq_x_n_u16): Likewise. 12625 (__arm_vhaddq_x_n_u32): Likewise. 12626 (__arm_vhaddq_x_s8): Likewise. 12627 (__arm_vhaddq_x_s16): Likewise. 12628 (__arm_vhaddq_x_s32): Likewise. 12629 (__arm_vhaddq_x_u8): Likewise. 12630 (__arm_vhaddq_x_u16): Likewise. 12631 (__arm_vhaddq_x_u32): Likewise. 12632 (__arm_vhcaddq_rot90_x_s8): Likewise. 12633 (__arm_vhcaddq_rot90_x_s16): Likewise. 12634 (__arm_vhcaddq_rot90_x_s32): Likewise. 12635 (__arm_vhcaddq_rot270_x_s8): Likewise. 12636 (__arm_vhcaddq_rot270_x_s16): Likewise. 12637 (__arm_vhcaddq_rot270_x_s32): Likewise. 12638 (__arm_vhsubq_x_n_s8): Likewise. 12639 (__arm_vhsubq_x_n_s16): Likewise. 12640 (__arm_vhsubq_x_n_s32): Likewise. 12641 (__arm_vhsubq_x_n_u8): Likewise. 12642 (__arm_vhsubq_x_n_u16): Likewise. 12643 (__arm_vhsubq_x_n_u32): Likewise. 12644 (__arm_vhsubq_x_s8): Likewise. 12645 (__arm_vhsubq_x_s16): Likewise. 12646 (__arm_vhsubq_x_s32): Likewise. 12647 (__arm_vhsubq_x_u8): Likewise. 12648 (__arm_vhsubq_x_u16): Likewise. 12649 (__arm_vhsubq_x_u32): Likewise. 12650 (__arm_vrhaddq_x_s8): Likewise. 12651 (__arm_vrhaddq_x_s16): Likewise. 12652 (__arm_vrhaddq_x_s32): Likewise. 12653 (__arm_vrhaddq_x_u8): Likewise. 12654 (__arm_vrhaddq_x_u16): Likewise. 12655 (__arm_vrhaddq_x_u32): Likewise. 12656 (__arm_vrmulhq_x_s8): Likewise. 12657 (__arm_vrmulhq_x_s16): Likewise. 12658 (__arm_vrmulhq_x_s32): Likewise. 12659 (__arm_vrmulhq_x_u8): Likewise. 12660 (__arm_vrmulhq_x_u16): Likewise. 12661 (__arm_vrmulhq_x_u32): Likewise. 12662 (__arm_vandq_x_s8): Likewise. 12663 (__arm_vandq_x_s16): Likewise. 12664 (__arm_vandq_x_s32): Likewise. 12665 (__arm_vandq_x_u8): Likewise. 12666 (__arm_vandq_x_u16): Likewise. 12667 (__arm_vandq_x_u32): Likewise. 12668 (__arm_vbicq_x_s8): Likewise. 12669 (__arm_vbicq_x_s16): Likewise. 12670 (__arm_vbicq_x_s32): Likewise. 12671 (__arm_vbicq_x_u8): Likewise. 12672 (__arm_vbicq_x_u16): Likewise. 12673 (__arm_vbicq_x_u32): Likewise. 12674 (__arm_vbrsrq_x_n_s8): Likewise. 12675 (__arm_vbrsrq_x_n_s16): Likewise. 12676 (__arm_vbrsrq_x_n_s32): Likewise. 12677 (__arm_vbrsrq_x_n_u8): Likewise. 12678 (__arm_vbrsrq_x_n_u16): Likewise. 12679 (__arm_vbrsrq_x_n_u32): Likewise. 12680 (__arm_veorq_x_s8): Likewise. 12681 (__arm_veorq_x_s16): Likewise. 12682 (__arm_veorq_x_s32): Likewise. 12683 (__arm_veorq_x_u8): Likewise. 12684 (__arm_veorq_x_u16): Likewise. 12685 (__arm_veorq_x_u32): Likewise. 12686 (__arm_vmovlbq_x_s8): Likewise. 12687 (__arm_vmovlbq_x_s16): Likewise. 12688 (__arm_vmovlbq_x_u8): Likewise. 12689 (__arm_vmovlbq_x_u16): Likewise. 12690 (__arm_vmovltq_x_s8): Likewise. 12691 (__arm_vmovltq_x_s16): Likewise. 12692 (__arm_vmovltq_x_u8): Likewise. 12693 (__arm_vmovltq_x_u16): Likewise. 12694 (__arm_vmvnq_x_s8): Likewise. 12695 (__arm_vmvnq_x_s16): Likewise. 12696 (__arm_vmvnq_x_s32): Likewise. 12697 (__arm_vmvnq_x_u8): Likewise. 12698 (__arm_vmvnq_x_u16): Likewise. 12699 (__arm_vmvnq_x_u32): Likewise. 12700 (__arm_vmvnq_x_n_s16): Likewise. 12701 (__arm_vmvnq_x_n_s32): Likewise. 12702 (__arm_vmvnq_x_n_u16): Likewise. 12703 (__arm_vmvnq_x_n_u32): Likewise. 12704 (__arm_vornq_x_s8): Likewise. 12705 (__arm_vornq_x_s16): Likewise. 12706 (__arm_vornq_x_s32): Likewise. 12707 (__arm_vornq_x_u8): Likewise. 12708 (__arm_vornq_x_u16): Likewise. 12709 (__arm_vornq_x_u32): Likewise. 12710 (__arm_vorrq_x_s8): Likewise. 12711 (__arm_vorrq_x_s16): Likewise. 12712 (__arm_vorrq_x_s32): Likewise. 12713 (__arm_vorrq_x_u8): Likewise. 12714 (__arm_vorrq_x_u16): Likewise. 12715 (__arm_vorrq_x_u32): Likewise. 12716 (__arm_vrev16q_x_s8): Likewise. 12717 (__arm_vrev16q_x_u8): Likewise. 12718 (__arm_vrev32q_x_s8): Likewise. 12719 (__arm_vrev32q_x_s16): Likewise. 12720 (__arm_vrev32q_x_u8): Likewise. 12721 (__arm_vrev32q_x_u16): Likewise. 12722 (__arm_vrev64q_x_s8): Likewise. 12723 (__arm_vrev64q_x_s16): Likewise. 12724 (__arm_vrev64q_x_s32): Likewise. 12725 (__arm_vrev64q_x_u8): Likewise. 12726 (__arm_vrev64q_x_u16): Likewise. 12727 (__arm_vrev64q_x_u32): Likewise. 12728 (__arm_vrshlq_x_s8): Likewise. 12729 (__arm_vrshlq_x_s16): Likewise. 12730 (__arm_vrshlq_x_s32): Likewise. 12731 (__arm_vrshlq_x_u8): Likewise. 12732 (__arm_vrshlq_x_u16): Likewise. 12733 (__arm_vrshlq_x_u32): Likewise. 12734 (__arm_vshllbq_x_n_s8): Likewise. 12735 (__arm_vshllbq_x_n_s16): Likewise. 12736 (__arm_vshllbq_x_n_u8): Likewise. 12737 (__arm_vshllbq_x_n_u16): Likewise. 12738 (__arm_vshlltq_x_n_s8): Likewise. 12739 (__arm_vshlltq_x_n_s16): Likewise. 12740 (__arm_vshlltq_x_n_u8): Likewise. 12741 (__arm_vshlltq_x_n_u16): Likewise. 12742 (__arm_vshlq_x_s8): Likewise. 12743 (__arm_vshlq_x_s16): Likewise. 12744 (__arm_vshlq_x_s32): Likewise. 12745 (__arm_vshlq_x_u8): Likewise. 12746 (__arm_vshlq_x_u16): Likewise. 12747 (__arm_vshlq_x_u32): Likewise. 12748 (__arm_vshlq_x_n_s8): Likewise. 12749 (__arm_vshlq_x_n_s16): Likewise. 12750 (__arm_vshlq_x_n_s32): Likewise. 12751 (__arm_vshlq_x_n_u8): Likewise. 12752 (__arm_vshlq_x_n_u16): Likewise. 12753 (__arm_vshlq_x_n_u32): Likewise. 12754 (__arm_vrshrq_x_n_s8): Likewise. 12755 (__arm_vrshrq_x_n_s16): Likewise. 12756 (__arm_vrshrq_x_n_s32): Likewise. 12757 (__arm_vrshrq_x_n_u8): Likewise. 12758 (__arm_vrshrq_x_n_u16): Likewise. 12759 (__arm_vrshrq_x_n_u32): Likewise. 12760 (__arm_vshrq_x_n_s8): Likewise. 12761 (__arm_vshrq_x_n_s16): Likewise. 12762 (__arm_vshrq_x_n_s32): Likewise. 12763 (__arm_vshrq_x_n_u8): Likewise. 12764 (__arm_vshrq_x_n_u16): Likewise. 12765 (__arm_vshrq_x_n_u32): Likewise. 12766 (__arm_vdupq_x_n_f16): Likewise. 12767 (__arm_vdupq_x_n_f32): Likewise. 12768 (__arm_vminnmq_x_f16): Likewise. 12769 (__arm_vminnmq_x_f32): Likewise. 12770 (__arm_vmaxnmq_x_f16): Likewise. 12771 (__arm_vmaxnmq_x_f32): Likewise. 12772 (__arm_vabdq_x_f16): Likewise. 12773 (__arm_vabdq_x_f32): Likewise. 12774 (__arm_vabsq_x_f16): Likewise. 12775 (__arm_vabsq_x_f32): Likewise. 12776 (__arm_vaddq_x_f16): Likewise. 12777 (__arm_vaddq_x_f32): Likewise. 12778 (__arm_vaddq_x_n_f16): Likewise. 12779 (__arm_vaddq_x_n_f32): Likewise. 12780 (__arm_vnegq_x_f16): Likewise. 12781 (__arm_vnegq_x_f32): Likewise. 12782 (__arm_vmulq_x_f16): Likewise. 12783 (__arm_vmulq_x_f32): Likewise. 12784 (__arm_vmulq_x_n_f16): Likewise. 12785 (__arm_vmulq_x_n_f32): Likewise. 12786 (__arm_vsubq_x_f16): Likewise. 12787 (__arm_vsubq_x_f32): Likewise. 12788 (__arm_vsubq_x_n_f16): Likewise. 12789 (__arm_vsubq_x_n_f32): Likewise. 12790 (__arm_vcaddq_rot90_x_f16): Likewise. 12791 (__arm_vcaddq_rot90_x_f32): Likewise. 12792 (__arm_vcaddq_rot270_x_f16): Likewise. 12793 (__arm_vcaddq_rot270_x_f32): Likewise. 12794 (__arm_vcmulq_x_f16): Likewise. 12795 (__arm_vcmulq_x_f32): Likewise. 12796 (__arm_vcmulq_rot90_x_f16): Likewise. 12797 (__arm_vcmulq_rot90_x_f32): Likewise. 12798 (__arm_vcmulq_rot180_x_f16): Likewise. 12799 (__arm_vcmulq_rot180_x_f32): Likewise. 12800 (__arm_vcmulq_rot270_x_f16): Likewise. 12801 (__arm_vcmulq_rot270_x_f32): Likewise. 12802 (__arm_vcvtaq_x_s16_f16): Likewise. 12803 (__arm_vcvtaq_x_s32_f32): Likewise. 12804 (__arm_vcvtaq_x_u16_f16): Likewise. 12805 (__arm_vcvtaq_x_u32_f32): Likewise. 12806 (__arm_vcvtnq_x_s16_f16): Likewise. 12807 (__arm_vcvtnq_x_s32_f32): Likewise. 12808 (__arm_vcvtnq_x_u16_f16): Likewise. 12809 (__arm_vcvtnq_x_u32_f32): Likewise. 12810 (__arm_vcvtpq_x_s16_f16): Likewise. 12811 (__arm_vcvtpq_x_s32_f32): Likewise. 12812 (__arm_vcvtpq_x_u16_f16): Likewise. 12813 (__arm_vcvtpq_x_u32_f32): Likewise. 12814 (__arm_vcvtmq_x_s16_f16): Likewise. 12815 (__arm_vcvtmq_x_s32_f32): Likewise. 12816 (__arm_vcvtmq_x_u16_f16): Likewise. 12817 (__arm_vcvtmq_x_u32_f32): Likewise. 12818 (__arm_vcvtbq_x_f32_f16): Likewise. 12819 (__arm_vcvttq_x_f32_f16): Likewise. 12820 (__arm_vcvtq_x_f16_u16): Likewise. 12821 (__arm_vcvtq_x_f16_s16): Likewise. 12822 (__arm_vcvtq_x_f32_s32): Likewise. 12823 (__arm_vcvtq_x_f32_u32): Likewise. 12824 (__arm_vcvtq_x_n_f16_s16): Likewise. 12825 (__arm_vcvtq_x_n_f16_u16): Likewise. 12826 (__arm_vcvtq_x_n_f32_s32): Likewise. 12827 (__arm_vcvtq_x_n_f32_u32): Likewise. 12828 (__arm_vcvtq_x_s16_f16): Likewise. 12829 (__arm_vcvtq_x_s32_f32): Likewise. 12830 (__arm_vcvtq_x_u16_f16): Likewise. 12831 (__arm_vcvtq_x_u32_f32): Likewise. 12832 (__arm_vcvtq_x_n_s16_f16): Likewise. 12833 (__arm_vcvtq_x_n_s32_f32): Likewise. 12834 (__arm_vcvtq_x_n_u16_f16): Likewise. 12835 (__arm_vcvtq_x_n_u32_f32): Likewise. 12836 (__arm_vrndq_x_f16): Likewise. 12837 (__arm_vrndq_x_f32): Likewise. 12838 (__arm_vrndnq_x_f16): Likewise. 12839 (__arm_vrndnq_x_f32): Likewise. 12840 (__arm_vrndmq_x_f16): Likewise. 12841 (__arm_vrndmq_x_f32): Likewise. 12842 (__arm_vrndpq_x_f16): Likewise. 12843 (__arm_vrndpq_x_f32): Likewise. 12844 (__arm_vrndaq_x_f16): Likewise. 12845 (__arm_vrndaq_x_f32): Likewise. 12846 (__arm_vrndxq_x_f16): Likewise. 12847 (__arm_vrndxq_x_f32): Likewise. 12848 (__arm_vandq_x_f16): Likewise. 12849 (__arm_vandq_x_f32): Likewise. 12850 (__arm_vbicq_x_f16): Likewise. 12851 (__arm_vbicq_x_f32): Likewise. 12852 (__arm_vbrsrq_x_n_f16): Likewise. 12853 (__arm_vbrsrq_x_n_f32): Likewise. 12854 (__arm_veorq_x_f16): Likewise. 12855 (__arm_veorq_x_f32): Likewise. 12856 (__arm_vornq_x_f16): Likewise. 12857 (__arm_vornq_x_f32): Likewise. 12858 (__arm_vorrq_x_f16): Likewise. 12859 (__arm_vorrq_x_f32): Likewise. 12860 (__arm_vrev32q_x_f16): Likewise. 12861 (__arm_vrev64q_x_f16): Likewise. 12862 (__arm_vrev64q_x_f32): Likewise. 12863 (vabdq_x): Define polymorphic variant. 12864 (vabsq_x): Likewise. 12865 (vaddq_x): Likewise. 12866 (vandq_x): Likewise. 12867 (vbicq_x): Likewise. 12868 (vbrsrq_x): Likewise. 12869 (vcaddq_rot270_x): Likewise. 12870 (vcaddq_rot90_x): Likewise. 12871 (vcmulq_rot180_x): Likewise. 12872 (vcmulq_rot270_x): Likewise. 12873 (vcmulq_x): Likewise. 12874 (vcvtq_x): Likewise. 12875 (vcvtq_x_n): Likewise. 12876 (vcvtnq_m): Likewise. 12877 (veorq_x): Likewise. 12878 (vmaxnmq_x): Likewise. 12879 (vminnmq_x): Likewise. 12880 (vmulq_x): Likewise. 12881 (vnegq_x): Likewise. 12882 (vornq_x): Likewise. 12883 (vorrq_x): Likewise. 12884 (vrev32q_x): Likewise. 12885 (vrev64q_x): Likewise. 12886 (vrndaq_x): Likewise. 12887 (vrndmq_x): Likewise. 12888 (vrndnq_x): Likewise. 12889 (vrndpq_x): Likewise. 12890 (vrndq_x): Likewise. 12891 (vrndxq_x): Likewise. 12892 (vsubq_x): Likewise. 12893 (vcmulq_rot90_x): Likewise. 12894 (vadciq): Likewise. 12895 (vclsq_x): Likewise. 12896 (vclzq_x): Likewise. 12897 (vhaddq_x): Likewise. 12898 (vhcaddq_rot270_x): Likewise. 12899 (vhcaddq_rot90_x): Likewise. 12900 (vhsubq_x): Likewise. 12901 (vmaxq_x): Likewise. 12902 (vminq_x): Likewise. 12903 (vmovlbq_x): Likewise. 12904 (vmovltq_x): Likewise. 12905 (vmulhq_x): Likewise. 12906 (vmullbq_int_x): Likewise. 12907 (vmullbq_poly_x): Likewise. 12908 (vmulltq_int_x): Likewise. 12909 (vmulltq_poly_x): Likewise. 12910 (vmvnq_x): Likewise. 12911 (vrev16q_x): Likewise. 12912 (vrhaddq_x): Likewise. 12913 (vrmulhq_x): Likewise. 12914 (vrshlq_x): Likewise. 12915 (vrshrq_x): Likewise. 12916 (vshllbq_x): Likewise. 12917 (vshlltq_x): Likewise. 12918 (vshlq_x_n): Likewise. 12919 (vshlq_x): Likewise. 12920 (vdwdupq_x_u8): Likewise. 12921 (vdwdupq_x_u16): Likewise. 12922 (vdwdupq_x_u32): Likewise. 12923 (viwdupq_x_u8): Likewise. 12924 (viwdupq_x_u16): Likewise. 12925 (viwdupq_x_u32): Likewise. 12926 (vidupq_x_u8): Likewise. 12927 (vddupq_x_u8): Likewise. 12928 (vidupq_x_u16): Likewise. 12929 (vddupq_x_u16): Likewise. 12930 (vidupq_x_u32): Likewise. 12931 (vddupq_x_u32): Likewise. 12932 (vshrq_x): Likewise. 12933 129342020-03-20 Richard Biener <rguenther@suse.de> 12935 12936 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts 12937 to vectorize for CTOR defs. 12938 129392020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 12940 Andre Vieira <andre.simoesdiasvieira@arm.com> 12941 Mihail Ionescu <mihail.ionescu@arm.com> 12942 12943 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin 12944 qualifier. 12945 (LDRGBWBU_QUALIFIERS): Likewise. 12946 (LDRGBWBS_Z_QUALIFIERS): Likewise. 12947 (LDRGBWBU_Z_QUALIFIERS): Likewise. 12948 (STRSBWBS_QUALIFIERS): Likewise. 12949 (STRSBWBU_QUALIFIERS): Likewise. 12950 (STRSBWBS_P_QUALIFIERS): Likewise. 12951 (STRSBWBU_P_QUALIFIERS): Likewise. 12952 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro. 12953 (vldrdq_gather_base_wb_u64): Likewise. 12954 (vldrdq_gather_base_wb_z_s64): Likewise. 12955 (vldrdq_gather_base_wb_z_u64): Likewise. 12956 (vldrwq_gather_base_wb_f32): Likewise. 12957 (vldrwq_gather_base_wb_s32): Likewise. 12958 (vldrwq_gather_base_wb_u32): Likewise. 12959 (vldrwq_gather_base_wb_z_f32): Likewise. 12960 (vldrwq_gather_base_wb_z_s32): Likewise. 12961 (vldrwq_gather_base_wb_z_u32): Likewise. 12962 (vstrdq_scatter_base_wb_p_s64): Likewise. 12963 (vstrdq_scatter_base_wb_p_u64): Likewise. 12964 (vstrdq_scatter_base_wb_s64): Likewise. 12965 (vstrdq_scatter_base_wb_u64): Likewise. 12966 (vstrwq_scatter_base_wb_p_s32): Likewise. 12967 (vstrwq_scatter_base_wb_p_f32): Likewise. 12968 (vstrwq_scatter_base_wb_p_u32): Likewise. 12969 (vstrwq_scatter_base_wb_s32): Likewise. 12970 (vstrwq_scatter_base_wb_u32): Likewise. 12971 (vstrwq_scatter_base_wb_f32): Likewise. 12972 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic. 12973 (__arm_vldrdq_gather_base_wb_u64): Likewise. 12974 (__arm_vldrdq_gather_base_wb_z_s64): Likewise. 12975 (__arm_vldrdq_gather_base_wb_z_u64): Likewise. 12976 (__arm_vldrwq_gather_base_wb_s32): Likewise. 12977 (__arm_vldrwq_gather_base_wb_u32): Likewise. 12978 (__arm_vldrwq_gather_base_wb_z_s32): Likewise. 12979 (__arm_vldrwq_gather_base_wb_z_u32): Likewise. 12980 (__arm_vstrdq_scatter_base_wb_s64): Likewise. 12981 (__arm_vstrdq_scatter_base_wb_u64): Likewise. 12982 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. 12983 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. 12984 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. 12985 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. 12986 (__arm_vstrwq_scatter_base_wb_s32): Likewise. 12987 (__arm_vstrwq_scatter_base_wb_u32): Likewise. 12988 (__arm_vldrwq_gather_base_wb_f32): Likewise. 12989 (__arm_vldrwq_gather_base_wb_z_f32): Likewise. 12990 (__arm_vstrwq_scatter_base_wb_f32): Likewise. 12991 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. 12992 (vstrwq_scatter_base_wb): Define polymorphic variant. 12993 (vstrwq_scatter_base_wb_p): Likewise. 12994 (vstrdq_scatter_base_wb_p): Likewise. 12995 (vstrdq_scatter_base_wb): Likewise. 12996 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin 12997 qualifier. 12998 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL 12999 pattern. 13000 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise. 13001 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise. 13002 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise. 13003 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise. 13004 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise. 13005 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. 13006 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. 13007 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise. 13008 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. 13009 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. 13010 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise. 13011 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise. 13012 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise. 13013 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise. 13014 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise. 13015 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise. 13016 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise. 13017 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise. 13018 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise. 13019 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise. 13020 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise. 13021 (mve_vldrwq_gather_base_wb_fv4sf): Likewise. 13022 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. 13023 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise. 13024 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. 13025 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise. 13026 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise. 13027 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise. 13028 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise. 13029 130302020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13031 Andre Vieira <andre.simoesdiasvieira@arm.com> 13032 Mihail Ionescu <mihail.ionescu@arm.com> 13033 13034 * config/arm/arm-builtins.c 13035 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary 13036 builtin qualifier. 13037 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro. 13038 (vddupq_m_n_u32): Likewise. 13039 (vddupq_m_n_u16): Likewise. 13040 (vddupq_m_wb_u8): Likewise. 13041 (vddupq_m_wb_u16): Likewise. 13042 (vddupq_m_wb_u32): Likewise. 13043 (vddupq_n_u8): Likewise. 13044 (vddupq_n_u32): Likewise. 13045 (vddupq_n_u16): Likewise. 13046 (vddupq_wb_u8): Likewise. 13047 (vddupq_wb_u16): Likewise. 13048 (vddupq_wb_u32): Likewise. 13049 (vdwdupq_m_n_u8): Likewise. 13050 (vdwdupq_m_n_u32): Likewise. 13051 (vdwdupq_m_n_u16): Likewise. 13052 (vdwdupq_m_wb_u8): Likewise. 13053 (vdwdupq_m_wb_u32): Likewise. 13054 (vdwdupq_m_wb_u16): Likewise. 13055 (vdwdupq_n_u8): Likewise. 13056 (vdwdupq_n_u32): Likewise. 13057 (vdwdupq_n_u16): Likewise. 13058 (vdwdupq_wb_u8): Likewise. 13059 (vdwdupq_wb_u32): Likewise. 13060 (vdwdupq_wb_u16): Likewise. 13061 (vidupq_m_n_u8): Likewise. 13062 (vidupq_m_n_u32): Likewise. 13063 (vidupq_m_n_u16): Likewise. 13064 (vidupq_m_wb_u8): Likewise. 13065 (vidupq_m_wb_u16): Likewise. 13066 (vidupq_m_wb_u32): Likewise. 13067 (vidupq_n_u8): Likewise. 13068 (vidupq_n_u32): Likewise. 13069 (vidupq_n_u16): Likewise. 13070 (vidupq_wb_u8): Likewise. 13071 (vidupq_wb_u16): Likewise. 13072 (vidupq_wb_u32): Likewise. 13073 (viwdupq_m_n_u8): Likewise. 13074 (viwdupq_m_n_u32): Likewise. 13075 (viwdupq_m_n_u16): Likewise. 13076 (viwdupq_m_wb_u8): Likewise. 13077 (viwdupq_m_wb_u32): Likewise. 13078 (viwdupq_m_wb_u16): Likewise. 13079 (viwdupq_n_u8): Likewise. 13080 (viwdupq_n_u32): Likewise. 13081 (viwdupq_n_u16): Likewise. 13082 (viwdupq_wb_u8): Likewise. 13083 (viwdupq_wb_u32): Likewise. 13084 (viwdupq_wb_u16): Likewise. 13085 (__arm_vddupq_m_n_u8): Define intrinsic. 13086 (__arm_vddupq_m_n_u32): Likewise. 13087 (__arm_vddupq_m_n_u16): Likewise. 13088 (__arm_vddupq_m_wb_u8): Likewise. 13089 (__arm_vddupq_m_wb_u16): Likewise. 13090 (__arm_vddupq_m_wb_u32): Likewise. 13091 (__arm_vddupq_n_u8): Likewise. 13092 (__arm_vddupq_n_u32): Likewise. 13093 (__arm_vddupq_n_u16): Likewise. 13094 (__arm_vdwdupq_m_n_u8): Likewise. 13095 (__arm_vdwdupq_m_n_u32): Likewise. 13096 (__arm_vdwdupq_m_n_u16): Likewise. 13097 (__arm_vdwdupq_m_wb_u8): Likewise. 13098 (__arm_vdwdupq_m_wb_u32): Likewise. 13099 (__arm_vdwdupq_m_wb_u16): Likewise. 13100 (__arm_vdwdupq_n_u8): Likewise. 13101 (__arm_vdwdupq_n_u32): Likewise. 13102 (__arm_vdwdupq_n_u16): Likewise. 13103 (__arm_vdwdupq_wb_u8): Likewise. 13104 (__arm_vdwdupq_wb_u32): Likewise. 13105 (__arm_vdwdupq_wb_u16): Likewise. 13106 (__arm_vidupq_m_n_u8): Likewise. 13107 (__arm_vidupq_m_n_u32): Likewise. 13108 (__arm_vidupq_m_n_u16): Likewise. 13109 (__arm_vidupq_n_u8): Likewise. 13110 (__arm_vidupq_m_wb_u8): Likewise. 13111 (__arm_vidupq_m_wb_u16): Likewise. 13112 (__arm_vidupq_m_wb_u32): Likewise. 13113 (__arm_vidupq_n_u32): Likewise. 13114 (__arm_vidupq_n_u16): Likewise. 13115 (__arm_vidupq_wb_u8): Likewise. 13116 (__arm_vidupq_wb_u16): Likewise. 13117 (__arm_vidupq_wb_u32): Likewise. 13118 (__arm_vddupq_wb_u8): Likewise. 13119 (__arm_vddupq_wb_u16): Likewise. 13120 (__arm_vddupq_wb_u32): Likewise. 13121 (__arm_viwdupq_m_n_u8): Likewise. 13122 (__arm_viwdupq_m_n_u32): Likewise. 13123 (__arm_viwdupq_m_n_u16): Likewise. 13124 (__arm_viwdupq_m_wb_u8): Likewise. 13125 (__arm_viwdupq_m_wb_u32): Likewise. 13126 (__arm_viwdupq_m_wb_u16): Likewise. 13127 (__arm_viwdupq_n_u8): Likewise. 13128 (__arm_viwdupq_n_u32): Likewise. 13129 (__arm_viwdupq_n_u16): Likewise. 13130 (__arm_viwdupq_wb_u8): Likewise. 13131 (__arm_viwdupq_wb_u32): Likewise. 13132 (__arm_viwdupq_wb_u16): Likewise. 13133 (vidupq_m): Define polymorphic variant. 13134 (vddupq_m): Likewise. 13135 (vidupq_u16): Likewise. 13136 (vidupq_u32): Likewise. 13137 (vidupq_u8): Likewise. 13138 (vddupq_u16): Likewise. 13139 (vddupq_u32): Likewise. 13140 (vddupq_u8): Likewise. 13141 (viwdupq_m): Likewise. 13142 (viwdupq_u16): Likewise. 13143 (viwdupq_u32): Likewise. 13144 (viwdupq_u8): Likewise. 13145 (vdwdupq_m): Likewise. 13146 (vdwdupq_u16): Likewise. 13147 (vdwdupq_u32): Likewise. 13148 (vdwdupq_u8): Likewise. 13149 * config/arm/arm_mve_builtins.def 13150 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin 13151 qualifier. 13152 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern. 13153 (mve_vidupq_u<mode>_insn): Likewise. 13154 (mve_vidupq_m_n_u<mode>): Likewise. 13155 (mve_vidupq_m_wb_u<mode>_insn): Likewise. 13156 (mve_vddupq_n_u<mode>): Likewise. 13157 (mve_vddupq_u<mode>_insn): Likewise. 13158 (mve_vddupq_m_n_u<mode>): Likewise. 13159 (mve_vddupq_m_wb_u<mode>_insn): Likewise. 13160 (mve_vdwdupq_n_u<mode>): Likewise. 13161 (mve_vdwdupq_wb_u<mode>): Likewise. 13162 (mve_vdwdupq_wb_u<mode>_insn): Likewise. 13163 (mve_vdwdupq_m_n_u<mode>): Likewise. 13164 (mve_vdwdupq_m_wb_u<mode>): Likewise. 13165 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise. 13166 (mve_viwdupq_n_u<mode>): Likewise. 13167 (mve_viwdupq_wb_u<mode>): Likewise. 13168 (mve_viwdupq_wb_u<mode>_insn): Likewise. 13169 (mve_viwdupq_m_n_u<mode>): Likewise. 13170 (mve_viwdupq_m_wb_u<mode>): Likewise. 13171 (mve_viwdupq_m_wb_u<mode>_insn): Likewise. 13172 131732020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13174 13175 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. 13176 (vreinterpretq_s16_s64): Likewise. 13177 (vreinterpretq_s16_s8): Likewise. 13178 (vreinterpretq_s16_u16): Likewise. 13179 (vreinterpretq_s16_u32): Likewise. 13180 (vreinterpretq_s16_u64): Likewise. 13181 (vreinterpretq_s16_u8): Likewise. 13182 (vreinterpretq_s32_s16): Likewise. 13183 (vreinterpretq_s32_s64): Likewise. 13184 (vreinterpretq_s32_s8): Likewise. 13185 (vreinterpretq_s32_u16): Likewise. 13186 (vreinterpretq_s32_u32): Likewise. 13187 (vreinterpretq_s32_u64): Likewise. 13188 (vreinterpretq_s32_u8): Likewise. 13189 (vreinterpretq_s64_s16): Likewise. 13190 (vreinterpretq_s64_s32): Likewise. 13191 (vreinterpretq_s64_s8): Likewise. 13192 (vreinterpretq_s64_u16): Likewise. 13193 (vreinterpretq_s64_u32): Likewise. 13194 (vreinterpretq_s64_u64): Likewise. 13195 (vreinterpretq_s64_u8): Likewise. 13196 (vreinterpretq_s8_s16): Likewise. 13197 (vreinterpretq_s8_s32): Likewise. 13198 (vreinterpretq_s8_s64): Likewise. 13199 (vreinterpretq_s8_u16): Likewise. 13200 (vreinterpretq_s8_u32): Likewise. 13201 (vreinterpretq_s8_u64): Likewise. 13202 (vreinterpretq_s8_u8): Likewise. 13203 (vreinterpretq_u16_s16): Likewise. 13204 (vreinterpretq_u16_s32): Likewise. 13205 (vreinterpretq_u16_s64): Likewise. 13206 (vreinterpretq_u16_s8): Likewise. 13207 (vreinterpretq_u16_u32): Likewise. 13208 (vreinterpretq_u16_u64): Likewise. 13209 (vreinterpretq_u16_u8): Likewise. 13210 (vreinterpretq_u32_s16): Likewise. 13211 (vreinterpretq_u32_s32): Likewise. 13212 (vreinterpretq_u32_s64): Likewise. 13213 (vreinterpretq_u32_s8): Likewise. 13214 (vreinterpretq_u32_u16): Likewise. 13215 (vreinterpretq_u32_u64): Likewise. 13216 (vreinterpretq_u32_u8): Likewise. 13217 (vreinterpretq_u64_s16): Likewise. 13218 (vreinterpretq_u64_s32): Likewise. 13219 (vreinterpretq_u64_s64): Likewise. 13220 (vreinterpretq_u64_s8): Likewise. 13221 (vreinterpretq_u64_u16): Likewise. 13222 (vreinterpretq_u64_u32): Likewise. 13223 (vreinterpretq_u64_u8): Likewise. 13224 (vreinterpretq_u8_s16): Likewise. 13225 (vreinterpretq_u8_s32): Likewise. 13226 (vreinterpretq_u8_s64): Likewise. 13227 (vreinterpretq_u8_s8): Likewise. 13228 (vreinterpretq_u8_u16): Likewise. 13229 (vreinterpretq_u8_u32): Likewise. 13230 (vreinterpretq_u8_u64): Likewise. 13231 (vreinterpretq_s32_f16): Likewise. 13232 (vreinterpretq_s32_f32): Likewise. 13233 (vreinterpretq_u16_f16): Likewise. 13234 (vreinterpretq_u16_f32): Likewise. 13235 (vreinterpretq_u32_f16): Likewise. 13236 (vreinterpretq_u32_f32): Likewise. 13237 (vreinterpretq_u64_f16): Likewise. 13238 (vreinterpretq_u64_f32): Likewise. 13239 (vreinterpretq_u8_f16): Likewise. 13240 (vreinterpretq_u8_f32): Likewise. 13241 (vreinterpretq_f16_f32): Likewise. 13242 (vreinterpretq_f16_s16): Likewise. 13243 (vreinterpretq_f16_s32): Likewise. 13244 (vreinterpretq_f16_s64): Likewise. 13245 (vreinterpretq_f16_s8): Likewise. 13246 (vreinterpretq_f16_u16): Likewise. 13247 (vreinterpretq_f16_u32): Likewise. 13248 (vreinterpretq_f16_u64): Likewise. 13249 (vreinterpretq_f16_u8): Likewise. 13250 (vreinterpretq_f32_f16): Likewise. 13251 (vreinterpretq_f32_s16): Likewise. 13252 (vreinterpretq_f32_s32): Likewise. 13253 (vreinterpretq_f32_s64): Likewise. 13254 (vreinterpretq_f32_s8): Likewise. 13255 (vreinterpretq_f32_u16): Likewise. 13256 (vreinterpretq_f32_u32): Likewise. 13257 (vreinterpretq_f32_u64): Likewise. 13258 (vreinterpretq_f32_u8): Likewise. 13259 (vreinterpretq_s16_f16): Likewise. 13260 (vreinterpretq_s16_f32): Likewise. 13261 (vreinterpretq_s64_f16): Likewise. 13262 (vreinterpretq_s64_f32): Likewise. 13263 (vreinterpretq_s8_f16): Likewise. 13264 (vreinterpretq_s8_f32): Likewise. 13265 (vuninitializedq_u8): Likewise. 13266 (vuninitializedq_u16): Likewise. 13267 (vuninitializedq_u32): Likewise. 13268 (vuninitializedq_u64): Likewise. 13269 (vuninitializedq_s8): Likewise. 13270 (vuninitializedq_s16): Likewise. 13271 (vuninitializedq_s32): Likewise. 13272 (vuninitializedq_s64): Likewise. 13273 (vuninitializedq_f16): Likewise. 13274 (vuninitializedq_f32): Likewise. 13275 (__arm_vuninitializedq_u8): Define intrinsic. 13276 (__arm_vuninitializedq_u16): Likewise. 13277 (__arm_vuninitializedq_u32): Likewise. 13278 (__arm_vuninitializedq_u64): Likewise. 13279 (__arm_vuninitializedq_s8): Likewise. 13280 (__arm_vuninitializedq_s16): Likewise. 13281 (__arm_vuninitializedq_s32): Likewise. 13282 (__arm_vuninitializedq_s64): Likewise. 13283 (__arm_vreinterpretq_s16_s32): Likewise. 13284 (__arm_vreinterpretq_s16_s64): Likewise. 13285 (__arm_vreinterpretq_s16_s8): Likewise. 13286 (__arm_vreinterpretq_s16_u16): Likewise. 13287 (__arm_vreinterpretq_s16_u32): Likewise. 13288 (__arm_vreinterpretq_s16_u64): Likewise. 13289 (__arm_vreinterpretq_s16_u8): Likewise. 13290 (__arm_vreinterpretq_s32_s16): Likewise. 13291 (__arm_vreinterpretq_s32_s64): Likewise. 13292 (__arm_vreinterpretq_s32_s8): Likewise. 13293 (__arm_vreinterpretq_s32_u16): Likewise. 13294 (__arm_vreinterpretq_s32_u32): Likewise. 13295 (__arm_vreinterpretq_s32_u64): Likewise. 13296 (__arm_vreinterpretq_s32_u8): Likewise. 13297 (__arm_vreinterpretq_s64_s16): Likewise. 13298 (__arm_vreinterpretq_s64_s32): Likewise. 13299 (__arm_vreinterpretq_s64_s8): Likewise. 13300 (__arm_vreinterpretq_s64_u16): Likewise. 13301 (__arm_vreinterpretq_s64_u32): Likewise. 13302 (__arm_vreinterpretq_s64_u64): Likewise. 13303 (__arm_vreinterpretq_s64_u8): Likewise. 13304 (__arm_vreinterpretq_s8_s16): Likewise. 13305 (__arm_vreinterpretq_s8_s32): Likewise. 13306 (__arm_vreinterpretq_s8_s64): Likewise. 13307 (__arm_vreinterpretq_s8_u16): Likewise. 13308 (__arm_vreinterpretq_s8_u32): Likewise. 13309 (__arm_vreinterpretq_s8_u64): Likewise. 13310 (__arm_vreinterpretq_s8_u8): Likewise. 13311 (__arm_vreinterpretq_u16_s16): Likewise. 13312 (__arm_vreinterpretq_u16_s32): Likewise. 13313 (__arm_vreinterpretq_u16_s64): Likewise. 13314 (__arm_vreinterpretq_u16_s8): Likewise. 13315 (__arm_vreinterpretq_u16_u32): Likewise. 13316 (__arm_vreinterpretq_u16_u64): Likewise. 13317 (__arm_vreinterpretq_u16_u8): Likewise. 13318 (__arm_vreinterpretq_u32_s16): Likewise. 13319 (__arm_vreinterpretq_u32_s32): Likewise. 13320 (__arm_vreinterpretq_u32_s64): Likewise. 13321 (__arm_vreinterpretq_u32_s8): Likewise. 13322 (__arm_vreinterpretq_u32_u16): Likewise. 13323 (__arm_vreinterpretq_u32_u64): Likewise. 13324 (__arm_vreinterpretq_u32_u8): Likewise. 13325 (__arm_vreinterpretq_u64_s16): Likewise. 13326 (__arm_vreinterpretq_u64_s32): Likewise. 13327 (__arm_vreinterpretq_u64_s64): Likewise. 13328 (__arm_vreinterpretq_u64_s8): Likewise. 13329 (__arm_vreinterpretq_u64_u16): Likewise. 13330 (__arm_vreinterpretq_u64_u32): Likewise. 13331 (__arm_vreinterpretq_u64_u8): Likewise. 13332 (__arm_vreinterpretq_u8_s16): Likewise. 13333 (__arm_vreinterpretq_u8_s32): Likewise. 13334 (__arm_vreinterpretq_u8_s64): Likewise. 13335 (__arm_vreinterpretq_u8_s8): Likewise. 13336 (__arm_vreinterpretq_u8_u16): Likewise. 13337 (__arm_vreinterpretq_u8_u32): Likewise. 13338 (__arm_vreinterpretq_u8_u64): Likewise. 13339 (__arm_vuninitializedq_f16): Likewise. 13340 (__arm_vuninitializedq_f32): Likewise. 13341 (__arm_vreinterpretq_s32_f16): Likewise. 13342 (__arm_vreinterpretq_s32_f32): Likewise. 13343 (__arm_vreinterpretq_s16_f16): Likewise. 13344 (__arm_vreinterpretq_s16_f32): Likewise. 13345 (__arm_vreinterpretq_s64_f16): Likewise. 13346 (__arm_vreinterpretq_s64_f32): Likewise. 13347 (__arm_vreinterpretq_s8_f16): Likewise. 13348 (__arm_vreinterpretq_s8_f32): Likewise. 13349 (__arm_vreinterpretq_u16_f16): Likewise. 13350 (__arm_vreinterpretq_u16_f32): Likewise. 13351 (__arm_vreinterpretq_u32_f16): Likewise. 13352 (__arm_vreinterpretq_u32_f32): Likewise. 13353 (__arm_vreinterpretq_u64_f16): Likewise. 13354 (__arm_vreinterpretq_u64_f32): Likewise. 13355 (__arm_vreinterpretq_u8_f16): Likewise. 13356 (__arm_vreinterpretq_u8_f32): Likewise. 13357 (__arm_vreinterpretq_f16_f32): Likewise. 13358 (__arm_vreinterpretq_f16_s16): Likewise. 13359 (__arm_vreinterpretq_f16_s32): Likewise. 13360 (__arm_vreinterpretq_f16_s64): Likewise. 13361 (__arm_vreinterpretq_f16_s8): Likewise. 13362 (__arm_vreinterpretq_f16_u16): Likewise. 13363 (__arm_vreinterpretq_f16_u32): Likewise. 13364 (__arm_vreinterpretq_f16_u64): Likewise. 13365 (__arm_vreinterpretq_f16_u8): Likewise. 13366 (__arm_vreinterpretq_f32_f16): Likewise. 13367 (__arm_vreinterpretq_f32_s16): Likewise. 13368 (__arm_vreinterpretq_f32_s32): Likewise. 13369 (__arm_vreinterpretq_f32_s64): Likewise. 13370 (__arm_vreinterpretq_f32_s8): Likewise. 13371 (__arm_vreinterpretq_f32_u16): Likewise. 13372 (__arm_vreinterpretq_f32_u32): Likewise. 13373 (__arm_vreinterpretq_f32_u64): Likewise. 13374 (__arm_vreinterpretq_f32_u8): Likewise. 13375 (vuninitializedq): Define polymorphic variant. 13376 (vreinterpretq_f16): Likewise. 13377 (vreinterpretq_f32): Likewise. 13378 (vreinterpretq_s16): Likewise. 13379 (vreinterpretq_s32): Likewise. 13380 (vreinterpretq_s64): Likewise. 13381 (vreinterpretq_s8): Likewise. 13382 (vreinterpretq_u16): Likewise. 13383 (vreinterpretq_u32): Likewise. 13384 (vreinterpretq_u64): Likewise. 13385 (vreinterpretq_u8): Likewise. 13386 133872020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13388 Andre Vieira <andre.simoesdiasvieira@arm.com> 13389 Mihail Ionescu <mihail.ionescu@arm.com> 13390 13391 * config/arm/arm_mve.h (vaddq_s8): Define macro. 13392 (vaddq_s16): Likewise. 13393 (vaddq_s32): Likewise. 13394 (vaddq_u8): Likewise. 13395 (vaddq_u16): Likewise. 13396 (vaddq_u32): Likewise. 13397 (vaddq_f16): Likewise. 13398 (vaddq_f32): Likewise. 13399 (__arm_vaddq_s8): Define intrinsic. 13400 (__arm_vaddq_s16): Likewise. 13401 (__arm_vaddq_s32): Likewise. 13402 (__arm_vaddq_u8): Likewise. 13403 (__arm_vaddq_u16): Likewise. 13404 (__arm_vaddq_u32): Likewise. 13405 (__arm_vaddq_f16): Likewise. 13406 (__arm_vaddq_f32): Likewise. 13407 (vaddq): Define polymorphic variant. 13408 * config/arm/iterators.md (VNIM): Define mode iterator for common types 13409 Neon, IWMMXT and MVE. 13410 (VNINOTM): Likewise. 13411 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern. 13412 (mve_vaddq_f<mode>): Define RTL pattern. 13413 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern. 13414 (addv8hf3_neon): Define RTL pattern. 13415 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern 13416 to support MVE. 13417 (addv8hf3): Define standard RTL pattern for MVE and Neon. 13418 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT. 13419 134202020-03-20 Martin Liska <mliska@suse.cz> 13421 13422 PR ipa/94232 13423 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously 13424 build_ref_for_offset function was used and it transforms off to bytes 13425 from bits. 13426 134272020-03-20 Richard Biener <rguenther@suse.de> 13428 13429 PR tree-optimization/94266 13430 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the 13431 type of the underlying object to adjust for the containing 13432 field if available. 13433 134342020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 13435 13436 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... 13437 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. 13438 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. 13439 134402020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 13441 13442 * config/arm/mve.md (mve_mov<mode>): Fix R->R case. 13443 134442020-03-20 Jakub Jelinek <jakub@redhat.com> 13445 13446 PR tree-optimization/94224 13447 * gimple-ssa-store-merging.c 13448 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping 13449 or adjacent INTEGER_CST rhs_code stores as mergeable if they have 13450 different lp_nr. 13451 134522020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> 13453 13454 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. 13455 134562020-03-19 Jan Hubicka <hubicka@ucw.cz> 13457 13458 PR ipa/94202 13459 * cgraph.c (cgraph_node::function_symbol): Fix availability computation. 13460 (cgraph_node::function_or_virtual_thunk_symbol): Likewise. 13461 134622020-03-19 Jan Hubicka <hubicka@ucw.cz> 13463 13464 PR ipa/92372 13465 * cgraphunit.c (process_function_and_variable_attributes): warn 13466 for flatten attribute on alias. 13467 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. 13468 134692020-03-19 Martin Liska <mliska@suse.cz> 13470 13471 * lto-section-in.c: Add ext_symtab. 13472 * lto-streamer-out.c (write_symbol_extension_info): New. 13473 (produce_symtab_extension): New. 13474 (produce_asm_for_decls): Stream also produce_symtab_extension. 13475 * lto-streamer.h (enum lto_section_type): New section. 13476 134772020-03-19 Jakub Jelinek <jakub@redhat.com> 13478 13479 PR tree-optimization/94211 13480 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq 13481 instead of estimate_num_insns for bb_seq (middle_bb). Rename 13482 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust 13483 all uses. 13484 134852020-03-19 Richard Biener <rguenther@suse.de> 13486 13487 PR ipa/94217 13488 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr 13489 and build_ref_for_offset. 13490 134912020-03-19 Richard Biener <rguenther@suse.de> 13492 13493 PR middle-end/94216 13494 * fold-const.c (fold_binary_loc): Avoid using 13495 build_fold_addr_expr when we really want an ADDR_EXPR. 13496 134972020-03-18 Segher Boessenkool <segher@kernel.crashing.org> 13498 13499 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented 13500 aliases for "wa". 13501 135022020-03-12 Richard Sandiford <richard.sandiford@arm.com> 13503 13504 PR rtl-optimization/90275 13505 * cse.c (cse_insn): Delete no-op register moves too. 13506 135072020-03-18 Martin Sebor <msebor@redhat.com> 13508 13509 PR ipa/92799 13510 * cgraphunit.c (process_function_and_variable_attributes): Also 13511 complain about weakref function definitions and drop all effects 13512 of the attribute. 13513 135142020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 13515 Mihail Ionescu <mihail.ionescu@arm.com> 13516 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13517 13518 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. 13519 (vstrdq_scatter_base_p_u64): Likewise. 13520 (vstrdq_scatter_base_s64): Likewise. 13521 (vstrdq_scatter_base_u64): Likewise. 13522 (vstrdq_scatter_offset_p_s64): Likewise. 13523 (vstrdq_scatter_offset_p_u64): Likewise. 13524 (vstrdq_scatter_offset_s64): Likewise. 13525 (vstrdq_scatter_offset_u64): Likewise. 13526 (vstrdq_scatter_shifted_offset_p_s64): Likewise. 13527 (vstrdq_scatter_shifted_offset_p_u64): Likewise. 13528 (vstrdq_scatter_shifted_offset_s64): Likewise. 13529 (vstrdq_scatter_shifted_offset_u64): Likewise. 13530 (vstrhq_scatter_offset_f16): Likewise. 13531 (vstrhq_scatter_offset_p_f16): Likewise. 13532 (vstrhq_scatter_shifted_offset_f16): Likewise. 13533 (vstrhq_scatter_shifted_offset_p_f16): Likewise. 13534 (vstrwq_scatter_base_f32): Likewise. 13535 (vstrwq_scatter_base_p_f32): Likewise. 13536 (vstrwq_scatter_offset_f32): Likewise. 13537 (vstrwq_scatter_offset_p_f32): Likewise. 13538 (vstrwq_scatter_offset_p_s32): Likewise. 13539 (vstrwq_scatter_offset_p_u32): Likewise. 13540 (vstrwq_scatter_offset_s32): Likewise. 13541 (vstrwq_scatter_offset_u32): Likewise. 13542 (vstrwq_scatter_shifted_offset_f32): Likewise. 13543 (vstrwq_scatter_shifted_offset_p_f32): Likewise. 13544 (vstrwq_scatter_shifted_offset_p_s32): Likewise. 13545 (vstrwq_scatter_shifted_offset_p_u32): Likewise. 13546 (vstrwq_scatter_shifted_offset_s32): Likewise. 13547 (vstrwq_scatter_shifted_offset_u32): Likewise. 13548 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. 13549 (__arm_vstrdq_scatter_base_p_u64): Likewise. 13550 (__arm_vstrdq_scatter_base_s64): Likewise. 13551 (__arm_vstrdq_scatter_base_u64): Likewise. 13552 (__arm_vstrdq_scatter_offset_p_s64): Likewise. 13553 (__arm_vstrdq_scatter_offset_p_u64): Likewise. 13554 (__arm_vstrdq_scatter_offset_s64): Likewise. 13555 (__arm_vstrdq_scatter_offset_u64): Likewise. 13556 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. 13557 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. 13558 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. 13559 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. 13560 (__arm_vstrwq_scatter_offset_p_s32): Likewise. 13561 (__arm_vstrwq_scatter_offset_p_u32): Likewise. 13562 (__arm_vstrwq_scatter_offset_s32): Likewise. 13563 (__arm_vstrwq_scatter_offset_u32): Likewise. 13564 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. 13565 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. 13566 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. 13567 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. 13568 (__arm_vstrhq_scatter_offset_f16): Likewise. 13569 (__arm_vstrhq_scatter_offset_p_f16): Likewise. 13570 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. 13571 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. 13572 (__arm_vstrwq_scatter_base_f32): Likewise. 13573 (__arm_vstrwq_scatter_base_p_f32): Likewise. 13574 (__arm_vstrwq_scatter_offset_f32): Likewise. 13575 (__arm_vstrwq_scatter_offset_p_f32): Likewise. 13576 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. 13577 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. 13578 (vstrhq_scatter_offset): Define polymorphic variant. 13579 (vstrhq_scatter_offset_p): Likewise. 13580 (vstrhq_scatter_shifted_offset): Likewise. 13581 (vstrhq_scatter_shifted_offset_p): Likewise. 13582 (vstrwq_scatter_base): Likewise. 13583 (vstrwq_scatter_base_p): Likewise. 13584 (vstrwq_scatter_offset): Likewise. 13585 (vstrwq_scatter_offset_p): Likewise. 13586 (vstrwq_scatter_shifted_offset): Likewise. 13587 (vstrwq_scatter_shifted_offset_p): Likewise. 13588 (vstrdq_scatter_base_p): Likewise. 13589 (vstrdq_scatter_base): Likewise. 13590 (vstrdq_scatter_offset_p): Likewise. 13591 (vstrdq_scatter_offset): Likewise. 13592 (vstrdq_scatter_shifted_offset_p): Likewise. 13593 (vstrdq_scatter_shifted_offset): Likewise. 13594 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. 13595 (STRSBS_P): Likewise. 13596 (STRSBU): Likewise. 13597 (STRSBU_P): Likewise. 13598 (STRSS): Likewise. 13599 (STRSS_P): Likewise. 13600 (STRSU): Likewise. 13601 (STRSU_P): Likewise. 13602 * config/arm/constraints.md (Ri): Define. 13603 * config/arm/mve.md (VSTRDSBQ): Define iterator. 13604 (VSTRDSOQ): Likewise. 13605 (VSTRDSSOQ): Likewise. 13606 (VSTRWSOQ): Likewise. 13607 (VSTRWSSOQ): Likewise. 13608 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern. 13609 (mve_vstrdq_scatter_base_<supf>v2di): Likewise. 13610 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise. 13611 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise. 13612 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise. 13613 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise. 13614 (mve_vstrhq_scatter_offset_fv8hf): Likewise. 13615 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. 13616 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. 13617 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. 13618 (mve_vstrwq_scatter_base_fv4sf): Likewise. 13619 (mve_vstrwq_scatter_base_p_fv4sf): Likewise. 13620 (mve_vstrwq_scatter_offset_fv4sf): Likewise. 13621 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. 13622 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise. 13623 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise. 13624 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. 13625 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. 13626 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise. 13627 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise. 13628 * config/arm/predicates.md (Ri): Define predicate to check immediate 13629 is the range +/-1016 and multiple of 8. 13630 136312020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 13632 Mihail Ionescu <mihail.ionescu@arm.com> 13633 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13634 13635 * config/arm/arm_mve.h (vst1q_f32): Define macro. 13636 (vst1q_f16): Likewise. 13637 (vst1q_s8): Likewise. 13638 (vst1q_s32): Likewise. 13639 (vst1q_s16): Likewise. 13640 (vst1q_u8): Likewise. 13641 (vst1q_u32): Likewise. 13642 (vst1q_u16): Likewise. 13643 (vstrhq_f16): Likewise. 13644 (vstrhq_scatter_offset_s32): Likewise. 13645 (vstrhq_scatter_offset_s16): Likewise. 13646 (vstrhq_scatter_offset_u32): Likewise. 13647 (vstrhq_scatter_offset_u16): Likewise. 13648 (vstrhq_scatter_offset_p_s32): Likewise. 13649 (vstrhq_scatter_offset_p_s16): Likewise. 13650 (vstrhq_scatter_offset_p_u32): Likewise. 13651 (vstrhq_scatter_offset_p_u16): Likewise. 13652 (vstrhq_scatter_shifted_offset_s32): Likewise. 13653 (vstrhq_scatter_shifted_offset_s16): Likewise. 13654 (vstrhq_scatter_shifted_offset_u32): Likewise. 13655 (vstrhq_scatter_shifted_offset_u16): Likewise. 13656 (vstrhq_scatter_shifted_offset_p_s32): Likewise. 13657 (vstrhq_scatter_shifted_offset_p_s16): Likewise. 13658 (vstrhq_scatter_shifted_offset_p_u32): Likewise. 13659 (vstrhq_scatter_shifted_offset_p_u16): Likewise. 13660 (vstrhq_s32): Likewise. 13661 (vstrhq_s16): Likewise. 13662 (vstrhq_u32): Likewise. 13663 (vstrhq_u16): Likewise. 13664 (vstrhq_p_f16): Likewise. 13665 (vstrhq_p_s32): Likewise. 13666 (vstrhq_p_s16): Likewise. 13667 (vstrhq_p_u32): Likewise. 13668 (vstrhq_p_u16): Likewise. 13669 (vstrwq_f32): Likewise. 13670 (vstrwq_s32): Likewise. 13671 (vstrwq_u32): Likewise. 13672 (vstrwq_p_f32): Likewise. 13673 (vstrwq_p_s32): Likewise. 13674 (vstrwq_p_u32): Likewise. 13675 (__arm_vst1q_s8): Define intrinsic. 13676 (__arm_vst1q_s32): Likewise. 13677 (__arm_vst1q_s16): Likewise. 13678 (__arm_vst1q_u8): Likewise. 13679 (__arm_vst1q_u32): Likewise. 13680 (__arm_vst1q_u16): Likewise. 13681 (__arm_vstrhq_scatter_offset_s32): Likewise. 13682 (__arm_vstrhq_scatter_offset_s16): Likewise. 13683 (__arm_vstrhq_scatter_offset_u32): Likewise. 13684 (__arm_vstrhq_scatter_offset_u16): Likewise. 13685 (__arm_vstrhq_scatter_offset_p_s32): Likewise. 13686 (__arm_vstrhq_scatter_offset_p_s16): Likewise. 13687 (__arm_vstrhq_scatter_offset_p_u32): Likewise. 13688 (__arm_vstrhq_scatter_offset_p_u16): Likewise. 13689 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. 13690 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. 13691 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. 13692 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. 13693 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. 13694 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. 13695 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. 13696 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. 13697 (__arm_vstrhq_s32): Likewise. 13698 (__arm_vstrhq_s16): Likewise. 13699 (__arm_vstrhq_u32): Likewise. 13700 (__arm_vstrhq_u16): Likewise. 13701 (__arm_vstrhq_p_s32): Likewise. 13702 (__arm_vstrhq_p_s16): Likewise. 13703 (__arm_vstrhq_p_u32): Likewise. 13704 (__arm_vstrhq_p_u16): Likewise. 13705 (__arm_vstrwq_s32): Likewise. 13706 (__arm_vstrwq_u32): Likewise. 13707 (__arm_vstrwq_p_s32): Likewise. 13708 (__arm_vstrwq_p_u32): Likewise. 13709 (__arm_vstrwq_p_f32): Likewise. 13710 (__arm_vstrwq_f32): Likewise. 13711 (__arm_vst1q_f32): Likewise. 13712 (__arm_vst1q_f16): Likewise. 13713 (__arm_vstrhq_f16): Likewise. 13714 (__arm_vstrhq_p_f16): Likewise. 13715 (vst1q): Define polymorphic variant. 13716 (vstrhq): Likewise. 13717 (vstrhq_p): Likewise. 13718 (vstrhq_scatter_offset_p): Likewise. 13719 (vstrhq_scatter_offset): Likewise. 13720 (vstrhq_scatter_shifted_offset_p): Likewise. 13721 (vstrhq_scatter_shifted_offset): Likewise. 13722 (vstrwq_p): Likewise. 13723 (vstrwq): Likewise. 13724 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. 13725 (STRS_P): Likewise. 13726 (STRSS): Likewise. 13727 (STRSS_P): Likewise. 13728 (STRSU): Likewise. 13729 (STRSU_P): Likewise. 13730 (STRU): Likewise. 13731 (STRU_P): Likewise. 13732 * config/arm/mve.md (VST1Q): Define iterator. 13733 (VSTRHSOQ): Likewise. 13734 (VSTRHSSOQ): Likewise. 13735 (VSTRHQ): Likewise. 13736 (VSTRWQ): Likewise. 13737 (mve_vstrhq_fv8hf): Define RTL pattern. 13738 (mve_vstrhq_p_fv8hf): Likewise. 13739 (mve_vstrhq_p_<supf><mode>): Likewise. 13740 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise. 13741 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise. 13742 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise. 13743 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise. 13744 (mve_vstrhq_<supf><mode>): Likewise. 13745 (mve_vstrwq_fv4sf): Likewise. 13746 (mve_vstrwq_p_fv4sf): Likewise. 13747 (mve_vstrwq_p_<supf>v4si): Likewise. 13748 (mve_vstrwq_<supf>v4si): Likewise. 13749 (mve_vst1q_f<mode>): Define expand. 13750 (mve_vst1q_<supf><mode>): Likewise. 13751 137522020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 13753 Mihail Ionescu <mihail.ionescu@arm.com> 13754 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13755 13756 * config/arm/arm_mve.h (vld1q_s8): Define macro. 13757 (vld1q_s32): Likewise. 13758 (vld1q_s16): Likewise. 13759 (vld1q_u8): Likewise. 13760 (vld1q_u32): Likewise. 13761 (vld1q_u16): Likewise. 13762 (vldrhq_gather_offset_s32): Likewise. 13763 (vldrhq_gather_offset_s16): Likewise. 13764 (vldrhq_gather_offset_u32): Likewise. 13765 (vldrhq_gather_offset_u16): Likewise. 13766 (vldrhq_gather_offset_z_s32): Likewise. 13767 (vldrhq_gather_offset_z_s16): Likewise. 13768 (vldrhq_gather_offset_z_u32): Likewise. 13769 (vldrhq_gather_offset_z_u16): Likewise. 13770 (vldrhq_gather_shifted_offset_s32): Likewise. 13771 (vldrhq_gather_shifted_offset_s16): Likewise. 13772 (vldrhq_gather_shifted_offset_u32): Likewise. 13773 (vldrhq_gather_shifted_offset_u16): Likewise. 13774 (vldrhq_gather_shifted_offset_z_s32): Likewise. 13775 (vldrhq_gather_shifted_offset_z_s16): Likewise. 13776 (vldrhq_gather_shifted_offset_z_u32): Likewise. 13777 (vldrhq_gather_shifted_offset_z_u16): Likewise. 13778 (vldrhq_s32): Likewise. 13779 (vldrhq_s16): Likewise. 13780 (vldrhq_u32): Likewise. 13781 (vldrhq_u16): Likewise. 13782 (vldrhq_z_s32): Likewise. 13783 (vldrhq_z_s16): Likewise. 13784 (vldrhq_z_u32): Likewise. 13785 (vldrhq_z_u16): Likewise. 13786 (vldrwq_s32): Likewise. 13787 (vldrwq_u32): Likewise. 13788 (vldrwq_z_s32): Likewise. 13789 (vldrwq_z_u32): Likewise. 13790 (vld1q_f32): Likewise. 13791 (vld1q_f16): Likewise. 13792 (vldrhq_f16): Likewise. 13793 (vldrhq_z_f16): Likewise. 13794 (vldrwq_f32): Likewise. 13795 (vldrwq_z_f32): Likewise. 13796 (__arm_vld1q_s8): Define intrinsic. 13797 (__arm_vld1q_s32): Likewise. 13798 (__arm_vld1q_s16): Likewise. 13799 (__arm_vld1q_u8): Likewise. 13800 (__arm_vld1q_u32): Likewise. 13801 (__arm_vld1q_u16): Likewise. 13802 (__arm_vldrhq_gather_offset_s32): Likewise. 13803 (__arm_vldrhq_gather_offset_s16): Likewise. 13804 (__arm_vldrhq_gather_offset_u32): Likewise. 13805 (__arm_vldrhq_gather_offset_u16): Likewise. 13806 (__arm_vldrhq_gather_offset_z_s32): Likewise. 13807 (__arm_vldrhq_gather_offset_z_s16): Likewise. 13808 (__arm_vldrhq_gather_offset_z_u32): Likewise. 13809 (__arm_vldrhq_gather_offset_z_u16): Likewise. 13810 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 13811 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 13812 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 13813 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 13814 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 13815 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 13816 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 13817 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 13818 (__arm_vldrhq_s32): Likewise. 13819 (__arm_vldrhq_s16): Likewise. 13820 (__arm_vldrhq_u32): Likewise. 13821 (__arm_vldrhq_u16): Likewise. 13822 (__arm_vldrhq_z_s32): Likewise. 13823 (__arm_vldrhq_z_s16): Likewise. 13824 (__arm_vldrhq_z_u32): Likewise. 13825 (__arm_vldrhq_z_u16): Likewise. 13826 (__arm_vldrwq_s32): Likewise. 13827 (__arm_vldrwq_u32): Likewise. 13828 (__arm_vldrwq_z_s32): Likewise. 13829 (__arm_vldrwq_z_u32): Likewise. 13830 (__arm_vld1q_f32): Likewise. 13831 (__arm_vld1q_f16): Likewise. 13832 (__arm_vldrwq_f32): Likewise. 13833 (__arm_vldrwq_z_f32): Likewise. 13834 (__arm_vldrhq_z_f16): Likewise. 13835 (__arm_vldrhq_f16): Likewise. 13836 (vld1q): Define polymorphic variant. 13837 (vldrhq_gather_offset): Likewise. 13838 (vldrhq_gather_offset_z): Likewise. 13839 (vldrhq_gather_shifted_offset): Likewise. 13840 (vldrhq_gather_shifted_offset_z): Likewise. 13841 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. 13842 (LDRS): Likewise. 13843 (LDRU_Z): Likewise. 13844 (LDRS_Z): Likewise. 13845 (LDRGU_Z): Likewise. 13846 (LDRGU): Likewise. 13847 (LDRGS_Z): Likewise. 13848 (LDRGS): Likewise. 13849 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. 13850 (V_sz_elem1): Likewise. 13851 (VLD1Q): Define iterator. 13852 (VLDRHGOQ): Likewise. 13853 (VLDRHGSOQ): Likewise. 13854 (VLDRHQ): Likewise. 13855 (VLDRWQ): Likewise. 13856 (mve_vldrhq_fv8hf): Define RTL pattern. 13857 (mve_vldrhq_gather_offset_<supf><mode>): Likewise. 13858 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. 13859 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. 13860 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. 13861 (mve_vldrhq_<supf><mode>): Likewise. 13862 (mve_vldrhq_z_fv8hf): Likewise. 13863 (mve_vldrhq_z_<supf><mode>): Likewise. 13864 (mve_vldrwq_fv4sf): Likewise. 13865 (mve_vldrwq_<supf>v4si): Likewise. 13866 (mve_vldrwq_z_fv4sf): Likewise. 13867 (mve_vldrwq_z_<supf>v4si): Likewise. 13868 (mve_vld1q_f<mode>): Define RTL expand pattern. 13869 (mve_vld1q_<supf><mode>): Likewise. 13870 138712020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 13872 Mihail Ionescu <mihail.ionescu@arm.com> 13873 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13874 13875 * config/arm/arm_mve.h (vld1q_s8): Define macro. 13876 (vld1q_s32): Likewise. 13877 (vld1q_s16): Likewise. 13878 (vld1q_u8): Likewise. 13879 (vld1q_u32): Likewise. 13880 (vld1q_u16): Likewise. 13881 (vldrhq_gather_offset_s32): Likewise. 13882 (vldrhq_gather_offset_s16): Likewise. 13883 (vldrhq_gather_offset_u32): Likewise. 13884 (vldrhq_gather_offset_u16): Likewise. 13885 (vldrhq_gather_offset_z_s32): Likewise. 13886 (vldrhq_gather_offset_z_s16): Likewise. 13887 (vldrhq_gather_offset_z_u32): Likewise. 13888 (vldrhq_gather_offset_z_u16): Likewise. 13889 (vldrhq_gather_shifted_offset_s32): Likewise. 13890 (vldrhq_gather_shifted_offset_s16): Likewise. 13891 (vldrhq_gather_shifted_offset_u32): Likewise. 13892 (vldrhq_gather_shifted_offset_u16): Likewise. 13893 (vldrhq_gather_shifted_offset_z_s32): Likewise. 13894 (vldrhq_gather_shifted_offset_z_s16): Likewise. 13895 (vldrhq_gather_shifted_offset_z_u32): Likewise. 13896 (vldrhq_gather_shifted_offset_z_u16): Likewise. 13897 (vldrhq_s32): Likewise. 13898 (vldrhq_s16): Likewise. 13899 (vldrhq_u32): Likewise. 13900 (vldrhq_u16): Likewise. 13901 (vldrhq_z_s32): Likewise. 13902 (vldrhq_z_s16): Likewise. 13903 (vldrhq_z_u32): Likewise. 13904 (vldrhq_z_u16): Likewise. 13905 (vldrwq_s32): Likewise. 13906 (vldrwq_u32): Likewise. 13907 (vldrwq_z_s32): Likewise. 13908 (vldrwq_z_u32): Likewise. 13909 (vld1q_f32): Likewise. 13910 (vld1q_f16): Likewise. 13911 (vldrhq_f16): Likewise. 13912 (vldrhq_z_f16): Likewise. 13913 (vldrwq_f32): Likewise. 13914 (vldrwq_z_f32): Likewise. 13915 (__arm_vld1q_s8): Define intrinsic. 13916 (__arm_vld1q_s32): Likewise. 13917 (__arm_vld1q_s16): Likewise. 13918 (__arm_vld1q_u8): Likewise. 13919 (__arm_vld1q_u32): Likewise. 13920 (__arm_vld1q_u16): Likewise. 13921 (__arm_vldrhq_gather_offset_s32): Likewise. 13922 (__arm_vldrhq_gather_offset_s16): Likewise. 13923 (__arm_vldrhq_gather_offset_u32): Likewise. 13924 (__arm_vldrhq_gather_offset_u16): Likewise. 13925 (__arm_vldrhq_gather_offset_z_s32): Likewise. 13926 (__arm_vldrhq_gather_offset_z_s16): Likewise. 13927 (__arm_vldrhq_gather_offset_z_u32): Likewise. 13928 (__arm_vldrhq_gather_offset_z_u16): Likewise. 13929 (__arm_vldrhq_gather_shifted_offset_s32): Likewise. 13930 (__arm_vldrhq_gather_shifted_offset_s16): Likewise. 13931 (__arm_vldrhq_gather_shifted_offset_u32): Likewise. 13932 (__arm_vldrhq_gather_shifted_offset_u16): Likewise. 13933 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. 13934 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. 13935 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. 13936 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. 13937 (__arm_vldrhq_s32): Likewise. 13938 (__arm_vldrhq_s16): Likewise. 13939 (__arm_vldrhq_u32): Likewise. 13940 (__arm_vldrhq_u16): Likewise. 13941 (__arm_vldrhq_z_s32): Likewise. 13942 (__arm_vldrhq_z_s16): Likewise. 13943 (__arm_vldrhq_z_u32): Likewise. 13944 (__arm_vldrhq_z_u16): Likewise. 13945 (__arm_vldrwq_s32): Likewise. 13946 (__arm_vldrwq_u32): Likewise. 13947 (__arm_vldrwq_z_s32): Likewise. 13948 (__arm_vldrwq_z_u32): Likewise. 13949 (__arm_vld1q_f32): Likewise. 13950 (__arm_vld1q_f16): Likewise. 13951 (__arm_vldrwq_f32): Likewise. 13952 (__arm_vldrwq_z_f32): Likewise. 13953 (__arm_vldrhq_z_f16): Likewise. 13954 (__arm_vldrhq_f16): Likewise. 13955 (vld1q): Define polymorphic variant. 13956 (vldrhq_gather_offset): Likewise. 13957 (vldrhq_gather_offset_z): Likewise. 13958 (vldrhq_gather_shifted_offset): Likewise. 13959 (vldrhq_gather_shifted_offset_z): Likewise. 13960 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. 13961 (LDRS): Likewise. 13962 (LDRU_Z): Likewise. 13963 (LDRS_Z): Likewise. 13964 (LDRGU_Z): Likewise. 13965 (LDRGU): Likewise. 13966 (LDRGS_Z): Likewise. 13967 (LDRGS): Likewise. 13968 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. 13969 (V_sz_elem1): Likewise. 13970 (VLD1Q): Define iterator. 13971 (VLDRHGOQ): Likewise. 13972 (VLDRHGSOQ): Likewise. 13973 (VLDRHQ): Likewise. 13974 (VLDRWQ): Likewise. 13975 (mve_vldrhq_fv8hf): Define RTL pattern. 13976 (mve_vldrhq_gather_offset_<supf><mode>): Likewise. 13977 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. 13978 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. 13979 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. 13980 (mve_vldrhq_<supf><mode>): Likewise. 13981 (mve_vldrhq_z_fv8hf): Likewise. 13982 (mve_vldrhq_z_<supf><mode>): Likewise. 13983 (mve_vldrwq_fv4sf): Likewise. 13984 (mve_vldrwq_<supf>v4si): Likewise. 13985 (mve_vldrwq_z_fv4sf): Likewise. 13986 (mve_vldrwq_z_<supf>v4si): Likewise. 13987 (mve_vld1q_f<mode>): Define RTL expand pattern. 13988 (mve_vld1q_<supf><mode>): Likewise. 13989 139902020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 13991 Mihail Ionescu <mihail.ionescu@arm.com> 13992 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 13993 13994 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin 13995 qualifier. 13996 (LDRGBU_Z_QUALIFIERS): Likewise. 13997 (LDRGS_Z_QUALIFIERS): Likewise. 13998 (LDRGU_Z_QUALIFIERS): Likewise. 13999 (LDRS_Z_QUALIFIERS): Likewise. 14000 (LDRU_Z_QUALIFIERS): Likewise. 14001 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. 14002 (vldrbq_gather_offset_z_u8): Likewise. 14003 (vldrbq_gather_offset_z_s32): Likewise. 14004 (vldrbq_gather_offset_z_u16): Likewise. 14005 (vldrbq_gather_offset_z_u32): Likewise. 14006 (vldrbq_gather_offset_z_s8): Likewise. 14007 (vldrbq_z_s16): Likewise. 14008 (vldrbq_z_u8): Likewise. 14009 (vldrbq_z_s8): Likewise. 14010 (vldrbq_z_s32): Likewise. 14011 (vldrbq_z_u16): Likewise. 14012 (vldrbq_z_u32): Likewise. 14013 (vldrwq_gather_base_z_u32): Likewise. 14014 (vldrwq_gather_base_z_s32): Likewise. 14015 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. 14016 (__arm_vldrbq_gather_offset_z_s32): Likewise. 14017 (__arm_vldrbq_gather_offset_z_s16): Likewise. 14018 (__arm_vldrbq_gather_offset_z_u8): Likewise. 14019 (__arm_vldrbq_gather_offset_z_u32): Likewise. 14020 (__arm_vldrbq_gather_offset_z_u16): Likewise. 14021 (__arm_vldrbq_z_s8): Likewise. 14022 (__arm_vldrbq_z_s32): Likewise. 14023 (__arm_vldrbq_z_s16): Likewise. 14024 (__arm_vldrbq_z_u8): Likewise. 14025 (__arm_vldrbq_z_u32): Likewise. 14026 (__arm_vldrbq_z_u16): Likewise. 14027 (__arm_vldrwq_gather_base_z_s32): Likewise. 14028 (__arm_vldrwq_gather_base_z_u32): Likewise. 14029 (vldrbq_gather_offset_z): Define polymorphic variant. 14030 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin 14031 qualifier. 14032 (LDRGBU_Z_QUALIFIERS): Likewise. 14033 (LDRGS_Z_QUALIFIERS): Likewise. 14034 (LDRGU_Z_QUALIFIERS): Likewise. 14035 (LDRS_Z_QUALIFIERS): Likewise. 14036 (LDRU_Z_QUALIFIERS): Likewise. 14037 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define 14038 RTL pattern. 14039 (mve_vldrbq_z_<supf><mode>): Likewise. 14040 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise. 14041 140422020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14043 Mihail Ionescu <mihail.ionescu@arm.com> 14044 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14045 14046 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin 14047 qualifier. 14048 (STRU_P_QUALIFIERS): Likewise. 14049 (STRSU_P_QUALIFIERS): Likewise. 14050 (STRSS_P_QUALIFIERS): Likewise. 14051 (STRSBS_P_QUALIFIERS): Likewise. 14052 (STRSBU_P_QUALIFIERS): Likewise. 14053 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. 14054 (vstrbq_p_s32): Likewise. 14055 (vstrbq_p_s16): Likewise. 14056 (vstrbq_p_u8): Likewise. 14057 (vstrbq_p_u32): Likewise. 14058 (vstrbq_p_u16): Likewise. 14059 (vstrbq_scatter_offset_p_s8): Likewise. 14060 (vstrbq_scatter_offset_p_s32): Likewise. 14061 (vstrbq_scatter_offset_p_s16): Likewise. 14062 (vstrbq_scatter_offset_p_u8): Likewise. 14063 (vstrbq_scatter_offset_p_u32): Likewise. 14064 (vstrbq_scatter_offset_p_u16): Likewise. 14065 (vstrwq_scatter_base_p_s32): Likewise. 14066 (vstrwq_scatter_base_p_u32): Likewise. 14067 (__arm_vstrbq_p_s8): Define intrinsic. 14068 (__arm_vstrbq_p_s32): Likewise. 14069 (__arm_vstrbq_p_s16): Likewise. 14070 (__arm_vstrbq_p_u8): Likewise. 14071 (__arm_vstrbq_p_u32): Likewise. 14072 (__arm_vstrbq_p_u16): Likewise. 14073 (__arm_vstrbq_scatter_offset_p_s8): Likewise. 14074 (__arm_vstrbq_scatter_offset_p_s32): Likewise. 14075 (__arm_vstrbq_scatter_offset_p_s16): Likewise. 14076 (__arm_vstrbq_scatter_offset_p_u8): Likewise. 14077 (__arm_vstrbq_scatter_offset_p_u32): Likewise. 14078 (__arm_vstrbq_scatter_offset_p_u16): Likewise. 14079 (__arm_vstrwq_scatter_base_p_s32): Likewise. 14080 (__arm_vstrwq_scatter_base_p_u32): Likewise. 14081 (vstrbq_p): Define polymorphic variant. 14082 (vstrbq_scatter_offset_p): Likewise. 14083 (vstrwq_scatter_base_p): Likewise. 14084 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin 14085 qualifier. 14086 (STRU_P_QUALIFIERS): Likewise. 14087 (STRSU_P_QUALIFIERS): Likewise. 14088 (STRSS_P_QUALIFIERS): Likewise. 14089 (STRSBS_P_QUALIFIERS): Likewise. 14090 (STRSBU_P_QUALIFIERS): Likewise. 14091 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define 14092 RTL pattern. 14093 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise. 14094 (mve_vstrbq_p_<supf><mode>): Likewise. 14095 140962020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14097 Mihail Ionescu <mihail.ionescu@arm.com> 14098 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14099 14100 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin 14101 qualifier. 14102 (LDRGS_QUALIFIERS): Likewise. 14103 (LDRS_QUALIFIERS): Likewise. 14104 (LDRU_QUALIFIERS): Likewise. 14105 (LDRGBS_QUALIFIERS): Likewise. 14106 (LDRGBU_QUALIFIERS): Likewise. 14107 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. 14108 (vldrbq_gather_offset_s8): Likewise. 14109 (vldrbq_s8): Likewise. 14110 (vldrbq_u8): Likewise. 14111 (vldrbq_gather_offset_u16): Likewise. 14112 (vldrbq_gather_offset_s16): Likewise. 14113 (vldrbq_s16): Likewise. 14114 (vldrbq_u16): Likewise. 14115 (vldrbq_gather_offset_u32): Likewise. 14116 (vldrbq_gather_offset_s32): Likewise. 14117 (vldrbq_s32): Likewise. 14118 (vldrbq_u32): Likewise. 14119 (vldrwq_gather_base_s32): Likewise. 14120 (vldrwq_gather_base_u32): Likewise. 14121 (__arm_vldrbq_gather_offset_u8): Define intrinsic. 14122 (__arm_vldrbq_gather_offset_s8): Likewise. 14123 (__arm_vldrbq_s8): Likewise. 14124 (__arm_vldrbq_u8): Likewise. 14125 (__arm_vldrbq_gather_offset_u16): Likewise. 14126 (__arm_vldrbq_gather_offset_s16): Likewise. 14127 (__arm_vldrbq_s16): Likewise. 14128 (__arm_vldrbq_u16): Likewise. 14129 (__arm_vldrbq_gather_offset_u32): Likewise. 14130 (__arm_vldrbq_gather_offset_s32): Likewise. 14131 (__arm_vldrbq_s32): Likewise. 14132 (__arm_vldrbq_u32): Likewise. 14133 (__arm_vldrwq_gather_base_s32): Likewise. 14134 (__arm_vldrwq_gather_base_u32): Likewise. 14135 (vldrbq_gather_offset): Define polymorphic variant. 14136 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin 14137 qualifier. 14138 (LDRGS_QUALIFIERS): Likewise. 14139 (LDRS_QUALIFIERS): Likewise. 14140 (LDRU_QUALIFIERS): Likewise. 14141 (LDRGBS_QUALIFIERS): Likewise. 14142 (LDRGBU_QUALIFIERS): Likewise. 14143 * config/arm/mve.md (VLDRBGOQ): Define iterator. 14144 (VLDRBQ): Likewise. 14145 (VLDRWGBQ): Likewise. 14146 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern. 14147 (mve_vldrbq_<supf><mode>): Likewise. 14148 (mve_vldrwq_gather_base_<supf>v4si): Likewise. 14149 141502020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14151 Mihail Ionescu <mihail.ionescu@arm.com> 14152 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14153 14154 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. 14155 (STRU_QUALIFIERS): Likewise. 14156 (STRSS_QUALIFIERS): Likewise. 14157 (STRSU_QUALIFIERS): Likewise. 14158 (STRSBS_QUALIFIERS): Likewise. 14159 (STRSBU_QUALIFIERS): Likewise. 14160 * config/arm/arm_mve.h (vstrbq_s8): Define macro. 14161 (vstrbq_u8): Likewise. 14162 (vstrbq_u16): Likewise. 14163 (vstrbq_scatter_offset_s8): Likewise. 14164 (vstrbq_scatter_offset_u8): Likewise. 14165 (vstrbq_scatter_offset_u16): Likewise. 14166 (vstrbq_s16): Likewise. 14167 (vstrbq_u32): Likewise. 14168 (vstrbq_scatter_offset_s16): Likewise. 14169 (vstrbq_scatter_offset_u32): Likewise. 14170 (vstrbq_s32): Likewise. 14171 (vstrbq_scatter_offset_s32): Likewise. 14172 (vstrwq_scatter_base_s32): Likewise. 14173 (vstrwq_scatter_base_u32): Likewise. 14174 (__arm_vstrbq_scatter_offset_s8): Define intrinsic. 14175 (__arm_vstrbq_scatter_offset_s32): Likewise. 14176 (__arm_vstrbq_scatter_offset_s16): Likewise. 14177 (__arm_vstrbq_scatter_offset_u8): Likewise. 14178 (__arm_vstrbq_scatter_offset_u32): Likewise. 14179 (__arm_vstrbq_scatter_offset_u16): Likewise. 14180 (__arm_vstrbq_s8): Likewise. 14181 (__arm_vstrbq_s32): Likewise. 14182 (__arm_vstrbq_s16): Likewise. 14183 (__arm_vstrbq_u8): Likewise. 14184 (__arm_vstrbq_u32): Likewise. 14185 (__arm_vstrbq_u16): Likewise. 14186 (__arm_vstrwq_scatter_base_s32): Likewise. 14187 (__arm_vstrwq_scatter_base_u32): Likewise. 14188 (vstrbq): Define polymorphic variant. 14189 (vstrbq_scatter_offset): Likewise. 14190 (vstrwq_scatter_base): Likewise. 14191 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin 14192 qualifier. 14193 (STRU_QUALIFIERS): Likewise. 14194 (STRSS_QUALIFIERS): Likewise. 14195 (STRSU_QUALIFIERS): Likewise. 14196 (STRSBS_QUALIFIERS): Likewise. 14197 (STRSBU_QUALIFIERS): Likewise. 14198 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. 14199 (VSTRWSBQ): Define iterators. 14200 (VSTRBSOQ): Likewise. 14201 (VSTRBQ): Likewise. 14202 (mve_vstrbq_<supf><mode>): Define RTL pattern. 14203 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise. 14204 (mve_vstrwq_scatter_base_<supf>v4si): Likewise. 14205 142062020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14207 Mihail Ionescu <mihail.ionescu@arm.com> 14208 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14209 14210 * config/arm/arm_mve.h (vabdq_m_f32): Define macro. 14211 (vabdq_m_f16): Likewise. 14212 (vaddq_m_f32): Likewise. 14213 (vaddq_m_f16): Likewise. 14214 (vaddq_m_n_f32): Likewise. 14215 (vaddq_m_n_f16): Likewise. 14216 (vandq_m_f32): Likewise. 14217 (vandq_m_f16): Likewise. 14218 (vbicq_m_f32): Likewise. 14219 (vbicq_m_f16): Likewise. 14220 (vbrsrq_m_n_f32): Likewise. 14221 (vbrsrq_m_n_f16): Likewise. 14222 (vcaddq_rot270_m_f32): Likewise. 14223 (vcaddq_rot270_m_f16): Likewise. 14224 (vcaddq_rot90_m_f32): Likewise. 14225 (vcaddq_rot90_m_f16): Likewise. 14226 (vcmlaq_m_f32): Likewise. 14227 (vcmlaq_m_f16): Likewise. 14228 (vcmlaq_rot180_m_f32): Likewise. 14229 (vcmlaq_rot180_m_f16): Likewise. 14230 (vcmlaq_rot270_m_f32): Likewise. 14231 (vcmlaq_rot270_m_f16): Likewise. 14232 (vcmlaq_rot90_m_f32): Likewise. 14233 (vcmlaq_rot90_m_f16): Likewise. 14234 (vcmulq_m_f32): Likewise. 14235 (vcmulq_m_f16): Likewise. 14236 (vcmulq_rot180_m_f32): Likewise. 14237 (vcmulq_rot180_m_f16): Likewise. 14238 (vcmulq_rot270_m_f32): Likewise. 14239 (vcmulq_rot270_m_f16): Likewise. 14240 (vcmulq_rot90_m_f32): Likewise. 14241 (vcmulq_rot90_m_f16): Likewise. 14242 (vcvtq_m_n_s32_f32): Likewise. 14243 (vcvtq_m_n_s16_f16): Likewise. 14244 (vcvtq_m_n_u32_f32): Likewise. 14245 (vcvtq_m_n_u16_f16): Likewise. 14246 (veorq_m_f32): Likewise. 14247 (veorq_m_f16): Likewise. 14248 (vfmaq_m_f32): Likewise. 14249 (vfmaq_m_f16): Likewise. 14250 (vfmaq_m_n_f32): Likewise. 14251 (vfmaq_m_n_f16): Likewise. 14252 (vfmasq_m_n_f32): Likewise. 14253 (vfmasq_m_n_f16): Likewise. 14254 (vfmsq_m_f32): Likewise. 14255 (vfmsq_m_f16): Likewise. 14256 (vmaxnmq_m_f32): Likewise. 14257 (vmaxnmq_m_f16): Likewise. 14258 (vminnmq_m_f32): Likewise. 14259 (vminnmq_m_f16): Likewise. 14260 (vmulq_m_f32): Likewise. 14261 (vmulq_m_f16): Likewise. 14262 (vmulq_m_n_f32): Likewise. 14263 (vmulq_m_n_f16): Likewise. 14264 (vornq_m_f32): Likewise. 14265 (vornq_m_f16): Likewise. 14266 (vorrq_m_f32): Likewise. 14267 (vorrq_m_f16): Likewise. 14268 (vsubq_m_f32): Likewise. 14269 (vsubq_m_f16): Likewise. 14270 (vsubq_m_n_f32): Likewise. 14271 (vsubq_m_n_f16): Likewise. 14272 (__attribute__): Likewise. 14273 (__arm_vabdq_m_f32): Likewise. 14274 (__arm_vabdq_m_f16): Likewise. 14275 (__arm_vaddq_m_f32): Likewise. 14276 (__arm_vaddq_m_f16): Likewise. 14277 (__arm_vaddq_m_n_f32): Likewise. 14278 (__arm_vaddq_m_n_f16): Likewise. 14279 (__arm_vandq_m_f32): Likewise. 14280 (__arm_vandq_m_f16): Likewise. 14281 (__arm_vbicq_m_f32): Likewise. 14282 (__arm_vbicq_m_f16): Likewise. 14283 (__arm_vbrsrq_m_n_f32): Likewise. 14284 (__arm_vbrsrq_m_n_f16): Likewise. 14285 (__arm_vcaddq_rot270_m_f32): Likewise. 14286 (__arm_vcaddq_rot270_m_f16): Likewise. 14287 (__arm_vcaddq_rot90_m_f32): Likewise. 14288 (__arm_vcaddq_rot90_m_f16): Likewise. 14289 (__arm_vcmlaq_m_f32): Likewise. 14290 (__arm_vcmlaq_m_f16): Likewise. 14291 (__arm_vcmlaq_rot180_m_f32): Likewise. 14292 (__arm_vcmlaq_rot180_m_f16): Likewise. 14293 (__arm_vcmlaq_rot270_m_f32): Likewise. 14294 (__arm_vcmlaq_rot270_m_f16): Likewise. 14295 (__arm_vcmlaq_rot90_m_f32): Likewise. 14296 (__arm_vcmlaq_rot90_m_f16): Likewise. 14297 (__arm_vcmulq_m_f32): Likewise. 14298 (__arm_vcmulq_m_f16): Likewise. 14299 (__arm_vcmulq_rot180_m_f32): Define intrinsic. 14300 (__arm_vcmulq_rot180_m_f16): Likewise. 14301 (__arm_vcmulq_rot270_m_f32): Likewise. 14302 (__arm_vcmulq_rot270_m_f16): Likewise. 14303 (__arm_vcmulq_rot90_m_f32): Likewise. 14304 (__arm_vcmulq_rot90_m_f16): Likewise. 14305 (__arm_vcvtq_m_n_s32_f32): Likewise. 14306 (__arm_vcvtq_m_n_s16_f16): Likewise. 14307 (__arm_vcvtq_m_n_u32_f32): Likewise. 14308 (__arm_vcvtq_m_n_u16_f16): Likewise. 14309 (__arm_veorq_m_f32): Likewise. 14310 (__arm_veorq_m_f16): Likewise. 14311 (__arm_vfmaq_m_f32): Likewise. 14312 (__arm_vfmaq_m_f16): Likewise. 14313 (__arm_vfmaq_m_n_f32): Likewise. 14314 (__arm_vfmaq_m_n_f16): Likewise. 14315 (__arm_vfmasq_m_n_f32): Likewise. 14316 (__arm_vfmasq_m_n_f16): Likewise. 14317 (__arm_vfmsq_m_f32): Likewise. 14318 (__arm_vfmsq_m_f16): Likewise. 14319 (__arm_vmaxnmq_m_f32): Likewise. 14320 (__arm_vmaxnmq_m_f16): Likewise. 14321 (__arm_vminnmq_m_f32): Likewise. 14322 (__arm_vminnmq_m_f16): Likewise. 14323 (__arm_vmulq_m_f32): Likewise. 14324 (__arm_vmulq_m_f16): Likewise. 14325 (__arm_vmulq_m_n_f32): Likewise. 14326 (__arm_vmulq_m_n_f16): Likewise. 14327 (__arm_vornq_m_f32): Likewise. 14328 (__arm_vornq_m_f16): Likewise. 14329 (__arm_vorrq_m_f32): Likewise. 14330 (__arm_vorrq_m_f16): Likewise. 14331 (__arm_vsubq_m_f32): Likewise. 14332 (__arm_vsubq_m_f16): Likewise. 14333 (__arm_vsubq_m_n_f32): Likewise. 14334 (__arm_vsubq_m_n_f16): Likewise. 14335 (vabdq_m): Define polymorphic variant. 14336 (vaddq_m): Likewise. 14337 (vaddq_m_n): Likewise. 14338 (vandq_m): Likewise. 14339 (vbicq_m): Likewise. 14340 (vbrsrq_m_n): Likewise. 14341 (vcaddq_rot270_m): Likewise. 14342 (vcaddq_rot90_m): Likewise. 14343 (vcmlaq_m): Likewise. 14344 (vcmlaq_rot180_m): Likewise. 14345 (vcmlaq_rot270_m): Likewise. 14346 (vcmlaq_rot90_m): Likewise. 14347 (vcmulq_m): Likewise. 14348 (vcmulq_rot180_m): Likewise. 14349 (vcmulq_rot270_m): Likewise. 14350 (vcmulq_rot90_m): Likewise. 14351 (veorq_m): Likewise. 14352 (vfmaq_m): Likewise. 14353 (vfmaq_m_n): Likewise. 14354 (vfmasq_m_n): Likewise. 14355 (vfmsq_m): Likewise. 14356 (vmaxnmq_m): Likewise. 14357 (vminnmq_m): Likewise. 14358 (vmulq_m): Likewise. 14359 (vmulq_m_n): Likewise. 14360 (vornq_m): Likewise. 14361 (vsubq_m): Likewise. 14362 (vsubq_m_n): Likewise. 14363 (vorrq_m): Likewise. 14364 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 14365 builtin qualifier. 14366 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 14367 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. 14368 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern. 14369 (mve_vaddq_m_f<mode>): Likewise. 14370 (mve_vaddq_m_n_f<mode>): Likewise. 14371 (mve_vandq_m_f<mode>): Likewise. 14372 (mve_vbicq_m_f<mode>): Likewise. 14373 (mve_vbrsrq_m_n_f<mode>): Likewise. 14374 (mve_vcaddq_rot270_m_f<mode>): Likewise. 14375 (mve_vcaddq_rot90_m_f<mode>): Likewise. 14376 (mve_vcmlaq_m_f<mode>): Likewise. 14377 (mve_vcmlaq_rot180_m_f<mode>): Likewise. 14378 (mve_vcmlaq_rot270_m_f<mode>): Likewise. 14379 (mve_vcmlaq_rot90_m_f<mode>): Likewise. 14380 (mve_vcmulq_m_f<mode>): Likewise. 14381 (mve_vcmulq_rot180_m_f<mode>): Likewise. 14382 (mve_vcmulq_rot270_m_f<mode>): Likewise. 14383 (mve_vcmulq_rot90_m_f<mode>): Likewise. 14384 (mve_veorq_m_f<mode>): Likewise. 14385 (mve_vfmaq_m_f<mode>): Likewise. 14386 (mve_vfmaq_m_n_f<mode>): Likewise. 14387 (mve_vfmasq_m_n_f<mode>): Likewise. 14388 (mve_vfmsq_m_f<mode>): Likewise. 14389 (mve_vmaxnmq_m_f<mode>): Likewise. 14390 (mve_vminnmq_m_f<mode>): Likewise. 14391 (mve_vmulq_m_f<mode>): Likewise. 14392 (mve_vmulq_m_n_f<mode>): Likewise. 14393 (mve_vornq_m_f<mode>): Likewise. 14394 (mve_vorrq_m_f<mode>): Likewise. 14395 (mve_vsubq_m_f<mode>): Likewise. 14396 (mve_vsubq_m_n_f<mode>): Likewise. 14397 143982020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14399 Mihail Ionescu <mihail.ionescu@arm.com> 14400 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14401 14402 * config/arm/arm-protos.h (arm_mve_immediate_check): 14403 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check 14404 mode and interger value. 14405 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. 14406 (vmlaldavaq_p_s16): Likewise. 14407 (vmlaldavaq_p_u32): Likewise. 14408 (vmlaldavaq_p_u16): Likewise. 14409 (vmlaldavaxq_p_s32): Likewise. 14410 (vmlaldavaxq_p_s16): Likewise. 14411 (vmlaldavaxq_p_u32): Likewise. 14412 (vmlaldavaxq_p_u16): Likewise. 14413 (vmlsldavaq_p_s32): Likewise. 14414 (vmlsldavaq_p_s16): Likewise. 14415 (vmlsldavaxq_p_s32): Likewise. 14416 (vmlsldavaxq_p_s16): Likewise. 14417 (vmullbq_poly_m_p8): Likewise. 14418 (vmullbq_poly_m_p16): Likewise. 14419 (vmulltq_poly_m_p8): Likewise. 14420 (vmulltq_poly_m_p16): Likewise. 14421 (vqdmullbq_m_n_s32): Likewise. 14422 (vqdmullbq_m_n_s16): Likewise. 14423 (vqdmullbq_m_s32): Likewise. 14424 (vqdmullbq_m_s16): Likewise. 14425 (vqdmulltq_m_n_s32): Likewise. 14426 (vqdmulltq_m_n_s16): Likewise. 14427 (vqdmulltq_m_s32): Likewise. 14428 (vqdmulltq_m_s16): Likewise. 14429 (vqrshrnbq_m_n_s32): Likewise. 14430 (vqrshrnbq_m_n_s16): Likewise. 14431 (vqrshrnbq_m_n_u32): Likewise. 14432 (vqrshrnbq_m_n_u16): Likewise. 14433 (vqrshrntq_m_n_s32): Likewise. 14434 (vqrshrntq_m_n_s16): Likewise. 14435 (vqrshrntq_m_n_u32): Likewise. 14436 (vqrshrntq_m_n_u16): Likewise. 14437 (vqrshrunbq_m_n_s32): Likewise. 14438 (vqrshrunbq_m_n_s16): Likewise. 14439 (vqrshruntq_m_n_s32): Likewise. 14440 (vqrshruntq_m_n_s16): Likewise. 14441 (vqshrnbq_m_n_s32): Likewise. 14442 (vqshrnbq_m_n_s16): Likewise. 14443 (vqshrnbq_m_n_u32): Likewise. 14444 (vqshrnbq_m_n_u16): Likewise. 14445 (vqshrntq_m_n_s32): Likewise. 14446 (vqshrntq_m_n_s16): Likewise. 14447 (vqshrntq_m_n_u32): Likewise. 14448 (vqshrntq_m_n_u16): Likewise. 14449 (vqshrunbq_m_n_s32): Likewise. 14450 (vqshrunbq_m_n_s16): Likewise. 14451 (vqshruntq_m_n_s32): Likewise. 14452 (vqshruntq_m_n_s16): Likewise. 14453 (vrmlaldavhaq_p_s32): Likewise. 14454 (vrmlaldavhaq_p_u32): Likewise. 14455 (vrmlaldavhaxq_p_s32): Likewise. 14456 (vrmlsldavhaq_p_s32): Likewise. 14457 (vrmlsldavhaxq_p_s32): Likewise. 14458 (vrshrnbq_m_n_s32): Likewise. 14459 (vrshrnbq_m_n_s16): Likewise. 14460 (vrshrnbq_m_n_u32): Likewise. 14461 (vrshrnbq_m_n_u16): Likewise. 14462 (vrshrntq_m_n_s32): Likewise. 14463 (vrshrntq_m_n_s16): Likewise. 14464 (vrshrntq_m_n_u32): Likewise. 14465 (vrshrntq_m_n_u16): Likewise. 14466 (vshllbq_m_n_s8): Likewise. 14467 (vshllbq_m_n_s16): Likewise. 14468 (vshllbq_m_n_u8): Likewise. 14469 (vshllbq_m_n_u16): Likewise. 14470 (vshlltq_m_n_s8): Likewise. 14471 (vshlltq_m_n_s16): Likewise. 14472 (vshlltq_m_n_u8): Likewise. 14473 (vshlltq_m_n_u16): Likewise. 14474 (vshrnbq_m_n_s32): Likewise. 14475 (vshrnbq_m_n_s16): Likewise. 14476 (vshrnbq_m_n_u32): Likewise. 14477 (vshrnbq_m_n_u16): Likewise. 14478 (vshrntq_m_n_s32): Likewise. 14479 (vshrntq_m_n_s16): Likewise. 14480 (vshrntq_m_n_u32): Likewise. 14481 (vshrntq_m_n_u16): Likewise. 14482 (__arm_vmlaldavaq_p_s32): Define intrinsic. 14483 (__arm_vmlaldavaq_p_s16): Likewise. 14484 (__arm_vmlaldavaq_p_u32): Likewise. 14485 (__arm_vmlaldavaq_p_u16): Likewise. 14486 (__arm_vmlaldavaxq_p_s32): Likewise. 14487 (__arm_vmlaldavaxq_p_s16): Likewise. 14488 (__arm_vmlaldavaxq_p_u32): Likewise. 14489 (__arm_vmlaldavaxq_p_u16): Likewise. 14490 (__arm_vmlsldavaq_p_s32): Likewise. 14491 (__arm_vmlsldavaq_p_s16): Likewise. 14492 (__arm_vmlsldavaxq_p_s32): Likewise. 14493 (__arm_vmlsldavaxq_p_s16): Likewise. 14494 (__arm_vmullbq_poly_m_p8): Likewise. 14495 (__arm_vmullbq_poly_m_p16): Likewise. 14496 (__arm_vmulltq_poly_m_p8): Likewise. 14497 (__arm_vmulltq_poly_m_p16): Likewise. 14498 (__arm_vqdmullbq_m_n_s32): Likewise. 14499 (__arm_vqdmullbq_m_n_s16): Likewise. 14500 (__arm_vqdmullbq_m_s32): Likewise. 14501 (__arm_vqdmullbq_m_s16): Likewise. 14502 (__arm_vqdmulltq_m_n_s32): Likewise. 14503 (__arm_vqdmulltq_m_n_s16): Likewise. 14504 (__arm_vqdmulltq_m_s32): Likewise. 14505 (__arm_vqdmulltq_m_s16): Likewise. 14506 (__arm_vqrshrnbq_m_n_s32): Likewise. 14507 (__arm_vqrshrnbq_m_n_s16): Likewise. 14508 (__arm_vqrshrnbq_m_n_u32): Likewise. 14509 (__arm_vqrshrnbq_m_n_u16): Likewise. 14510 (__arm_vqrshrntq_m_n_s32): Likewise. 14511 (__arm_vqrshrntq_m_n_s16): Likewise. 14512 (__arm_vqrshrntq_m_n_u32): Likewise. 14513 (__arm_vqrshrntq_m_n_u16): Likewise. 14514 (__arm_vqrshrunbq_m_n_s32): Likewise. 14515 (__arm_vqrshrunbq_m_n_s16): Likewise. 14516 (__arm_vqrshruntq_m_n_s32): Likewise. 14517 (__arm_vqrshruntq_m_n_s16): Likewise. 14518 (__arm_vqshrnbq_m_n_s32): Likewise. 14519 (__arm_vqshrnbq_m_n_s16): Likewise. 14520 (__arm_vqshrnbq_m_n_u32): Likewise. 14521 (__arm_vqshrnbq_m_n_u16): Likewise. 14522 (__arm_vqshrntq_m_n_s32): Likewise. 14523 (__arm_vqshrntq_m_n_s16): Likewise. 14524 (__arm_vqshrntq_m_n_u32): Likewise. 14525 (__arm_vqshrntq_m_n_u16): Likewise. 14526 (__arm_vqshrunbq_m_n_s32): Likewise. 14527 (__arm_vqshrunbq_m_n_s16): Likewise. 14528 (__arm_vqshruntq_m_n_s32): Likewise. 14529 (__arm_vqshruntq_m_n_s16): Likewise. 14530 (__arm_vrmlaldavhaq_p_s32): Likewise. 14531 (__arm_vrmlaldavhaq_p_u32): Likewise. 14532 (__arm_vrmlaldavhaxq_p_s32): Likewise. 14533 (__arm_vrmlsldavhaq_p_s32): Likewise. 14534 (__arm_vrmlsldavhaxq_p_s32): Likewise. 14535 (__arm_vrshrnbq_m_n_s32): Likewise. 14536 (__arm_vrshrnbq_m_n_s16): Likewise. 14537 (__arm_vrshrnbq_m_n_u32): Likewise. 14538 (__arm_vrshrnbq_m_n_u16): Likewise. 14539 (__arm_vrshrntq_m_n_s32): Likewise. 14540 (__arm_vrshrntq_m_n_s16): Likewise. 14541 (__arm_vrshrntq_m_n_u32): Likewise. 14542 (__arm_vrshrntq_m_n_u16): Likewise. 14543 (__arm_vshllbq_m_n_s8): Likewise. 14544 (__arm_vshllbq_m_n_s16): Likewise. 14545 (__arm_vshllbq_m_n_u8): Likewise. 14546 (__arm_vshllbq_m_n_u16): Likewise. 14547 (__arm_vshlltq_m_n_s8): Likewise. 14548 (__arm_vshlltq_m_n_s16): Likewise. 14549 (__arm_vshlltq_m_n_u8): Likewise. 14550 (__arm_vshlltq_m_n_u16): Likewise. 14551 (__arm_vshrnbq_m_n_s32): Likewise. 14552 (__arm_vshrnbq_m_n_s16): Likewise. 14553 (__arm_vshrnbq_m_n_u32): Likewise. 14554 (__arm_vshrnbq_m_n_u16): Likewise. 14555 (__arm_vshrntq_m_n_s32): Likewise. 14556 (__arm_vshrntq_m_n_s16): Likewise. 14557 (__arm_vshrntq_m_n_u32): Likewise. 14558 (__arm_vshrntq_m_n_u16): Likewise. 14559 (vmullbq_poly_m): Define polymorphic variant. 14560 (vmulltq_poly_m): Likewise. 14561 (vshllbq_m): Likewise. 14562 (vshrntq_m_n): Likewise. 14563 (vshrnbq_m_n): Likewise. 14564 (vshlltq_m_n): Likewise. 14565 (vshllbq_m_n): Likewise. 14566 (vrshrntq_m_n): Likewise. 14567 (vrshrnbq_m_n): Likewise. 14568 (vqshruntq_m_n): Likewise. 14569 (vqshrunbq_m_n): Likewise. 14570 (vqdmullbq_m_n): Likewise. 14571 (vqdmullbq_m): Likewise. 14572 (vqdmulltq_m_n): Likewise. 14573 (vqdmulltq_m): Likewise. 14574 (vqrshrnbq_m_n): Likewise. 14575 (vqrshrntq_m_n): Likewise. 14576 (vqrshrunbq_m_n): Likewise. 14577 (vqrshruntq_m_n): Likewise. 14578 (vqshrnbq_m_n): Likewise. 14579 (vqshrntq_m_n): Likewise. 14580 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 14581 builtin qualifiers. 14582 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 14583 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. 14584 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 14585 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 14586 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. 14587 (VMLALDAVAXQ_P): Likewise. 14588 (VQRSHRNBQ_M_N): Likewise. 14589 (VQRSHRNTQ_M_N): Likewise. 14590 (VQSHRNBQ_M_N): Likewise. 14591 (VQSHRNTQ_M_N): Likewise. 14592 (VRSHRNBQ_M_N): Likewise. 14593 (VRSHRNTQ_M_N): Likewise. 14594 (VSHLLBQ_M_N): Likewise. 14595 (VSHLLTQ_M_N): Likewise. 14596 (VSHRNBQ_M_N): Likewise. 14597 (VSHRNTQ_M_N): Likewise. 14598 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern. 14599 (mve_vmlaldavaxq_p_<supf><mode>): Likewise. 14600 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. 14601 (mve_vqrshrntq_m_n_<supf><mode>): Likewise. 14602 (mve_vqshrnbq_m_n_<supf><mode>): Likewise. 14603 (mve_vqshrntq_m_n_<supf><mode>): Likewise. 14604 (mve_vrmlaldavhaq_p_sv4si): Likewise. 14605 (mve_vrshrnbq_m_n_<supf><mode>): Likewise. 14606 (mve_vrshrntq_m_n_<supf><mode>): Likewise. 14607 (mve_vshllbq_m_n_<supf><mode>): Likewise. 14608 (mve_vshlltq_m_n_<supf><mode>): Likewise. 14609 (mve_vshrnbq_m_n_<supf><mode>): Likewise. 14610 (mve_vshrntq_m_n_<supf><mode>): Likewise. 14611 (mve_vmlsldavaq_p_s<mode>): Likewise. 14612 (mve_vmlsldavaxq_p_s<mode>): Likewise. 14613 (mve_vmullbq_poly_m_p<mode>): Likewise. 14614 (mve_vmulltq_poly_m_p<mode>): Likewise. 14615 (mve_vqdmullbq_m_n_s<mode>): Likewise. 14616 (mve_vqdmullbq_m_s<mode>): Likewise. 14617 (mve_vqdmulltq_m_n_s<mode>): Likewise. 14618 (mve_vqdmulltq_m_s<mode>): Likewise. 14619 (mve_vqrshrunbq_m_n_s<mode>): Likewise. 14620 (mve_vqrshruntq_m_n_s<mode>): Likewise. 14621 (mve_vqshrunbq_m_n_s<mode>): Likewise. 14622 (mve_vqshruntq_m_n_s<mode>): Likewise. 14623 (mve_vrmlaldavhaq_p_uv4si): Likewise. 14624 (mve_vrmlaldavhaxq_p_sv4si): Likewise. 14625 (mve_vrmlsldavhaq_p_sv4si): Likewise. 14626 (mve_vrmlsldavhaxq_p_sv4si): Likewise. 14627 146282020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 14629 Mihail Ionescu <mihail.ionescu@arm.com> 14630 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 14631 14632 * config/arm/arm_mve.h (vabdq_m_s8): Define macro. 14633 (vabdq_m_s32): Likewise. 14634 (vabdq_m_s16): Likewise. 14635 (vabdq_m_u8): Likewise. 14636 (vabdq_m_u32): Likewise. 14637 (vabdq_m_u16): Likewise. 14638 (vaddq_m_n_s8): Likewise. 14639 (vaddq_m_n_s32): Likewise. 14640 (vaddq_m_n_s16): Likewise. 14641 (vaddq_m_n_u8): Likewise. 14642 (vaddq_m_n_u32): Likewise. 14643 (vaddq_m_n_u16): Likewise. 14644 (vaddq_m_s8): Likewise. 14645 (vaddq_m_s32): Likewise. 14646 (vaddq_m_s16): Likewise. 14647 (vaddq_m_u8): Likewise. 14648 (vaddq_m_u32): Likewise. 14649 (vaddq_m_u16): Likewise. 14650 (vandq_m_s8): Likewise. 14651 (vandq_m_s32): Likewise. 14652 (vandq_m_s16): Likewise. 14653 (vandq_m_u8): Likewise. 14654 (vandq_m_u32): Likewise. 14655 (vandq_m_u16): Likewise. 14656 (vbicq_m_s8): Likewise. 14657 (vbicq_m_s32): Likewise. 14658 (vbicq_m_s16): Likewise. 14659 (vbicq_m_u8): Likewise. 14660 (vbicq_m_u32): Likewise. 14661 (vbicq_m_u16): Likewise. 14662 (vbrsrq_m_n_s8): Likewise. 14663 (vbrsrq_m_n_s32): Likewise. 14664 (vbrsrq_m_n_s16): Likewise. 14665 (vbrsrq_m_n_u8): Likewise. 14666 (vbrsrq_m_n_u32): Likewise. 14667 (vbrsrq_m_n_u16): Likewise. 14668 (vcaddq_rot270_m_s8): Likewise. 14669 (vcaddq_rot270_m_s32): Likewise. 14670 (vcaddq_rot270_m_s16): Likewise. 14671 (vcaddq_rot270_m_u8): Likewise. 14672 (vcaddq_rot270_m_u32): Likewise. 14673 (vcaddq_rot270_m_u16): Likewise. 14674 (vcaddq_rot90_m_s8): Likewise. 14675 (vcaddq_rot90_m_s32): Likewise. 14676 (vcaddq_rot90_m_s16): Likewise. 14677 (vcaddq_rot90_m_u8): Likewise. 14678 (vcaddq_rot90_m_u32): Likewise. 14679 (vcaddq_rot90_m_u16): Likewise. 14680 (veorq_m_s8): Likewise. 14681 (veorq_m_s32): Likewise. 14682 (veorq_m_s16): Likewise. 14683 (veorq_m_u8): Likewise. 14684 (veorq_m_u32): Likewise. 14685 (veorq_m_u16): Likewise. 14686 (vhaddq_m_n_s8): Likewise. 14687 (vhaddq_m_n_s32): Likewise. 14688 (vhaddq_m_n_s16): Likewise. 14689 (vhaddq_m_n_u8): Likewise. 14690 (vhaddq_m_n_u32): Likewise. 14691 (vhaddq_m_n_u16): Likewise. 14692 (vhaddq_m_s8): Likewise. 14693 (vhaddq_m_s32): Likewise. 14694 (vhaddq_m_s16): Likewise. 14695 (vhaddq_m_u8): Likewise. 14696 (vhaddq_m_u32): Likewise. 14697 (vhaddq_m_u16): Likewise. 14698 (vhcaddq_rot270_m_s8): Likewise. 14699 (vhcaddq_rot270_m_s32): Likewise. 14700 (vhcaddq_rot270_m_s16): Likewise. 14701 (vhcaddq_rot90_m_s8): Likewise. 14702 (vhcaddq_rot90_m_s32): Likewise. 14703 (vhcaddq_rot90_m_s16): Likewise. 14704 (vhsubq_m_n_s8): Likewise. 14705 (vhsubq_m_n_s32): Likewise. 14706 (vhsubq_m_n_s16): Likewise. 14707 (vhsubq_m_n_u8): Likewise. 14708 (vhsubq_m_n_u32): Likewise. 14709 (vhsubq_m_n_u16): Likewise. 14710 (vhsubq_m_s8): Likewise. 14711 (vhsubq_m_s32): Likewise. 14712 (vhsubq_m_s16): Likewise. 14713 (vhsubq_m_u8): Likewise. 14714 (vhsubq_m_u32): Likewise. 14715 (vhsubq_m_u16): Likewise. 14716 (vmaxq_m_s8): Likewise. 14717 (vmaxq_m_s32): Likewise. 14718 (vmaxq_m_s16): Likewise. 14719 (vmaxq_m_u8): Likewise. 14720 (vmaxq_m_u32): Likewise. 14721 (vmaxq_m_u16): Likewise. 14722 (vminq_m_s8): Likewise. 14723 (vminq_m_s32): Likewise. 14724 (vminq_m_s16): Likewise. 14725 (vminq_m_u8): Likewise. 14726 (vminq_m_u32): Likewise. 14727 (vminq_m_u16): Likewise. 14728 (vmladavaq_p_s8): Likewise. 14729 (vmladavaq_p_s32): Likewise. 14730 (vmladavaq_p_s16): Likewise. 14731 (vmladavaq_p_u8): Likewise. 14732 (vmladavaq_p_u32): Likewise. 14733 (vmladavaq_p_u16): Likewise. 14734 (vmladavaxq_p_s8): Likewise. 14735 (vmladavaxq_p_s32): Likewise. 14736 (vmladavaxq_p_s16): Likewise. 14737 (vmlaq_m_n_s8): Likewise. 14738 (vmlaq_m_n_s32): Likewise. 14739 (vmlaq_m_n_s16): Likewise. 14740 (vmlaq_m_n_u8): Likewise. 14741 (vmlaq_m_n_u32): Likewise. 14742 (vmlaq_m_n_u16): Likewise. 14743 (vmlasq_m_n_s8): Likewise. 14744 (vmlasq_m_n_s32): Likewise. 14745 (vmlasq_m_n_s16): Likewise. 14746 (vmlasq_m_n_u8): Likewise. 14747 (vmlasq_m_n_u32): Likewise. 14748 (vmlasq_m_n_u16): Likewise. 14749 (vmlsdavaq_p_s8): Likewise. 14750 (vmlsdavaq_p_s32): Likewise. 14751 (vmlsdavaq_p_s16): Likewise. 14752 (vmlsdavaxq_p_s8): Likewise. 14753 (vmlsdavaxq_p_s32): Likewise. 14754 (vmlsdavaxq_p_s16): Likewise. 14755 (vmulhq_m_s8): Likewise. 14756 (vmulhq_m_s32): Likewise. 14757 (vmulhq_m_s16): Likewise. 14758 (vmulhq_m_u8): Likewise. 14759 (vmulhq_m_u32): Likewise. 14760 (vmulhq_m_u16): Likewise. 14761 (vmullbq_int_m_s8): Likewise. 14762 (vmullbq_int_m_s32): Likewise. 14763 (vmullbq_int_m_s16): Likewise. 14764 (vmullbq_int_m_u8): Likewise. 14765 (vmullbq_int_m_u32): Likewise. 14766 (vmullbq_int_m_u16): Likewise. 14767 (vmulltq_int_m_s8): Likewise. 14768 (vmulltq_int_m_s32): Likewise. 14769 (vmulltq_int_m_s16): Likewise. 14770 (vmulltq_int_m_u8): Likewise. 14771 (vmulltq_int_m_u32): Likewise. 14772 (vmulltq_int_m_u16): Likewise. 14773 (vmulq_m_n_s8): Likewise. 14774 (vmulq_m_n_s32): Likewise. 14775 (vmulq_m_n_s16): Likewise. 14776 (vmulq_m_n_u8): Likewise. 14777 (vmulq_m_n_u32): Likewise. 14778 (vmulq_m_n_u16): Likewise. 14779 (vmulq_m_s8): Likewise. 14780 (vmulq_m_s32): Likewise. 14781 (vmulq_m_s16): Likewise. 14782 (vmulq_m_u8): Likewise. 14783 (vmulq_m_u32): Likewise. 14784 (vmulq_m_u16): Likewise. 14785 (vornq_m_s8): Likewise. 14786 (vornq_m_s32): Likewise. 14787 (vornq_m_s16): Likewise. 14788 (vornq_m_u8): Likewise. 14789 (vornq_m_u32): Likewise. 14790 (vornq_m_u16): Likewise. 14791 (vorrq_m_s8): Likewise. 14792 (vorrq_m_s32): Likewise. 14793 (vorrq_m_s16): Likewise. 14794 (vorrq_m_u8): Likewise. 14795 (vorrq_m_u32): Likewise. 14796 (vorrq_m_u16): Likewise. 14797 (vqaddq_m_n_s8): Likewise. 14798 (vqaddq_m_n_s32): Likewise. 14799 (vqaddq_m_n_s16): Likewise. 14800 (vqaddq_m_n_u8): Likewise. 14801 (vqaddq_m_n_u32): Likewise. 14802 (vqaddq_m_n_u16): Likewise. 14803 (vqaddq_m_s8): Likewise. 14804 (vqaddq_m_s32): Likewise. 14805 (vqaddq_m_s16): Likewise. 14806 (vqaddq_m_u8): Likewise. 14807 (vqaddq_m_u32): Likewise. 14808 (vqaddq_m_u16): Likewise. 14809 (vqdmladhq_m_s8): Likewise. 14810 (vqdmladhq_m_s32): Likewise. 14811 (vqdmladhq_m_s16): Likewise. 14812 (vqdmladhxq_m_s8): Likewise. 14813 (vqdmladhxq_m_s32): Likewise. 14814 (vqdmladhxq_m_s16): Likewise. 14815 (vqdmlahq_m_n_s8): Likewise. 14816 (vqdmlahq_m_n_s32): Likewise. 14817 (vqdmlahq_m_n_s16): Likewise. 14818 (vqdmlahq_m_n_u8): Likewise. 14819 (vqdmlahq_m_n_u32): Likewise. 14820 (vqdmlahq_m_n_u16): Likewise. 14821 (vqdmlsdhq_m_s8): Likewise. 14822 (vqdmlsdhq_m_s32): Likewise. 14823 (vqdmlsdhq_m_s16): Likewise. 14824 (vqdmlsdhxq_m_s8): Likewise. 14825 (vqdmlsdhxq_m_s32): Likewise. 14826 (vqdmlsdhxq_m_s16): Likewise. 14827 (vqdmulhq_m_n_s8): Likewise. 14828 (vqdmulhq_m_n_s32): Likewise. 14829 (vqdmulhq_m_n_s16): Likewise. 14830 (vqdmulhq_m_s8): Likewise. 14831 (vqdmulhq_m_s32): Likewise. 14832 (vqdmulhq_m_s16): Likewise. 14833 (vqrdmladhq_m_s8): Likewise. 14834 (vqrdmladhq_m_s32): Likewise. 14835 (vqrdmladhq_m_s16): Likewise. 14836 (vqrdmladhxq_m_s8): Likewise. 14837 (vqrdmladhxq_m_s32): Likewise. 14838 (vqrdmladhxq_m_s16): Likewise. 14839 (vqrdmlahq_m_n_s8): Likewise. 14840 (vqrdmlahq_m_n_s32): Likewise. 14841 (vqrdmlahq_m_n_s16): Likewise. 14842 (vqrdmlahq_m_n_u8): Likewise. 14843 (vqrdmlahq_m_n_u32): Likewise. 14844 (vqrdmlahq_m_n_u16): Likewise. 14845 (vqrdmlashq_m_n_s8): Likewise. 14846 (vqrdmlashq_m_n_s32): Likewise. 14847 (vqrdmlashq_m_n_s16): Likewise. 14848 (vqrdmlashq_m_n_u8): Likewise. 14849 (vqrdmlashq_m_n_u32): Likewise. 14850 (vqrdmlashq_m_n_u16): Likewise. 14851 (vqrdmlsdhq_m_s8): Likewise. 14852 (vqrdmlsdhq_m_s32): Likewise. 14853 (vqrdmlsdhq_m_s16): Likewise. 14854 (vqrdmlsdhxq_m_s8): Likewise. 14855 (vqrdmlsdhxq_m_s32): Likewise. 14856 (vqrdmlsdhxq_m_s16): Likewise. 14857 (vqrdmulhq_m_n_s8): Likewise. 14858 (vqrdmulhq_m_n_s32): Likewise. 14859 (vqrdmulhq_m_n_s16): Likewise. 14860 (vqrdmulhq_m_s8): Likewise. 14861 (vqrdmulhq_m_s32): Likewise. 14862 (vqrdmulhq_m_s16): Likewise. 14863 (vqrshlq_m_s8): Likewise. 14864 (vqrshlq_m_s32): Likewise. 14865 (vqrshlq_m_s16): Likewise. 14866 (vqrshlq_m_u8): Likewise. 14867 (vqrshlq_m_u32): Likewise. 14868 (vqrshlq_m_u16): Likewise. 14869 (vqshlq_m_n_s8): Likewise. 14870 (vqshlq_m_n_s32): Likewise. 14871 (vqshlq_m_n_s16): Likewise. 14872 (vqshlq_m_n_u8): Likewise. 14873 (vqshlq_m_n_u32): Likewise. 14874 (vqshlq_m_n_u16): Likewise. 14875 (vqshlq_m_s8): Likewise. 14876 (vqshlq_m_s32): Likewise. 14877 (vqshlq_m_s16): Likewise. 14878 (vqshlq_m_u8): Likewise. 14879 (vqshlq_m_u32): Likewise. 14880 (vqshlq_m_u16): Likewise. 14881 (vqsubq_m_n_s8): Likewise. 14882 (vqsubq_m_n_s32): Likewise. 14883 (vqsubq_m_n_s16): Likewise. 14884 (vqsubq_m_n_u8): Likewise. 14885 (vqsubq_m_n_u32): Likewise. 14886 (vqsubq_m_n_u16): Likewise. 14887 (vqsubq_m_s8): Likewise. 14888 (vqsubq_m_s32): Likewise. 14889 (vqsubq_m_s16): Likewise. 14890 (vqsubq_m_u8): Likewise. 14891 (vqsubq_m_u32): Likewise. 14892 (vqsubq_m_u16): Likewise. 14893 (vrhaddq_m_s8): Likewise. 14894 (vrhaddq_m_s32): Likewise. 14895 (vrhaddq_m_s16): Likewise. 14896 (vrhaddq_m_u8): Likewise. 14897 (vrhaddq_m_u32): Likewise. 14898 (vrhaddq_m_u16): Likewise. 14899 (vrmulhq_m_s8): Likewise. 14900 (vrmulhq_m_s32): Likewise. 14901 (vrmulhq_m_s16): Likewise. 14902 (vrmulhq_m_u8): Likewise. 14903 (vrmulhq_m_u32): Likewise. 14904 (vrmulhq_m_u16): Likewise. 14905 (vrshlq_m_s8): Likewise. 14906 (vrshlq_m_s32): Likewise. 14907 (vrshlq_m_s16): Likewise. 14908 (vrshlq_m_u8): Likewise. 14909 (vrshlq_m_u32): Likewise. 14910 (vrshlq_m_u16): Likewise. 14911 (vrshrq_m_n_s8): Likewise. 14912 (vrshrq_m_n_s32): Likewise. 14913 (vrshrq_m_n_s16): Likewise. 14914 (vrshrq_m_n_u8): Likewise. 14915 (vrshrq_m_n_u32): Likewise. 14916 (vrshrq_m_n_u16): Likewise. 14917 (vshlq_m_n_s8): Likewise. 14918 (vshlq_m_n_s32): Likewise. 14919 (vshlq_m_n_s16): Likewise. 14920 (vshlq_m_n_u8): Likewise. 14921 (vshlq_m_n_u32): Likewise. 14922 (vshlq_m_n_u16): Likewise. 14923 (vshrq_m_n_s8): Likewise. 14924 (vshrq_m_n_s32): Likewise. 14925 (vshrq_m_n_s16): Likewise. 14926 (vshrq_m_n_u8): Likewise. 14927 (vshrq_m_n_u32): Likewise. 14928 (vshrq_m_n_u16): Likewise. 14929 (vsliq_m_n_s8): Likewise. 14930 (vsliq_m_n_s32): Likewise. 14931 (vsliq_m_n_s16): Likewise. 14932 (vsliq_m_n_u8): Likewise. 14933 (vsliq_m_n_u32): Likewise. 14934 (vsliq_m_n_u16): Likewise. 14935 (vsubq_m_n_s8): Likewise. 14936 (vsubq_m_n_s32): Likewise. 14937 (vsubq_m_n_s16): Likewise. 14938 (vsubq_m_n_u8): Likewise. 14939 (vsubq_m_n_u32): Likewise. 14940 (vsubq_m_n_u16): Likewise. 14941 (__arm_vabdq_m_s8): Define intrinsic. 14942 (__arm_vabdq_m_s32): Likewise. 14943 (__arm_vabdq_m_s16): Likewise. 14944 (__arm_vabdq_m_u8): Likewise. 14945 (__arm_vabdq_m_u32): Likewise. 14946 (__arm_vabdq_m_u16): Likewise. 14947 (__arm_vaddq_m_n_s8): Likewise. 14948 (__arm_vaddq_m_n_s32): Likewise. 14949 (__arm_vaddq_m_n_s16): Likewise. 14950 (__arm_vaddq_m_n_u8): Likewise. 14951 (__arm_vaddq_m_n_u32): Likewise. 14952 (__arm_vaddq_m_n_u16): Likewise. 14953 (__arm_vaddq_m_s8): Likewise. 14954 (__arm_vaddq_m_s32): Likewise. 14955 (__arm_vaddq_m_s16): Likewise. 14956 (__arm_vaddq_m_u8): Likewise. 14957 (__arm_vaddq_m_u32): Likewise. 14958 (__arm_vaddq_m_u16): Likewise. 14959 (__arm_vandq_m_s8): Likewise. 14960 (__arm_vandq_m_s32): Likewise. 14961 (__arm_vandq_m_s16): Likewise. 14962 (__arm_vandq_m_u8): Likewise. 14963 (__arm_vandq_m_u32): Likewise. 14964 (__arm_vandq_m_u16): Likewise. 14965 (__arm_vbicq_m_s8): Likewise. 14966 (__arm_vbicq_m_s32): Likewise. 14967 (__arm_vbicq_m_s16): Likewise. 14968 (__arm_vbicq_m_u8): Likewise. 14969 (__arm_vbicq_m_u32): Likewise. 14970 (__arm_vbicq_m_u16): Likewise. 14971 (__arm_vbrsrq_m_n_s8): Likewise. 14972 (__arm_vbrsrq_m_n_s32): Likewise. 14973 (__arm_vbrsrq_m_n_s16): Likewise. 14974 (__arm_vbrsrq_m_n_u8): Likewise. 14975 (__arm_vbrsrq_m_n_u32): Likewise. 14976 (__arm_vbrsrq_m_n_u16): Likewise. 14977 (__arm_vcaddq_rot270_m_s8): Likewise. 14978 (__arm_vcaddq_rot270_m_s32): Likewise. 14979 (__arm_vcaddq_rot270_m_s16): Likewise. 14980 (__arm_vcaddq_rot270_m_u8): Likewise. 14981 (__arm_vcaddq_rot270_m_u32): Likewise. 14982 (__arm_vcaddq_rot270_m_u16): Likewise. 14983 (__arm_vcaddq_rot90_m_s8): Likewise. 14984 (__arm_vcaddq_rot90_m_s32): Likewise. 14985 (__arm_vcaddq_rot90_m_s16): Likewise. 14986 (__arm_vcaddq_rot90_m_u8): Likewise. 14987 (__arm_vcaddq_rot90_m_u32): Likewise. 14988 (__arm_vcaddq_rot90_m_u16): Likewise. 14989 (__arm_veorq_m_s8): Likewise. 14990 (__arm_veorq_m_s32): Likewise. 14991 (__arm_veorq_m_s16): Likewise. 14992 (__arm_veorq_m_u8): Likewise. 14993 (__arm_veorq_m_u32): Likewise. 14994 (__arm_veorq_m_u16): Likewise. 14995 (__arm_vhaddq_m_n_s8): Likewise. 14996 (__arm_vhaddq_m_n_s32): Likewise. 14997 (__arm_vhaddq_m_n_s16): Likewise. 14998 (__arm_vhaddq_m_n_u8): Likewise. 14999 (__arm_vhaddq_m_n_u32): Likewise. 15000 (__arm_vhaddq_m_n_u16): Likewise. 15001 (__arm_vhaddq_m_s8): Likewise. 15002 (__arm_vhaddq_m_s32): Likewise. 15003 (__arm_vhaddq_m_s16): Likewise. 15004 (__arm_vhaddq_m_u8): Likewise. 15005 (__arm_vhaddq_m_u32): Likewise. 15006 (__arm_vhaddq_m_u16): Likewise. 15007 (__arm_vhcaddq_rot270_m_s8): Likewise. 15008 (__arm_vhcaddq_rot270_m_s32): Likewise. 15009 (__arm_vhcaddq_rot270_m_s16): Likewise. 15010 (__arm_vhcaddq_rot90_m_s8): Likewise. 15011 (__arm_vhcaddq_rot90_m_s32): Likewise. 15012 (__arm_vhcaddq_rot90_m_s16): Likewise. 15013 (__arm_vhsubq_m_n_s8): Likewise. 15014 (__arm_vhsubq_m_n_s32): Likewise. 15015 (__arm_vhsubq_m_n_s16): Likewise. 15016 (__arm_vhsubq_m_n_u8): Likewise. 15017 (__arm_vhsubq_m_n_u32): Likewise. 15018 (__arm_vhsubq_m_n_u16): Likewise. 15019 (__arm_vhsubq_m_s8): Likewise. 15020 (__arm_vhsubq_m_s32): Likewise. 15021 (__arm_vhsubq_m_s16): Likewise. 15022 (__arm_vhsubq_m_u8): Likewise. 15023 (__arm_vhsubq_m_u32): Likewise. 15024 (__arm_vhsubq_m_u16): Likewise. 15025 (__arm_vmaxq_m_s8): Likewise. 15026 (__arm_vmaxq_m_s32): Likewise. 15027 (__arm_vmaxq_m_s16): Likewise. 15028 (__arm_vmaxq_m_u8): Likewise. 15029 (__arm_vmaxq_m_u32): Likewise. 15030 (__arm_vmaxq_m_u16): Likewise. 15031 (__arm_vminq_m_s8): Likewise. 15032 (__arm_vminq_m_s32): Likewise. 15033 (__arm_vminq_m_s16): Likewise. 15034 (__arm_vminq_m_u8): Likewise. 15035 (__arm_vminq_m_u32): Likewise. 15036 (__arm_vminq_m_u16): Likewise. 15037 (__arm_vmladavaq_p_s8): Likewise. 15038 (__arm_vmladavaq_p_s32): Likewise. 15039 (__arm_vmladavaq_p_s16): Likewise. 15040 (__arm_vmladavaq_p_u8): Likewise. 15041 (__arm_vmladavaq_p_u32): Likewise. 15042 (__arm_vmladavaq_p_u16): Likewise. 15043 (__arm_vmladavaxq_p_s8): Likewise. 15044 (__arm_vmladavaxq_p_s32): Likewise. 15045 (__arm_vmladavaxq_p_s16): Likewise. 15046 (__arm_vmlaq_m_n_s8): Likewise. 15047 (__arm_vmlaq_m_n_s32): Likewise. 15048 (__arm_vmlaq_m_n_s16): Likewise. 15049 (__arm_vmlaq_m_n_u8): Likewise. 15050 (__arm_vmlaq_m_n_u32): Likewise. 15051 (__arm_vmlaq_m_n_u16): Likewise. 15052 (__arm_vmlasq_m_n_s8): Likewise. 15053 (__arm_vmlasq_m_n_s32): Likewise. 15054 (__arm_vmlasq_m_n_s16): Likewise. 15055 (__arm_vmlasq_m_n_u8): Likewise. 15056 (__arm_vmlasq_m_n_u32): Likewise. 15057 (__arm_vmlasq_m_n_u16): Likewise. 15058 (__arm_vmlsdavaq_p_s8): Likewise. 15059 (__arm_vmlsdavaq_p_s32): Likewise. 15060 (__arm_vmlsdavaq_p_s16): Likewise. 15061 (__arm_vmlsdavaxq_p_s8): Likewise. 15062 (__arm_vmlsdavaxq_p_s32): Likewise. 15063 (__arm_vmlsdavaxq_p_s16): Likewise. 15064 (__arm_vmulhq_m_s8): Likewise. 15065 (__arm_vmulhq_m_s32): Likewise. 15066 (__arm_vmulhq_m_s16): Likewise. 15067 (__arm_vmulhq_m_u8): Likewise. 15068 (__arm_vmulhq_m_u32): Likewise. 15069 (__arm_vmulhq_m_u16): Likewise. 15070 (__arm_vmullbq_int_m_s8): Likewise. 15071 (__arm_vmullbq_int_m_s32): Likewise. 15072 (__arm_vmullbq_int_m_s16): Likewise. 15073 (__arm_vmullbq_int_m_u8): Likewise. 15074 (__arm_vmullbq_int_m_u32): Likewise. 15075 (__arm_vmullbq_int_m_u16): Likewise. 15076 (__arm_vmulltq_int_m_s8): Likewise. 15077 (__arm_vmulltq_int_m_s32): Likewise. 15078 (__arm_vmulltq_int_m_s16): Likewise. 15079 (__arm_vmulltq_int_m_u8): Likewise. 15080 (__arm_vmulltq_int_m_u32): Likewise. 15081 (__arm_vmulltq_int_m_u16): Likewise. 15082 (__arm_vmulq_m_n_s8): Likewise. 15083 (__arm_vmulq_m_n_s32): Likewise. 15084 (__arm_vmulq_m_n_s16): Likewise. 15085 (__arm_vmulq_m_n_u8): Likewise. 15086 (__arm_vmulq_m_n_u32): Likewise. 15087 (__arm_vmulq_m_n_u16): Likewise. 15088 (__arm_vmulq_m_s8): Likewise. 15089 (__arm_vmulq_m_s32): Likewise. 15090 (__arm_vmulq_m_s16): Likewise. 15091 (__arm_vmulq_m_u8): Likewise. 15092 (__arm_vmulq_m_u32): Likewise. 15093 (__arm_vmulq_m_u16): Likewise. 15094 (__arm_vornq_m_s8): Likewise. 15095 (__arm_vornq_m_s32): Likewise. 15096 (__arm_vornq_m_s16): Likewise. 15097 (__arm_vornq_m_u8): Likewise. 15098 (__arm_vornq_m_u32): Likewise. 15099 (__arm_vornq_m_u16): Likewise. 15100 (__arm_vorrq_m_s8): Likewise. 15101 (__arm_vorrq_m_s32): Likewise. 15102 (__arm_vorrq_m_s16): Likewise. 15103 (__arm_vorrq_m_u8): Likewise. 15104 (__arm_vorrq_m_u32): Likewise. 15105 (__arm_vorrq_m_u16): Likewise. 15106 (__arm_vqaddq_m_n_s8): Likewise. 15107 (__arm_vqaddq_m_n_s32): Likewise. 15108 (__arm_vqaddq_m_n_s16): Likewise. 15109 (__arm_vqaddq_m_n_u8): Likewise. 15110 (__arm_vqaddq_m_n_u32): Likewise. 15111 (__arm_vqaddq_m_n_u16): Likewise. 15112 (__arm_vqaddq_m_s8): Likewise. 15113 (__arm_vqaddq_m_s32): Likewise. 15114 (__arm_vqaddq_m_s16): Likewise. 15115 (__arm_vqaddq_m_u8): Likewise. 15116 (__arm_vqaddq_m_u32): Likewise. 15117 (__arm_vqaddq_m_u16): Likewise. 15118 (__arm_vqdmladhq_m_s8): Likewise. 15119 (__arm_vqdmladhq_m_s32): Likewise. 15120 (__arm_vqdmladhq_m_s16): Likewise. 15121 (__arm_vqdmladhxq_m_s8): Likewise. 15122 (__arm_vqdmladhxq_m_s32): Likewise. 15123 (__arm_vqdmladhxq_m_s16): Likewise. 15124 (__arm_vqdmlahq_m_n_s8): Likewise. 15125 (__arm_vqdmlahq_m_n_s32): Likewise. 15126 (__arm_vqdmlahq_m_n_s16): Likewise. 15127 (__arm_vqdmlahq_m_n_u8): Likewise. 15128 (__arm_vqdmlahq_m_n_u32): Likewise. 15129 (__arm_vqdmlahq_m_n_u16): Likewise. 15130 (__arm_vqdmlsdhq_m_s8): Likewise. 15131 (__arm_vqdmlsdhq_m_s32): Likewise. 15132 (__arm_vqdmlsdhq_m_s16): Likewise. 15133 (__arm_vqdmlsdhxq_m_s8): Likewise. 15134 (__arm_vqdmlsdhxq_m_s32): Likewise. 15135 (__arm_vqdmlsdhxq_m_s16): Likewise. 15136 (__arm_vqdmulhq_m_n_s8): Likewise. 15137 (__arm_vqdmulhq_m_n_s32): Likewise. 15138 (__arm_vqdmulhq_m_n_s16): Likewise. 15139 (__arm_vqdmulhq_m_s8): Likewise. 15140 (__arm_vqdmulhq_m_s32): Likewise. 15141 (__arm_vqdmulhq_m_s16): Likewise. 15142 (__arm_vqrdmladhq_m_s8): Likewise. 15143 (__arm_vqrdmladhq_m_s32): Likewise. 15144 (__arm_vqrdmladhq_m_s16): Likewise. 15145 (__arm_vqrdmladhxq_m_s8): Likewise. 15146 (__arm_vqrdmladhxq_m_s32): Likewise. 15147 (__arm_vqrdmladhxq_m_s16): Likewise. 15148 (__arm_vqrdmlahq_m_n_s8): Likewise. 15149 (__arm_vqrdmlahq_m_n_s32): Likewise. 15150 (__arm_vqrdmlahq_m_n_s16): Likewise. 15151 (__arm_vqrdmlahq_m_n_u8): Likewise. 15152 (__arm_vqrdmlahq_m_n_u32): Likewise. 15153 (__arm_vqrdmlahq_m_n_u16): Likewise. 15154 (__arm_vqrdmlashq_m_n_s8): Likewise. 15155 (__arm_vqrdmlashq_m_n_s32): Likewise. 15156 (__arm_vqrdmlashq_m_n_s16): Likewise. 15157 (__arm_vqrdmlashq_m_n_u8): Likewise. 15158 (__arm_vqrdmlashq_m_n_u32): Likewise. 15159 (__arm_vqrdmlashq_m_n_u16): Likewise. 15160 (__arm_vqrdmlsdhq_m_s8): Likewise. 15161 (__arm_vqrdmlsdhq_m_s32): Likewise. 15162 (__arm_vqrdmlsdhq_m_s16): Likewise. 15163 (__arm_vqrdmlsdhxq_m_s8): Likewise. 15164 (__arm_vqrdmlsdhxq_m_s32): Likewise. 15165 (__arm_vqrdmlsdhxq_m_s16): Likewise. 15166 (__arm_vqrdmulhq_m_n_s8): Likewise. 15167 (__arm_vqrdmulhq_m_n_s32): Likewise. 15168 (__arm_vqrdmulhq_m_n_s16): Likewise. 15169 (__arm_vqrdmulhq_m_s8): Likewise. 15170 (__arm_vqrdmulhq_m_s32): Likewise. 15171 (__arm_vqrdmulhq_m_s16): Likewise. 15172 (__arm_vqrshlq_m_s8): Likewise. 15173 (__arm_vqrshlq_m_s32): Likewise. 15174 (__arm_vqrshlq_m_s16): Likewise. 15175 (__arm_vqrshlq_m_u8): Likewise. 15176 (__arm_vqrshlq_m_u32): Likewise. 15177 (__arm_vqrshlq_m_u16): Likewise. 15178 (__arm_vqshlq_m_n_s8): Likewise. 15179 (__arm_vqshlq_m_n_s32): Likewise. 15180 (__arm_vqshlq_m_n_s16): Likewise. 15181 (__arm_vqshlq_m_n_u8): Likewise. 15182 (__arm_vqshlq_m_n_u32): Likewise. 15183 (__arm_vqshlq_m_n_u16): Likewise. 15184 (__arm_vqshlq_m_s8): Likewise. 15185 (__arm_vqshlq_m_s32): Likewise. 15186 (__arm_vqshlq_m_s16): Likewise. 15187 (__arm_vqshlq_m_u8): Likewise. 15188 (__arm_vqshlq_m_u32): Likewise. 15189 (__arm_vqshlq_m_u16): Likewise. 15190 (__arm_vqsubq_m_n_s8): Likewise. 15191 (__arm_vqsubq_m_n_s32): Likewise. 15192 (__arm_vqsubq_m_n_s16): Likewise. 15193 (__arm_vqsubq_m_n_u8): Likewise. 15194 (__arm_vqsubq_m_n_u32): Likewise. 15195 (__arm_vqsubq_m_n_u16): Likewise. 15196 (__arm_vqsubq_m_s8): Likewise. 15197 (__arm_vqsubq_m_s32): Likewise. 15198 (__arm_vqsubq_m_s16): Likewise. 15199 (__arm_vqsubq_m_u8): Likewise. 15200 (__arm_vqsubq_m_u32): Likewise. 15201 (__arm_vqsubq_m_u16): Likewise. 15202 (__arm_vrhaddq_m_s8): Likewise. 15203 (__arm_vrhaddq_m_s32): Likewise. 15204 (__arm_vrhaddq_m_s16): Likewise. 15205 (__arm_vrhaddq_m_u8): Likewise. 15206 (__arm_vrhaddq_m_u32): Likewise. 15207 (__arm_vrhaddq_m_u16): Likewise. 15208 (__arm_vrmulhq_m_s8): Likewise. 15209 (__arm_vrmulhq_m_s32): Likewise. 15210 (__arm_vrmulhq_m_s16): Likewise. 15211 (__arm_vrmulhq_m_u8): Likewise. 15212 (__arm_vrmulhq_m_u32): Likewise. 15213 (__arm_vrmulhq_m_u16): Likewise. 15214 (__arm_vrshlq_m_s8): Likewise. 15215 (__arm_vrshlq_m_s32): Likewise. 15216 (__arm_vrshlq_m_s16): Likewise. 15217 (__arm_vrshlq_m_u8): Likewise. 15218 (__arm_vrshlq_m_u32): Likewise. 15219 (__arm_vrshlq_m_u16): Likewise. 15220 (__arm_vrshrq_m_n_s8): Likewise. 15221 (__arm_vrshrq_m_n_s32): Likewise. 15222 (__arm_vrshrq_m_n_s16): Likewise. 15223 (__arm_vrshrq_m_n_u8): Likewise. 15224 (__arm_vrshrq_m_n_u32): Likewise. 15225 (__arm_vrshrq_m_n_u16): Likewise. 15226 (__arm_vshlq_m_n_s8): Likewise. 15227 (__arm_vshlq_m_n_s32): Likewise. 15228 (__arm_vshlq_m_n_s16): Likewise. 15229 (__arm_vshlq_m_n_u8): Likewise. 15230 (__arm_vshlq_m_n_u32): Likewise. 15231 (__arm_vshlq_m_n_u16): Likewise. 15232 (__arm_vshrq_m_n_s8): Likewise. 15233 (__arm_vshrq_m_n_s32): Likewise. 15234 (__arm_vshrq_m_n_s16): Likewise. 15235 (__arm_vshrq_m_n_u8): Likewise. 15236 (__arm_vshrq_m_n_u32): Likewise. 15237 (__arm_vshrq_m_n_u16): Likewise. 15238 (__arm_vsliq_m_n_s8): Likewise. 15239 (__arm_vsliq_m_n_s32): Likewise. 15240 (__arm_vsliq_m_n_s16): Likewise. 15241 (__arm_vsliq_m_n_u8): Likewise. 15242 (__arm_vsliq_m_n_u32): Likewise. 15243 (__arm_vsliq_m_n_u16): Likewise. 15244 (__arm_vsubq_m_n_s8): Likewise. 15245 (__arm_vsubq_m_n_s32): Likewise. 15246 (__arm_vsubq_m_n_s16): Likewise. 15247 (__arm_vsubq_m_n_u8): Likewise. 15248 (__arm_vsubq_m_n_u32): Likewise. 15249 (__arm_vsubq_m_n_u16): Likewise. 15250 (vqdmladhq_m): Define polymorphic variant. 15251 (vqdmladhxq_m): Likewise. 15252 (vqdmlsdhq_m): Likewise. 15253 (vqdmlsdhxq_m): Likewise. 15254 (vabdq_m): Likewise. 15255 (vandq_m): Likewise. 15256 (vbicq_m): Likewise. 15257 (vbrsrq_m_n): Likewise. 15258 (vcaddq_rot270_m): Likewise. 15259 (vcaddq_rot90_m): Likewise. 15260 (veorq_m): Likewise. 15261 (vmaxq_m): Likewise. 15262 (vminq_m): Likewise. 15263 (vmladavaq_p): Likewise. 15264 (vmlaq_m_n): Likewise. 15265 (vmlasq_m_n): Likewise. 15266 (vmulhq_m): Likewise. 15267 (vmullbq_int_m): Likewise. 15268 (vmulltq_int_m): Likewise. 15269 (vornq_m): Likewise. 15270 (vorrq_m): Likewise. 15271 (vqdmlahq_m_n): Likewise. 15272 (vqrdmlahq_m_n): Likewise. 15273 (vqrdmlashq_m_n): Likewise. 15274 (vqrshlq_m): Likewise. 15275 (vqshlq_m_n): Likewise. 15276 (vqshlq_m): Likewise. 15277 (vrhaddq_m): Likewise. 15278 (vrmulhq_m): Likewise. 15279 (vrshlq_m): Likewise. 15280 (vrshrq_m_n): Likewise. 15281 (vshlq_m_n): Likewise. 15282 (vshrq_m_n): Likewise. 15283 (vsliq_m): Likewise. 15284 (vaddq_m_n): Likewise. 15285 (vaddq_m): Likewise. 15286 (vhaddq_m_n): Likewise. 15287 (vhaddq_m): Likewise. 15288 (vhcaddq_rot270_m): Likewise. 15289 (vhcaddq_rot90_m): Likewise. 15290 (vhsubq_m): Likewise. 15291 (vhsubq_m_n): Likewise. 15292 (vmulq_m_n): Likewise. 15293 (vmulq_m): Likewise. 15294 (vqaddq_m_n): Likewise. 15295 (vqaddq_m): Likewise. 15296 (vqdmulhq_m_n): Likewise. 15297 (vqdmulhq_m): Likewise. 15298 (vsubq_m_n): Likewise. 15299 (vsliq_m_n): Likewise. 15300 (vqsubq_m_n): Likewise. 15301 (vqsubq_m): Likewise. 15302 (vqrdmulhq_m): Likewise. 15303 (vqrdmulhq_m_n): Likewise. 15304 (vqrdmlsdhxq_m): Likewise. 15305 (vqrdmlsdhq_m): Likewise. 15306 (vqrdmladhq_m): Likewise. 15307 (vqrdmladhxq_m): Likewise. 15308 (vmlsdavaxq_p): Likewise. 15309 (vmlsdavaq_p): Likewise. 15310 (vmladavaxq_p): Likewise. 15311 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use 15312 builtin qualifier. 15313 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. 15314 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. 15315 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. 15316 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. 15317 * config/arm/mve.md (VHSUBQ_M): Define iterators. 15318 (VSLIQ_M_N): Likewise. 15319 (VQRDMLAHQ_M_N): Likewise. 15320 (VRSHLQ_M): Likewise. 15321 (VMINQ_M): Likewise. 15322 (VMULLBQ_INT_M): Likewise. 15323 (VMULHQ_M): Likewise. 15324 (VMULQ_M): Likewise. 15325 (VHSUBQ_M_N): Likewise. 15326 (VHADDQ_M_N): Likewise. 15327 (VORRQ_M): Likewise. 15328 (VRMULHQ_M): Likewise. 15329 (VQADDQ_M): Likewise. 15330 (VRSHRQ_M_N): Likewise. 15331 (VQSUBQ_M_N): Likewise. 15332 (VADDQ_M): Likewise. 15333 (VORNQ_M): Likewise. 15334 (VQDMLAHQ_M_N): Likewise. 15335 (VRHADDQ_M): Likewise. 15336 (VQSHLQ_M): Likewise. 15337 (VANDQ_M): Likewise. 15338 (VBICQ_M): Likewise. 15339 (VSHLQ_M_N): Likewise. 15340 (VCADDQ_ROT270_M): Likewise. 15341 (VQRSHLQ_M): Likewise. 15342 (VQADDQ_M_N): Likewise. 15343 (VADDQ_M_N): Likewise. 15344 (VMAXQ_M): Likewise. 15345 (VQSUBQ_M): Likewise. 15346 (VMLASQ_M_N): Likewise. 15347 (VMLADAVAQ_P): Likewise. 15348 (VBRSRQ_M_N): Likewise. 15349 (VMULQ_M_N): Likewise. 15350 (VCADDQ_ROT90_M): Likewise. 15351 (VMULLTQ_INT_M): Likewise. 15352 (VEORQ_M): Likewise. 15353 (VSHRQ_M_N): Likewise. 15354 (VSUBQ_M_N): Likewise. 15355 (VHADDQ_M): Likewise. 15356 (VABDQ_M): Likewise. 15357 (VQRDMLASHQ_M_N): Likewise. 15358 (VMLAQ_M_N): Likewise. 15359 (VQSHLQ_M_N): Likewise. 15360 (mve_vabdq_m_<supf><mode>): Define RTL pattern. 15361 (mve_vaddq_m_n_<supf><mode>): Likewise. 15362 (mve_vaddq_m_<supf><mode>): Likewise. 15363 (mve_vandq_m_<supf><mode>): Likewise. 15364 (mve_vbicq_m_<supf><mode>): Likewise. 15365 (mve_vbrsrq_m_n_<supf><mode>): Likewise. 15366 (mve_vcaddq_rot270_m_<supf><mode>): Likewise. 15367 (mve_vcaddq_rot90_m_<supf><mode>): Likewise. 15368 (mve_veorq_m_<supf><mode>): Likewise. 15369 (mve_vhaddq_m_n_<supf><mode>): Likewise. 15370 (mve_vhaddq_m_<supf><mode>): Likewise. 15371 (mve_vhsubq_m_n_<supf><mode>): Likewise. 15372 (mve_vhsubq_m_<supf><mode>): Likewise. 15373 (mve_vmaxq_m_<supf><mode>): Likewise. 15374 (mve_vminq_m_<supf><mode>): Likewise. 15375 (mve_vmladavaq_p_<supf><mode>): Likewise. 15376 (mve_vmlaq_m_n_<supf><mode>): Likewise. 15377 (mve_vmlasq_m_n_<supf><mode>): Likewise. 15378 (mve_vmulhq_m_<supf><mode>): Likewise. 15379 (mve_vmullbq_int_m_<supf><mode>): Likewise. 15380 (mve_vmulltq_int_m_<supf><mode>): Likewise. 15381 (mve_vmulq_m_n_<supf><mode>): Likewise. 15382 (mve_vmulq_m_<supf><mode>): Likewise. 15383 (mve_vornq_m_<supf><mode>): Likewise. 15384 (mve_vorrq_m_<supf><mode>): Likewise. 15385 (mve_vqaddq_m_n_<supf><mode>): Likewise. 15386 (mve_vqaddq_m_<supf><mode>): Likewise. 15387 (mve_vqdmlahq_m_n_<supf><mode>): Likewise. 15388 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise. 15389 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise. 15390 (mve_vqrshlq_m_<supf><mode>): Likewise. 15391 (mve_vqshlq_m_n_<supf><mode>): Likewise. 15392 (mve_vqshlq_m_<supf><mode>): Likewise. 15393 (mve_vqsubq_m_n_<supf><mode>): Likewise. 15394 (mve_vqsubq_m_<supf><mode>): Likewise. 15395 (mve_vrhaddq_m_<supf><mode>): Likewise. 15396 (mve_vrmulhq_m_<supf><mode>): Likewise. 15397 (mve_vrshlq_m_<supf><mode>): Likewise. 15398 (mve_vrshrq_m_n_<supf><mode>): Likewise. 15399 (mve_vshlq_m_n_<supf><mode>): Likewise. 15400 (mve_vshrq_m_n_<supf><mode>): Likewise. 15401 (mve_vsliq_m_n_<supf><mode>): Likewise. 15402 (mve_vsubq_m_n_<supf><mode>): Likewise. 15403 (mve_vhcaddq_rot270_m_s<mode>): Likewise. 15404 (mve_vhcaddq_rot90_m_s<mode>): Likewise. 15405 (mve_vmladavaxq_p_s<mode>): Likewise. 15406 (mve_vmlsdavaq_p_s<mode>): Likewise. 15407 (mve_vmlsdavaxq_p_s<mode>): Likewise. 15408 (mve_vqdmladhq_m_s<mode>): Likewise. 15409 (mve_vqdmladhxq_m_s<mode>): Likewise. 15410 (mve_vqdmlsdhq_m_s<mode>): Likewise. 15411 (mve_vqdmlsdhxq_m_s<mode>): Likewise. 15412 (mve_vqdmulhq_m_n_s<mode>): Likewise. 15413 (mve_vqdmulhq_m_s<mode>): Likewise. 15414 (mve_vqrdmladhq_m_s<mode>): Likewise. 15415 (mve_vqrdmladhxq_m_s<mode>): Likewise. 15416 (mve_vqrdmlsdhq_m_s<mode>): Likewise. 15417 (mve_vqrdmlsdhxq_m_s<mode>): Likewise. 15418 (mve_vqrdmulhq_m_n_s<mode>): Likewise. 15419 (mve_vqrdmulhq_m_s<mode>): Likewise. 15420 154212020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 15422 Mihail Ionescu <mihail.ionescu@arm.com> 15423 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 15424 15425 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): 15426 Define builtin qualifier. 15427 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 15428 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 15429 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 15430 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 15431 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 15432 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 15433 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 15434 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. 15435 (vsubq_m_s8): Likewise. 15436 (vcvtq_m_n_f16_u16): Likewise. 15437 (vqshluq_m_n_s8): Likewise. 15438 (vabavq_p_s8): Likewise. 15439 (vsriq_m_n_u8): Likewise. 15440 (vshlq_m_u8): Likewise. 15441 (vsubq_m_u8): Likewise. 15442 (vabavq_p_u8): Likewise. 15443 (vshlq_m_s8): Likewise. 15444 (vcvtq_m_n_f16_s16): Likewise. 15445 (vsriq_m_n_s16): Likewise. 15446 (vsubq_m_s16): Likewise. 15447 (vcvtq_m_n_f32_u32): Likewise. 15448 (vqshluq_m_n_s16): Likewise. 15449 (vabavq_p_s16): Likewise. 15450 (vsriq_m_n_u16): Likewise. 15451 (vshlq_m_u16): Likewise. 15452 (vsubq_m_u16): Likewise. 15453 (vabavq_p_u16): Likewise. 15454 (vshlq_m_s16): Likewise. 15455 (vcvtq_m_n_f32_s32): Likewise. 15456 (vsriq_m_n_s32): Likewise. 15457 (vsubq_m_s32): Likewise. 15458 (vqshluq_m_n_s32): Likewise. 15459 (vabavq_p_s32): Likewise. 15460 (vsriq_m_n_u32): Likewise. 15461 (vshlq_m_u32): Likewise. 15462 (vsubq_m_u32): Likewise. 15463 (vabavq_p_u32): Likewise. 15464 (vshlq_m_s32): Likewise. 15465 (__arm_vsriq_m_n_s8): Define intrinsic. 15466 (__arm_vsubq_m_s8): Likewise. 15467 (__arm_vqshluq_m_n_s8): Likewise. 15468 (__arm_vabavq_p_s8): Likewise. 15469 (__arm_vsriq_m_n_u8): Likewise. 15470 (__arm_vshlq_m_u8): Likewise. 15471 (__arm_vsubq_m_u8): Likewise. 15472 (__arm_vabavq_p_u8): Likewise. 15473 (__arm_vshlq_m_s8): Likewise. 15474 (__arm_vsriq_m_n_s16): Likewise. 15475 (__arm_vsubq_m_s16): Likewise. 15476 (__arm_vqshluq_m_n_s16): Likewise. 15477 (__arm_vabavq_p_s16): Likewise. 15478 (__arm_vsriq_m_n_u16): Likewise. 15479 (__arm_vshlq_m_u16): Likewise. 15480 (__arm_vsubq_m_u16): Likewise. 15481 (__arm_vabavq_p_u16): Likewise. 15482 (__arm_vshlq_m_s16): Likewise. 15483 (__arm_vsriq_m_n_s32): Likewise. 15484 (__arm_vsubq_m_s32): Likewise. 15485 (__arm_vqshluq_m_n_s32): Likewise. 15486 (__arm_vabavq_p_s32): Likewise. 15487 (__arm_vsriq_m_n_u32): Likewise. 15488 (__arm_vshlq_m_u32): Likewise. 15489 (__arm_vsubq_m_u32): Likewise. 15490 (__arm_vabavq_p_u32): Likewise. 15491 (__arm_vshlq_m_s32): Likewise. 15492 (__arm_vcvtq_m_n_f16_u16): Likewise. 15493 (__arm_vcvtq_m_n_f16_s16): Likewise. 15494 (__arm_vcvtq_m_n_f32_u32): Likewise. 15495 (__arm_vcvtq_m_n_f32_s32): Likewise. 15496 (vcvtq_m_n): Define polymorphic variant. 15497 (vqshluq_m_n): Likewise. 15498 (vshlq_m): Likewise. 15499 (vsriq_m_n): Likewise. 15500 (vsubq_m): Likewise. 15501 (vabavq_p): Likewise. 15502 * config/arm/arm_mve_builtins.def 15503 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. 15504 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 15505 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 15506 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 15507 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 15508 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 15509 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 15510 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 15511 * config/arm/mve.md (VABAVQ_P): Define iterator. 15512 (VSHLQ_M): Likewise. 15513 (VSRIQ_M_N): Likewise. 15514 (VSUBQ_M): Likewise. 15515 (VCVTQ_M_N_TO_F): Likewise. 15516 (mve_vabavq_p_<supf><mode>): Define RTL pattern. 15517 (mve_vqshluq_m_n_s<mode>): Likewise. 15518 (mve_vshlq_m_<supf><mode>): Likewise. 15519 (mve_vsriq_m_n_<supf><mode>): Likewise. 15520 (mve_vsubq_m_<supf><mode>): Likewise. 15521 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise. 15522 155232020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 15524 Mihail Ionescu <mihail.ionescu@arm.com> 15525 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 15526 15527 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. 15528 (vrmlsldavhaq_s32): Likewise. 15529 (vrmlsldavhaxq_s32): Likewise. 15530 (vaddlvaq_p_s32): Likewise. 15531 (vcvtbq_m_f16_f32): Likewise. 15532 (vcvtbq_m_f32_f16): Likewise. 15533 (vcvttq_m_f16_f32): Likewise. 15534 (vcvttq_m_f32_f16): Likewise. 15535 (vrev16q_m_s8): Likewise. 15536 (vrev32q_m_f16): Likewise. 15537 (vrmlaldavhq_p_s32): Likewise. 15538 (vrmlaldavhxq_p_s32): Likewise. 15539 (vrmlsldavhq_p_s32): Likewise. 15540 (vrmlsldavhxq_p_s32): Likewise. 15541 (vaddlvaq_p_u32): Likewise. 15542 (vrev16q_m_u8): Likewise. 15543 (vrmlaldavhq_p_u32): Likewise. 15544 (vmvnq_m_n_s16): Likewise. 15545 (vorrq_m_n_s16): Likewise. 15546 (vqrshrntq_n_s16): Likewise. 15547 (vqshrnbq_n_s16): Likewise. 15548 (vqshrntq_n_s16): Likewise. 15549 (vrshrnbq_n_s16): Likewise. 15550 (vrshrntq_n_s16): Likewise. 15551 (vshrnbq_n_s16): Likewise. 15552 (vshrntq_n_s16): Likewise. 15553 (vcmlaq_f16): Likewise. 15554 (vcmlaq_rot180_f16): Likewise. 15555 (vcmlaq_rot270_f16): Likewise. 15556 (vcmlaq_rot90_f16): Likewise. 15557 (vfmaq_f16): Likewise. 15558 (vfmaq_n_f16): Likewise. 15559 (vfmasq_n_f16): Likewise. 15560 (vfmsq_f16): Likewise. 15561 (vmlaldavaq_s16): Likewise. 15562 (vmlaldavaxq_s16): Likewise. 15563 (vmlsldavaq_s16): Likewise. 15564 (vmlsldavaxq_s16): Likewise. 15565 (vabsq_m_f16): Likewise. 15566 (vcvtmq_m_s16_f16): Likewise. 15567 (vcvtnq_m_s16_f16): Likewise. 15568 (vcvtpq_m_s16_f16): Likewise. 15569 (vcvtq_m_s16_f16): Likewise. 15570 (vdupq_m_n_f16): Likewise. 15571 (vmaxnmaq_m_f16): Likewise. 15572 (vmaxnmavq_p_f16): Likewise. 15573 (vmaxnmvq_p_f16): Likewise. 15574 (vminnmaq_m_f16): Likewise. 15575 (vminnmavq_p_f16): Likewise. 15576 (vminnmvq_p_f16): Likewise. 15577 (vmlaldavq_p_s16): Likewise. 15578 (vmlaldavxq_p_s16): Likewise. 15579 (vmlsldavq_p_s16): Likewise. 15580 (vmlsldavxq_p_s16): Likewise. 15581 (vmovlbq_m_s8): Likewise. 15582 (vmovltq_m_s8): Likewise. 15583 (vmovnbq_m_s16): Likewise. 15584 (vmovntq_m_s16): Likewise. 15585 (vnegq_m_f16): Likewise. 15586 (vpselq_f16): Likewise. 15587 (vqmovnbq_m_s16): Likewise. 15588 (vqmovntq_m_s16): Likewise. 15589 (vrev32q_m_s8): Likewise. 15590 (vrev64q_m_f16): Likewise. 15591 (vrndaq_m_f16): Likewise. 15592 (vrndmq_m_f16): Likewise. 15593 (vrndnq_m_f16): Likewise. 15594 (vrndpq_m_f16): Likewise. 15595 (vrndq_m_f16): Likewise. 15596 (vrndxq_m_f16): Likewise. 15597 (vcmpeqq_m_n_f16): Likewise. 15598 (vcmpgeq_m_f16): Likewise. 15599 (vcmpgeq_m_n_f16): Likewise. 15600 (vcmpgtq_m_f16): Likewise. 15601 (vcmpgtq_m_n_f16): Likewise. 15602 (vcmpleq_m_f16): Likewise. 15603 (vcmpleq_m_n_f16): Likewise. 15604 (vcmpltq_m_f16): Likewise. 15605 (vcmpltq_m_n_f16): Likewise. 15606 (vcmpneq_m_f16): Likewise. 15607 (vcmpneq_m_n_f16): Likewise. 15608 (vmvnq_m_n_u16): Likewise. 15609 (vorrq_m_n_u16): Likewise. 15610 (vqrshruntq_n_s16): Likewise. 15611 (vqshrunbq_n_s16): Likewise. 15612 (vqshruntq_n_s16): Likewise. 15613 (vcvtmq_m_u16_f16): Likewise. 15614 (vcvtnq_m_u16_f16): Likewise. 15615 (vcvtpq_m_u16_f16): Likewise. 15616 (vcvtq_m_u16_f16): Likewise. 15617 (vqmovunbq_m_s16): Likewise. 15618 (vqmovuntq_m_s16): Likewise. 15619 (vqrshrntq_n_u16): Likewise. 15620 (vqshrnbq_n_u16): Likewise. 15621 (vqshrntq_n_u16): Likewise. 15622 (vrshrnbq_n_u16): Likewise. 15623 (vrshrntq_n_u16): Likewise. 15624 (vshrnbq_n_u16): Likewise. 15625 (vshrntq_n_u16): Likewise. 15626 (vmlaldavaq_u16): Likewise. 15627 (vmlaldavaxq_u16): Likewise. 15628 (vmlaldavq_p_u16): Likewise. 15629 (vmlaldavxq_p_u16): Likewise. 15630 (vmovlbq_m_u8): Likewise. 15631 (vmovltq_m_u8): Likewise. 15632 (vmovnbq_m_u16): Likewise. 15633 (vmovntq_m_u16): Likewise. 15634 (vqmovnbq_m_u16): Likewise. 15635 (vqmovntq_m_u16): Likewise. 15636 (vrev32q_m_u8): Likewise. 15637 (vmvnq_m_n_s32): Likewise. 15638 (vorrq_m_n_s32): Likewise. 15639 (vqrshrntq_n_s32): Likewise. 15640 (vqshrnbq_n_s32): Likewise. 15641 (vqshrntq_n_s32): Likewise. 15642 (vrshrnbq_n_s32): Likewise. 15643 (vrshrntq_n_s32): Likewise. 15644 (vshrnbq_n_s32): Likewise. 15645 (vshrntq_n_s32): Likewise. 15646 (vcmlaq_f32): Likewise. 15647 (vcmlaq_rot180_f32): Likewise. 15648 (vcmlaq_rot270_f32): Likewise. 15649 (vcmlaq_rot90_f32): Likewise. 15650 (vfmaq_f32): Likewise. 15651 (vfmaq_n_f32): Likewise. 15652 (vfmasq_n_f32): Likewise. 15653 (vfmsq_f32): Likewise. 15654 (vmlaldavaq_s32): Likewise. 15655 (vmlaldavaxq_s32): Likewise. 15656 (vmlsldavaq_s32): Likewise. 15657 (vmlsldavaxq_s32): Likewise. 15658 (vabsq_m_f32): Likewise. 15659 (vcvtmq_m_s32_f32): Likewise. 15660 (vcvtnq_m_s32_f32): Likewise. 15661 (vcvtpq_m_s32_f32): Likewise. 15662 (vcvtq_m_s32_f32): Likewise. 15663 (vdupq_m_n_f32): Likewise. 15664 (vmaxnmaq_m_f32): Likewise. 15665 (vmaxnmavq_p_f32): Likewise. 15666 (vmaxnmvq_p_f32): Likewise. 15667 (vminnmaq_m_f32): Likewise. 15668 (vminnmavq_p_f32): Likewise. 15669 (vminnmvq_p_f32): Likewise. 15670 (vmlaldavq_p_s32): Likewise. 15671 (vmlaldavxq_p_s32): Likewise. 15672 (vmlsldavq_p_s32): Likewise. 15673 (vmlsldavxq_p_s32): Likewise. 15674 (vmovlbq_m_s16): Likewise. 15675 (vmovltq_m_s16): Likewise. 15676 (vmovnbq_m_s32): Likewise. 15677 (vmovntq_m_s32): Likewise. 15678 (vnegq_m_f32): Likewise. 15679 (vpselq_f32): Likewise. 15680 (vqmovnbq_m_s32): Likewise. 15681 (vqmovntq_m_s32): Likewise. 15682 (vrev32q_m_s16): Likewise. 15683 (vrev64q_m_f32): Likewise. 15684 (vrndaq_m_f32): Likewise. 15685 (vrndmq_m_f32): Likewise. 15686 (vrndnq_m_f32): Likewise. 15687 (vrndpq_m_f32): Likewise. 15688 (vrndq_m_f32): Likewise. 15689 (vrndxq_m_f32): Likewise. 15690 (vcmpeqq_m_n_f32): Likewise. 15691 (vcmpgeq_m_f32): Likewise. 15692 (vcmpgeq_m_n_f32): Likewise. 15693 (vcmpgtq_m_f32): Likewise. 15694 (vcmpgtq_m_n_f32): Likewise. 15695 (vcmpleq_m_f32): Likewise. 15696 (vcmpleq_m_n_f32): Likewise. 15697 (vcmpltq_m_f32): Likewise. 15698 (vcmpltq_m_n_f32): Likewise. 15699 (vcmpneq_m_f32): Likewise. 15700 (vcmpneq_m_n_f32): Likewise. 15701 (vmvnq_m_n_u32): Likewise. 15702 (vorrq_m_n_u32): Likewise. 15703 (vqrshruntq_n_s32): Likewise. 15704 (vqshrunbq_n_s32): Likewise. 15705 (vqshruntq_n_s32): Likewise. 15706 (vcvtmq_m_u32_f32): Likewise. 15707 (vcvtnq_m_u32_f32): Likewise. 15708 (vcvtpq_m_u32_f32): Likewise. 15709 (vcvtq_m_u32_f32): Likewise. 15710 (vqmovunbq_m_s32): Likewise. 15711 (vqmovuntq_m_s32): Likewise. 15712 (vqrshrntq_n_u32): Likewise. 15713 (vqshrnbq_n_u32): Likewise. 15714 (vqshrntq_n_u32): Likewise. 15715 (vrshrnbq_n_u32): Likewise. 15716 (vrshrntq_n_u32): Likewise. 15717 (vshrnbq_n_u32): Likewise. 15718 (vshrntq_n_u32): Likewise. 15719 (vmlaldavaq_u32): Likewise. 15720 (vmlaldavaxq_u32): Likewise. 15721 (vmlaldavq_p_u32): Likewise. 15722 (vmlaldavxq_p_u32): Likewise. 15723 (vmovlbq_m_u16): Likewise. 15724 (vmovltq_m_u16): Likewise. 15725 (vmovnbq_m_u32): Likewise. 15726 (vmovntq_m_u32): Likewise. 15727 (vqmovnbq_m_u32): Likewise. 15728 (vqmovntq_m_u32): Likewise. 15729 (vrev32q_m_u16): Likewise. 15730 (__arm_vrmlaldavhaxq_s32): Define intrinsic. 15731 (__arm_vrmlsldavhaq_s32): Likewise. 15732 (__arm_vrmlsldavhaxq_s32): Likewise. 15733 (__arm_vaddlvaq_p_s32): Likewise. 15734 (__arm_vrev16q_m_s8): Likewise. 15735 (__arm_vrmlaldavhq_p_s32): Likewise. 15736 (__arm_vrmlaldavhxq_p_s32): Likewise. 15737 (__arm_vrmlsldavhq_p_s32): Likewise. 15738 (__arm_vrmlsldavhxq_p_s32): Likewise. 15739 (__arm_vaddlvaq_p_u32): Likewise. 15740 (__arm_vrev16q_m_u8): Likewise. 15741 (__arm_vrmlaldavhq_p_u32): Likewise. 15742 (__arm_vmvnq_m_n_s16): Likewise. 15743 (__arm_vorrq_m_n_s16): Likewise. 15744 (__arm_vqrshrntq_n_s16): Likewise. 15745 (__arm_vqshrnbq_n_s16): Likewise. 15746 (__arm_vqshrntq_n_s16): Likewise. 15747 (__arm_vrshrnbq_n_s16): Likewise. 15748 (__arm_vrshrntq_n_s16): Likewise. 15749 (__arm_vshrnbq_n_s16): Likewise. 15750 (__arm_vshrntq_n_s16): Likewise. 15751 (__arm_vmlaldavaq_s16): Likewise. 15752 (__arm_vmlaldavaxq_s16): Likewise. 15753 (__arm_vmlsldavaq_s16): Likewise. 15754 (__arm_vmlsldavaxq_s16): Likewise. 15755 (__arm_vmlaldavq_p_s16): Likewise. 15756 (__arm_vmlaldavxq_p_s16): Likewise. 15757 (__arm_vmlsldavq_p_s16): Likewise. 15758 (__arm_vmlsldavxq_p_s16): Likewise. 15759 (__arm_vmovlbq_m_s8): Likewise. 15760 (__arm_vmovltq_m_s8): Likewise. 15761 (__arm_vmovnbq_m_s16): Likewise. 15762 (__arm_vmovntq_m_s16): Likewise. 15763 (__arm_vqmovnbq_m_s16): Likewise. 15764 (__arm_vqmovntq_m_s16): Likewise. 15765 (__arm_vrev32q_m_s8): Likewise. 15766 (__arm_vmvnq_m_n_u16): Likewise. 15767 (__arm_vorrq_m_n_u16): Likewise. 15768 (__arm_vqrshruntq_n_s16): Likewise. 15769 (__arm_vqshrunbq_n_s16): Likewise. 15770 (__arm_vqshruntq_n_s16): Likewise. 15771 (__arm_vqmovunbq_m_s16): Likewise. 15772 (__arm_vqmovuntq_m_s16): Likewise. 15773 (__arm_vqrshrntq_n_u16): Likewise. 15774 (__arm_vqshrnbq_n_u16): Likewise. 15775 (__arm_vqshrntq_n_u16): Likewise. 15776 (__arm_vrshrnbq_n_u16): Likewise. 15777 (__arm_vrshrntq_n_u16): Likewise. 15778 (__arm_vshrnbq_n_u16): Likewise. 15779 (__arm_vshrntq_n_u16): Likewise. 15780 (__arm_vmlaldavaq_u16): Likewise. 15781 (__arm_vmlaldavaxq_u16): Likewise. 15782 (__arm_vmlaldavq_p_u16): Likewise. 15783 (__arm_vmlaldavxq_p_u16): Likewise. 15784 (__arm_vmovlbq_m_u8): Likewise. 15785 (__arm_vmovltq_m_u8): Likewise. 15786 (__arm_vmovnbq_m_u16): Likewise. 15787 (__arm_vmovntq_m_u16): Likewise. 15788 (__arm_vqmovnbq_m_u16): Likewise. 15789 (__arm_vqmovntq_m_u16): Likewise. 15790 (__arm_vrev32q_m_u8): Likewise. 15791 (__arm_vmvnq_m_n_s32): Likewise. 15792 (__arm_vorrq_m_n_s32): Likewise. 15793 (__arm_vqrshrntq_n_s32): Likewise. 15794 (__arm_vqshrnbq_n_s32): Likewise. 15795 (__arm_vqshrntq_n_s32): Likewise. 15796 (__arm_vrshrnbq_n_s32): Likewise. 15797 (__arm_vrshrntq_n_s32): Likewise. 15798 (__arm_vshrnbq_n_s32): Likewise. 15799 (__arm_vshrntq_n_s32): Likewise. 15800 (__arm_vmlaldavaq_s32): Likewise. 15801 (__arm_vmlaldavaxq_s32): Likewise. 15802 (__arm_vmlsldavaq_s32): Likewise. 15803 (__arm_vmlsldavaxq_s32): Likewise. 15804 (__arm_vmlaldavq_p_s32): Likewise. 15805 (__arm_vmlaldavxq_p_s32): Likewise. 15806 (__arm_vmlsldavq_p_s32): Likewise. 15807 (__arm_vmlsldavxq_p_s32): Likewise. 15808 (__arm_vmovlbq_m_s16): Likewise. 15809 (__arm_vmovltq_m_s16): Likewise. 15810 (__arm_vmovnbq_m_s32): Likewise. 15811 (__arm_vmovntq_m_s32): Likewise. 15812 (__arm_vqmovnbq_m_s32): Likewise. 15813 (__arm_vqmovntq_m_s32): Likewise. 15814 (__arm_vrev32q_m_s16): Likewise. 15815 (__arm_vmvnq_m_n_u32): Likewise. 15816 (__arm_vorrq_m_n_u32): Likewise. 15817 (__arm_vqrshruntq_n_s32): Likewise. 15818 (__arm_vqshrunbq_n_s32): Likewise. 15819 (__arm_vqshruntq_n_s32): Likewise. 15820 (__arm_vqmovunbq_m_s32): Likewise. 15821 (__arm_vqmovuntq_m_s32): Likewise. 15822 (__arm_vqrshrntq_n_u32): Likewise. 15823 (__arm_vqshrnbq_n_u32): Likewise. 15824 (__arm_vqshrntq_n_u32): Likewise. 15825 (__arm_vrshrnbq_n_u32): Likewise. 15826 (__arm_vrshrntq_n_u32): Likewise. 15827 (__arm_vshrnbq_n_u32): Likewise. 15828 (__arm_vshrntq_n_u32): Likewise. 15829 (__arm_vmlaldavaq_u32): Likewise. 15830 (__arm_vmlaldavaxq_u32): Likewise. 15831 (__arm_vmlaldavq_p_u32): Likewise. 15832 (__arm_vmlaldavxq_p_u32): Likewise. 15833 (__arm_vmovlbq_m_u16): Likewise. 15834 (__arm_vmovltq_m_u16): Likewise. 15835 (__arm_vmovnbq_m_u32): Likewise. 15836 (__arm_vmovntq_m_u32): Likewise. 15837 (__arm_vqmovnbq_m_u32): Likewise. 15838 (__arm_vqmovntq_m_u32): Likewise. 15839 (__arm_vrev32q_m_u16): Likewise. 15840 (__arm_vcvtbq_m_f16_f32): Likewise. 15841 (__arm_vcvtbq_m_f32_f16): Likewise. 15842 (__arm_vcvttq_m_f16_f32): Likewise. 15843 (__arm_vcvttq_m_f32_f16): Likewise. 15844 (__arm_vrev32q_m_f16): Likewise. 15845 (__arm_vcmlaq_f16): Likewise. 15846 (__arm_vcmlaq_rot180_f16): Likewise. 15847 (__arm_vcmlaq_rot270_f16): Likewise. 15848 (__arm_vcmlaq_rot90_f16): Likewise. 15849 (__arm_vfmaq_f16): Likewise. 15850 (__arm_vfmaq_n_f16): Likewise. 15851 (__arm_vfmasq_n_f16): Likewise. 15852 (__arm_vfmsq_f16): Likewise. 15853 (__arm_vabsq_m_f16): Likewise. 15854 (__arm_vcvtmq_m_s16_f16): Likewise. 15855 (__arm_vcvtnq_m_s16_f16): Likewise. 15856 (__arm_vcvtpq_m_s16_f16): Likewise. 15857 (__arm_vcvtq_m_s16_f16): Likewise. 15858 (__arm_vdupq_m_n_f16): Likewise. 15859 (__arm_vmaxnmaq_m_f16): Likewise. 15860 (__arm_vmaxnmavq_p_f16): Likewise. 15861 (__arm_vmaxnmvq_p_f16): Likewise. 15862 (__arm_vminnmaq_m_f16): Likewise. 15863 (__arm_vminnmavq_p_f16): Likewise. 15864 (__arm_vminnmvq_p_f16): Likewise. 15865 (__arm_vnegq_m_f16): Likewise. 15866 (__arm_vpselq_f16): Likewise. 15867 (__arm_vrev64q_m_f16): Likewise. 15868 (__arm_vrndaq_m_f16): Likewise. 15869 (__arm_vrndmq_m_f16): Likewise. 15870 (__arm_vrndnq_m_f16): Likewise. 15871 (__arm_vrndpq_m_f16): Likewise. 15872 (__arm_vrndq_m_f16): Likewise. 15873 (__arm_vrndxq_m_f16): Likewise. 15874 (__arm_vcmpeqq_m_n_f16): Likewise. 15875 (__arm_vcmpgeq_m_f16): Likewise. 15876 (__arm_vcmpgeq_m_n_f16): Likewise. 15877 (__arm_vcmpgtq_m_f16): Likewise. 15878 (__arm_vcmpgtq_m_n_f16): Likewise. 15879 (__arm_vcmpleq_m_f16): Likewise. 15880 (__arm_vcmpleq_m_n_f16): Likewise. 15881 (__arm_vcmpltq_m_f16): Likewise. 15882 (__arm_vcmpltq_m_n_f16): Likewise. 15883 (__arm_vcmpneq_m_f16): Likewise. 15884 (__arm_vcmpneq_m_n_f16): Likewise. 15885 (__arm_vcvtmq_m_u16_f16): Likewise. 15886 (__arm_vcvtnq_m_u16_f16): Likewise. 15887 (__arm_vcvtpq_m_u16_f16): Likewise. 15888 (__arm_vcvtq_m_u16_f16): Likewise. 15889 (__arm_vcmlaq_f32): Likewise. 15890 (__arm_vcmlaq_rot180_f32): Likewise. 15891 (__arm_vcmlaq_rot270_f32): Likewise. 15892 (__arm_vcmlaq_rot90_f32): Likewise. 15893 (__arm_vfmaq_f32): Likewise. 15894 (__arm_vfmaq_n_f32): Likewise. 15895 (__arm_vfmasq_n_f32): Likewise. 15896 (__arm_vfmsq_f32): Likewise. 15897 (__arm_vabsq_m_f32): Likewise. 15898 (__arm_vcvtmq_m_s32_f32): Likewise. 15899 (__arm_vcvtnq_m_s32_f32): Likewise. 15900 (__arm_vcvtpq_m_s32_f32): Likewise. 15901 (__arm_vcvtq_m_s32_f32): Likewise. 15902 (__arm_vdupq_m_n_f32): Likewise. 15903 (__arm_vmaxnmaq_m_f32): Likewise. 15904 (__arm_vmaxnmavq_p_f32): Likewise. 15905 (__arm_vmaxnmvq_p_f32): Likewise. 15906 (__arm_vminnmaq_m_f32): Likewise. 15907 (__arm_vminnmavq_p_f32): Likewise. 15908 (__arm_vminnmvq_p_f32): Likewise. 15909 (__arm_vnegq_m_f32): Likewise. 15910 (__arm_vpselq_f32): Likewise. 15911 (__arm_vrev64q_m_f32): Likewise. 15912 (__arm_vrndaq_m_f32): Likewise. 15913 (__arm_vrndmq_m_f32): Likewise. 15914 (__arm_vrndnq_m_f32): Likewise. 15915 (__arm_vrndpq_m_f32): Likewise. 15916 (__arm_vrndq_m_f32): Likewise. 15917 (__arm_vrndxq_m_f32): Likewise. 15918 (__arm_vcmpeqq_m_n_f32): Likewise. 15919 (__arm_vcmpgeq_m_f32): Likewise. 15920 (__arm_vcmpgeq_m_n_f32): Likewise. 15921 (__arm_vcmpgtq_m_f32): Likewise. 15922 (__arm_vcmpgtq_m_n_f32): Likewise. 15923 (__arm_vcmpleq_m_f32): Likewise. 15924 (__arm_vcmpleq_m_n_f32): Likewise. 15925 (__arm_vcmpltq_m_f32): Likewise. 15926 (__arm_vcmpltq_m_n_f32): Likewise. 15927 (__arm_vcmpneq_m_f32): Likewise. 15928 (__arm_vcmpneq_m_n_f32): Likewise. 15929 (__arm_vcvtmq_m_u32_f32): Likewise. 15930 (__arm_vcvtnq_m_u32_f32): Likewise. 15931 (__arm_vcvtpq_m_u32_f32): Likewise. 15932 (__arm_vcvtq_m_u32_f32): Likewise. 15933 (vcvtq_m): Define polymorphic variant. 15934 (vabsq_m): Likewise. 15935 (vcmlaq): Likewise. 15936 (vcmlaq_rot180): Likewise. 15937 (vcmlaq_rot270): Likewise. 15938 (vcmlaq_rot90): Likewise. 15939 (vcmpeqq_m_n): Likewise. 15940 (vcmpgeq_m_n): Likewise. 15941 (vrndxq_m): Likewise. 15942 (vrndq_m): Likewise. 15943 (vrndpq_m): Likewise. 15944 (vcmpgtq_m_n): Likewise. 15945 (vcmpgtq_m): Likewise. 15946 (vcmpleq_m): Likewise. 15947 (vcmpleq_m_n): Likewise. 15948 (vcmpltq_m_n): Likewise. 15949 (vcmpltq_m): Likewise. 15950 (vcmpneq_m): Likewise. 15951 (vcmpneq_m_n): Likewise. 15952 (vcvtbq_m): Likewise. 15953 (vcvttq_m): Likewise. 15954 (vcvtmq_m): Likewise. 15955 (vcvtnq_m): Likewise. 15956 (vcvtpq_m): Likewise. 15957 (vdupq_m_n): Likewise. 15958 (vfmaq_n): Likewise. 15959 (vfmaq): Likewise. 15960 (vfmasq_n): Likewise. 15961 (vfmsq): Likewise. 15962 (vmaxnmaq_m): Likewise. 15963 (vmaxnmavq_m): Likewise. 15964 (vmaxnmvq_m): Likewise. 15965 (vmaxnmavq_p): Likewise. 15966 (vmaxnmvq_p): Likewise. 15967 (vminnmaq_m): Likewise. 15968 (vminnmavq_p): Likewise. 15969 (vminnmvq_p): Likewise. 15970 (vrndnq_m): Likewise. 15971 (vrndaq_m): Likewise. 15972 (vrndmq_m): Likewise. 15973 (vrev64q_m): Likewise. 15974 (vrev32q_m): Likewise. 15975 (vpselq): Likewise. 15976 (vnegq_m): Likewise. 15977 (vcmpgeq_m): Likewise. 15978 (vshrntq_n): Likewise. 15979 (vrshrntq_n): Likewise. 15980 (vmovlbq_m): Likewise. 15981 (vmovnbq_m): Likewise. 15982 (vmovntq_m): Likewise. 15983 (vmvnq_m_n): Likewise. 15984 (vmvnq_m): Likewise. 15985 (vshrnbq_n): Likewise. 15986 (vrshrnbq_n): Likewise. 15987 (vqshruntq_n): Likewise. 15988 (vrev16q_m): Likewise. 15989 (vqshrunbq_n): Likewise. 15990 (vqshrntq_n): Likewise. 15991 (vqrshruntq_n): Likewise. 15992 (vqrshrntq_n): Likewise. 15993 (vqshrnbq_n): Likewise. 15994 (vqmovuntq_m): Likewise. 15995 (vqmovntq_m): Likewise. 15996 (vqmovnbq_m): Likewise. 15997 (vorrq_m_n): Likewise. 15998 (vmovltq_m): Likewise. 15999 (vqmovunbq_m): Likewise. 16000 (vaddlvaq_p): Likewise. 16001 (vmlaldavaq): Likewise. 16002 (vmlaldavaxq): Likewise. 16003 (vmlaldavq_p): Likewise. 16004 (vmlaldavxq_p): Likewise. 16005 (vmlsldavaq): Likewise. 16006 (vmlsldavaxq): Likewise. 16007 (vmlsldavq_p): Likewise. 16008 (vmlsldavxq_p): Likewise. 16009 (vrmlaldavhaxq): Likewise. 16010 (vrmlaldavhq_p): Likewise. 16011 (vrmlaldavhxq_p): Likewise. 16012 (vrmlsldavhaq): Likewise. 16013 (vrmlsldavhaxq): Likewise. 16014 (vrmlsldavhq_p): Likewise. 16015 (vrmlsldavhxq_p): Likewise. 16016 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use 16017 builtin qualifier. 16018 (TERNOP_NONE_NONE_NONE_IMM): Likewise. 16019 (TERNOP_NONE_NONE_NONE_NONE): Likewise. 16020 (TERNOP_NONE_NONE_NONE_UNONE): Likewise. 16021 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. 16022 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. 16023 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. 16024 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. 16025 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. 16026 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. 16027 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. 16028 (MVE_pred3): Likewise. 16029 (MVE_constraint1): Likewise. 16030 (MVE_pred1): Likewise. 16031 (VMLALDAVQ_P): Define iterator. 16032 (VQMOVNBQ_M): Likewise. 16033 (VMOVLTQ_M): Likewise. 16034 (VMOVNBQ_M): Likewise. 16035 (VRSHRNTQ_N): Likewise. 16036 (VORRQ_M_N): Likewise. 16037 (VREV32Q_M): Likewise. 16038 (VREV16Q_M): Likewise. 16039 (VQRSHRNTQ_N): Likewise. 16040 (VMOVNTQ_M): Likewise. 16041 (VMOVLBQ_M): Likewise. 16042 (VMLALDAVAQ): Likewise. 16043 (VQSHRNBQ_N): Likewise. 16044 (VSHRNBQ_N): Likewise. 16045 (VRSHRNBQ_N): Likewise. 16046 (VMLALDAVXQ_P): Likewise. 16047 (VQMOVNTQ_M): Likewise. 16048 (VMVNQ_M_N): Likewise. 16049 (VQSHRNTQ_N): Likewise. 16050 (VMLALDAVAXQ): Likewise. 16051 (VSHRNTQ_N): Likewise. 16052 (VCVTMQ_M): Likewise. 16053 (VCVTNQ_M): Likewise. 16054 (VCVTPQ_M): Likewise. 16055 (VCVTQ_M_N_FROM_F): Likewise. 16056 (VCVTQ_M_FROM_F): Likewise. 16057 (VRMLALDAVHQ_P): Likewise. 16058 (VADDLVAQ_P): Likewise. 16059 (mve_vrndq_m_f<mode>): Define RTL pattern. 16060 (mve_vabsq_m_f<mode>): Likewise. 16061 (mve_vaddlvaq_p_<supf>v4si): Likewise. 16062 (mve_vcmlaq_f<mode>): Likewise. 16063 (mve_vcmlaq_rot180_f<mode>): Likewise. 16064 (mve_vcmlaq_rot270_f<mode>): Likewise. 16065 (mve_vcmlaq_rot90_f<mode>): Likewise. 16066 (mve_vcmpeqq_m_n_f<mode>): Likewise. 16067 (mve_vcmpgeq_m_f<mode>): Likewise. 16068 (mve_vcmpgeq_m_n_f<mode>): Likewise. 16069 (mve_vcmpgtq_m_f<mode>): Likewise. 16070 (mve_vcmpgtq_m_n_f<mode>): Likewise. 16071 (mve_vcmpleq_m_f<mode>): Likewise. 16072 (mve_vcmpleq_m_n_f<mode>): Likewise. 16073 (mve_vcmpltq_m_f<mode>): Likewise. 16074 (mve_vcmpltq_m_n_f<mode>): Likewise. 16075 (mve_vcmpneq_m_f<mode>): Likewise. 16076 (mve_vcmpneq_m_n_f<mode>): Likewise. 16077 (mve_vcvtbq_m_f16_f32v8hf): Likewise. 16078 (mve_vcvtbq_m_f32_f16v4sf): Likewise. 16079 (mve_vcvttq_m_f16_f32v8hf): Likewise. 16080 (mve_vcvttq_m_f32_f16v4sf): Likewise. 16081 (mve_vdupq_m_n_f<mode>): Likewise. 16082 (mve_vfmaq_f<mode>): Likewise. 16083 (mve_vfmaq_n_f<mode>): Likewise. 16084 (mve_vfmasq_n_f<mode>): Likewise. 16085 (mve_vfmsq_f<mode>): Likewise. 16086 (mve_vmaxnmaq_m_f<mode>): Likewise. 16087 (mve_vmaxnmavq_p_f<mode>): Likewise. 16088 (mve_vmaxnmvq_p_f<mode>): Likewise. 16089 (mve_vminnmaq_m_f<mode>): Likewise. 16090 (mve_vminnmavq_p_f<mode>): Likewise. 16091 (mve_vminnmvq_p_f<mode>): Likewise. 16092 (mve_vmlaldavaq_<supf><mode>): Likewise. 16093 (mve_vmlaldavaxq_<supf><mode>): Likewise. 16094 (mve_vmlaldavq_p_<supf><mode>): Likewise. 16095 (mve_vmlaldavxq_p_<supf><mode>): Likewise. 16096 (mve_vmlsldavaq_s<mode>): Likewise. 16097 (mve_vmlsldavaxq_s<mode>): Likewise. 16098 (mve_vmlsldavq_p_s<mode>): Likewise. 16099 (mve_vmlsldavxq_p_s<mode>): Likewise. 16100 (mve_vmovlbq_m_<supf><mode>): Likewise. 16101 (mve_vmovltq_m_<supf><mode>): Likewise. 16102 (mve_vmovnbq_m_<supf><mode>): Likewise. 16103 (mve_vmovntq_m_<supf><mode>): Likewise. 16104 (mve_vmvnq_m_n_<supf><mode>): Likewise. 16105 (mve_vnegq_m_f<mode>): Likewise. 16106 (mve_vorrq_m_n_<supf><mode>): Likewise. 16107 (mve_vpselq_f<mode>): Likewise. 16108 (mve_vqmovnbq_m_<supf><mode>): Likewise. 16109 (mve_vqmovntq_m_<supf><mode>): Likewise. 16110 (mve_vqmovunbq_m_s<mode>): Likewise. 16111 (mve_vqmovuntq_m_s<mode>): Likewise. 16112 (mve_vqrshrntq_n_<supf><mode>): Likewise. 16113 (mve_vqrshruntq_n_s<mode>): Likewise. 16114 (mve_vqshrnbq_n_<supf><mode>): Likewise. 16115 (mve_vqshrntq_n_<supf><mode>): Likewise. 16116 (mve_vqshrunbq_n_s<mode>): Likewise. 16117 (mve_vqshruntq_n_s<mode>): Likewise. 16118 (mve_vrev32q_m_fv8hf): Likewise. 16119 (mve_vrev32q_m_<supf><mode>): Likewise. 16120 (mve_vrev64q_m_f<mode>): Likewise. 16121 (mve_vrmlaldavhaxq_sv4si): Likewise. 16122 (mve_vrmlaldavhxq_p_sv4si): Likewise. 16123 (mve_vrmlsldavhaxq_sv4si): Likewise. 16124 (mve_vrmlsldavhq_p_sv4si): Likewise. 16125 (mve_vrmlsldavhxq_p_sv4si): Likewise. 16126 (mve_vrndaq_m_f<mode>): Likewise. 16127 (mve_vrndmq_m_f<mode>): Likewise. 16128 (mve_vrndnq_m_f<mode>): Likewise. 16129 (mve_vrndpq_m_f<mode>): Likewise. 16130 (mve_vrndxq_m_f<mode>): Likewise. 16131 (mve_vrshrnbq_n_<supf><mode>): Likewise. 16132 (mve_vrshrntq_n_<supf><mode>): Likewise. 16133 (mve_vshrnbq_n_<supf><mode>): Likewise. 16134 (mve_vshrntq_n_<supf><mode>): Likewise. 16135 (mve_vcvtmq_m_<supf><mode>): Likewise. 16136 (mve_vcvtpq_m_<supf><mode>): Likewise. 16137 (mve_vcvtnq_m_<supf><mode>): Likewise. 16138 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise. 16139 (mve_vrev16q_m_<supf>v16qi): Likewise. 16140 (mve_vcvtq_m_from_f_<supf><mode>): Likewise. 16141 (mve_vrmlaldavhq_p_<supf>v4si): Likewise. 16142 (mve_vrmlsldavhaq_sv4si): Likewise. 16143 161442020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> 16145 Mihail Ionescu <mihail.ionescu@arm.com> 16146 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 16147 16148 * config/arm/arm_mve.h (vpselq_u8): Define macro. 16149 (vpselq_s8): Likewise. 16150 (vrev64q_m_u8): Likewise. 16151 (vqrdmlashq_n_u8): Likewise. 16152 (vqrdmlahq_n_u8): Likewise. 16153 (vqdmlahq_n_u8): Likewise. 16154 (vmvnq_m_u8): Likewise. 16155 (vmlasq_n_u8): Likewise. 16156 (vmlaq_n_u8): Likewise. 16157 (vmladavq_p_u8): Likewise. 16158 (vmladavaq_u8): Likewise. 16159 (vminvq_p_u8): Likewise. 16160 (vmaxvq_p_u8): Likewise. 16161 (vdupq_m_n_u8): Likewise. 16162 (vcmpneq_m_u8): Likewise. 16163 (vcmpneq_m_n_u8): Likewise. 16164 (vcmphiq_m_u8): Likewise. 16165 (vcmphiq_m_n_u8): Likewise. 16166 (vcmpeqq_m_u8): Likewise. 16167 (vcmpeqq_m_n_u8): Likewise. 16168 (vcmpcsq_m_u8): Likewise. 16169 (vcmpcsq_m_n_u8): Likewise. 16170 (vclzq_m_u8): Likewise. 16171 (vaddvaq_p_u8): Likewise. 16172 (vsriq_n_u8): Likewise. 16173 (vsliq_n_u8): Likewise. 16174 (vshlq_m_r_u8): Likewise. 16175 (vrshlq_m_n_u8): Likewise. 16176 (vqshlq_m_r_u8): Likewise. 16177 (vqrshlq_m_n_u8): Likewise. 16178 (vminavq_p_s8): Likewise. 16179 (vminaq_m_s8): Likewise. 16180 (vmaxavq_p_s8): Likewise. 16181 (vmaxaq_m_s8): Likewise. 16182 (vcmpneq_m_s8): Likewise. 16183 (vcmpneq_m_n_s8): Likewise. 16184 (vcmpltq_m_s8): Likewise. 16185 (vcmpltq_m_n_s8): Likewise. 16186 (vcmpleq_m_s8): Likewise. 16187 (vcmpleq_m_n_s8): Likewise. 16188 (vcmpgtq_m_s8): Likewise. 16189 (vcmpgtq_m_n_s8): Likewise. 16190 (vcmpgeq_m_s8): Likewise. 16191 (vcmpgeq_m_n_s8): Likewise. 16192 (vcmpeqq_m_s8): Likewise. 16193 (vcmpeqq_m_n_s8): Likewise. 16194 (vshlq_m_r_s8): Likewise. 16195 (vrshlq_m_n_s8): Likewise. 16196 (vrev64q_m_s8): Likewise. 16197 (vqshlq_m_r_s8): Likewise. 16198 (vqrshlq_m_n_s8): Likewise. 16199 (vqnegq_m_s8): Likewise. 16200 (vqabsq_m_s8): Likewise. 16201 (vnegq_m_s8): Likewise. 16202 (vmvnq_m_s8): Likewise. 16203 (vmlsdavxq_p_s8): Likewise. 16204 (vmlsdavq_p_s8): Likewise. 16205 (vmladavxq_p_s8): Likewise. 16206 (vmladavq_p_s8): Likewise. 16207 (vminvq_p_s8): Likewise. 16208 (vmaxvq_p_s8): Likewise. 16209 (vdupq_m_n_s8): Likewise. 16210 (vclzq_m_s8): Likewise. 16211 (vclsq_m_s8): Likewise. 16212 (vaddvaq_p_s8): Likewise. 16213 (vabsq_m_s8): Likewise. 16214 (vqrdmlsdhxq_s8): Likewise. 16215 (vqrdmlsdhq_s8): Likewise. 16216 (vqrdmlashq_n_s8): Likewise. 16217 (vqrdmlahq_n_s8): Likewise. 16218 (vqrdmladhxq_s8): Likewise. 16219 (vqrdmladhq_s8): Likewise. 16220 (vqdmlsdhxq_s8): Likewise. 16221 (vqdmlsdhq_s8): Likewise. 16222 (vqdmlahq_n_s8): Likewise. 16223 (vqdmladhxq_s8): Likewise. 16224 (vqdmladhq_s8): Likewise. 16225 (vmlsdavaxq_s8): Likewise. 16226 (vmlsdavaq_s8): Likewise. 16227 (vmlasq_n_s8): Likewise. 16228 (vmlaq_n_s8): Likewise. 16229 (vmladavaxq_s8): Likewise. 16230 (vmladavaq_s8): Likewise. 16231 (vsriq_n_s8): Likewise. 16232 (vsliq_n_s8): Likewise. 16233 (vpselq_u16): Likewise. 16234 (vpselq_s16): Likewise. 16235 (vrev64q_m_u16): Likewise. 16236 (vqrdmlashq_n_u16): Likewise. 16237 (vqrdmlahq_n_u16): Likewise. 16238 (vqdmlahq_n_u16): Likewise. 16239 (vmvnq_m_u16): Likewise. 16240 (vmlasq_n_u16): Likewise. 16241 (vmlaq_n_u16): Likewise. 16242 (vmladavq_p_u16): Likewise. 16243 (vmladavaq_u16): Likewise. 16244 (vminvq_p_u16): Likewise. 16245 (vmaxvq_p_u16): Likewise. 16246 (vdupq_m_n_u16): Likewise. 16247 (vcmpneq_m_u16): Likewise. 16248 (vcmpneq_m_n_u16): Likewise. 16249 (vcmphiq_m_u16): Likewise. 16250 (vcmphiq_m_n_u16): Likewise. 16251 (vcmpeqq_m_u16): Likewise. 16252 (vcmpeqq_m_n_u16): Likewise. 16253 (vcmpcsq_m_u16): Likewise. 16254 (vcmpcsq_m_n_u16): Likewise. 16255 (vclzq_m_u16): Likewise. 16256 (vaddvaq_p_u16): Likewise. 16257 (vsriq_n_u16): Likewise. 16258 (vsliq_n_u16): Likewise. 16259 (vshlq_m_r_u16): Likewise. 16260 (vrshlq_m_n_u16): Likewise. 16261 (vqshlq_m_r_u16): Likewise. 16262 (vqrshlq_m_n_u16): Likewise. 16263 (vminavq_p_s16): Likewise. 16264 (vminaq_m_s16): Likewise. 16265 (vmaxavq_p_s16): Likewise. 16266 (vmaxaq_m_s16): Likewise. 16267 (vcmpneq_m_s16): Likewise. 16268 (vcmpneq_m_n_s16): Likewise. 16269 (vcmpltq_m_s16): Likewise. 16270 (vcmpltq_m_n_s16): Likewise. 16271 (vcmpleq_m_s16): Likewise. 16272 (vcmpleq_m_n_s16): Likewise. 16273 (vcmpgtq_m_s16): Likewise. 16274 (vcmpgtq_m_n_s16): Likewise. 16275 (vcmpgeq_m_s16): Likewise. 16276 (vcmpgeq_m_n_s16): Likewise. 16277 (vcmpeqq_m_s16): Likewise. 16278 (vcmpeqq_m_n_s16): Likewise. 16279 (vshlq_m_r_s16): Likewise. 16280 (vrshlq_m_n_s16): Likewise. 16281 (vrev64q_m_s16): Likewise. 16282 (vqshlq_m_r_s16): Likewise. 16283 (vqrshlq_m_n_s16): Likewise. 16284 (vqnegq_m_s16): Likewise. 16285 (vqabsq_m_s16): Likewise. 16286 (vnegq_m_s16): Likewise. 16287 (vmvnq_m_s16): Likewise. 16288 (vmlsdavxq_p_s16): Likewise. 16289 (vmlsdavq_p_s16): Likewise. 16290 (vmladavxq_p_s16): Likewise. 16291 (vmladavq_p_s16): Likewise. 16292 (vminvq_p_s16): Likewise. 16293 (vmaxvq_p_s16): Likewise. 16294 (vdupq_m_n_s16): Likewise. 16295 (vclzq_m_s16): Likewise. 16296 (vclsq_m_s16): Likewise. 16297 (vaddvaq_p_s16): Likewise. 16298 (vabsq_m_s16): Likewise. 16299 (vqrdmlsdhxq_s16): Likewise. 16300 (vqrdmlsdhq_s16): Likewise. 16301 (vqrdmlashq_n_s16): Likewise. 16302 (vqrdmlahq_n_s16): Likewise. 16303 (vqrdmladhxq_s16): Likewise. 16304 (vqrdmladhq_s16): Likewise. 16305 (vqdmlsdhxq_s16): Likewise. 16306 (vqdmlsdhq_s16): Likewise. 16307 (vqdmlahq_n_s16): Likewise. 16308 (vqdmladhxq_s16): Likewise. 16309 (vqdmladhq_s16): Likewise. 16310 (vmlsdavaxq_s16): Likewise. 16311 (vmlsdavaq_s16): Likewise. 16312 (vmlasq_n_s16): Likewise. 16313 (vmlaq_n_s16): Likewise. 16314 (vmladavaxq_s16): Likewise. 16315 (vmladavaq_s16): Likewise. 16316 (vsriq_n_s16): Likewise. 16317 (vsliq_n_s16): Likewise. 16318 (vpselq_u32): Likewise. 16319 (vpselq_s32): Likewise. 16320 (vrev64q_m_u32): Likewise. 16321 (vqrdmlashq_n_u32): Likewise. 16322 (vqrdmlahq_n_u32): Likewise. 16323 (vqdmlahq_n_u32): Likewise. 16324 (vmvnq_m_u32): Likewise. 16325 (vmlasq_n_u32): Likewise. 16326 (vmlaq_n_u32): Likewise. 16327 (vmladavq_p_u32): Likewise. 16328 (vmladavaq_u32): Likewise. 16329 (vminvq_p_u32): Likewise. 16330 (vmaxvq_p_u32): Likewise. 16331 (vdupq_m_n_u32): Likewise. 16332 (vcmpneq_m_u32): Likewise. 16333 (vcmpneq_m_n_u32): Likewise. 16334 (vcmphiq_m_u32): Likewise. 16335 (vcmphiq_m_n_u32): Likewise. 16336 (vcmpeqq_m_u32): Likewise. 16337 (vcmpeqq_m_n_u32): Likewise. 16338 (vcmpcsq_m_u32): Likewise. 16339 (vcmpcsq_m_n_u32): Likewise. 16340 (vclzq_m_u32): Likewise. 16341 (vaddvaq_p_u32): Likewise. 16342 (vsriq_n_u32): Likewise. 16343 (vsliq_n_u32): Likewise. 16344 (vshlq_m_r_u32): Likewise. 16345 (vrshlq_m_n_u32): Likewise. 16346 (vqshlq_m_r_u32): Likewise. 16347 (vqrshlq_m_n_u32): Likewise. 16348 (vminavq_p_s32): Likewise. 16349 (vminaq_m_s32): Likewise. 16350 (vmaxavq_p_s32): Likewise. 16351 (vmaxaq_m_s32): Likewise. 16352 (vcmpneq_m_s32): Likewise. 16353 (vcmpneq_m_n_s32): Likewise. 16354 (vcmpltq_m_s32): Likewise. 16355 (vcmpltq_m_n_s32): Likewise. 16356 (vcmpleq_m_s32): Likewise. 16357 (vcmpleq_m_n_s32): Likewise. 16358 (vcmpgtq_m_s32): Likewise. 16359 (vcmpgtq_m_n_s32): Likewise. 16360 (vcmpgeq_m_s32): Likewise. 16361 (vcmpgeq_m_n_s32): Likewise. 16362 (vcmpeqq_m_s32): Likewise. 16363 (vcmpeqq_m_n_s32): Likewise. 16364 (vshlq_m_r_s32): Likewise. 16365 (vrshlq_m_n_s32): Likewise. 16366 (vrev64q_m_s32): Likewise. 16367 (vqshlq_m_r_s32): Likewise. 16368 (vqrshlq_m_n_s32): Likewise. 16369 (vqnegq_m_s32): Likewise. 16370 (vqabsq_m_s32): Likewise. 16371 (vnegq_m_s32): Likewise. 16372 (vmvnq_m_s32): Likewise. 16373 (vmlsdavxq_p_s32): Likewise. 16374 (vmlsdavq_p_s32): Likewise. 16375 (vmladavxq_p_s32): Likewise. 16376 (vmladavq_p_s32): Likewise. 16377 (vminvq_p_s32): Likewise. 16378 (vmaxvq_p_s32): Likewise. 16379 (vdupq_m_n_s32): Likewise. 16380 (vclzq_m_s32): Likewise. 16381 (vclsq_m_s32): Likewise. 16382 (vaddvaq_p_s32): Likewise. 16383 (vabsq_m_s32): Likewise. 16384 (vqrdmlsdhxq_s32): Likewise. 16385 (vqrdmlsdhq_s32): Likewise. 16386 (vqrdmlashq_n_s32): Likewise. 16387 (vqrdmlahq_n_s32): Likewise. 16388 (vqrdmladhxq_s32): Likewise. 16389 (vqrdmladhq_s32): Likewise. 16390 (vqdmlsdhxq_s32): Likewise. 16391 (vqdmlsdhq_s32): Likewise. 16392 (vqdmlahq_n_s32): Likewise. 16393 (vqdmladhxq_s32): Likewise. 16394 (vqdmladhq_s32): Likewise. 16395 (vmlsdavaxq_s32): Likewise. 16396 (vmlsdavaq_s32): Likewise. 16397 (vmlasq_n_s32): Likewise. 16398 (vmlaq_n_s32): Likewise. 16399 (vmladavaxq_s32): Likewise. 16400 (vmladavaq_s32): Likewise. 16401 (vsriq_n_s32): Likewise. 16402 (vsliq_n_s32): Likewise. 16403 (vpselq_u64): Likewise. 16404 (vpselq_s64): Likewise. 16405 (__arm_vpselq_u8): Define intrinsic. 16406 (__arm_vpselq_s8): Likewise. 16407 (__arm_vrev64q_m_u8): Likewise. 16408 (__arm_vqrdmlashq_n_u8): Likewise. 16409 (__arm_vqrdmlahq_n_u8): Likewise. 16410 (__arm_vqdmlahq_n_u8): Likewise. 16411 (__arm_vmvnq_m_u8): Likewise. 16412 (__arm_vmlasq_n_u8): Likewise. 16413 (__arm_vmlaq_n_u8): Likewise. 16414 (__arm_vmladavq_p_u8): Likewise. 16415 (__arm_vmladavaq_u8): Likewise. 16416 (__arm_vminvq_p_u8): Likewise. 16417 (__arm_vmaxvq_p_u8): Likewise. 16418 (__arm_vdupq_m_n_u8): Likewise. 16419 (__arm_vcmpneq_m_u8): Likewise. 16420 (__arm_vcmpneq_m_n_u8): Likewise. 16421 (__arm_vcmphiq_m_u8): Likewise. 16422 (__arm_vcmphiq_m_n_u8): Likewise. 16423 (__arm_vcmpeqq_m_u8): Likewise. 16424 (__arm_vcmpeqq_m_n_u8): Likewise. 16425 (__arm_vcmpcsq_m_u8): Likewise. 16426 (__arm_vcmpcsq_m_n_u8): Likewise. 16427 (__arm_vclzq_m_u8): Likewise. 16428 (__arm_vaddvaq_p_u8): Likewise. 16429 (__arm_vsriq_n_u8): Likewise. 16430 (__arm_vsliq_n_u8): Likewise. 16431 (__arm_vshlq_m_r_u8): Likewise. 16432 (__arm_vrshlq_m_n_u8): Likewise. 16433 (__arm_vqshlq_m_r_u8): Likewise. 16434 (__arm_vqrshlq_m_n_u8): Likewise. 16435 (__arm_vminavq_p_s8): Likewise. 16436 (__arm_vminaq_m_s8): Likewise. 16437 (__arm_vmaxavq_p_s8): Likewise. 16438 (__arm_vmaxaq_m_s8): Likewise. 16439 (__arm_vcmpneq_m_s8): Likewise. 16440 (__arm_vcmpneq_m_n_s8): Likewise. 16441 (__arm_vcmpltq_m_s8): Likewise. 16442 (__arm_vcmpltq_m_n_s8): Likewise. 16443 (__arm_vcmpleq_m_s8): Likewise. 16444 (__arm_vcmpleq_m_n_s8): Likewise. 16445 (__arm_vcmpgtq_m_s8): Likewise. 16446 (__arm_vcmpgtq_m_n_s8): Likewise. 16447 (__arm_vcmpgeq_m_s8): Likewise. 16448 (__arm_vcmpgeq_m_n_s8): Likewise. 16449 (__arm_vcmpeqq_m_s8): Likewise. 16450 (__arm_vcmpeqq_m_n_s8): Likewise. 16451 (__arm_vshlq_m_r_s8): Likewise. 16452 (__arm_vrshlq_m_n_s8): Likewise. 16453 (__arm_vrev64q_m_s8): Likewise. 16454 (__arm_vqshlq_m_r_s8): Likewise. 16455 (__arm_vqrshlq_m_n_s8): Likewise. 16456 (__arm_vqnegq_m_s8): Likewise. 16457 (__arm_vqabsq_m_s8): Likewise. 16458 (__arm_vnegq_m_s8): Likewise. 16459 (__arm_vmvnq_m_s8): Likewise. 16460 (__arm_vmlsdavxq_p_s8): Likewise. 16461 (__arm_vmlsdavq_p_s8): Likewise. 16462 (__arm_vmladavxq_p_s8): Likewise. 16463 (__arm_vmladavq_p_s8): Likewise. 16464 (__arm_vminvq_p_s8): Likewise. 16465 (__arm_vmaxvq_p_s8): Likewise. 16466 (__arm_vdupq_m_n_s8): Likewise. 16467 (__arm_vclzq_m_s8): Likewise. 16468 (__arm_vclsq_m_s8): Likewise. 16469 (__arm_vaddvaq_p_s8): Likewise. 16470 (__arm_vabsq_m_s8): Likewise. 16471 (__arm_vqrdmlsdhxq_s8): Likewise. 16472 (__arm_vqrdmlsdhq_s8): Likewise. 16473 (__arm_vqrdmlashq_n_s8): Likewise. 16474 (__arm_vqrdmlahq_n_s8): Likewise. 16475 (__arm_vqrdmladhxq_s8): Likewise. 16476 (__arm_vqrdmladhq_s8): Likewise. 16477 (__arm_vqdmlsdhxq_s8): Likewise. 16478 (__arm_vqdmlsdhq_s8): Likewise. 16479 (__arm_vqdmlahq_n_s8): Likewise. 16480 (__arm_vqdmladhxq_s8): Likewise. 16481 (__arm_vqdmladhq_s8): Likewise. 16482 (__arm_vmlsdavaxq_s8): Likewise. 16483 (__arm_vmlsdavaq_s8): Likewise. 16484 (__arm_vmlasq_n_s8): Likewise. 16485 (__arm_vmlaq_n_s8): Likewise. 16486 (__arm_vmladavaxq_s8): Likewise. 16487 (__arm_vmladavaq_s8): Likewise. 16488 (__arm_vsriq_n_s8): Likewise. 16489 (__arm_vsliq_n_s8): Likewise. 16490 (__arm_vpselq_u16): Likewise. 16491 (__arm_vpselq_s16): Likewise. 16492 (__arm_vrev64q_m_u16): Likewise. 16493 (__arm_vqrdmlashq_n_u16): Likewise. 16494 (__arm_vqrdmlahq_n_u16): Likewise. 16495 (__arm_vqdmlahq_n_u16): Likewise. 16496 (__arm_vmvnq_m_u16): Likewise. 16497 (__arm_vmlasq_n_u16): Likewise. 16498 (__arm_vmlaq_n_u16): Likewise. 16499 (__arm_vmladavq_p_u16): Likewise. 16500 (__arm_vmladavaq_u16): Likewise. 16501 (__arm_vminvq_p_u16): Likewise. 16502 (__arm_vmaxvq_p_u16): Likewise. 16503 (__arm_vdupq_m_n_u16): Likewise. 16504 (__arm_vcmpneq_m_u16): Likewise. 16505 (__arm_vcmpneq_m_n_u16): Likewise. 16506 (__arm_vcmphiq_m_u16): Likewise. 16507 (__arm_vcmphiq_m_n_u16): Likewise. 16508 (__arm_vcmpeqq_m_u16): Likewise. 16509 (__arm_vcmpeqq_m_n_u16): Likewise. 16510 (__arm_vcmpcsq_m_u16): Likewise. 16511 (__arm_vcmpcsq_m_n_u16): Likewise. 16512 (__arm_vclzq_m_u16): Likewise. 16513 (__arm_vaddvaq_p_u16): Likewise. 16514 (__arm_vsriq_n_u16): Likewise. 16515 (__arm_vsliq_n_u16): Likewise. 16516 (__arm_vshlq_m_r_u16): Likewise. 16517 (__arm_vrshlq_m_n_u16): Likewise. 16518 (__arm_vqshlq_m_r_u16): Likewise. 16519 (__arm_vqrshlq_m_n_u16): Likewise. 16520 (__arm_vminavq_p_s16): Likewise. 16521 (__arm_vminaq_m_s16): Likewise. 16522 (__arm_vmaxavq_p_s16): Likewise. 16523 (__arm_vmaxaq_m_s16): Likewise. 16524 (__arm_vcmpneq_m_s16): Likewise. 16525 (__arm_vcmpneq_m_n_s16): Likewise. 16526 (__arm_vcmpltq_m_s16): Likewise. 16527 (__arm_vcmpltq_m_n_s16): Likewise. 16528 (__arm_vcmpleq_m_s16): Likewise. 16529 (__arm_vcmpleq_m_n_s16): Likewise. 16530 (__arm_vcmpgtq_m_s16): Likewise. 16531 (__arm_vcmpgtq_m_n_s16): Likewise. 16532 (__arm_vcmpgeq_m_s16): Likewise. 16533 (__arm_vcmpgeq_m_n_s16): Likewise. 16534 (__arm_vcmpeqq_m_s16): Likewise. 16535 (__arm_vcmpeqq_m_n_s16): Likewise. 16536 (__arm_vshlq_m_r_s16): Likewise. 16537 (__arm_vrshlq_m_n_s16): Likewise. 16538 (__arm_vrev64q_m_s16): Likewise. 16539 (__arm_vqshlq_m_r_s16): Likewise. 16540 (__arm_vqrshlq_m_n_s16): Likewise. 16541 (__arm_vqnegq_m_s16): Likewise. 16542 (__arm_vqabsq_m_s16): Likewise. 16543 (__arm_vnegq_m_s16): Likewise. 16544 (__arm_vmvnq_m_s16): Likewise. 16545 (__arm_vmlsdavxq_p_s16): Likewise. 16546 (__arm_vmlsdavq_p_s16): Likewise. 16547 (__arm_vmladavxq_p_s16): Likewise. 16548 (__arm_vmladavq_p_s16): Likewise. 16549 (__arm_vminvq_p_s16): Likewise. 16550 (__arm_vmaxvq_p_s16): Likewise. 16551 (__arm_vdupq_m_n_s16): Likewise. 16552 (__arm_vclzq_m_s16): Likewise. 16553 (__arm_vclsq_m_s16): Likewise. 16554 (__arm_vaddvaq_p_s16): Likewise. 16555 (__arm_vabsq_m_s16): Likewise. 16556 (__arm_vqrdmlsdhxq_s16): Likewise. 16557 (__arm_vqrdmlsdhq_s16): Likewise. 16558 (__arm_vqrdmlashq_n_s16): Likewise. 16559 (__arm_vqrdmlahq_n_s16): Likewise. 16560 (__arm_vqrdmladhxq_s16): Likewise. 16561 (__arm_vqrdmladhq_s16): Likewise. 16562 (__arm_vqdmlsdhxq_s16): Likewise. 16563 (__arm_vqdmlsdhq_s16): Likewise. 16564 (__arm_vqdmlahq_n_s16): Likewise. 16565 (__arm_vqdmladhxq_s16): Likewise. 16566 (__arm_vqdmladhq_s16): Likewise. 16567 (__arm_vmlsdavaxq_s16): Likewise. 16568 (__arm_vmlsdavaq_s16): Likewise. 16569 (__arm_vmlasq_n_s16): Likewise. 16570 (__arm_vmlaq_n_s16): Likewise. 16571 (__arm_vmladavaxq_s16): Likewise. 16572 (__arm_vmladavaq_s16): Likewise. 16573 (__arm_vsriq_n_s16): Likewise. 16574 (__arm_vsliq_n_s16): Likewise. 16575 (__arm_vpselq_u32): Likewise. 16576 (__arm_vpselq_s32): Likewise. 16577 (__arm_vrev64q_m_u32): Likewise. 16578 (__arm_vqrdmlashq_n_u32): Likewise. 16579 (__arm_vqrdmlahq_n_u32): Likewise. 16580 (__arm_vqdmlahq_n_u32): Likewise. 16581 (__arm_vmvnq_m_u32): Likewise. 16582 (__arm_vmlasq_n_u32): Likewise. 16583 (__arm_vmlaq_n_u32): Likewise. 16584 (__arm_vmladavq_p_u32): Likewise. 16585 (__arm_vmladavaq_u32): Likewise. 16586 (__arm_vminvq_p_u32): Likewise. 16587 (__arm_vmaxvq_p_u32): Likewise. 16588 (__arm_vdupq_m_n_u32): Likewise. 16589 (__arm_vcmpneq_m_u32): Likewise. 16590 (__arm_vcmpneq_m_n_u32): Likewise. 16591 (__arm_vcmphiq_m_u32): Likewise. 16592 (__arm_vcmphiq_m_n_u32): Likewise. 16593 (__arm_vcmpeqq_m_u32): Likewise. 16594 (__arm_vcmpeqq_m_n_u32): Likewise. 16595 (__arm_vcmpcsq_m_u32): Likewise. 16596 (__arm_vcmpcsq_m_n_u32): Likewise. 16597 (__arm_vclzq_m_u32): Likewise. 16598 (__arm_vaddvaq_p_u32): Likewise. 16599 (__arm_vsriq_n_u32): Likewise. 16600 (__arm_vsliq_n_u32): Likewise. 16601 (__arm_vshlq_m_r_u32): Likewise. 16602 (__arm_vrshlq_m_n_u32): Likewise. 16603 (__arm_vqshlq_m_r_u32): Likewise. 16604 (__arm_vqrshlq_m_n_u32): Likewise. 16605 (__arm_vminavq_p_s32): Likewise. 16606 (__arm_vminaq_m_s32): Likewise. 16607 (__arm_vmaxavq_p_s32): Likewise. 16608 (__arm_vmaxaq_m_s32): Likewise. 16609 (__arm_vcmpneq_m_s32): Likewise. 16610 (__arm_vcmpneq_m_n_s32): Likewise. 16611 (__arm_vcmpltq_m_s32): Likewise. 16612 (__arm_vcmpltq_m_n_s32): Likewise. 16613 (__arm_vcmpleq_m_s32): Likewise. 16614 (__arm_vcmpleq_m_n_s32): Likewise. 16615 (__arm_vcmpgtq_m_s32): Likewise. 16616 (__arm_vcmpgtq_m_n_s32): Likewise. 16617 (__arm_vcmpgeq_m_s32): Likewise. 16618 (__arm_vcmpgeq_m_n_s32): Likewise. 16619 (__arm_vcmpeqq_m_s32): Likewise. 16620 (__arm_vcmpeqq_m_n_s32): Likewise. 16621 (__arm_vshlq_m_r_s32): Likewise. 16622 (__arm_vrshlq_m_n_s32): Likewise. 16623 (__arm_vrev64q_m_s32): Likewise. 16624 (__arm_vqshlq_m_r_s32): Likewise. 16625 (__arm_vqrshlq_m_n_s32): Likewise. 16626 (__arm_vqnegq_m_s32): Likewise. 16627 (__arm_vqabsq_m_s32): Likewise. 16628 (__arm_vnegq_m_s32): Likewise. 16629 (__arm_vmvnq_m_s32): Likewise. 16630 (__arm_vmlsdavxq_p_s32): Likewise. 16631 (__arm_vmlsdavq_p_s32): Likewise. 16632 (__arm_vmladavxq_p_s32): Likewise. 16633 (__arm_vmladavq_p_s32): Likewise. 16634 (__arm_vminvq_p_s32): Likewise. 16635 (__arm_vmaxvq_p_s32): Likewise. 16636 (__arm_vdupq_m_n_s32): Likewise. 16637 (__arm_vclzq_m_s32): Likewise. 16638 (__arm_vclsq_m_s32): Likewise. 16639 (__arm_vaddvaq_p_s32): Likewise. 16640 (__arm_vabsq_m_s32): Likewise. 16641 (__arm_vqrdmlsdhxq_s32): Likewise. 16642 (__arm_vqrdmlsdhq_s32): Likewise. 16643 (__arm_vqrdmlashq_n_s32): Likewise. 16644 (__arm_vqrdmlahq_n_s32): Likewise. 16645 (__arm_vqrdmladhxq_s32): Likewise. 16646 (__arm_vqrdmladhq_s32): Likewise. 16647 (__arm_vqdmlsdhxq_s32): Likewise. 16648 (__arm_vqdmlsdhq_s32): Likewise. 16649 (__arm_vqdmlahq_n_s32): Likewise. 16650 (__arm_vqdmladhxq_s32): Likewise. 16651 (__arm_vqdmladhq_s32): Likewise. 16652 (__arm_vmlsdavaxq_s32): Likewise. 16653 (__arm_vmlsdavaq_s32): Likewise. 16654 (__arm_vmlasq_n_s32): Likewise. 16655 (__arm_vmlaq_n_s32): Likewise. 16656 (__arm_vmladavaxq_s32): Likewise. 16657 (__arm_vmladavaq_s32): Likewise. 16658 (__arm_vsriq_n_s32): Likewise. 16659 (__arm_vsliq_n_s32): Likewise. 16660 (__arm_vpselq_u64): Likewise. 16661 (__arm_vpselq_s64): Likewise. 16662 (vcmpneq_m_n): Define polymorphic variant. 16663 (vcmpneq_m): Likewise. 16664 (vqrdmlsdhq): Likewise. 16665 (vqrdmlsdhxq): Likewise. 16666 (vqrshlq_m_n): Likewise. 16667 (vqshlq_m_r): Likewise. 16668 (vrev64q_m): Likewise. 16669 (vrshlq_m_n): Likewise. 16670 (vshlq_m_r): Likewise. 16671 (vsliq_n): Likewise. 16672 (vsriq_n): Likewise. 16673 (vqrdmlashq_n): Likewise. 16674 (vqrdmlahq): Likewise. 16675 (vqrdmladhxq): Likewise. 16676 (vqrdmladhq): Likewise. 16677 (vqnegq_m): Likewise. 16678 (vqdmlsdhxq): Likewise. 16679 (vabsq_m): Likewise. 16680 (vclsq_m): Likewise. 16681 (vclzq_m): Likewise. 16682 (vcmpgeq_m): Likewise. 16683 (vcmpgeq_m_n): Likewise. 16684 (vdupq_m_n): Likewise. 16685 (vmaxaq_m): Likewise. 16686 (vmlaq_n): Likewise. 16687 (vmlasq_n): Likewise. 16688 (vmvnq_m): Likewise. 16689 (vnegq_m): Likewise. 16690 (vpselq): Likewise. 16691 (vqdmlahq_n): Likewise. 16692 (vqrdmlahq_n): Likewise. 16693 (vqdmlsdhq): Likewise. 16694 (vqdmladhq): Likewise. 16695 (vqabsq_m): Likewise. 16696 (vminaq_m): Likewise. 16697 (vrmlaldavhaq): Likewise. 16698 (vmlsdavxq_p): Likewise. 16699 (vmlsdavq_p): Likewise. 16700 (vmlsdavaxq): Likewise. 16701 (vmlsdavaq): Likewise. 16702 (vaddvaq_p): Likewise. 16703 (vcmpcsq_m_n): Likewise. 16704 (vcmpcsq_m): Likewise. 16705 (vcmpeqq_m_n): Likewise. 16706 (vcmpeqq_m): Likewise. 16707 (vmladavxq_p): Likewise. 16708 (vmladavq_p): Likewise. 16709 (vmladavaxq): Likewise. 16710 (vmladavaq): Likewise. 16711 (vminvq_p): Likewise. 16712 (vminavq_p): Likewise. 16713 (vmaxvq_p): Likewise. 16714 (vmaxavq_p): Likewise. 16715 (vcmpltq_m_n): Likewise. 16716 (vcmpltq_m): Likewise. 16717 (vcmpleq_m): Likewise. 16718 (vcmpleq_m_n): Likewise. 16719 (vcmphiq_m_n): Likewise. 16720 (vcmphiq_m): Likewise. 16721 (vcmpgtq_m_n): Likewise. 16722 (vcmpgtq_m): Likewise. 16723 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use 16724 builtin qualifier. 16725 (TERNOP_NONE_NONE_NONE_NONE): Likewise. 16726 (TERNOP_NONE_NONE_NONE_UNONE): Likewise. 16727 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. 16728 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. 16729 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. 16730 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. 16731 * config/arm/constraints.md (Rc): Define constraint to check constant is 16732 in the range of 0 to 15. 16733 (Re): Define constraint to check constant is in the range of 0 to 31. 16734 * config/arm/mve.md (VADDVAQ_P): Define iterator. 16735 (VCLZQ_M): Likewise. 16736 (VCMPEQQ_M_N): Likewise. 16737 (VCMPEQQ_M): Likewise. 16738 (VCMPNEQ_M_N): Likewise. 16739 (VCMPNEQ_M): Likewise. 16740 (VDUPQ_M_N): Likewise. 16741 (VMAXVQ_P): Likewise. 16742 (VMINVQ_P): Likewise. 16743 (VMLADAVAQ): Likewise. 16744 (VMLADAVQ_P): Likewise. 16745 (VMLAQ_N): Likewise. 16746 (VMLASQ_N): Likewise. 16747 (VMVNQ_M): Likewise. 16748 (VPSELQ): Likewise. 16749 (VQDMLAHQ_N): Likewise. 16750 (VQRDMLAHQ_N): Likewise. 16751 (VQRDMLASHQ_N): Likewise. 16752 (VQRSHLQ_M_N): Likewise. 16753 (VQSHLQ_M_R): Likewise. 16754 (VREV64Q_M): Likewise. 16755 (VRSHLQ_M_N): Likewise. 16756 (VSHLQ_M_R): Likewise. 16757 (VSLIQ_N): Likewise. 16758 (VSRIQ_N): Likewise. 16759 (mve_vabsq_m_s<mode>): Define RTL pattern. 16760 (mve_vaddvaq_p_<supf><mode>): Likewise. 16761 (mve_vclsq_m_s<mode>): Likewise. 16762 (mve_vclzq_m_<supf><mode>): Likewise. 16763 (mve_vcmpcsq_m_n_u<mode>): Likewise. 16764 (mve_vcmpcsq_m_u<mode>): Likewise. 16765 (mve_vcmpeqq_m_n_<supf><mode>): Likewise. 16766 (mve_vcmpeqq_m_<supf><mode>): Likewise. 16767 (mve_vcmpgeq_m_n_s<mode>): Likewise. 16768 (mve_vcmpgeq_m_s<mode>): Likewise. 16769 (mve_vcmpgtq_m_n_s<mode>): Likewise. 16770 (mve_vcmpgtq_m_s<mode>): Likewise. 16771 (mve_vcmphiq_m_n_u<mode>): Likewise. 16772 (mve_vcmphiq_m_u<mode>): Likewise. 16773 (mve_vcmpleq_m_n_s<mode>): Likewise. 16774 (mve_vcmpleq_m_s<mode>): Likewise. 16775 (mve_vcmpltq_m_n_s<mode>): Likewise. 16776 (mve_vcmpltq_m_s<mode>): Likewise. 16777 (mve_vcmpneq_m_n_<supf><mode>): Likewise. 16778 (mve_vcmpneq_m_<supf><mode>): Likewise. 16779 (mve_vdupq_m_n_<supf><mode>): Likewise. 16780 (mve_vmaxaq_m_s<mode>): Likewise. 16781 (mve_vmaxavq_p_s<mode>): Likewise. 16782 (mve_vmaxvq_p_<supf><mode>): Likewise. 16783 (mve_vminaq_m_s<mode>): Likewise. 16784 (mve_vminavq_p_s<mode>): Likewise. 16785 (mve_vminvq_p_<supf><mode>): Likewise. 16786 (mve_vmladavaq_<supf><mode>): Likewise. 16787 (mve_vmladavq_p_<supf><mode>): Likewise. 16788 (mve_vmladavxq_p_s<mode>): Likewise. 16789 (mve_vmlaq_n_<supf><mode>): Likewise. 16790 (mve_vmlasq_n_<supf><mode>): Likewise. 16791 (mve_vmlsdavq_p_s<mode>): Likewise. 16792 (mve_vmlsdavxq_p_s<mode>): Likewise. 16793 (mve_vmvnq_m_<supf><mode>): Likewise. 16794 (mve_vnegq_m_s<mode>): Likewise. 16795 (mve_vpselq_<supf><mode>): Likewise. 16796 (mve_vqabsq_m_s<mode>): Likewise. 16797 (mve_vqdmlahq_n_<supf><mode>): Likewise. 16798 (mve_vqnegq_m_s<mode>): Likewise. 16799 (mve_vqrdmladhq_s<mode>): Likewise. 16800 (mve_vqrdmladhxq_s<mode>): Likewise. 16801 (mve_vqrdmlahq_n_<supf><mode>): Likewise. 16802 (mve_vqrdmlashq_n_<supf><mode>): Likewise. 16803 (mve_vqrdmlsdhq_s<mode>): Likewise. 16804 (mve_vqrdmlsdhxq_s<mode>): Likewise. 16805 (mve_vqrshlq_m_n_<supf><mode>): Likewise. 16806 (mve_vqshlq_m_r_<supf><mode>): Likewise. 16807 (mve_vrev64q_m_<supf><mode>): Likewise. 16808 (mve_vrshlq_m_n_<supf><mode>): Likewise. 16809 (mve_vshlq_m_r_<supf><mode>): Likewise. 16810 (mve_vsliq_n_<supf><mode>): Likewise. 16811 (mve_vsriq_n_<supf><mode>): Likewise. 16812 (mve_vqdmlsdhxq_s<mode>): Likewise. 16813 (mve_vqdmlsdhq_s<mode>): Likewise. 16814 (mve_vqdmladhxq_s<mode>): Likewise. 16815 (mve_vqdmladhq_s<mode>): Likewise. 16816 (mve_vmlsdavaxq_s<mode>): Likewise. 16817 (mve_vmlsdavaq_s<mode>): Likewise. 16818 (mve_vmladavaxq_s<mode>): Likewise. 16819 * config/arm/predicates.md (mve_imm_15):Define predicate to check the 16820 matching constraint Rc. 16821 (mve_imm_31): Define predicate to check the matching constraint Re. 16822 168232020-03-18 Andrew Stubbs <ams@codesourcery.com> 16824 16825 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode. 16826 (vec_cmp<mode>di_dup): Likewise. 16827 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. 16828 168292020-03-18 Andrew Stubbs <ams@codesourcery.com> 16830 16831 * config/gcn/gcn-valu.md (COND_MODE): Delete. 16832 (COND_INT_MODE): Delete. 16833 (cond_op): Add "mult". 16834 (cond_<expander><mode>): Use VEC_ALLREG_MODE. 16835 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE. 16836 168372020-03-18 Richard Biener <rguenther@suse.de> 16838 16839 PR middle-end/94206 16840 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using 16841 partial int modes or not mode-precision integer types for 16842 the store. 16843 168442020-03-18 Jakub Jelinek <jakub@redhat.com> 16845 16846 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue 16847 in a comment. 16848 * config/arc/arc.c (frame_stack_add): Likewise. 16849 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): 16850 Likewise. 16851 * ipa-predicate.c (predicate::remap_after_inlining): Likewise. 16852 * tree-ssa-strlen.h (handle_printf_call): Likewise. 16853 * tree-ssa-strlen.c (is_strlen_related_p): Likewise. 16854 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. 16855 168562020-03-18 Duan bo <duanbo3@huawei.com> 16857 16858 PR target/94201 16859 * config/aarch64/aarch64.md (ldr_got_tiny): Delete. 16860 (@ldr_got_tiny_<mode>): New pattern. 16861 (ldr_got_tiny_sidi): Likewise. 16862 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use 16863 them to handle SYMBOL_TINY_GOT for ILP32. 16864 168652020-03-18 Richard Sandiford <richard.sandiford@arm.com> 16866 16867 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as 16868 call-preserved for SVE PCS functions. 16869 (aarch64_layout_frame): Cope with up to 12 predicate save slots. 16870 Optimize the case in which there are no following vector save slots. 16871 168722020-03-18 Richard Biener <rguenther@suse.de> 16873 16874 PR middle-end/94188 16875 * fold-const.c (build_fold_addr_expr): Convert address to 16876 correct type. 16877 * asan.c (maybe_create_ssa_name): Strip useless type conversions. 16878 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1 16879 to build the ADDR_EXPR which we don't really want to simplify. 16880 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise. 16881 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise. 16882 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise. 16883 (simplify_builtin_call): Strip useless type conversions. 16884 * tree-ssa-strlen.c (new_strinfo): Likewise. 16885 168862020-03-17 Alexey Neyman <stilor@att.net> 16887 16888 PR debug/93751 16889 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if 16890 the debug level is terse and the declaration is public. Do not 16891 generate type info. 16892 (dwarf2out_decl): Same. 16893 (add_type_attribute): Return immediately if debug level is 16894 terse. 16895 168962020-03-17 Richard Sandiford <richard.sandiford@arm.com> 16897 16898 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. 16899 169002020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 16901 Mihail Ionescu <mihail.ionescu@arm.com> 16902 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 16903 16904 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): 16905 Define qualifier for ternary operands. 16906 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. 16907 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 16908 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 16909 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. 16910 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 16911 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 16912 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 16913 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. 16914 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 16915 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 16916 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 16917 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 16918 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. 16919 * config/arm/arm_mve.h (vabavq_s8): Define macro. 16920 (vabavq_s16): Likewise. 16921 (vabavq_s32): Likewise. 16922 (vbicq_m_n_s16): Likewise. 16923 (vbicq_m_n_s32): Likewise. 16924 (vbicq_m_n_u16): Likewise. 16925 (vbicq_m_n_u32): Likewise. 16926 (vcmpeqq_m_f16): Likewise. 16927 (vcmpeqq_m_f32): Likewise. 16928 (vcvtaq_m_s16_f16): Likewise. 16929 (vcvtaq_m_u16_f16): Likewise. 16930 (vcvtaq_m_s32_f32): Likewise. 16931 (vcvtaq_m_u32_f32): Likewise. 16932 (vcvtq_m_f16_s16): Likewise. 16933 (vcvtq_m_f16_u16): Likewise. 16934 (vcvtq_m_f32_s32): Likewise. 16935 (vcvtq_m_f32_u32): Likewise. 16936 (vqrshrnbq_n_s16): Likewise. 16937 (vqrshrnbq_n_u16): Likewise. 16938 (vqrshrnbq_n_s32): Likewise. 16939 (vqrshrnbq_n_u32): Likewise. 16940 (vqrshrunbq_n_s16): Likewise. 16941 (vqrshrunbq_n_s32): Likewise. 16942 (vrmlaldavhaq_s32): Likewise. 16943 (vrmlaldavhaq_u32): Likewise. 16944 (vshlcq_s8): Likewise. 16945 (vshlcq_u8): Likewise. 16946 (vshlcq_s16): Likewise. 16947 (vshlcq_u16): Likewise. 16948 (vshlcq_s32): Likewise. 16949 (vshlcq_u32): Likewise. 16950 (vabavq_u8): Likewise. 16951 (vabavq_u16): Likewise. 16952 (vabavq_u32): Likewise. 16953 (__arm_vabavq_s8): Define intrinsic. 16954 (__arm_vabavq_s16): Likewise. 16955 (__arm_vabavq_s32): Likewise. 16956 (__arm_vabavq_u8): Likewise. 16957 (__arm_vabavq_u16): Likewise. 16958 (__arm_vabavq_u32): Likewise. 16959 (__arm_vbicq_m_n_s16): Likewise. 16960 (__arm_vbicq_m_n_s32): Likewise. 16961 (__arm_vbicq_m_n_u16): Likewise. 16962 (__arm_vbicq_m_n_u32): Likewise. 16963 (__arm_vqrshrnbq_n_s16): Likewise. 16964 (__arm_vqrshrnbq_n_u16): Likewise. 16965 (__arm_vqrshrnbq_n_s32): Likewise. 16966 (__arm_vqrshrnbq_n_u32): Likewise. 16967 (__arm_vqrshrunbq_n_s16): Likewise. 16968 (__arm_vqrshrunbq_n_s32): Likewise. 16969 (__arm_vrmlaldavhaq_s32): Likewise. 16970 (__arm_vrmlaldavhaq_u32): Likewise. 16971 (__arm_vshlcq_s8): Likewise. 16972 (__arm_vshlcq_u8): Likewise. 16973 (__arm_vshlcq_s16): Likewise. 16974 (__arm_vshlcq_u16): Likewise. 16975 (__arm_vshlcq_s32): Likewise. 16976 (__arm_vshlcq_u32): Likewise. 16977 (__arm_vcmpeqq_m_f16): Likewise. 16978 (__arm_vcmpeqq_m_f32): Likewise. 16979 (__arm_vcvtaq_m_s16_f16): Likewise. 16980 (__arm_vcvtaq_m_u16_f16): Likewise. 16981 (__arm_vcvtaq_m_s32_f32): Likewise. 16982 (__arm_vcvtaq_m_u32_f32): Likewise. 16983 (__arm_vcvtq_m_f16_s16): Likewise. 16984 (__arm_vcvtq_m_f16_u16): Likewise. 16985 (__arm_vcvtq_m_f32_s32): Likewise. 16986 (__arm_vcvtq_m_f32_u32): Likewise. 16987 (vcvtaq_m): Define polymorphic variant. 16988 (vcvtq_m): Likewise. 16989 (vabavq): Likewise. 16990 (vshlcq): Likewise. 16991 (vbicq_m_n): Likewise. 16992 (vqrshrnbq_n): Likewise. 16993 (vqrshrunbq_n): Likewise. 16994 * config/arm/arm_mve_builtins.def 16995 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer. 16996 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. 16997 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 16998 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. 16999 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. 17000 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. 17001 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. 17002 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 17003 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. 17004 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. 17005 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. 17006 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 17007 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 17008 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. 17009 * config/arm/mve.md (VBICQ_M_N): Define iterator. 17010 (VCVTAQ_M): Likewise. 17011 (VCVTQ_M_TO_F): Likewise. 17012 (VQRSHRNBQ_N): Likewise. 17013 (VABAVQ): Likewise. 17014 (VSHLCQ): Likewise. 17015 (VRMLALDAVHAQ): Likewise. 17016 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern. 17017 (mve_vcmpeqq_m_f<mode>): Likewise. 17018 (mve_vcvtaq_m_<supf><mode>): Likewise. 17019 (mve_vcvtq_m_to_f_<supf><mode>): Likewise. 17020 (mve_vqrshrnbq_n_<supf><mode>): Likewise. 17021 (mve_vqrshrunbq_n_s<mode>): Likewise. 17022 (mve_vrmlaldavhaq_<supf>v4si): Likewise. 17023 (mve_vabavq_<supf><mode>): Likewise. 17024 (mve_vshlcq_<supf><mode>): Likewise. 17025 (mve_vshlcq_<supf><mode>): Likewise. 17026 (mve_vshlcq_vec_<supf><mode>): Define RTL expand. 17027 (mve_vshlcq_carry_<supf><mode>): Likewise. 17028 170292020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 17030 Mihail Ionescu <mihail.ionescu@arm.com> 17031 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 17032 17033 * config/arm/arm_mve.h (vqmovntq_u16): Define macro. 17034 (vqmovnbq_u16): Likewise. 17035 (vmulltq_poly_p8): Likewise. 17036 (vmullbq_poly_p8): Likewise. 17037 (vmovntq_u16): Likewise. 17038 (vmovnbq_u16): Likewise. 17039 (vmlaldavxq_u16): Likewise. 17040 (vmlaldavq_u16): Likewise. 17041 (vqmovuntq_s16): Likewise. 17042 (vqmovunbq_s16): Likewise. 17043 (vshlltq_n_u8): Likewise. 17044 (vshllbq_n_u8): Likewise. 17045 (vorrq_n_u16): Likewise. 17046 (vbicq_n_u16): Likewise. 17047 (vcmpneq_n_f16): Likewise. 17048 (vcmpneq_f16): Likewise. 17049 (vcmpltq_n_f16): Likewise. 17050 (vcmpltq_f16): Likewise. 17051 (vcmpleq_n_f16): Likewise. 17052 (vcmpleq_f16): Likewise. 17053 (vcmpgtq_n_f16): Likewise. 17054 (vcmpgtq_f16): Likewise. 17055 (vcmpgeq_n_f16): Likewise. 17056 (vcmpgeq_f16): Likewise. 17057 (vcmpeqq_n_f16): Likewise. 17058 (vcmpeqq_f16): Likewise. 17059 (vsubq_f16): Likewise. 17060 (vqmovntq_s16): Likewise. 17061 (vqmovnbq_s16): Likewise. 17062 (vqdmulltq_s16): Likewise. 17063 (vqdmulltq_n_s16): Likewise. 17064 (vqdmullbq_s16): Likewise. 17065 (vqdmullbq_n_s16): Likewise. 17066 (vorrq_f16): Likewise. 17067 (vornq_f16): Likewise. 17068 (vmulq_n_f16): Likewise. 17069 (vmulq_f16): Likewise. 17070 (vmovntq_s16): Likewise. 17071 (vmovnbq_s16): Likewise. 17072 (vmlsldavxq_s16): Likewise. 17073 (vmlsldavq_s16): Likewise. 17074 (vmlaldavxq_s16): Likewise. 17075 (vmlaldavq_s16): Likewise. 17076 (vminnmvq_f16): Likewise. 17077 (vminnmq_f16): Likewise. 17078 (vminnmavq_f16): Likewise. 17079 (vminnmaq_f16): Likewise. 17080 (vmaxnmvq_f16): Likewise. 17081 (vmaxnmq_f16): Likewise. 17082 (vmaxnmavq_f16): Likewise. 17083 (vmaxnmaq_f16): Likewise. 17084 (veorq_f16): Likewise. 17085 (vcmulq_rot90_f16): Likewise. 17086 (vcmulq_rot270_f16): Likewise. 17087 (vcmulq_rot180_f16): Likewise. 17088 (vcmulq_f16): Likewise. 17089 (vcaddq_rot90_f16): Likewise. 17090 (vcaddq_rot270_f16): Likewise. 17091 (vbicq_f16): Likewise. 17092 (vandq_f16): Likewise. 17093 (vaddq_n_f16): Likewise. 17094 (vabdq_f16): Likewise. 17095 (vshlltq_n_s8): Likewise. 17096 (vshllbq_n_s8): Likewise. 17097 (vorrq_n_s16): Likewise. 17098 (vbicq_n_s16): Likewise. 17099 (vqmovntq_u32): Likewise. 17100 (vqmovnbq_u32): Likewise. 17101 (vmulltq_poly_p16): Likewise. 17102 (vmullbq_poly_p16): Likewise. 17103 (vmovntq_u32): Likewise. 17104 (vmovnbq_u32): Likewise. 17105 (vmlaldavxq_u32): Likewise. 17106 (vmlaldavq_u32): Likewise. 17107 (vqmovuntq_s32): Likewise. 17108 (vqmovunbq_s32): Likewise. 17109 (vshlltq_n_u16): Likewise. 17110 (vshllbq_n_u16): Likewise. 17111 (vorrq_n_u32): Likewise. 17112 (vbicq_n_u32): Likewise. 17113 (vcmpneq_n_f32): Likewise. 17114 (vcmpneq_f32): Likewise. 17115 (vcmpltq_n_f32): Likewise. 17116 (vcmpltq_f32): Likewise. 17117 (vcmpleq_n_f32): Likewise. 17118 (vcmpleq_f32): Likewise. 17119 (vcmpgtq_n_f32): Likewise. 17120 (vcmpgtq_f32): Likewise. 17121 (vcmpgeq_n_f32): Likewise. 17122 (vcmpgeq_f32): Likewise. 17123 (vcmpeqq_n_f32): Likewise. 17124 (vcmpeqq_f32): Likewise. 17125 (vsubq_f32): Likewise. 17126 (vqmovntq_s32): Likewise. 17127 (vqmovnbq_s32): Likewise. 17128 (vqdmulltq_s32): Likewise. 17129 (vqdmulltq_n_s32): Likewise. 17130 (vqdmullbq_s32): Likewise. 17131 (vqdmullbq_n_s32): Likewise. 17132 (vorrq_f32): Likewise. 17133 (vornq_f32): Likewise. 17134 (vmulq_n_f32): Likewise. 17135 (vmulq_f32): Likewise. 17136 (vmovntq_s32): Likewise. 17137 (vmovnbq_s32): Likewise. 17138 (vmlsldavxq_s32): Likewise. 17139 (vmlsldavq_s32): Likewise. 17140 (vmlaldavxq_s32): Likewise. 17141 (vmlaldavq_s32): Likewise. 17142 (vminnmvq_f32): Likewise. 17143 (vminnmq_f32): Likewise. 17144 (vminnmavq_f32): Likewise. 17145 (vminnmaq_f32): Likewise. 17146 (vmaxnmvq_f32): Likewise. 17147 (vmaxnmq_f32): Likewise. 17148 (vmaxnmavq_f32): Likewise. 17149 (vmaxnmaq_f32): Likewise. 17150 (veorq_f32): Likewise. 17151 (vcmulq_rot90_f32): Likewise. 17152 (vcmulq_rot270_f32): Likewise. 17153 (vcmulq_rot180_f32): Likewise. 17154 (vcmulq_f32): Likewise. 17155 (vcaddq_rot90_f32): Likewise. 17156 (vcaddq_rot270_f32): Likewise. 17157 (vbicq_f32): Likewise. 17158 (vandq_f32): Likewise. 17159 (vaddq_n_f32): Likewise. 17160 (vabdq_f32): Likewise. 17161 (vshlltq_n_s16): Likewise. 17162 (vshllbq_n_s16): Likewise. 17163 (vorrq_n_s32): Likewise. 17164 (vbicq_n_s32): Likewise. 17165 (vrmlaldavhq_u32): Likewise. 17166 (vctp8q_m): Likewise. 17167 (vctp64q_m): Likewise. 17168 (vctp32q_m): Likewise. 17169 (vctp16q_m): Likewise. 17170 (vaddlvaq_u32): Likewise. 17171 (vrmlsldavhxq_s32): Likewise. 17172 (vrmlsldavhq_s32): Likewise. 17173 (vrmlaldavhxq_s32): Likewise. 17174 (vrmlaldavhq_s32): Likewise. 17175 (vcvttq_f16_f32): Likewise. 17176 (vcvtbq_f16_f32): Likewise. 17177 (vaddlvaq_s32): Likewise. 17178 (__arm_vqmovntq_u16): Define intrinsic. 17179 (__arm_vqmovnbq_u16): Likewise. 17180 (__arm_vmulltq_poly_p8): Likewise. 17181 (__arm_vmullbq_poly_p8): Likewise. 17182 (__arm_vmovntq_u16): Likewise. 17183 (__arm_vmovnbq_u16): Likewise. 17184 (__arm_vmlaldavxq_u16): Likewise. 17185 (__arm_vmlaldavq_u16): Likewise. 17186 (__arm_vqmovuntq_s16): Likewise. 17187 (__arm_vqmovunbq_s16): Likewise. 17188 (__arm_vshlltq_n_u8): Likewise. 17189 (__arm_vshllbq_n_u8): Likewise. 17190 (__arm_vorrq_n_u16): Likewise. 17191 (__arm_vbicq_n_u16): Likewise. 17192 (__arm_vcmpneq_n_f16): Likewise. 17193 (__arm_vcmpneq_f16): Likewise. 17194 (__arm_vcmpltq_n_f16): Likewise. 17195 (__arm_vcmpltq_f16): Likewise. 17196 (__arm_vcmpleq_n_f16): Likewise. 17197 (__arm_vcmpleq_f16): Likewise. 17198 (__arm_vcmpgtq_n_f16): Likewise. 17199 (__arm_vcmpgtq_f16): Likewise. 17200 (__arm_vcmpgeq_n_f16): Likewise. 17201 (__arm_vcmpgeq_f16): Likewise. 17202 (__arm_vcmpeqq_n_f16): Likewise. 17203 (__arm_vcmpeqq_f16): Likewise. 17204 (__arm_vsubq_f16): Likewise. 17205 (__arm_vqmovntq_s16): Likewise. 17206 (__arm_vqmovnbq_s16): Likewise. 17207 (__arm_vqdmulltq_s16): Likewise. 17208 (__arm_vqdmulltq_n_s16): Likewise. 17209 (__arm_vqdmullbq_s16): Likewise. 17210 (__arm_vqdmullbq_n_s16): Likewise. 17211 (__arm_vorrq_f16): Likewise. 17212 (__arm_vornq_f16): Likewise. 17213 (__arm_vmulq_n_f16): Likewise. 17214 (__arm_vmulq_f16): Likewise. 17215 (__arm_vmovntq_s16): Likewise. 17216 (__arm_vmovnbq_s16): Likewise. 17217 (__arm_vmlsldavxq_s16): Likewise. 17218 (__arm_vmlsldavq_s16): Likewise. 17219 (__arm_vmlaldavxq_s16): Likewise. 17220 (__arm_vmlaldavq_s16): Likewise. 17221 (__arm_vminnmvq_f16): Likewise. 17222 (__arm_vminnmq_f16): Likewise. 17223 (__arm_vminnmavq_f16): Likewise. 17224 (__arm_vminnmaq_f16): Likewise. 17225 (__arm_vmaxnmvq_f16): Likewise. 17226 (__arm_vmaxnmq_f16): Likewise. 17227 (__arm_vmaxnmavq_f16): Likewise. 17228 (__arm_vmaxnmaq_f16): Likewise. 17229 (__arm_veorq_f16): Likewise. 17230 (__arm_vcmulq_rot90_f16): Likewise. 17231 (__arm_vcmulq_rot270_f16): Likewise. 17232 (__arm_vcmulq_rot180_f16): Likewise. 17233 (__arm_vcmulq_f16): Likewise. 17234 (__arm_vcaddq_rot90_f16): Likewise. 17235 (__arm_vcaddq_rot270_f16): Likewise. 17236 (__arm_vbicq_f16): Likewise. 17237 (__arm_vandq_f16): Likewise. 17238 (__arm_vaddq_n_f16): Likewise. 17239 (__arm_vabdq_f16): Likewise. 17240 (__arm_vshlltq_n_s8): Likewise. 17241 (__arm_vshllbq_n_s8): Likewise. 17242 (__arm_vorrq_n_s16): Likewise. 17243 (__arm_vbicq_n_s16): Likewise. 17244 (__arm_vqmovntq_u32): Likewise. 17245 (__arm_vqmovnbq_u32): Likewise. 17246 (__arm_vmulltq_poly_p16): Likewise. 17247 (__arm_vmullbq_poly_p16): Likewise. 17248 (__arm_vmovntq_u32): Likewise. 17249 (__arm_vmovnbq_u32): Likewise. 17250 (__arm_vmlaldavxq_u32): Likewise. 17251 (__arm_vmlaldavq_u32): Likewise. 17252 (__arm_vqmovuntq_s32): Likewise. 17253 (__arm_vqmovunbq_s32): Likewise. 17254 (__arm_vshlltq_n_u16): Likewise. 17255 (__arm_vshllbq_n_u16): Likewise. 17256 (__arm_vorrq_n_u32): Likewise. 17257 (__arm_vbicq_n_u32): Likewise. 17258 (__arm_vcmpneq_n_f32): Likewise. 17259 (__arm_vcmpneq_f32): Likewise. 17260 (__arm_vcmpltq_n_f32): Likewise. 17261 (__arm_vcmpltq_f32): Likewise. 17262 (__arm_vcmpleq_n_f32): Likewise. 17263 (__arm_vcmpleq_f32): Likewise. 17264 (__arm_vcmpgtq_n_f32): Likewise. 17265 (__arm_vcmpgtq_f32): Likewise. 17266 (__arm_vcmpgeq_n_f32): Likewise. 17267 (__arm_vcmpgeq_f32): Likewise. 17268 (__arm_vcmpeqq_n_f32): Likewise. 17269 (__arm_vcmpeqq_f32): Likewise. 17270 (__arm_vsubq_f32): Likewise. 17271 (__arm_vqmovntq_s32): Likewise. 17272 (__arm_vqmovnbq_s32): Likewise. 17273 (__arm_vqdmulltq_s32): Likewise. 17274 (__arm_vqdmulltq_n_s32): Likewise. 17275 (__arm_vqdmullbq_s32): Likewise. 17276 (__arm_vqdmullbq_n_s32): Likewise. 17277 (__arm_vorrq_f32): Likewise. 17278 (__arm_vornq_f32): Likewise. 17279 (__arm_vmulq_n_f32): Likewise. 17280 (__arm_vmulq_f32): Likewise. 17281 (__arm_vmovntq_s32): Likewise. 17282 (__arm_vmovnbq_s32): Likewise. 17283 (__arm_vmlsldavxq_s32): Likewise. 17284 (__arm_vmlsldavq_s32): Likewise. 17285 (__arm_vmlaldavxq_s32): Likewise. 17286 (__arm_vmlaldavq_s32): Likewise. 17287 (__arm_vminnmvq_f32): Likewise. 17288 (__arm_vminnmq_f32): Likewise. 17289 (__arm_vminnmavq_f32): Likewise. 17290 (__arm_vminnmaq_f32): Likewise. 17291 (__arm_vmaxnmvq_f32): Likewise. 17292 (__arm_vmaxnmq_f32): Likewise. 17293 (__arm_vmaxnmavq_f32): Likewise. 17294 (__arm_vmaxnmaq_f32): Likewise. 17295 (__arm_veorq_f32): Likewise. 17296 (__arm_vcmulq_rot90_f32): Likewise. 17297 (__arm_vcmulq_rot270_f32): Likewise. 17298 (__arm_vcmulq_rot180_f32): Likewise. 17299 (__arm_vcmulq_f32): Likewise. 17300 (__arm_vcaddq_rot90_f32): Likewise. 17301 (__arm_vcaddq_rot270_f32): Likewise. 17302 (__arm_vbicq_f32): Likewise. 17303 (__arm_vandq_f32): Likewise. 17304 (__arm_vaddq_n_f32): Likewise. 17305 (__arm_vabdq_f32): Likewise. 17306 (__arm_vshlltq_n_s16): Likewise. 17307 (__arm_vshllbq_n_s16): Likewise. 17308 (__arm_vorrq_n_s32): Likewise. 17309 (__arm_vbicq_n_s32): Likewise. 17310 (__arm_vrmlaldavhq_u32): Likewise. 17311 (__arm_vctp8q_m): Likewise. 17312 (__arm_vctp64q_m): Likewise. 17313 (__arm_vctp32q_m): Likewise. 17314 (__arm_vctp16q_m): Likewise. 17315 (__arm_vaddlvaq_u32): Likewise. 17316 (__arm_vrmlsldavhxq_s32): Likewise. 17317 (__arm_vrmlsldavhq_s32): Likewise. 17318 (__arm_vrmlaldavhxq_s32): Likewise. 17319 (__arm_vrmlaldavhq_s32): Likewise. 17320 (__arm_vcvttq_f16_f32): Likewise. 17321 (__arm_vcvtbq_f16_f32): Likewise. 17322 (__arm_vaddlvaq_s32): Likewise. 17323 (vst4q): Define polymorphic variant. 17324 (vrndxq): Likewise. 17325 (vrndq): Likewise. 17326 (vrndpq): Likewise. 17327 (vrndnq): Likewise. 17328 (vrndmq): Likewise. 17329 (vrndaq): Likewise. 17330 (vrev64q): Likewise. 17331 (vnegq): Likewise. 17332 (vdupq_n): Likewise. 17333 (vabsq): Likewise. 17334 (vrev32q): Likewise. 17335 (vcvtbq_f32): Likewise. 17336 (vcvttq_f32): Likewise. 17337 (vcvtq): Likewise. 17338 (vsubq_n): Likewise. 17339 (vbrsrq_n): Likewise. 17340 (vcvtq_n): Likewise. 17341 (vsubq): Likewise. 17342 (vorrq): Likewise. 17343 (vabdq): Likewise. 17344 (vaddq_n): Likewise. 17345 (vandq): Likewise. 17346 (vbicq): Likewise. 17347 (vornq): Likewise. 17348 (vmulq_n): Likewise. 17349 (vmulq): Likewise. 17350 (vcaddq_rot270): Likewise. 17351 (vcmpeqq_n): Likewise. 17352 (vcmpeqq): Likewise. 17353 (vcaddq_rot90): Likewise. 17354 (vcmpgeq_n): Likewise. 17355 (vcmpgeq): Likewise. 17356 (vcmpgtq_n): Likewise. 17357 (vcmpgtq): Likewise. 17358 (vcmpgtq): Likewise. 17359 (vcmpleq_n): Likewise. 17360 (vcmpleq_n): Likewise. 17361 (vcmpleq): Likewise. 17362 (vcmpleq): Likewise. 17363 (vcmpltq_n): Likewise. 17364 (vcmpltq_n): Likewise. 17365 (vcmpltq): Likewise. 17366 (vcmpltq): Likewise. 17367 (vcmpneq_n): Likewise. 17368 (vcmpneq_n): Likewise. 17369 (vcmpneq): Likewise. 17370 (vcmpneq): Likewise. 17371 (vcmulq): Likewise. 17372 (vcmulq): Likewise. 17373 (vcmulq_rot180): Likewise. 17374 (vcmulq_rot180): Likewise. 17375 (vcmulq_rot270): Likewise. 17376 (vcmulq_rot270): Likewise. 17377 (vcmulq_rot90): Likewise. 17378 (vcmulq_rot90): Likewise. 17379 (veorq): Likewise. 17380 (veorq): Likewise. 17381 (vmaxnmaq): Likewise. 17382 (vmaxnmaq): Likewise. 17383 (vmaxnmavq): Likewise. 17384 (vmaxnmavq): Likewise. 17385 (vmaxnmq): Likewise. 17386 (vmaxnmq): Likewise. 17387 (vmaxnmvq): Likewise. 17388 (vmaxnmvq): Likewise. 17389 (vminnmaq): Likewise. 17390 (vminnmaq): Likewise. 17391 (vminnmavq): Likewise. 17392 (vminnmavq): Likewise. 17393 (vminnmq): Likewise. 17394 (vminnmq): Likewise. 17395 (vminnmvq): Likewise. 17396 (vminnmvq): Likewise. 17397 (vbicq_n): Likewise. 17398 (vqmovntq): Likewise. 17399 (vqmovntq): Likewise. 17400 (vqmovnbq): Likewise. 17401 (vqmovnbq): Likewise. 17402 (vmulltq_poly): Likewise. 17403 (vmulltq_poly): Likewise. 17404 (vmullbq_poly): Likewise. 17405 (vmullbq_poly): Likewise. 17406 (vmovntq): Likewise. 17407 (vmovntq): Likewise. 17408 (vmovnbq): Likewise. 17409 (vmovnbq): Likewise. 17410 (vmlaldavxq): Likewise. 17411 (vmlaldavxq): Likewise. 17412 (vqmovuntq): Likewise. 17413 (vqmovuntq): Likewise. 17414 (vshlltq_n): Likewise. 17415 (vshlltq_n): Likewise. 17416 (vshllbq_n): Likewise. 17417 (vshllbq_n): Likewise. 17418 (vorrq_n): Likewise. 17419 (vorrq_n): Likewise. 17420 (vmlaldavq): Likewise. 17421 (vmlaldavq): Likewise. 17422 (vqmovunbq): Likewise. 17423 (vqmovunbq): Likewise. 17424 (vqdmulltq_n): Likewise. 17425 (vqdmulltq_n): Likewise. 17426 (vqdmulltq): Likewise. 17427 (vqdmulltq): Likewise. 17428 (vqdmullbq_n): Likewise. 17429 (vqdmullbq_n): Likewise. 17430 (vqdmullbq): Likewise. 17431 (vqdmullbq): Likewise. 17432 (vaddlvaq): Likewise. 17433 (vaddlvaq): Likewise. 17434 (vrmlaldavhq): Likewise. 17435 (vrmlaldavhq): Likewise. 17436 (vrmlaldavhxq): Likewise. 17437 (vrmlaldavhxq): Likewise. 17438 (vrmlsldavhq): Likewise. 17439 (vrmlsldavhq): Likewise. 17440 (vrmlsldavhxq): Likewise. 17441 (vrmlsldavhxq): Likewise. 17442 (vmlsldavxq): Likewise. 17443 (vmlsldavxq): Likewise. 17444 (vmlsldavq): Likewise. 17445 (vmlsldavq): Likewise. 17446 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. 17447 (BINOP_NONE_NONE_NONE): Likewise. 17448 (BINOP_UNONE_NONE_NONE): Likewise. 17449 (BINOP_UNONE_UNONE_IMM): Likewise. 17450 (BINOP_UNONE_UNONE_NONE): Likewise. 17451 (BINOP_UNONE_UNONE_UNONE): Likewise. 17452 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern. 17453 (mve_vaddlvaq_<supf>v4si): Likewise. 17454 (mve_vaddq_n_f<mode>): Likewise. 17455 (mve_vandq_f<mode>): Likewise. 17456 (mve_vbicq_f<mode>): Likewise. 17457 (mve_vbicq_n_<supf><mode>): Likewise. 17458 (mve_vcaddq_rot270_f<mode>): Likewise. 17459 (mve_vcaddq_rot90_f<mode>): Likewise. 17460 (mve_vcmpeqq_f<mode>): Likewise. 17461 (mve_vcmpeqq_n_f<mode>): Likewise. 17462 (mve_vcmpgeq_f<mode>): Likewise. 17463 (mve_vcmpgeq_n_f<mode>): Likewise. 17464 (mve_vcmpgtq_f<mode>): Likewise. 17465 (mve_vcmpgtq_n_f<mode>): Likewise. 17466 (mve_vcmpleq_f<mode>): Likewise. 17467 (mve_vcmpleq_n_f<mode>): Likewise. 17468 (mve_vcmpltq_f<mode>): Likewise. 17469 (mve_vcmpltq_n_f<mode>): Likewise. 17470 (mve_vcmpneq_f<mode>): Likewise. 17471 (mve_vcmpneq_n_f<mode>): Likewise. 17472 (mve_vcmulq_f<mode>): Likewise. 17473 (mve_vcmulq_rot180_f<mode>): Likewise. 17474 (mve_vcmulq_rot270_f<mode>): Likewise. 17475 (mve_vcmulq_rot90_f<mode>): Likewise. 17476 (mve_vctp<mode1>q_mhi): Likewise. 17477 (mve_vcvtbq_f16_f32v8hf): Likewise. 17478 (mve_vcvttq_f16_f32v8hf): Likewise. 17479 (mve_veorq_f<mode>): Likewise. 17480 (mve_vmaxnmaq_f<mode>): Likewise. 17481 (mve_vmaxnmavq_f<mode>): Likewise. 17482 (mve_vmaxnmq_f<mode>): Likewise. 17483 (mve_vmaxnmvq_f<mode>): Likewise. 17484 (mve_vminnmaq_f<mode>): Likewise. 17485 (mve_vminnmavq_f<mode>): Likewise. 17486 (mve_vminnmq_f<mode>): Likewise. 17487 (mve_vminnmvq_f<mode>): Likewise. 17488 (mve_vmlaldavq_<supf><mode>): Likewise. 17489 (mve_vmlaldavxq_<supf><mode>): Likewise. 17490 (mve_vmlsldavq_s<mode>): Likewise. 17491 (mve_vmlsldavxq_s<mode>): Likewise. 17492 (mve_vmovnbq_<supf><mode>): Likewise. 17493 (mve_vmovntq_<supf><mode>): Likewise. 17494 (mve_vmulq_f<mode>): Likewise. 17495 (mve_vmulq_n_f<mode>): Likewise. 17496 (mve_vornq_f<mode>): Likewise. 17497 (mve_vorrq_f<mode>): Likewise. 17498 (mve_vorrq_n_<supf><mode>): Likewise. 17499 (mve_vqdmullbq_n_s<mode>): Likewise. 17500 (mve_vqdmullbq_s<mode>): Likewise. 17501 (mve_vqdmulltq_n_s<mode>): Likewise. 17502 (mve_vqdmulltq_s<mode>): Likewise. 17503 (mve_vqmovnbq_<supf><mode>): Likewise. 17504 (mve_vqmovntq_<supf><mode>): Likewise. 17505 (mve_vqmovunbq_s<mode>): Likewise. 17506 (mve_vqmovuntq_s<mode>): Likewise. 17507 (mve_vrmlaldavhxq_sv4si): Likewise. 17508 (mve_vrmlsldavhq_sv4si): Likewise. 17509 (mve_vrmlsldavhxq_sv4si): Likewise. 17510 (mve_vshllbq_n_<supf><mode>): Likewise. 17511 (mve_vshlltq_n_<supf><mode>): Likewise. 17512 (mve_vsubq_f<mode>): Likewise. 17513 (mve_vmulltq_poly_p<mode>): Likewise. 17514 (mve_vmullbq_poly_p<mode>): Likewise. 17515 (mve_vrmlaldavhq_<supf>v4si): Likewise. 17516 175172020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 17518 Mihail Ionescu <mihail.ionescu@arm.com> 17519 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 17520 17521 * config/arm/arm_mve.h (vsubq_u8): Define macro. 17522 (vsubq_n_u8): Likewise. 17523 (vrmulhq_u8): Likewise. 17524 (vrhaddq_u8): Likewise. 17525 (vqsubq_u8): Likewise. 17526 (vqsubq_n_u8): Likewise. 17527 (vqaddq_u8): Likewise. 17528 (vqaddq_n_u8): Likewise. 17529 (vorrq_u8): Likewise. 17530 (vornq_u8): Likewise. 17531 (vmulq_u8): Likewise. 17532 (vmulq_n_u8): Likewise. 17533 (vmulltq_int_u8): Likewise. 17534 (vmullbq_int_u8): Likewise. 17535 (vmulhq_u8): Likewise. 17536 (vmladavq_u8): Likewise. 17537 (vminvq_u8): Likewise. 17538 (vminq_u8): Likewise. 17539 (vmaxvq_u8): Likewise. 17540 (vmaxq_u8): Likewise. 17541 (vhsubq_u8): Likewise. 17542 (vhsubq_n_u8): Likewise. 17543 (vhaddq_u8): Likewise. 17544 (vhaddq_n_u8): Likewise. 17545 (veorq_u8): Likewise. 17546 (vcmpneq_n_u8): Likewise. 17547 (vcmphiq_u8): Likewise. 17548 (vcmphiq_n_u8): Likewise. 17549 (vcmpeqq_u8): Likewise. 17550 (vcmpeqq_n_u8): Likewise. 17551 (vcmpcsq_u8): Likewise. 17552 (vcmpcsq_n_u8): Likewise. 17553 (vcaddq_rot90_u8): Likewise. 17554 (vcaddq_rot270_u8): Likewise. 17555 (vbicq_u8): Likewise. 17556 (vandq_u8): Likewise. 17557 (vaddvq_p_u8): Likewise. 17558 (vaddvaq_u8): Likewise. 17559 (vaddq_n_u8): Likewise. 17560 (vabdq_u8): Likewise. 17561 (vshlq_r_u8): Likewise. 17562 (vrshlq_u8): Likewise. 17563 (vrshlq_n_u8): Likewise. 17564 (vqshlq_u8): Likewise. 17565 (vqshlq_r_u8): Likewise. 17566 (vqrshlq_u8): Likewise. 17567 (vqrshlq_n_u8): Likewise. 17568 (vminavq_s8): Likewise. 17569 (vminaq_s8): Likewise. 17570 (vmaxavq_s8): Likewise. 17571 (vmaxaq_s8): Likewise. 17572 (vbrsrq_n_u8): Likewise. 17573 (vshlq_n_u8): Likewise. 17574 (vrshrq_n_u8): Likewise. 17575 (vqshlq_n_u8): Likewise. 17576 (vcmpneq_n_s8): Likewise. 17577 (vcmpltq_s8): Likewise. 17578 (vcmpltq_n_s8): Likewise. 17579 (vcmpleq_s8): Likewise. 17580 (vcmpleq_n_s8): Likewise. 17581 (vcmpgtq_s8): Likewise. 17582 (vcmpgtq_n_s8): Likewise. 17583 (vcmpgeq_s8): Likewise. 17584 (vcmpgeq_n_s8): Likewise. 17585 (vcmpeqq_s8): Likewise. 17586 (vcmpeqq_n_s8): Likewise. 17587 (vqshluq_n_s8): Likewise. 17588 (vaddvq_p_s8): Likewise. 17589 (vsubq_s8): Likewise. 17590 (vsubq_n_s8): Likewise. 17591 (vshlq_r_s8): Likewise. 17592 (vrshlq_s8): Likewise. 17593 (vrshlq_n_s8): Likewise. 17594 (vrmulhq_s8): Likewise. 17595 (vrhaddq_s8): Likewise. 17596 (vqsubq_s8): Likewise. 17597 (vqsubq_n_s8): Likewise. 17598 (vqshlq_s8): Likewise. 17599 (vqshlq_r_s8): Likewise. 17600 (vqrshlq_s8): Likewise. 17601 (vqrshlq_n_s8): Likewise. 17602 (vqrdmulhq_s8): Likewise. 17603 (vqrdmulhq_n_s8): Likewise. 17604 (vqdmulhq_s8): Likewise. 17605 (vqdmulhq_n_s8): Likewise. 17606 (vqaddq_s8): Likewise. 17607 (vqaddq_n_s8): Likewise. 17608 (vorrq_s8): Likewise. 17609 (vornq_s8): Likewise. 17610 (vmulq_s8): Likewise. 17611 (vmulq_n_s8): Likewise. 17612 (vmulltq_int_s8): Likewise. 17613 (vmullbq_int_s8): Likewise. 17614 (vmulhq_s8): Likewise. 17615 (vmlsdavxq_s8): Likewise. 17616 (vmlsdavq_s8): Likewise. 17617 (vmladavxq_s8): Likewise. 17618 (vmladavq_s8): Likewise. 17619 (vminvq_s8): Likewise. 17620 (vminq_s8): Likewise. 17621 (vmaxvq_s8): Likewise. 17622 (vmaxq_s8): Likewise. 17623 (vhsubq_s8): Likewise. 17624 (vhsubq_n_s8): Likewise. 17625 (vhcaddq_rot90_s8): Likewise. 17626 (vhcaddq_rot270_s8): Likewise. 17627 (vhaddq_s8): Likewise. 17628 (vhaddq_n_s8): Likewise. 17629 (veorq_s8): Likewise. 17630 (vcaddq_rot90_s8): Likewise. 17631 (vcaddq_rot270_s8): Likewise. 17632 (vbrsrq_n_s8): Likewise. 17633 (vbicq_s8): Likewise. 17634 (vandq_s8): Likewise. 17635 (vaddvaq_s8): Likewise. 17636 (vaddq_n_s8): Likewise. 17637 (vabdq_s8): Likewise. 17638 (vshlq_n_s8): Likewise. 17639 (vrshrq_n_s8): Likewise. 17640 (vqshlq_n_s8): Likewise. 17641 (vsubq_u16): Likewise. 17642 (vsubq_n_u16): Likewise. 17643 (vrmulhq_u16): Likewise. 17644 (vrhaddq_u16): Likewise. 17645 (vqsubq_u16): Likewise. 17646 (vqsubq_n_u16): Likewise. 17647 (vqaddq_u16): Likewise. 17648 (vqaddq_n_u16): Likewise. 17649 (vorrq_u16): Likewise. 17650 (vornq_u16): Likewise. 17651 (vmulq_u16): Likewise. 17652 (vmulq_n_u16): Likewise. 17653 (vmulltq_int_u16): Likewise. 17654 (vmullbq_int_u16): Likewise. 17655 (vmulhq_u16): Likewise. 17656 (vmladavq_u16): Likewise. 17657 (vminvq_u16): Likewise. 17658 (vminq_u16): Likewise. 17659 (vmaxvq_u16): Likewise. 17660 (vmaxq_u16): Likewise. 17661 (vhsubq_u16): Likewise. 17662 (vhsubq_n_u16): Likewise. 17663 (vhaddq_u16): Likewise. 17664 (vhaddq_n_u16): Likewise. 17665 (veorq_u16): Likewise. 17666 (vcmpneq_n_u16): Likewise. 17667 (vcmphiq_u16): Likewise. 17668 (vcmphiq_n_u16): Likewise. 17669 (vcmpeqq_u16): Likewise. 17670 (vcmpeqq_n_u16): Likewise. 17671 (vcmpcsq_u16): Likewise. 17672 (vcmpcsq_n_u16): Likewise. 17673 (vcaddq_rot90_u16): Likewise. 17674 (vcaddq_rot270_u16): Likewise. 17675 (vbicq_u16): Likewise. 17676 (vandq_u16): Likewise. 17677 (vaddvq_p_u16): Likewise. 17678 (vaddvaq_u16): Likewise. 17679 (vaddq_n_u16): Likewise. 17680 (vabdq_u16): Likewise. 17681 (vshlq_r_u16): Likewise. 17682 (vrshlq_u16): Likewise. 17683 (vrshlq_n_u16): Likewise. 17684 (vqshlq_u16): Likewise. 17685 (vqshlq_r_u16): Likewise. 17686 (vqrshlq_u16): Likewise. 17687 (vqrshlq_n_u16): Likewise. 17688 (vminavq_s16): Likewise. 17689 (vminaq_s16): Likewise. 17690 (vmaxavq_s16): Likewise. 17691 (vmaxaq_s16): Likewise. 17692 (vbrsrq_n_u16): Likewise. 17693 (vshlq_n_u16): Likewise. 17694 (vrshrq_n_u16): Likewise. 17695 (vqshlq_n_u16): Likewise. 17696 (vcmpneq_n_s16): Likewise. 17697 (vcmpltq_s16): Likewise. 17698 (vcmpltq_n_s16): Likewise. 17699 (vcmpleq_s16): Likewise. 17700 (vcmpleq_n_s16): Likewise. 17701 (vcmpgtq_s16): Likewise. 17702 (vcmpgtq_n_s16): Likewise. 17703 (vcmpgeq_s16): Likewise. 17704 (vcmpgeq_n_s16): Likewise. 17705 (vcmpeqq_s16): Likewise. 17706 (vcmpeqq_n_s16): Likewise. 17707 (vqshluq_n_s16): Likewise. 17708 (vaddvq_p_s16): Likewise. 17709 (vsubq_s16): Likewise. 17710 (vsubq_n_s16): Likewise. 17711 (vshlq_r_s16): Likewise. 17712 (vrshlq_s16): Likewise. 17713 (vrshlq_n_s16): Likewise. 17714 (vrmulhq_s16): Likewise. 17715 (vrhaddq_s16): Likewise. 17716 (vqsubq_s16): Likewise. 17717 (vqsubq_n_s16): Likewise. 17718 (vqshlq_s16): Likewise. 17719 (vqshlq_r_s16): Likewise. 17720 (vqrshlq_s16): Likewise. 17721 (vqrshlq_n_s16): Likewise. 17722 (vqrdmulhq_s16): Likewise. 17723 (vqrdmulhq_n_s16): Likewise. 17724 (vqdmulhq_s16): Likewise. 17725 (vqdmulhq_n_s16): Likewise. 17726 (vqaddq_s16): Likewise. 17727 (vqaddq_n_s16): Likewise. 17728 (vorrq_s16): Likewise. 17729 (vornq_s16): Likewise. 17730 (vmulq_s16): Likewise. 17731 (vmulq_n_s16): Likewise. 17732 (vmulltq_int_s16): Likewise. 17733 (vmullbq_int_s16): Likewise. 17734 (vmulhq_s16): Likewise. 17735 (vmlsdavxq_s16): Likewise. 17736 (vmlsdavq_s16): Likewise. 17737 (vmladavxq_s16): Likewise. 17738 (vmladavq_s16): Likewise. 17739 (vminvq_s16): Likewise. 17740 (vminq_s16): Likewise. 17741 (vmaxvq_s16): Likewise. 17742 (vmaxq_s16): Likewise. 17743 (vhsubq_s16): Likewise. 17744 (vhsubq_n_s16): Likewise. 17745 (vhcaddq_rot90_s16): Likewise. 17746 (vhcaddq_rot270_s16): Likewise. 17747 (vhaddq_s16): Likewise. 17748 (vhaddq_n_s16): Likewise. 17749 (veorq_s16): Likewise. 17750 (vcaddq_rot90_s16): Likewise. 17751 (vcaddq_rot270_s16): Likewise. 17752 (vbrsrq_n_s16): Likewise. 17753 (vbicq_s16): Likewise. 17754 (vandq_s16): Likewise. 17755 (vaddvaq_s16): Likewise. 17756 (vaddq_n_s16): Likewise. 17757 (vabdq_s16): Likewise. 17758 (vshlq_n_s16): Likewise. 17759 (vrshrq_n_s16): Likewise. 17760 (vqshlq_n_s16): Likewise. 17761 (vsubq_u32): Likewise. 17762 (vsubq_n_u32): Likewise. 17763 (vrmulhq_u32): Likewise. 17764 (vrhaddq_u32): Likewise. 17765 (vqsubq_u32): Likewise. 17766 (vqsubq_n_u32): Likewise. 17767 (vqaddq_u32): Likewise. 17768 (vqaddq_n_u32): Likewise. 17769 (vorrq_u32): Likewise. 17770 (vornq_u32): Likewise. 17771 (vmulq_u32): Likewise. 17772 (vmulq_n_u32): Likewise. 17773 (vmulltq_int_u32): Likewise. 17774 (vmullbq_int_u32): Likewise. 17775 (vmulhq_u32): Likewise. 17776 (vmladavq_u32): Likewise. 17777 (vminvq_u32): Likewise. 17778 (vminq_u32): Likewise. 17779 (vmaxvq_u32): Likewise. 17780 (vmaxq_u32): Likewise. 17781 (vhsubq_u32): Likewise. 17782 (vhsubq_n_u32): Likewise. 17783 (vhaddq_u32): Likewise. 17784 (vhaddq_n_u32): Likewise. 17785 (veorq_u32): Likewise. 17786 (vcmpneq_n_u32): Likewise. 17787 (vcmphiq_u32): Likewise. 17788 (vcmphiq_n_u32): Likewise. 17789 (vcmpeqq_u32): Likewise. 17790 (vcmpeqq_n_u32): Likewise. 17791 (vcmpcsq_u32): Likewise. 17792 (vcmpcsq_n_u32): Likewise. 17793 (vcaddq_rot90_u32): Likewise. 17794 (vcaddq_rot270_u32): Likewise. 17795 (vbicq_u32): Likewise. 17796 (vandq_u32): Likewise. 17797 (vaddvq_p_u32): Likewise. 17798 (vaddvaq_u32): Likewise. 17799 (vaddq_n_u32): Likewise. 17800 (vabdq_u32): Likewise. 17801 (vshlq_r_u32): Likewise. 17802 (vrshlq_u32): Likewise. 17803 (vrshlq_n_u32): Likewise. 17804 (vqshlq_u32): Likewise. 17805 (vqshlq_r_u32): Likewise. 17806 (vqrshlq_u32): Likewise. 17807 (vqrshlq_n_u32): Likewise. 17808 (vminavq_s32): Likewise. 17809 (vminaq_s32): Likewise. 17810 (vmaxavq_s32): Likewise. 17811 (vmaxaq_s32): Likewise. 17812 (vbrsrq_n_u32): Likewise. 17813 (vshlq_n_u32): Likewise. 17814 (vrshrq_n_u32): Likewise. 17815 (vqshlq_n_u32): Likewise. 17816 (vcmpneq_n_s32): Likewise. 17817 (vcmpltq_s32): Likewise. 17818 (vcmpltq_n_s32): Likewise. 17819 (vcmpleq_s32): Likewise. 17820 (vcmpleq_n_s32): Likewise. 17821 (vcmpgtq_s32): Likewise. 17822 (vcmpgtq_n_s32): Likewise. 17823 (vcmpgeq_s32): Likewise. 17824 (vcmpgeq_n_s32): Likewise. 17825 (vcmpeqq_s32): Likewise. 17826 (vcmpeqq_n_s32): Likewise. 17827 (vqshluq_n_s32): Likewise. 17828 (vaddvq_p_s32): Likewise. 17829 (vsubq_s32): Likewise. 17830 (vsubq_n_s32): Likewise. 17831 (vshlq_r_s32): Likewise. 17832 (vrshlq_s32): Likewise. 17833 (vrshlq_n_s32): Likewise. 17834 (vrmulhq_s32): Likewise. 17835 (vrhaddq_s32): Likewise. 17836 (vqsubq_s32): Likewise. 17837 (vqsubq_n_s32): Likewise. 17838 (vqshlq_s32): Likewise. 17839 (vqshlq_r_s32): Likewise. 17840 (vqrshlq_s32): Likewise. 17841 (vqrshlq_n_s32): Likewise. 17842 (vqrdmulhq_s32): Likewise. 17843 (vqrdmulhq_n_s32): Likewise. 17844 (vqdmulhq_s32): Likewise. 17845 (vqdmulhq_n_s32): Likewise. 17846 (vqaddq_s32): Likewise. 17847 (vqaddq_n_s32): Likewise. 17848 (vorrq_s32): Likewise. 17849 (vornq_s32): Likewise. 17850 (vmulq_s32): Likewise. 17851 (vmulq_n_s32): Likewise. 17852 (vmulltq_int_s32): Likewise. 17853 (vmullbq_int_s32): Likewise. 17854 (vmulhq_s32): Likewise. 17855 (vmlsdavxq_s32): Likewise. 17856 (vmlsdavq_s32): Likewise. 17857 (vmladavxq_s32): Likewise. 17858 (vmladavq_s32): Likewise. 17859 (vminvq_s32): Likewise. 17860 (vminq_s32): Likewise. 17861 (vmaxvq_s32): Likewise. 17862 (vmaxq_s32): Likewise. 17863 (vhsubq_s32): Likewise. 17864 (vhsubq_n_s32): Likewise. 17865 (vhcaddq_rot90_s32): Likewise. 17866 (vhcaddq_rot270_s32): Likewise. 17867 (vhaddq_s32): Likewise. 17868 (vhaddq_n_s32): Likewise. 17869 (veorq_s32): Likewise. 17870 (vcaddq_rot90_s32): Likewise. 17871 (vcaddq_rot270_s32): Likewise. 17872 (vbrsrq_n_s32): Likewise. 17873 (vbicq_s32): Likewise. 17874 (vandq_s32): Likewise. 17875 (vaddvaq_s32): Likewise. 17876 (vaddq_n_s32): Likewise. 17877 (vabdq_s32): Likewise. 17878 (vshlq_n_s32): Likewise. 17879 (vrshrq_n_s32): Likewise. 17880 (vqshlq_n_s32): Likewise. 17881 (__arm_vsubq_u8): Define intrinsic. 17882 (__arm_vsubq_n_u8): Likewise. 17883 (__arm_vrmulhq_u8): Likewise. 17884 (__arm_vrhaddq_u8): Likewise. 17885 (__arm_vqsubq_u8): Likewise. 17886 (__arm_vqsubq_n_u8): Likewise. 17887 (__arm_vqaddq_u8): Likewise. 17888 (__arm_vqaddq_n_u8): Likewise. 17889 (__arm_vorrq_u8): Likewise. 17890 (__arm_vornq_u8): Likewise. 17891 (__arm_vmulq_u8): Likewise. 17892 (__arm_vmulq_n_u8): Likewise. 17893 (__arm_vmulltq_int_u8): Likewise. 17894 (__arm_vmullbq_int_u8): Likewise. 17895 (__arm_vmulhq_u8): Likewise. 17896 (__arm_vmladavq_u8): Likewise. 17897 (__arm_vminvq_u8): Likewise. 17898 (__arm_vminq_u8): Likewise. 17899 (__arm_vmaxvq_u8): Likewise. 17900 (__arm_vmaxq_u8): Likewise. 17901 (__arm_vhsubq_u8): Likewise. 17902 (__arm_vhsubq_n_u8): Likewise. 17903 (__arm_vhaddq_u8): Likewise. 17904 (__arm_vhaddq_n_u8): Likewise. 17905 (__arm_veorq_u8): Likewise. 17906 (__arm_vcmpneq_n_u8): Likewise. 17907 (__arm_vcmphiq_u8): Likewise. 17908 (__arm_vcmphiq_n_u8): Likewise. 17909 (__arm_vcmpeqq_u8): Likewise. 17910 (__arm_vcmpeqq_n_u8): Likewise. 17911 (__arm_vcmpcsq_u8): Likewise. 17912 (__arm_vcmpcsq_n_u8): Likewise. 17913 (__arm_vcaddq_rot90_u8): Likewise. 17914 (__arm_vcaddq_rot270_u8): Likewise. 17915 (__arm_vbicq_u8): Likewise. 17916 (__arm_vandq_u8): Likewise. 17917 (__arm_vaddvq_p_u8): Likewise. 17918 (__arm_vaddvaq_u8): Likewise. 17919 (__arm_vaddq_n_u8): Likewise. 17920 (__arm_vabdq_u8): Likewise. 17921 (__arm_vshlq_r_u8): Likewise. 17922 (__arm_vrshlq_u8): Likewise. 17923 (__arm_vrshlq_n_u8): Likewise. 17924 (__arm_vqshlq_u8): Likewise. 17925 (__arm_vqshlq_r_u8): Likewise. 17926 (__arm_vqrshlq_u8): Likewise. 17927 (__arm_vqrshlq_n_u8): Likewise. 17928 (__arm_vminavq_s8): Likewise. 17929 (__arm_vminaq_s8): Likewise. 17930 (__arm_vmaxavq_s8): Likewise. 17931 (__arm_vmaxaq_s8): Likewise. 17932 (__arm_vbrsrq_n_u8): Likewise. 17933 (__arm_vshlq_n_u8): Likewise. 17934 (__arm_vrshrq_n_u8): Likewise. 17935 (__arm_vqshlq_n_u8): Likewise. 17936 (__arm_vcmpneq_n_s8): Likewise. 17937 (__arm_vcmpltq_s8): Likewise. 17938 (__arm_vcmpltq_n_s8): Likewise. 17939 (__arm_vcmpleq_s8): Likewise. 17940 (__arm_vcmpleq_n_s8): Likewise. 17941 (__arm_vcmpgtq_s8): Likewise. 17942 (__arm_vcmpgtq_n_s8): Likewise. 17943 (__arm_vcmpgeq_s8): Likewise. 17944 (__arm_vcmpgeq_n_s8): Likewise. 17945 (__arm_vcmpeqq_s8): Likewise. 17946 (__arm_vcmpeqq_n_s8): Likewise. 17947 (__arm_vqshluq_n_s8): Likewise. 17948 (__arm_vaddvq_p_s8): Likewise. 17949 (__arm_vsubq_s8): Likewise. 17950 (__arm_vsubq_n_s8): Likewise. 17951 (__arm_vshlq_r_s8): Likewise. 17952 (__arm_vrshlq_s8): Likewise. 17953 (__arm_vrshlq_n_s8): Likewise. 17954 (__arm_vrmulhq_s8): Likewise. 17955 (__arm_vrhaddq_s8): Likewise. 17956 (__arm_vqsubq_s8): Likewise. 17957 (__arm_vqsubq_n_s8): Likewise. 17958 (__arm_vqshlq_s8): Likewise. 17959 (__arm_vqshlq_r_s8): Likewise. 17960 (__arm_vqrshlq_s8): Likewise. 17961 (__arm_vqrshlq_n_s8): Likewise. 17962 (__arm_vqrdmulhq_s8): Likewise. 17963 (__arm_vqrdmulhq_n_s8): Likewise. 17964 (__arm_vqdmulhq_s8): Likewise. 17965 (__arm_vqdmulhq_n_s8): Likewise. 17966 (__arm_vqaddq_s8): Likewise. 17967 (__arm_vqaddq_n_s8): Likewise. 17968 (__arm_vorrq_s8): Likewise. 17969 (__arm_vornq_s8): Likewise. 17970 (__arm_vmulq_s8): Likewise. 17971 (__arm_vmulq_n_s8): Likewise. 17972 (__arm_vmulltq_int_s8): Likewise. 17973 (__arm_vmullbq_int_s8): Likewise. 17974 (__arm_vmulhq_s8): Likewise. 17975 (__arm_vmlsdavxq_s8): Likewise. 17976 (__arm_vmlsdavq_s8): Likewise. 17977 (__arm_vmladavxq_s8): Likewise. 17978 (__arm_vmladavq_s8): Likewise. 17979 (__arm_vminvq_s8): Likewise. 17980 (__arm_vminq_s8): Likewise. 17981 (__arm_vmaxvq_s8): Likewise. 17982 (__arm_vmaxq_s8): Likewise. 17983 (__arm_vhsubq_s8): Likewise. 17984 (__arm_vhsubq_n_s8): Likewise. 17985 (__arm_vhcaddq_rot90_s8): Likewise. 17986 (__arm_vhcaddq_rot270_s8): Likewise. 17987 (__arm_vhaddq_s8): Likewise. 17988 (__arm_vhaddq_n_s8): Likewise. 17989 (__arm_veorq_s8): Likewise. 17990 (__arm_vcaddq_rot90_s8): Likewise. 17991 (__arm_vcaddq_rot270_s8): Likewise. 17992 (__arm_vbrsrq_n_s8): Likewise. 17993 (__arm_vbicq_s8): Likewise. 17994 (__arm_vandq_s8): Likewise. 17995 (__arm_vaddvaq_s8): Likewise. 17996 (__arm_vaddq_n_s8): Likewise. 17997 (__arm_vabdq_s8): Likewise. 17998 (__arm_vshlq_n_s8): Likewise. 17999 (__arm_vrshrq_n_s8): Likewise. 18000 (__arm_vqshlq_n_s8): Likewise. 18001 (__arm_vsubq_u16): Likewise. 18002 (__arm_vsubq_n_u16): Likewise. 18003 (__arm_vrmulhq_u16): Likewise. 18004 (__arm_vrhaddq_u16): Likewise. 18005 (__arm_vqsubq_u16): Likewise. 18006 (__arm_vqsubq_n_u16): Likewise. 18007 (__arm_vqaddq_u16): Likewise. 18008 (__arm_vqaddq_n_u16): Likewise. 18009 (__arm_vorrq_u16): Likewise. 18010 (__arm_vornq_u16): Likewise. 18011 (__arm_vmulq_u16): Likewise. 18012 (__arm_vmulq_n_u16): Likewise. 18013 (__arm_vmulltq_int_u16): Likewise. 18014 (__arm_vmullbq_int_u16): Likewise. 18015 (__arm_vmulhq_u16): Likewise. 18016 (__arm_vmladavq_u16): Likewise. 18017 (__arm_vminvq_u16): Likewise. 18018 (__arm_vminq_u16): Likewise. 18019 (__arm_vmaxvq_u16): Likewise. 18020 (__arm_vmaxq_u16): Likewise. 18021 (__arm_vhsubq_u16): Likewise. 18022 (__arm_vhsubq_n_u16): Likewise. 18023 (__arm_vhaddq_u16): Likewise. 18024 (__arm_vhaddq_n_u16): Likewise. 18025 (__arm_veorq_u16): Likewise. 18026 (__arm_vcmpneq_n_u16): Likewise. 18027 (__arm_vcmphiq_u16): Likewise. 18028 (__arm_vcmphiq_n_u16): Likewise. 18029 (__arm_vcmpeqq_u16): Likewise. 18030 (__arm_vcmpeqq_n_u16): Likewise. 18031 (__arm_vcmpcsq_u16): Likewise. 18032 (__arm_vcmpcsq_n_u16): Likewise. 18033 (__arm_vcaddq_rot90_u16): Likewise. 18034 (__arm_vcaddq_rot270_u16): Likewise. 18035 (__arm_vbicq_u16): Likewise. 18036 (__arm_vandq_u16): Likewise. 18037 (__arm_vaddvq_p_u16): Likewise. 18038 (__arm_vaddvaq_u16): Likewise. 18039 (__arm_vaddq_n_u16): Likewise. 18040 (__arm_vabdq_u16): Likewise. 18041 (__arm_vshlq_r_u16): Likewise. 18042 (__arm_vrshlq_u16): Likewise. 18043 (__arm_vrshlq_n_u16): Likewise. 18044 (__arm_vqshlq_u16): Likewise. 18045 (__arm_vqshlq_r_u16): Likewise. 18046 (__arm_vqrshlq_u16): Likewise. 18047 (__arm_vqrshlq_n_u16): Likewise. 18048 (__arm_vminavq_s16): Likewise. 18049 (__arm_vminaq_s16): Likewise. 18050 (__arm_vmaxavq_s16): Likewise. 18051 (__arm_vmaxaq_s16): Likewise. 18052 (__arm_vbrsrq_n_u16): Likewise. 18053 (__arm_vshlq_n_u16): Likewise. 18054 (__arm_vrshrq_n_u16): Likewise. 18055 (__arm_vqshlq_n_u16): Likewise. 18056 (__arm_vcmpneq_n_s16): Likewise. 18057 (__arm_vcmpltq_s16): Likewise. 18058 (__arm_vcmpltq_n_s16): Likewise. 18059 (__arm_vcmpleq_s16): Likewise. 18060 (__arm_vcmpleq_n_s16): Likewise. 18061 (__arm_vcmpgtq_s16): Likewise. 18062 (__arm_vcmpgtq_n_s16): Likewise. 18063 (__arm_vcmpgeq_s16): Likewise. 18064 (__arm_vcmpgeq_n_s16): Likewise. 18065 (__arm_vcmpeqq_s16): Likewise. 18066 (__arm_vcmpeqq_n_s16): Likewise. 18067 (__arm_vqshluq_n_s16): Likewise. 18068 (__arm_vaddvq_p_s16): Likewise. 18069 (__arm_vsubq_s16): Likewise. 18070 (__arm_vsubq_n_s16): Likewise. 18071 (__arm_vshlq_r_s16): Likewise. 18072 (__arm_vrshlq_s16): Likewise. 18073 (__arm_vrshlq_n_s16): Likewise. 18074 (__arm_vrmulhq_s16): Likewise. 18075 (__arm_vrhaddq_s16): Likewise. 18076 (__arm_vqsubq_s16): Likewise. 18077 (__arm_vqsubq_n_s16): Likewise. 18078 (__arm_vqshlq_s16): Likewise. 18079 (__arm_vqshlq_r_s16): Likewise. 18080 (__arm_vqrshlq_s16): Likewise. 18081 (__arm_vqrshlq_n_s16): Likewise. 18082 (__arm_vqrdmulhq_s16): Likewise. 18083 (__arm_vqrdmulhq_n_s16): Likewise. 18084 (__arm_vqdmulhq_s16): Likewise. 18085 (__arm_vqdmulhq_n_s16): Likewise. 18086 (__arm_vqaddq_s16): Likewise. 18087 (__arm_vqaddq_n_s16): Likewise. 18088 (__arm_vorrq_s16): Likewise. 18089 (__arm_vornq_s16): Likewise. 18090 (__arm_vmulq_s16): Likewise. 18091 (__arm_vmulq_n_s16): Likewise. 18092 (__arm_vmulltq_int_s16): Likewise. 18093 (__arm_vmullbq_int_s16): Likewise. 18094 (__arm_vmulhq_s16): Likewise. 18095 (__arm_vmlsdavxq_s16): Likewise. 18096 (__arm_vmlsdavq_s16): Likewise. 18097 (__arm_vmladavxq_s16): Likewise. 18098 (__arm_vmladavq_s16): Likewise. 18099 (__arm_vminvq_s16): Likewise. 18100 (__arm_vminq_s16): Likewise. 18101 (__arm_vmaxvq_s16): Likewise. 18102 (__arm_vmaxq_s16): Likewise. 18103 (__arm_vhsubq_s16): Likewise. 18104 (__arm_vhsubq_n_s16): Likewise. 18105 (__arm_vhcaddq_rot90_s16): Likewise. 18106 (__arm_vhcaddq_rot270_s16): Likewise. 18107 (__arm_vhaddq_s16): Likewise. 18108 (__arm_vhaddq_n_s16): Likewise. 18109 (__arm_veorq_s16): Likewise. 18110 (__arm_vcaddq_rot90_s16): Likewise. 18111 (__arm_vcaddq_rot270_s16): Likewise. 18112 (__arm_vbrsrq_n_s16): Likewise. 18113 (__arm_vbicq_s16): Likewise. 18114 (__arm_vandq_s16): Likewise. 18115 (__arm_vaddvaq_s16): Likewise. 18116 (__arm_vaddq_n_s16): Likewise. 18117 (__arm_vabdq_s16): Likewise. 18118 (__arm_vshlq_n_s16): Likewise. 18119 (__arm_vrshrq_n_s16): Likewise. 18120 (__arm_vqshlq_n_s16): Likewise. 18121 (__arm_vsubq_u32): Likewise. 18122 (__arm_vsubq_n_u32): Likewise. 18123 (__arm_vrmulhq_u32): Likewise. 18124 (__arm_vrhaddq_u32): Likewise. 18125 (__arm_vqsubq_u32): Likewise. 18126 (__arm_vqsubq_n_u32): Likewise. 18127 (__arm_vqaddq_u32): Likewise. 18128 (__arm_vqaddq_n_u32): Likewise. 18129 (__arm_vorrq_u32): Likewise. 18130 (__arm_vornq_u32): Likewise. 18131 (__arm_vmulq_u32): Likewise. 18132 (__arm_vmulq_n_u32): Likewise. 18133 (__arm_vmulltq_int_u32): Likewise. 18134 (__arm_vmullbq_int_u32): Likewise. 18135 (__arm_vmulhq_u32): Likewise. 18136 (__arm_vmladavq_u32): Likewise. 18137 (__arm_vminvq_u32): Likewise. 18138 (__arm_vminq_u32): Likewise. 18139 (__arm_vmaxvq_u32): Likewise. 18140 (__arm_vmaxq_u32): Likewise. 18141 (__arm_vhsubq_u32): Likewise. 18142 (__arm_vhsubq_n_u32): Likewise. 18143 (__arm_vhaddq_u32): Likewise. 18144 (__arm_vhaddq_n_u32): Likewise. 18145 (__arm_veorq_u32): Likewise. 18146 (__arm_vcmpneq_n_u32): Likewise. 18147 (__arm_vcmphiq_u32): Likewise. 18148 (__arm_vcmphiq_n_u32): Likewise. 18149 (__arm_vcmpeqq_u32): Likewise. 18150 (__arm_vcmpeqq_n_u32): Likewise. 18151 (__arm_vcmpcsq_u32): Likewise. 18152 (__arm_vcmpcsq_n_u32): Likewise. 18153 (__arm_vcaddq_rot90_u32): Likewise. 18154 (__arm_vcaddq_rot270_u32): Likewise. 18155 (__arm_vbicq_u32): Likewise. 18156 (__arm_vandq_u32): Likewise. 18157 (__arm_vaddvq_p_u32): Likewise. 18158 (__arm_vaddvaq_u32): Likewise. 18159 (__arm_vaddq_n_u32): Likewise. 18160 (__arm_vabdq_u32): Likewise. 18161 (__arm_vshlq_r_u32): Likewise. 18162 (__arm_vrshlq_u32): Likewise. 18163 (__arm_vrshlq_n_u32): Likewise. 18164 (__arm_vqshlq_u32): Likewise. 18165 (__arm_vqshlq_r_u32): Likewise. 18166 (__arm_vqrshlq_u32): Likewise. 18167 (__arm_vqrshlq_n_u32): Likewise. 18168 (__arm_vminavq_s32): Likewise. 18169 (__arm_vminaq_s32): Likewise. 18170 (__arm_vmaxavq_s32): Likewise. 18171 (__arm_vmaxaq_s32): Likewise. 18172 (__arm_vbrsrq_n_u32): Likewise. 18173 (__arm_vshlq_n_u32): Likewise. 18174 (__arm_vrshrq_n_u32): Likewise. 18175 (__arm_vqshlq_n_u32): Likewise. 18176 (__arm_vcmpneq_n_s32): Likewise. 18177 (__arm_vcmpltq_s32): Likewise. 18178 (__arm_vcmpltq_n_s32): Likewise. 18179 (__arm_vcmpleq_s32): Likewise. 18180 (__arm_vcmpleq_n_s32): Likewise. 18181 (__arm_vcmpgtq_s32): Likewise. 18182 (__arm_vcmpgtq_n_s32): Likewise. 18183 (__arm_vcmpgeq_s32): Likewise. 18184 (__arm_vcmpgeq_n_s32): Likewise. 18185 (__arm_vcmpeqq_s32): Likewise. 18186 (__arm_vcmpeqq_n_s32): Likewise. 18187 (__arm_vqshluq_n_s32): Likewise. 18188 (__arm_vaddvq_p_s32): Likewise. 18189 (__arm_vsubq_s32): Likewise. 18190 (__arm_vsubq_n_s32): Likewise. 18191 (__arm_vshlq_r_s32): Likewise. 18192 (__arm_vrshlq_s32): Likewise. 18193 (__arm_vrshlq_n_s32): Likewise. 18194 (__arm_vrmulhq_s32): Likewise. 18195 (__arm_vrhaddq_s32): Likewise. 18196 (__arm_vqsubq_s32): Likewise. 18197 (__arm_vqsubq_n_s32): Likewise. 18198 (__arm_vqshlq_s32): Likewise. 18199 (__arm_vqshlq_r_s32): Likewise. 18200 (__arm_vqrshlq_s32): Likewise. 18201 (__arm_vqrshlq_n_s32): Likewise. 18202 (__arm_vqrdmulhq_s32): Likewise. 18203 (__arm_vqrdmulhq_n_s32): Likewise. 18204 (__arm_vqdmulhq_s32): Likewise. 18205 (__arm_vqdmulhq_n_s32): Likewise. 18206 (__arm_vqaddq_s32): Likewise. 18207 (__arm_vqaddq_n_s32): Likewise. 18208 (__arm_vorrq_s32): Likewise. 18209 (__arm_vornq_s32): Likewise. 18210 (__arm_vmulq_s32): Likewise. 18211 (__arm_vmulq_n_s32): Likewise. 18212 (__arm_vmulltq_int_s32): Likewise. 18213 (__arm_vmullbq_int_s32): Likewise. 18214 (__arm_vmulhq_s32): Likewise. 18215 (__arm_vmlsdavxq_s32): Likewise. 18216 (__arm_vmlsdavq_s32): Likewise. 18217 (__arm_vmladavxq_s32): Likewise. 18218 (__arm_vmladavq_s32): Likewise. 18219 (__arm_vminvq_s32): Likewise. 18220 (__arm_vminq_s32): Likewise. 18221 (__arm_vmaxvq_s32): Likewise. 18222 (__arm_vmaxq_s32): Likewise. 18223 (__arm_vhsubq_s32): Likewise. 18224 (__arm_vhsubq_n_s32): Likewise. 18225 (__arm_vhcaddq_rot90_s32): Likewise. 18226 (__arm_vhcaddq_rot270_s32): Likewise. 18227 (__arm_vhaddq_s32): Likewise. 18228 (__arm_vhaddq_n_s32): Likewise. 18229 (__arm_veorq_s32): Likewise. 18230 (__arm_vcaddq_rot90_s32): Likewise. 18231 (__arm_vcaddq_rot270_s32): Likewise. 18232 (__arm_vbrsrq_n_s32): Likewise. 18233 (__arm_vbicq_s32): Likewise. 18234 (__arm_vandq_s32): Likewise. 18235 (__arm_vaddvaq_s32): Likewise. 18236 (__arm_vaddq_n_s32): Likewise. 18237 (__arm_vabdq_s32): Likewise. 18238 (__arm_vshlq_n_s32): Likewise. 18239 (__arm_vrshrq_n_s32): Likewise. 18240 (__arm_vqshlq_n_s32): Likewise. 18241 (vsubq): Define polymorphic variant. 18242 (vsubq_n): Likewise. 18243 (vshlq_r): Likewise. 18244 (vrshlq_n): Likewise. 18245 (vrshlq): Likewise. 18246 (vrmulhq): Likewise. 18247 (vrhaddq): Likewise. 18248 (vqsubq_n): Likewise. 18249 (vqsubq): Likewise. 18250 (vqshlq): Likewise. 18251 (vqshlq_r): Likewise. 18252 (vqshluq): Likewise. 18253 (vrshrq_n): Likewise. 18254 (vshlq_n): Likewise. 18255 (vqshluq_n): Likewise. 18256 (vqshlq_n): Likewise. 18257 (vqrshlq_n): Likewise. 18258 (vqrshlq): Likewise. 18259 (vqrdmulhq_n): Likewise. 18260 (vqrdmulhq): Likewise. 18261 (vqdmulhq_n): Likewise. 18262 (vqdmulhq): Likewise. 18263 (vqaddq_n): Likewise. 18264 (vqaddq): Likewise. 18265 (vorrq_n): Likewise. 18266 (vorrq): Likewise. 18267 (vornq): Likewise. 18268 (vmulq_n): Likewise. 18269 (vmulq): Likewise. 18270 (vmulltq_int): Likewise. 18271 (vmullbq_int): Likewise. 18272 (vmulhq): Likewise. 18273 (vminq): Likewise. 18274 (vminaq): Likewise. 18275 (vmaxq): Likewise. 18276 (vmaxaq): Likewise. 18277 (vhsubq_n): Likewise. 18278 (vhsubq): Likewise. 18279 (vhcaddq_rot90): Likewise. 18280 (vhcaddq_rot270): Likewise. 18281 (vhaddq_n): Likewise. 18282 (vhaddq): Likewise. 18283 (veorq): Likewise. 18284 (vcaddq_rot90): Likewise. 18285 (vcaddq_rot270): Likewise. 18286 (vbrsrq_n): Likewise. 18287 (vbicq_n): Likewise. 18288 (vbicq): Likewise. 18289 (vaddq): Likewise. 18290 (vaddq_n): Likewise. 18291 (vandq): Likewise. 18292 (vabdq): Likewise. 18293 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. 18294 (BINOP_NONE_NONE_NONE): Likewise. 18295 (BINOP_NONE_NONE_UNONE): Likewise. 18296 (BINOP_UNONE_NONE_IMM): Likewise. 18297 (BINOP_UNONE_NONE_NONE): Likewise. 18298 (BINOP_UNONE_UNONE_IMM): Likewise. 18299 (BINOP_UNONE_UNONE_NONE): Likewise. 18300 (BINOP_UNONE_UNONE_UNONE): Likewise. 18301 * config/arm/constraints.md (Ra): Define constraint to check constant is 18302 in the range of 0 to 7. 18303 (Rg): Define constriant to check the constant is one among 1, 2, 4 18304 and 8. 18305 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern. 18306 (mve_vaddq_n_<supf>): Likewise. 18307 (mve_vaddvaq_<supf>): Likewise. 18308 (mve_vaddvq_p_<supf>): Likewise. 18309 (mve_vandq_<supf>): Likewise. 18310 (mve_vbicq_<supf>): Likewise. 18311 (mve_vbrsrq_n_<supf>): Likewise. 18312 (mve_vcaddq_rot270_<supf>): Likewise. 18313 (mve_vcaddq_rot90_<supf>): Likewise. 18314 (mve_vcmpcsq_n_u): Likewise. 18315 (mve_vcmpcsq_u): Likewise. 18316 (mve_vcmpeqq_n_<supf>): Likewise. 18317 (mve_vcmpeqq_<supf>): Likewise. 18318 (mve_vcmpgeq_n_s): Likewise. 18319 (mve_vcmpgeq_s): Likewise. 18320 (mve_vcmpgtq_n_s): Likewise. 18321 (mve_vcmpgtq_s): Likewise. 18322 (mve_vcmphiq_n_u): Likewise. 18323 (mve_vcmphiq_u): Likewise. 18324 (mve_vcmpleq_n_s): Likewise. 18325 (mve_vcmpleq_s): Likewise. 18326 (mve_vcmpltq_n_s): Likewise. 18327 (mve_vcmpltq_s): Likewise. 18328 (mve_vcmpneq_n_<supf>): Likewise. 18329 (mve_vddupq_n_u): Likewise. 18330 (mve_veorq_<supf>): Likewise. 18331 (mve_vhaddq_n_<supf>): Likewise. 18332 (mve_vhaddq_<supf>): Likewise. 18333 (mve_vhcaddq_rot270_s): Likewise. 18334 (mve_vhcaddq_rot90_s): Likewise. 18335 (mve_vhsubq_n_<supf>): Likewise. 18336 (mve_vhsubq_<supf>): Likewise. 18337 (mve_vidupq_n_u): Likewise. 18338 (mve_vmaxaq_s): Likewise. 18339 (mve_vmaxavq_s): Likewise. 18340 (mve_vmaxq_<supf>): Likewise. 18341 (mve_vmaxvq_<supf>): Likewise. 18342 (mve_vminaq_s): Likewise. 18343 (mve_vminavq_s): Likewise. 18344 (mve_vminq_<supf>): Likewise. 18345 (mve_vminvq_<supf>): Likewise. 18346 (mve_vmladavq_<supf>): Likewise. 18347 (mve_vmladavxq_s): Likewise. 18348 (mve_vmlsdavq_s): Likewise. 18349 (mve_vmlsdavxq_s): Likewise. 18350 (mve_vmulhq_<supf>): Likewise. 18351 (mve_vmullbq_int_<supf>): Likewise. 18352 (mve_vmulltq_int_<supf>): Likewise. 18353 (mve_vmulq_n_<supf>): Likewise. 18354 (mve_vmulq_<supf>): Likewise. 18355 (mve_vornq_<supf>): Likewise. 18356 (mve_vorrq_<supf>): Likewise. 18357 (mve_vqaddq_n_<supf>): Likewise. 18358 (mve_vqaddq_<supf>): Likewise. 18359 (mve_vqdmulhq_n_s): Likewise. 18360 (mve_vqdmulhq_s): Likewise. 18361 (mve_vqrdmulhq_n_s): Likewise. 18362 (mve_vqrdmulhq_s): Likewise. 18363 (mve_vqrshlq_n_<supf>): Likewise. 18364 (mve_vqrshlq_<supf>): Likewise. 18365 (mve_vqshlq_n_<supf>): Likewise. 18366 (mve_vqshlq_r_<supf>): Likewise. 18367 (mve_vqshlq_<supf>): Likewise. 18368 (mve_vqshluq_n_s): Likewise. 18369 (mve_vqsubq_n_<supf>): Likewise. 18370 (mve_vqsubq_<supf>): Likewise. 18371 (mve_vrhaddq_<supf>): Likewise. 18372 (mve_vrmulhq_<supf>): Likewise. 18373 (mve_vrshlq_n_<supf>): Likewise. 18374 (mve_vrshlq_<supf>): Likewise. 18375 (mve_vrshrq_n_<supf>): Likewise. 18376 (mve_vshlq_n_<supf>): Likewise. 18377 (mve_vshlq_r_<supf>): Likewise. 18378 (mve_vsubq_n_<supf>): Likewise. 18379 (mve_vsubq_<supf>): Likewise. 18380 * config/arm/predicates.md (mve_imm_7): Define predicate to check 18381 the matching constraint Ra. 18382 (mve_imm_selective_upto_8): Define predicate to check the matching 18383 constraint Rg. 18384 183852020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18386 Mihail Ionescu <mihail.ionescu@arm.com> 18387 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18388 18389 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define 18390 qualifier for binary operands. 18391 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. 18392 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. 18393 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro. 18394 (vaddlvq_p_u32): Likewise. 18395 (vcmpneq_s8): Likewise. 18396 (vcmpneq_s16): Likewise. 18397 (vcmpneq_s32): Likewise. 18398 (vcmpneq_u8): Likewise. 18399 (vcmpneq_u16): Likewise. 18400 (vcmpneq_u32): Likewise. 18401 (vshlq_s8): Likewise. 18402 (vshlq_s16): Likewise. 18403 (vshlq_s32): Likewise. 18404 (vshlq_u8): Likewise. 18405 (vshlq_u16): Likewise. 18406 (vshlq_u32): Likewise. 18407 (__arm_vaddlvq_p_s32): Define intrinsic. 18408 (__arm_vaddlvq_p_u32): Likewise. 18409 (__arm_vcmpneq_s8): Likewise. 18410 (__arm_vcmpneq_s16): Likewise. 18411 (__arm_vcmpneq_s32): Likewise. 18412 (__arm_vcmpneq_u8): Likewise. 18413 (__arm_vcmpneq_u16): Likewise. 18414 (__arm_vcmpneq_u32): Likewise. 18415 (__arm_vshlq_s8): Likewise. 18416 (__arm_vshlq_s16): Likewise. 18417 (__arm_vshlq_s32): Likewise. 18418 (__arm_vshlq_u8): Likewise. 18419 (__arm_vshlq_u16): Likewise. 18420 (__arm_vshlq_u32): Likewise. 18421 (vaddlvq_p): Define polymorphic variant. 18422 (vcmpneq): Likewise. 18423 (vshlq): Likewise. 18424 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS): 18425 Use it. 18426 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. 18427 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. 18428 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern. 18429 (mve_vcmpneq_<supf><mode>): Likewise. 18430 (mve_vshlq_<supf><mode>): Likewise. 18431 184322020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18433 Mihail Ionescu <mihail.ionescu@arm.com> 18434 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18435 18436 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define 18437 qualifier for binary operands. 18438 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 18439 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. 18440 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. 18441 (vcvtq_n_s32_f32): Likewise. 18442 (vcvtq_n_u16_f16): Likewise. 18443 (vcvtq_n_u32_f32): Likewise. 18444 (vcreateq_u8): Likewise. 18445 (vcreateq_u16): Likewise. 18446 (vcreateq_u32): Likewise. 18447 (vcreateq_u64): Likewise. 18448 (vcreateq_s8): Likewise. 18449 (vcreateq_s16): Likewise. 18450 (vcreateq_s32): Likewise. 18451 (vcreateq_s64): Likewise. 18452 (vshrq_n_s8): Likewise. 18453 (vshrq_n_s16): Likewise. 18454 (vshrq_n_s32): Likewise. 18455 (vshrq_n_u8): Likewise. 18456 (vshrq_n_u16): Likewise. 18457 (vshrq_n_u32): Likewise. 18458 (__arm_vcreateq_u8): Define intrinsic. 18459 (__arm_vcreateq_u16): Likewise. 18460 (__arm_vcreateq_u32): Likewise. 18461 (__arm_vcreateq_u64): Likewise. 18462 (__arm_vcreateq_s8): Likewise. 18463 (__arm_vcreateq_s16): Likewise. 18464 (__arm_vcreateq_s32): Likewise. 18465 (__arm_vcreateq_s64): Likewise. 18466 (__arm_vshrq_n_s8): Likewise. 18467 (__arm_vshrq_n_s16): Likewise. 18468 (__arm_vshrq_n_s32): Likewise. 18469 (__arm_vshrq_n_u8): Likewise. 18470 (__arm_vshrq_n_u16): Likewise. 18471 (__arm_vshrq_n_u32): Likewise. 18472 (__arm_vcvtq_n_s16_f16): Likewise. 18473 (__arm_vcvtq_n_s32_f32): Likewise. 18474 (__arm_vcvtq_n_u16_f16): Likewise. 18475 (__arm_vcvtq_n_u32_f32): Likewise. 18476 (vshrq_n): Define polymorphic variant. 18477 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): 18478 Use it. 18479 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. 18480 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. 18481 * config/arm/constraints.md (Rb): Define constraint to check constant is 18482 in the range of 1 to 8. 18483 (Rf): Define constraint to check constant is in the range of 1 to 32. 18484 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern. 18485 (mve_vshrq_n_<supf><mode>): Likewise. 18486 (mve_vcvtq_n_from_f_<supf><mode>): Likewise. 18487 * config/arm/predicates.md (mve_imm_8): Define predicate to check 18488 the matching constraint Rb. 18489 (mve_imm_32): Define predicate to check the matching constraint Rf. 18490 184912020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18492 Mihail Ionescu <mihail.ionescu@arm.com> 18493 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18494 18495 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define 18496 qualifier for binary operands. 18497 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. 18498 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. 18499 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 18500 * config/arm/arm_mve.h (vsubq_n_f16): Define macro. 18501 (vsubq_n_f32): Likewise. 18502 (vbrsrq_n_f16): Likewise. 18503 (vbrsrq_n_f32): Likewise. 18504 (vcvtq_n_f16_s16): Likewise. 18505 (vcvtq_n_f32_s32): Likewise. 18506 (vcvtq_n_f16_u16): Likewise. 18507 (vcvtq_n_f32_u32): Likewise. 18508 (vcreateq_f16): Likewise. 18509 (vcreateq_f32): Likewise. 18510 (__arm_vsubq_n_f16): Define intrinsic. 18511 (__arm_vsubq_n_f32): Likewise. 18512 (__arm_vbrsrq_n_f16): Likewise. 18513 (__arm_vbrsrq_n_f32): Likewise. 18514 (__arm_vcvtq_n_f16_s16): Likewise. 18515 (__arm_vcvtq_n_f32_s32): Likewise. 18516 (__arm_vcvtq_n_f16_u16): Likewise. 18517 (__arm_vcvtq_n_f32_u32): Likewise. 18518 (__arm_vcreateq_f16): Likewise. 18519 (__arm_vcreateq_f32): Likewise. 18520 (vsubq): Define polymorphic variant. 18521 (vbrsrq): Likewise. 18522 (vcvtq_n): Likewise. 18523 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use 18524 it. 18525 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. 18526 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. 18527 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. 18528 * config/arm/constraints.md (Rd): Define constraint to check constant is 18529 in the range of 1 to 16. 18530 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern. 18531 mve_vbrsrq_n_f<mode>: Likewise. 18532 mve_vcvtq_n_to_f_<supf><mode>: Likewise. 18533 mve_vcreateq_f<mode>: Likewise. 18534 * config/arm/predicates.md (mve_imm_16): Define predicate to check 18535 the matching constraint Rd. 18536 185372020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18538 Mihail Ionescu <mihail.ionescu@arm.com> 18539 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18540 18541 * config/arm/arm-builtins.c (hi_UP): Define mode. 18542 * config/arm/arm.h (IS_VPR_REGNUM): Move. 18543 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. 18544 (APSRQ_REGNUM): Modify. 18545 (APSRGE_REGNUM): Modify. 18546 * config/arm/arm_mve.h (vctp16q): Define macro. 18547 (vctp32q): Likewise. 18548 (vctp64q): Likewise. 18549 (vctp8q): Likewise. 18550 (vpnot): Likewise. 18551 (__arm_vctp16q): Define intrinsic. 18552 (__arm_vctp32q): Likewise. 18553 (__arm_vctp64q): Likewise. 18554 (__arm_vctp8q): Likewise. 18555 (__arm_vpnot): Likewise. 18556 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin 18557 qualifier. 18558 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern. 18559 (mve_vpnothi): Likewise. 18560 185612020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18562 Mihail Ionescu <mihail.ionescu@arm.com> 18563 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18564 18565 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. 18566 * config/arm/arm_mve.h (vdupq_n_s8): Define macro. 18567 (vdupq_n_s16): Likewise. 18568 (vdupq_n_s32): Likewise. 18569 (vabsq_s8): Likewise. 18570 (vabsq_s16): Likewise. 18571 (vabsq_s32): Likewise. 18572 (vclsq_s8): Likewise. 18573 (vclsq_s16): Likewise. 18574 (vclsq_s32): Likewise. 18575 (vclzq_s8): Likewise. 18576 (vclzq_s16): Likewise. 18577 (vclzq_s32): Likewise. 18578 (vnegq_s8): Likewise. 18579 (vnegq_s16): Likewise. 18580 (vnegq_s32): Likewise. 18581 (vaddlvq_s32): Likewise. 18582 (vaddvq_s8): Likewise. 18583 (vaddvq_s16): Likewise. 18584 (vaddvq_s32): Likewise. 18585 (vmovlbq_s8): Likewise. 18586 (vmovlbq_s16): Likewise. 18587 (vmovltq_s8): Likewise. 18588 (vmovltq_s16): Likewise. 18589 (vmvnq_s8): Likewise. 18590 (vmvnq_s16): Likewise. 18591 (vmvnq_s32): Likewise. 18592 (vrev16q_s8): Likewise. 18593 (vrev32q_s8): Likewise. 18594 (vrev32q_s16): Likewise. 18595 (vqabsq_s8): Likewise. 18596 (vqabsq_s16): Likewise. 18597 (vqabsq_s32): Likewise. 18598 (vqnegq_s8): Likewise. 18599 (vqnegq_s16): Likewise. 18600 (vqnegq_s32): Likewise. 18601 (vcvtaq_s16_f16): Likewise. 18602 (vcvtaq_s32_f32): Likewise. 18603 (vcvtnq_s16_f16): Likewise. 18604 (vcvtnq_s32_f32): Likewise. 18605 (vcvtpq_s16_f16): Likewise. 18606 (vcvtpq_s32_f32): Likewise. 18607 (vcvtmq_s16_f16): Likewise. 18608 (vcvtmq_s32_f32): Likewise. 18609 (vmvnq_u8): Likewise. 18610 (vmvnq_u16): Likewise. 18611 (vmvnq_u32): Likewise. 18612 (vdupq_n_u8): Likewise. 18613 (vdupq_n_u16): Likewise. 18614 (vdupq_n_u32): Likewise. 18615 (vclzq_u8): Likewise. 18616 (vclzq_u16): Likewise. 18617 (vclzq_u32): Likewise. 18618 (vaddvq_u8): Likewise. 18619 (vaddvq_u16): Likewise. 18620 (vaddvq_u32): Likewise. 18621 (vrev32q_u8): Likewise. 18622 (vrev32q_u16): Likewise. 18623 (vmovltq_u8): Likewise. 18624 (vmovltq_u16): Likewise. 18625 (vmovlbq_u8): Likewise. 18626 (vmovlbq_u16): Likewise. 18627 (vrev16q_u8): Likewise. 18628 (vaddlvq_u32): Likewise. 18629 (vcvtpq_u16_f16): Likewise. 18630 (vcvtpq_u32_f32): Likewise. 18631 (vcvtnq_u16_f16): Likewise. 18632 (vcvtmq_u16_f16): Likewise. 18633 (vcvtmq_u32_f32): Likewise. 18634 (vcvtaq_u16_f16): Likewise. 18635 (vcvtaq_u32_f32): Likewise. 18636 (__arm_vdupq_n_s8): Define intrinsic. 18637 (__arm_vdupq_n_s16): Likewise. 18638 (__arm_vdupq_n_s32): Likewise. 18639 (__arm_vabsq_s8): Likewise. 18640 (__arm_vabsq_s16): Likewise. 18641 (__arm_vabsq_s32): Likewise. 18642 (__arm_vclsq_s8): Likewise. 18643 (__arm_vclsq_s16): Likewise. 18644 (__arm_vclsq_s32): Likewise. 18645 (__arm_vclzq_s8): Likewise. 18646 (__arm_vclzq_s16): Likewise. 18647 (__arm_vclzq_s32): Likewise. 18648 (__arm_vnegq_s8): Likewise. 18649 (__arm_vnegq_s16): Likewise. 18650 (__arm_vnegq_s32): Likewise. 18651 (__arm_vaddlvq_s32): Likewise. 18652 (__arm_vaddvq_s8): Likewise. 18653 (__arm_vaddvq_s16): Likewise. 18654 (__arm_vaddvq_s32): Likewise. 18655 (__arm_vmovlbq_s8): Likewise. 18656 (__arm_vmovlbq_s16): Likewise. 18657 (__arm_vmovltq_s8): Likewise. 18658 (__arm_vmovltq_s16): Likewise. 18659 (__arm_vmvnq_s8): Likewise. 18660 (__arm_vmvnq_s16): Likewise. 18661 (__arm_vmvnq_s32): Likewise. 18662 (__arm_vrev16q_s8): Likewise. 18663 (__arm_vrev32q_s8): Likewise. 18664 (__arm_vrev32q_s16): Likewise. 18665 (__arm_vqabsq_s8): Likewise. 18666 (__arm_vqabsq_s16): Likewise. 18667 (__arm_vqabsq_s32): Likewise. 18668 (__arm_vqnegq_s8): Likewise. 18669 (__arm_vqnegq_s16): Likewise. 18670 (__arm_vqnegq_s32): Likewise. 18671 (__arm_vmvnq_u8): Likewise. 18672 (__arm_vmvnq_u16): Likewise. 18673 (__arm_vmvnq_u32): Likewise. 18674 (__arm_vdupq_n_u8): Likewise. 18675 (__arm_vdupq_n_u16): Likewise. 18676 (__arm_vdupq_n_u32): Likewise. 18677 (__arm_vclzq_u8): Likewise. 18678 (__arm_vclzq_u16): Likewise. 18679 (__arm_vclzq_u32): Likewise. 18680 (__arm_vaddvq_u8): Likewise. 18681 (__arm_vaddvq_u16): Likewise. 18682 (__arm_vaddvq_u32): Likewise. 18683 (__arm_vrev32q_u8): Likewise. 18684 (__arm_vrev32q_u16): Likewise. 18685 (__arm_vmovltq_u8): Likewise. 18686 (__arm_vmovltq_u16): Likewise. 18687 (__arm_vmovlbq_u8): Likewise. 18688 (__arm_vmovlbq_u16): Likewise. 18689 (__arm_vrev16q_u8): Likewise. 18690 (__arm_vaddlvq_u32): Likewise. 18691 (__arm_vcvtpq_u16_f16): Likewise. 18692 (__arm_vcvtpq_u32_f32): Likewise. 18693 (__arm_vcvtnq_u16_f16): Likewise. 18694 (__arm_vcvtmq_u16_f16): Likewise. 18695 (__arm_vcvtmq_u32_f32): Likewise. 18696 (__arm_vcvtaq_u16_f16): Likewise. 18697 (__arm_vcvtaq_u32_f32): Likewise. 18698 (__arm_vcvtaq_s16_f16): Likewise. 18699 (__arm_vcvtaq_s32_f32): Likewise. 18700 (__arm_vcvtnq_s16_f16): Likewise. 18701 (__arm_vcvtnq_s32_f32): Likewise. 18702 (__arm_vcvtpq_s16_f16): Likewise. 18703 (__arm_vcvtpq_s32_f32): Likewise. 18704 (__arm_vcvtmq_s16_f16): Likewise. 18705 (__arm_vcvtmq_s32_f32): Likewise. 18706 (vdupq_n): Define polymorphic variant. 18707 (vabsq): Likewise. 18708 (vclsq): Likewise. 18709 (vclzq): Likewise. 18710 (vnegq): Likewise. 18711 (vaddlvq): Likewise. 18712 (vaddvq): Likewise. 18713 (vmovlbq): Likewise. 18714 (vmovltq): Likewise. 18715 (vmvnq): Likewise. 18716 (vrev16q): Likewise. 18717 (vrev32q): Likewise. 18718 (vqabsq): Likewise. 18719 (vqnegq): Likewise. 18720 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. 18721 (UNOP_SNONE_NONE): Likewise. 18722 (UNOP_UNONE_UNONE): Likewise. 18723 (UNOP_UNONE_NONE): Likewise. 18724 * config/arm/constraints.md (e): Define new constriant to allow only 18725 even registers. 18726 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern. 18727 (mve_vnegq_s<mode>): Likewise. 18728 (mve_vmvnq_<supf><mode>): Likewise. 18729 (mve_vdupq_n_<supf><mode>): Likewise. 18730 (mve_vclzq_<supf><mode>): Likewise. 18731 (mve_vclsq_s<mode>): Likewise. 18732 (mve_vaddvq_<supf><mode>): Likewise. 18733 (mve_vabsq_s<mode>): Likewise. 18734 (mve_vrev32q_<supf><mode>): Likewise. 18735 (mve_vmovltq_<supf><mode>): Likewise. 18736 (mve_vmovlbq_<supf><mode>): Likewise. 18737 (mve_vcvtpq_<supf><mode>): Likewise. 18738 (mve_vcvtnq_<supf><mode>): Likewise. 18739 (mve_vcvtmq_<supf><mode>): Likewise. 18740 (mve_vcvtaq_<supf><mode>): Likewise. 18741 (mve_vrev16q_<supf>v16qi): Likewise. 18742 (mve_vaddlvq_<supf>v4si): Likewise. 18743 187442020-03-17 Jakub Jelinek <jakub@redhat.com> 18745 18746 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in 18747 a dump message. 18748 * tree-sra.c (create_access_replacement): Fix up duplicated word issue 18749 in a comment. 18750 * read-rtl-function.c (find_param_by_name, 18751 function_reader::parse_enum_value, function_reader::get_insn_by_uid): 18752 Likewise. 18753 * spellcheck.c (get_edit_distance_cutoff): Likewise. 18754 * tree-data-ref.c (create_ifn_alias_checks): Likewise. 18755 * tree.def (SWITCH_EXPR): Likewise. 18756 * selftest.c (assert_str_contains): Likewise. 18757 * ipa-param-manipulation.h (class ipa_param_body_adjustments): 18758 Likewise. 18759 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. 18760 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. 18761 * langhooks.h (struct lang_hooks_for_decls): Likewise. 18762 * ipa-prop.h (struct ipa_param_descriptor): Likewise. 18763 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): 18764 Likewise. 18765 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. 18766 * tree-ssa-reassoc.c (reassociate_bb): Likewise. 18767 * tree.c (component_ref_size): Likewise. 18768 * hsa-common.c (hsa_init_compilation_unit_data): Likewise. 18769 * gimple-ssa-sprintf.c (get_string_length, format_string, 18770 format_directive): Likewise. 18771 * omp-grid.c (grid_process_kernel_body_copy): Likewise. 18772 * input.c (string_concat_db::get_string_concatenation, 18773 test_lexer_string_locations_ucn4): Likewise. 18774 * cfgexpand.c (pass_expand::execute): Likewise. 18775 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, 18776 maybe_diag_overlap): Likewise. 18777 * rtl.c (RTX_CODE_HWINT_P_1): Likewise. 18778 * shrink-wrap.c (spread_components): Likewise. 18779 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): 18780 Likewise. 18781 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): 18782 Likewise. 18783 * dwarf2out.c (dwarf2out_early_finish): Likewise. 18784 * gimple-ssa-store-merging.c: Likewise. 18785 * ira-costs.c (record_operand_costs): Likewise. 18786 * tree-vect-loop.c (vectorizable_reduction): Likewise. 18787 * target.def (dispatch): Likewise. 18788 (validate_dims, gen_ccmp_first): Fix up duplicated word issue 18789 in documentation text. 18790 * doc/tm.texi: Regenerated. 18791 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up 18792 duplicated word issue in a comment. 18793 * config/i386/i386.c (ix86_test_loading_unspec): Likewise. 18794 * config/i386/i386-features.c (remove_partial_avx_dependency): 18795 Likewise. 18796 * config/msp430/msp430.c (msp430_select_section): Likewise. 18797 * config/gcn/gcn-run.c (load_image): Likewise. 18798 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise. 18799 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. 18800 * config/aarch64/falkor-tag-collision-avoidance.c 18801 (single_dest_per_chain): Likewise. 18802 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. 18803 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. 18804 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. 18805 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): 18806 Likewise. 18807 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. 18808 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. 18809 * config/rs6000/rs6000-logue.c 18810 (rs6000_emit_probe_stack_range_stack_clash): Likewise. 18811 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. 18812 Fix various other issues in the comment. 18813 188142020-03-17 Mihail Ionescu <mihail.ionescu@arm.com> 18815 18816 * config/arm/t-rmprofile: create new multilib for 18817 armv8.1-m.main+mve hard float and reuse v8-m.main ones for 18818 v8.1-m.main+mve. 18819 188202020-03-17 Jakub Jelinek <jakub@redhat.com> 18821 18822 PR tree-optimization/94015 18823 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the 18824 function where EXP is address of the bytes being stored rather than 18825 the bytes themselves into count_nonzero_bytes_addr. Punt on zero 18826 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs. 18827 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before 18828 calling native_encode_expr if host or target doesn't have 8-bit 18829 chars. Formatting fixes. 18830 (count_nonzero_bytes_addr): New function. 18831 188322020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18833 Mihail Ionescu <mihail.ionescu@arm.com> 18834 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18835 18836 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define. 18837 (UNOP_SNONE_NONE_QUALIFIERS): Likewise. 18838 (UNOP_SNONE_IMM_QUALIFIERS): Likewise. 18839 (UNOP_UNONE_NONE_QUALIFIERS): Likewise. 18840 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise. 18841 (UNOP_UNONE_IMM_QUALIFIERS): Likewise. 18842 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro. 18843 (vmvnq_n_s32): Likewise. 18844 (vrev64q_s8): Likewise. 18845 (vrev64q_s16): Likewise. 18846 (vrev64q_s32): Likewise. 18847 (vcvtq_s16_f16): Likewise. 18848 (vcvtq_s32_f32): Likewise. 18849 (vrev64q_u8): Likewise. 18850 (vrev64q_u16): Likewise. 18851 (vrev64q_u32): Likewise. 18852 (vmvnq_n_u16): Likewise. 18853 (vmvnq_n_u32): Likewise. 18854 (vcvtq_u16_f16): Likewise. 18855 (vcvtq_u32_f32): Likewise. 18856 (__arm_vmvnq_n_s16): Define intrinsic. 18857 (__arm_vmvnq_n_s32): Likewise. 18858 (__arm_vrev64q_s8): Likewise. 18859 (__arm_vrev64q_s16): Likewise. 18860 (__arm_vrev64q_s32): Likewise. 18861 (__arm_vrev64q_u8): Likewise. 18862 (__arm_vrev64q_u16): Likewise. 18863 (__arm_vrev64q_u32): Likewise. 18864 (__arm_vmvnq_n_u16): Likewise. 18865 (__arm_vmvnq_n_u32): Likewise. 18866 (__arm_vcvtq_s16_f16): Likewise. 18867 (__arm_vcvtq_s32_f32): Likewise. 18868 (__arm_vcvtq_u16_f16): Likewise. 18869 (__arm_vcvtq_u32_f32): Likewise. 18870 (vrev64q): Define polymorphic variant. 18871 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. 18872 (UNOP_SNONE_NONE): Likewise. 18873 (UNOP_SNONE_IMM): Likewise. 18874 (UNOP_UNONE_UNONE): Likewise. 18875 (UNOP_UNONE_NONE): Likewise. 18876 (UNOP_UNONE_IMM): Likewise. 18877 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern. 18878 (mve_vcvtq_from_f_<supf><mode>): Likewise. 18879 (mve_vmvnq_n_<supf><mode>): Likewise. 18880 188812020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com> 18882 Mihail Ionescu <mihail.ionescu@arm.com> 18883 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18884 18885 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. 18886 (UNOP_NONE_SNONE_QUALIFIERS): Likewise. 18887 (UNOP_NONE_UNONE_QUALIFIERS): Likewise. 18888 * config/arm/arm_mve.h (vrndxq_f16): Define macro. 18889 (vrndxq_f32): Likewise. 18890 (vrndq_f16) Likewise. 18891 (vrndq_f32): Likewise. 18892 (vrndpq_f16): Likewise. 18893 (vrndpq_f32): Likewise. 18894 (vrndnq_f16): Likewise. 18895 (vrndnq_f32): Likewise. 18896 (vrndmq_f16): Likewise. 18897 (vrndmq_f32): Likewise. 18898 (vrndaq_f16): Likewise. 18899 (vrndaq_f32): Likewise. 18900 (vrev64q_f16): Likewise. 18901 (vrev64q_f32): Likewise. 18902 (vnegq_f16): Likewise. 18903 (vnegq_f32): Likewise. 18904 (vdupq_n_f16): Likewise. 18905 (vdupq_n_f32): Likewise. 18906 (vabsq_f16): Likewise. 18907 (vabsq_f32): Likewise. 18908 (vrev32q_f16): Likewise. 18909 (vcvttq_f32_f16): Likewise. 18910 (vcvtbq_f32_f16): Likewise. 18911 (vcvtq_f16_s16): Likewise. 18912 (vcvtq_f32_s32): Likewise. 18913 (vcvtq_f16_u16): Likewise. 18914 (vcvtq_f32_u32): Likewise. 18915 (__arm_vrndxq_f16): Define intrinsic. 18916 (__arm_vrndxq_f32): Likewise. 18917 (__arm_vrndq_f16): Likewise. 18918 (__arm_vrndq_f32): Likewise. 18919 (__arm_vrndpq_f16): Likewise. 18920 (__arm_vrndpq_f32): Likewise. 18921 (__arm_vrndnq_f16): Likewise. 18922 (__arm_vrndnq_f32): Likewise. 18923 (__arm_vrndmq_f16): Likewise. 18924 (__arm_vrndmq_f32): Likewise. 18925 (__arm_vrndaq_f16): Likewise. 18926 (__arm_vrndaq_f32): Likewise. 18927 (__arm_vrev64q_f16): Likewise. 18928 (__arm_vrev64q_f32): Likewise. 18929 (__arm_vnegq_f16): Likewise. 18930 (__arm_vnegq_f32): Likewise. 18931 (__arm_vdupq_n_f16): Likewise. 18932 (__arm_vdupq_n_f32): Likewise. 18933 (__arm_vabsq_f16): Likewise. 18934 (__arm_vabsq_f32): Likewise. 18935 (__arm_vrev32q_f16): Likewise. 18936 (__arm_vcvttq_f32_f16): Likewise. 18937 (__arm_vcvtbq_f32_f16): Likewise. 18938 (__arm_vcvtq_f16_s16): Likewise. 18939 (__arm_vcvtq_f32_s32): Likewise. 18940 (__arm_vcvtq_f16_u16): Likewise. 18941 (__arm_vcvtq_f32_u32): Likewise. 18942 (vrndxq): Define polymorphic variants. 18943 (vrndq): Likewise. 18944 (vrndpq): Likewise. 18945 (vrndnq): Likewise. 18946 (vrndmq): Likewise. 18947 (vrndaq): Likewise. 18948 (vrev64q): Likewise. 18949 (vnegq): Likewise. 18950 (vabsq): Likewise. 18951 (vrev32q): Likewise. 18952 (vcvtbq_f32): Likewise. 18953 (vcvttq_f32): Likewise. 18954 (vcvtq): Likewise. 18955 * config/arm/arm_mve_builtins.def (VAR2): Define. 18956 (VAR1): Define. 18957 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern. 18958 (mve_vrndq_f<mode>): Likewise. 18959 (mve_vrndpq_f<mode>): Likewise. 18960 (mve_vrndnq_f<mode>): Likewise. 18961 (mve_vrndmq_f<mode>): Likewise. 18962 (mve_vrndaq_f<mode>): Likewise. 18963 (mve_vrev64q_f<mode>): Likewise. 18964 (mve_vnegq_f<mode>): Likewise. 18965 (mve_vdupq_n_f<mode>): Likewise. 18966 (mve_vabsq_f<mode>): Likewise. 18967 (mve_vrev32q_fv8hf): Likewise. 18968 (mve_vcvttq_f32_f16v4sf): Likewise. 18969 (mve_vcvtbq_f32_f16v4sf): Likewise. 18970 (mve_vcvtq_to_f_<supf><mode>): Likewise. 18971 189722020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 18973 Mihail Ionescu <mihail.ionescu@arm.com> 18974 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 18975 18976 * config/arm/arm-builtins.c (CF): Define mve_builtin_data. 18977 (VAR1): Define. 18978 (ARM_BUILTIN_MVE_PATTERN_START): Define. 18979 (arm_init_mve_builtins): Define function. 18980 (arm_init_builtins): Add TARGET_HAVE_MVE check. 18981 (arm_expand_builtin_1): Check the range of fcode. 18982 (arm_expand_mve_builtin): Define function to expand MVE builtins. 18983 (arm_expand_builtin): Check the range of fcode. 18984 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point 18985 types. 18986 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. 18987 (vst4q_s8): Define macro. 18988 (vst4q_s16): Likewise. 18989 (vst4q_s32): Likewise. 18990 (vst4q_u8): Likewise. 18991 (vst4q_u16): Likewise. 18992 (vst4q_u32): Likewise. 18993 (vst4q_f16): Likewise. 18994 (vst4q_f32): Likewise. 18995 (__arm_vst4q_s8): Define inline builtin. 18996 (__arm_vst4q_s16): Likewise. 18997 (__arm_vst4q_s32): Likewise. 18998 (__arm_vst4q_u8): Likewise. 18999 (__arm_vst4q_u16): Likewise. 19000 (__arm_vst4q_u32): Likewise. 19001 (__arm_vst4q_f16): Likewise. 19002 (__arm_vst4q_f32): Likewise. 19003 (__ARM_mve_typeid): Define macro with MVE types. 19004 (__ARM_mve_coerce): Define macro with _Generic feature. 19005 (vst4q): Define polymorphic variant for different vst4q builtins. 19006 * config/arm/arm_mve_builtins.def: New file. 19007 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI 19008 modes in MVE. 19009 * config/arm/mve.md (MVE_VLD_ST): Define iterator. 19010 (unspec): Define unspec. 19011 (mve_vst4q<mode>): Define RTL pattern. 19012 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI 19013 modes in MVE. 19014 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes 19015 in MVE. 19016 (define_split): Allow OI mode split for MVE after reload. 19017 (define_split): Allow XI mode split for MVE after reload. 19018 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. 19019 (arm-builtins.o): Likewise. 19020 190212020-03-17 Christophe Lyon <christophe.lyon@linaro.org> 19022 19023 * c-typeck.c (process_init_element): Handle constructor_type with 19024 type size represented by POLY_INT_CST. 19025 190262020-03-17 Jakub Jelinek <jakub@redhat.com> 19027 19028 PR tree-optimization/94187 19029 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if 19030 nchars - offset < nbytes. 19031 19032 PR middle-end/94189 19033 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would 19034 emit a warning if it was enabled and don't depend on TREE_NO_WARNING 19035 for code-generation. 19036 190372020-03-16 Vladimir Makarov <vmakarov@redhat.com> 19038 19039 PR target/94185 19040 * lra-spills.c (remove_pseudos): Do not reuse insn alternative 19041 after changing memory subreg. 19042 190432020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 19044 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 19045 19046 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add 19047 emulator calls for dobule precision arithmetic operations for MVE. 19048 190492020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 19050 Mihail Ionescu <mihail.ionescu@arm.com> 19051 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 19052 19053 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base 19054 feature bit is on and -mfpu=auto is passed as compiler option, do not 19055 generate error on not finding any matching fpu. Because in this case 19056 fpu is not required. 19057 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is 19058 enabled for MVE and also for all VFP extensions. 19059 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 19060 is enabled. 19061 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. 19062 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 19063 along with feature bits mve_float. 19064 (mve): Modify add options in armv8.1-m.main arch for MVE. 19065 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with 19066 floating point. 19067 * config/arm/arm.c (use_return_insn): Replace the 19068 check with TARGET_VFP_BASE. 19069 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with 19070 TARGET_VFP_BASE. 19071 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" 19072 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as 19073 well. 19074 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with 19075 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE 19076 as well. 19077 (arm_compute_frame_layout): Likewise. 19078 (arm_save_coproc_regs): Likewise. 19079 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM 19080 in MVE as well. 19081 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" 19082 with equivalent macro TARGET_VFP_BASE. 19083 (arm_expand_epilogue_apcs_frame): Likewise. 19084 (arm_expand_epilogue): Likewise. 19085 (arm_conditional_register_usage): Likewise. 19086 (arm_declare_function_name): Add check to skip printing .fpu directive 19087 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is 19088 "softvfp". 19089 * config/arm/arm.h (TARGET_VFP_BASE): Define. 19090 * config/arm/arm.md (arch): Add "mve" to arch. 19091 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. 19092 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT 19093 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. 19094 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR 19095 in MVE. 19096 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard 19097 to not allow for MVE. 19098 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs 19099 enum. 19100 (VUNSPEC_GET_FPSCR): Define. 19101 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS 19102 instructions which move to general-purpose Register from Floating-point 19103 Special register and vice-versa. 19104 (thumb2_movhi_fp16): Likewise. 19105 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along 19106 with MCR and MRC instructions which set and get Floating-point Status 19107 and Control Register (FPSCR). 19108 (movdi_vfp): Modify pattern to enable Single-precision scalar float move 19109 in MVE. 19110 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar 19111 float move patterns in MVE. 19112 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional 19113 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. 19114 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional 19115 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. 19116 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding 19117 TARGET_VFP_BASE check. 19118 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern 19119 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR 19120 register. 19121 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern 19122 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR 19123 register. 19124 19125 191262020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 19127 Mihail Ionescu <mihail.ionescu@arm.com> 19128 Srinath Parvathaneni <srinath.parvathaneni@arm.com> 19129 19130 * config.gcc (arm_mve.h): Include mve intrinsics header file. 19131 * config/arm/aout.h (p0): Add new register name for MVE predicated 19132 cases. 19133 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro 19134 common to Neon and MVE. 19135 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. 19136 (arm_init_simd_builtin_types): Disable poly types for MVE. 19137 (arm_init_neon_builtins): Move a check to arm_init_builtins function. 19138 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of 19139 ARM_BUILTIN_NEON_LANE_CHECK. 19140 (mve_dereference_pointer): Add function. 19141 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is 19142 enabled. 19143 (arm_expand_neon_builtin): Moved to arm_expand_builtin function. 19144 (arm_expand_builtin): Moved from arm_expand_neon_builtin function. 19145 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE 19146 with floating point enabled. 19147 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to 19148 simd_immediate_valid_for_move. 19149 (simd_immediate_valid_for_move): Renamed from 19150 neon_immediate_valid_for_move function. 19151 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate 19152 error if vfpv2 feature bit is disabled and mve feature bit is also 19153 disabled for HARD_FLOAT_ABI. 19154 (use_return_insn): Check to not push VFP regs for MVE. 19155 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard 19156 as Neon. 19157 (aapcs_vfp_allocate_return_reg): Likewise. 19158 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 19159 address operand for MVE. 19160 (arm_rtx_costs_internal): MVE check to determine cost of rtx. 19161 (neon_valid_immediate): Rename to simd_valid_immediate. 19162 (simd_valid_immediate): Rename from neon_valid_immediate. 19163 (simd_valid_immediate): MVE check on size of vector is 128 bits. 19164 (neon_immediate_valid_for_move): Rename to 19165 simd_immediate_valid_for_move. 19166 (simd_immediate_valid_for_move): Rename from 19167 neon_immediate_valid_for_move. 19168 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate 19169 function. 19170 (neon_make_constant): Modify call to neon_valid_immediate function. 19171 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC 19172 for MVE. 19173 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. 19174 (arm_compute_frame_layout): Calculate space for saved VFP registers for 19175 MVE. 19176 (arm_save_coproc_regs): Save coproc registers for MVE. 19177 (arm_print_operand): Add case 'E' to print memory operands for MVE. 19178 (arm_print_operand_address): Check to print register number for MVE. 19179 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. 19180 (arm_modes_tieable_p): Check to allow structure mode for MVE. 19181 (arm_regno_class): Add VPR_REGNUM check. 19182 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code 19183 for APCS frame. 19184 (arm_expand_epilogue): MVE check for enabling pop instructions in 19185 epilogue. 19186 (arm_print_asm_arch_directives): Modify function to disable print of 19187 .arch_extension "mve" and "fp" for cases where MVE is enabled with 19188 "SOFT FLOAT ABI". 19189 (arm_vector_mode_supported_p): Check for modes available in MVE interger 19190 and MVE floating point. 19191 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode 19192 pointer support. 19193 (arm_conditional_register_usage): Enable usage of conditional regsiter 19194 for MVE. 19195 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. 19196 (arm_declare_function_name): Modify function to disable print of 19197 .arch_extension "mve" and "fp" for cases where MVE is enabled with 19198 "SOFT FLOAT ABI". 19199 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and 19200 when target general registers are required. 19201 (TARGET_HAVE_MVE_FLOAT): Likewise. 19202 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c 19203 for MVE. 19204 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS 19205 which indicate this is not available for across function calls. 19206 (FIRST_PSEUDO_REGISTER): Modify. 19207 (VALID_MVE_MODE): Define valid MVE mode. 19208 (VALID_MVE_SI_MODE): Define valid MVE SI mode. 19209 (VALID_MVE_SF_MODE): Define valid MVE SF mode. 19210 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. 19211 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence 19212 for MVE. 19213 (IS_VPR_REGNUM): Macro to check for VPR_REG register. 19214 (REG_ALLOC_ORDER): Add VPR_REGNUM entry. 19215 (enum reg_class): Add VPR_REG entry. 19216 (REG_CLASS_NAMES): Add VPR_REG entry. 19217 * config/arm/arm.md (VPR_REGNUM): Define. 19218 (conds): Check is_mve_type attrbiute to differentiate "conditional" and 19219 "unconditional" instructions. 19220 (arm_movsf_soft_insn): Modify RTL to not allow for MVE. 19221 (movdf_soft_insn): Modify RTL to not allow for MVE. 19222 (vfp_pop_multiple_with_writeback): Enable for MVE. 19223 (include "mve.md"): Include mve.md file. 19224 * config/arm/arm_mve.h: Add MVE intrinsics head file. 19225 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE 19226 for vector predicated operands. 19227 * config/arm/iterators.md (VNIM1): Define. 19228 (VNINOTM1): Define. 19229 (VHFBF_split): Define 19230 * config/arm/mve.md: New file. 19231 (mve_mov<mode>): Define RTL for move, store and load in MVE. 19232 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for 19233 second operand. 19234 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with 19235 simd_immediate_valid_for_move. 19236 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which 19237 is common to MVE and NEON to vec-common.md file. 19238 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check. 19239 * config/arm/predicates.md (vpr_register_operand): Define. 19240 * config/arm/t-arm: Add mve.md file. 19241 * config/arm/types.md (mve_move): Add MVE instructions mve_move to 19242 attribute "type". 19243 (mve_store): Add MVE instructions mve_store to attribute "type". 19244 (mve_load): Add MVE instructions mve_load to attribute "type". 19245 (is_mve_type): Define attribute. 19246 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support 19247 standard move patterns in MVE along with NEON and IWMMXT with mode 19248 iterator VNIM1. 19249 (mov<mode>): Modify RTL expand to support standard move patterns in NEON 19250 and IWMMXT with mode iterator V8HF. 19251 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in 19252 NEON and MVE. 19253 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to 19254 simd_immediate_valid_for_move. 19255 19256 192572020-03-16 H.J. Lu <hongjiu.lu@intel.com> 19258 19259 PR target/89229 19260 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov 19261 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL 19262 check. 19263 * config/i386/predicates.md (ext_sse_reg_operand): Removed. 19264 192652020-03-16 Jakub Jelinek <jakub@redhat.com> 19266 19267 PR debug/94167 19268 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands 19269 DEBUG_STMTs. 19270 19271 PR tree-optimization/94166 19272 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION 19273 as secondary comparison key. 19274 192752020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com> 19276 19277 PR tree-optimization/94125 19278 * tree-loop-distribution.c 19279 (loop_distribution::break_alias_scc_partitions): Update post order 19280 number for merged scc. 19281 192822020-03-15 H.J. Lu <hongjiu.lu@intel.com> 19283 19284 PR target/89229 19285 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and 19286 MODE_SF. 19287 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov 19288 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL 19289 and ext_sse_reg_operand check. 19290 192912020-03-15 Lewis Hyatt <lhyatt@gmail.com> 19292 19293 * common.opt: Avoid redundancy in the help text. 19294 * config/arc/arc.opt: Likewise. 19295 * config/cr16/cr16.opt: Likewise. 19296 192972020-03-14 Jakub Jelinek <jakub@redhat.com> 19298 19299 PR middle-end/93566 19300 * tree-nested.c (convert_nonlocal_omp_clauses, 19301 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses 19302 with C/C++ array sections. 19303 193042020-03-14 H.J. Lu <hongjiu.lu@intel.com> 19305 19306 PR target/89229 19307 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov 19308 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL 19309 check. 19310 193112020-03-14 Jakub Jelinek <jakub@redhat.com> 19312 19313 * gimple-fold.c (gimple_fold_builtin_strncpy): Change 19314 "a an" to "an" in a comment. 19315 * hsa-common.h (is_a_helper): Likewise. 19316 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise. 19317 * config/arc/arc.c (arc600_corereg_hazard): Likewise. 19318 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise. 19319 193202020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com> 19321 19322 PR target/92379 19323 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a 19324 64-bit value by 64 bits (UB). 19325 193262020-03-13 Vladimir Makarov <vmakarov@redhat.com> 19327 19328 PR rtl-optimization/92303 19329 * lra-spills.c (remove_pseudos): Try to simplify memory subreg. 19330 193312020-03-13 Segher Boessenkool <segher@kernel.crashing.org> 19332 19333 PR rtl-optimization/94148 19334 PR rtl-optimization/94042 19335 * df-core.c (BB_LAST_CHANGE_AGE): Delete. 19336 (df_worklist_propagate_forward): New parameter last_change_age, use 19337 that instead of bb->aux. 19338 (df_worklist_propagate_backward): Ditto. 19339 (df_worklist_dataflow_doublequeue): Use a local array last_change_age. 19340 193412020-03-13 Richard Biener <rguenther@suse.de> 19342 19343 PR tree-optimization/94163 19344 * tree-ssa-pre.c (create_expression_by_pieces): Check 19345 whether alignment would be zero. 19346 193472020-03-13 Martin Liska <mliska@suse.cz> 19348 19349 PR lto/94157 19350 * lto-wrapper.c (run_gcc): Use concat for appending 19351 to collect_gcc_options. 19352 193532020-03-13 Jakub Jelinek <jakub@redhat.com> 19354 19355 PR target/94121 19356 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode 19357 instead of GEN_INT. 19358 193592020-03-13 H.J. Lu <hongjiu.lu@intel.com> 19360 19361 PR target/89229 19362 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF. 19363 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov 19364 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256, 19365 TARGET_AVX512VL and ext_sse_reg_operand check. 19366 193672020-03-13 Bu Le <bule1@huawei.com> 19368 19369 PR target/94154 19370 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=) 19371 (-param=aarch64-double-recp-precision=): New options. 19372 * doc/invoke.texi: Document them. 19373 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them 19374 instead of hard-coding the choice of 1 for float and 2 for double. 19375 193762020-03-13 Eric Botcazou <ebotcazou@adacore.com> 19377 19378 PR rtl-optimization/94119 19379 * resource.h (clear_hashed_info_until_next_barrier): Declare. 19380 * resource.c (clear_hashed_info_until_next_barrier): New function. 19381 * reorg.c (add_to_delay_list): Fix formatting. 19382 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on 19383 the next instruction after removing a BARRIER. 19384 193852020-03-13 Eric Botcazou <ebotcazou@adacore.com> 19386 19387 PR middle-end/92071 19388 * expmed.c (store_integral_bit_field): For fields larger than a word, 19389 call extract_bit_field on the value if the mode is BLKmode. Remove 19390 specific path for big-endian targets and tidy things up a little bit. 19391 193922020-03-12 Richard Sandiford <richard.sandiford@arm.com> 19393 19394 PR rtl-optimization/90275 19395 * cse.c (cse_insn): Delete no-op register moves too. 19396 193972020-03-12 Darius Galis <darius.galis@cyberthorstudios.com> 19398 19399 * config/rx/rx.md (CTRLREG_CPEN): Remove. 19400 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support. 19401 194022020-03-12 Richard Biener <rguenther@suse.de> 19403 19404 PR tree-optimization/94103 19405 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type 19406 punning when the mode precision is not sufficient. 19407 194082020-03-12 H.J. Lu <hongjiu.lu@intel.com> 19409 19410 PR target/89229 19411 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI, 19412 MODE_V1DF and MODE_V2SF. 19413 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call 19414 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand 19415 check. 19416 194172020-03-12 Jakub Jelinek <jakub@redhat.com> 19418 19419 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change 19420 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL 19421 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL. 19422 * doc/tm.texi: Regenerated. 19423 19424 PR tree-optimization/94130 19425 * tree-ssa-dse.c: Include gimplify.h. 19426 (increment_start_addr): If stmt has lhs, drop the lhs from call and 19427 set it after the call to the original value of the first argument. 19428 Formatting fixes. 19429 (decrement_count): Formatting fix. 19430 194312020-03-11 Delia Burduv <delia.burduv@arm.com> 19432 19433 * config/arm/arm-builtins.c 19434 (arm_init_simd_builtin_scalar_types): New. 19435 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type. 19436 (vld2q_bf16): Used new builtin type. 19437 (vld3_bf16): Used new builtin type. 19438 (vld3q_bf16): Used new builtin type. 19439 (vld4_bf16): Used new builtin type. 19440 (vld4q_bf16): Used new builtin type. 19441 (vld2_dup_bf16): Used new builtin type. 19442 (vld2q_dup_bf16): Used new builtin type. 19443 (vld3_dup_bf16): Used new builtin type. 19444 (vld3q_dup_bf16): Used new builtin type. 19445 (vld4_dup_bf16): Used new builtin type. 19446 (vld4q_dup_bf16): Used new builtin type. 19447 194482020-03-11 Jakub Jelinek <jakub@redhat.com> 19449 19450 PR target/94134 19451 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section 19452 at the start to switch to data section. Don't print extra newline if 19453 .globl directive has not been emitted. 19454 194552020-03-11 Richard Biener <rguenther@suse.de> 19456 19457 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): 19458 New pattern. 19459 194602020-03-11 Eric Botcazou <ebotcazou@adacore.com> 19461 19462 PR middle-end/93961 19463 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields 19464 whose type is a qualified union. 19465 194662020-03-11 Jakub Jelinek <jakub@redhat.com> 19467 19468 PR target/94121 19469 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi 19470 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT. 19471 19472 PR bootstrap/93962 19473 * value-prof.c (dump_histogram_value): Use abs_hwi instead of 19474 std::abs. 19475 (get_nth_most_common_value): Use abs_hwi instead of abs. 19476 19477 PR middle-end/94111 19478 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl 19479 is rvc_normal, otherwise use real_to_decimal to print the number to 19480 string. 19481 19482 PR tree-optimization/94114 19483 * tree-loop-distribution.c (generate_memset_builtin): Call 19484 rewrite_to_non_trapping_overflow even on mem. 19485 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even 19486 on dest and src. 19487 194882020-03-10 Jeff Law <law@redhat.com> 19489 19490 * config/bfin/bfin.md (movsi_insv): Add length attribute. 19491 194922020-03-10 Jiufu Guo <guojiufu@linux.ibm.com> 19493 19494 PR target/93709 19495 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check 19496 NAN and SIGNED_ZEROR for smax/smin. 19497 194982020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com> 19499 19500 PR target/90763 19501 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add 19502 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments. 19503 195042020-03-10 Roman Zhuykov <zhroma@ispras.ru> 19505 19506 * loop-iv.c (find_simple_exit): Make it static. 19507 * cfgloop.h: Remove the corresponding prototype. 19508 195092020-03-10 Roman Zhuykov <zhroma@ispras.ru> 19510 19511 * ddg.c (create_ddg): Fix intendation. 19512 (set_recurrence_length): Likewise. 19513 (create_ddg_all_sccs): Likewise. 19514 195152020-03-10 Jakub Jelinek <jakub@redhat.com> 19516 19517 PR target/94088 19518 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with 19519 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len 19520 is 32. 19521 195222020-03-09 Jason Merrill <jason@redhat.com> 19523 19524 * gdbinit.in (pgs): Fix typo in documentation. 19525 195262020-03-09 Vladimir Makarov <vmakarov@redhat.com> 19527 19528 Revert: 19529 19530 2020-02-28 Vladimir Makarov <vmakarov@redhat.com> 19531 19532 PR rtl-optimization/93564 19533 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we 19534 do not honor reg alloc order. 19535 195362020-03-09 Andrew Pinski <apinski@marvell.com> 19537 19538 PR inline-asm/94095 19539 * doc/extend.texi (x86 Operand Modifiers): Fix column 19540 for 'A' modifier. 19541 195422020-03-09 Martin Liska <mliska@suse.cz> 19543 19544 PR target/93800 19545 * config/rs6000/rs6000.c (rs6000_option_override_internal): 19546 Remove set of str_align_loops and str_align_jumps as these 19547 should be set in previous 2 conditions in the function. 19548 195492020-03-09 Jakub Jelinek <jakub@redhat.com> 19550 19551 PR rtl-optimization/94045 19552 * params.opt (-param=max-find-base-term-values=): New option. 19553 * alias.c (find_base_term): Add cut-off for number of visited VALUEs 19554 in a single toplevel find_base_term call. 19555 195562020-03-06 Wilco Dijkstra <wdijkstr@arm.com> 19557 19558 PR target/91598 19559 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define. 19560 * config/aarch64/aarch64-simd.md 19561 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul. 19562 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise. 19563 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics. 19564 * config/aarch64/arm_neon.h: 19565 (vmlal_lane_s16): Expand using intrinsics rather than inline asm. 19566 (vmlal_lane_u16): Likewise. 19567 (vmlal_lane_s32): Likewise. 19568 (vmlal_lane_u32): Likewise. 19569 (vmlal_laneq_s16): Likewise. 19570 (vmlal_laneq_u16): Likewise. 19571 (vmlal_laneq_s32): Likewise. 19572 (vmlal_laneq_u32): Likewise. 19573 (vmull_lane_s16): Likewise. 19574 (vmull_lane_u16): Likewise. 19575 (vmull_lane_s32): Likewise. 19576 (vmull_lane_u32): Likewise. 19577 (vmull_laneq_s16): Likewise. 19578 (vmull_laneq_u16): Likewise. 19579 (vmull_laneq_s32): Likewise. 19580 (vmull_laneq_u32): Likewise. 19581 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul. 19582 (Qlane): Likewise. 19583 195842020-03-06 Wilco Dijkstra <wdijkstr@arm.com> 19585 19586 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax. 19587 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise. 19588 (aarch64_mls_elt<mode>): Likewise. 19589 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise. 19590 (aarch64_fma4_elt<mode>): Likewise. 19591 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. 19592 (aarch64_fma4_elt_to_64v2df): Likewise. 19593 (aarch64_fnma4_elt<mode>): Likewise. 19594 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. 19595 (aarch64_fnma4_elt_to_64v2df): Likewise. 19596 195972020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 19598 19599 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>: 19600 Specify movprfx attribute. 19601 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise. 19602 196032020-03-06 David Edelsohn <dje.gcc@gmail.com> 19604 19605 PR target/94065 19606 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for 19607 cmodel=large. 19608 (TARGET_NO_FP_IN_TOC): Same. 19609 * config/rs6000/aix71.h: Same. 19610 * config/rs6000/aix72.h: Same. 19611 196122020-03-06 Andrew Pinski <apinski@marvell.com> 19613 Jeff Law <law@redhat.com> 19614 19615 PR rtl-optimization/93996 19616 * haifa-sched.c (remove_notes): Be more careful when adding 19617 REG_SAVE_NOTE. 19618 196192020-03-06 Delia Burduv <delia.burduv@arm.com> 19620 19621 * config/arm/arm_neon.h (vld2_bf16): New. 19622 (vld2q_bf16): New. 19623 (vld3_bf16): New. 19624 (vld3q_bf16): New. 19625 (vld4_bf16): New. 19626 (vld4q_bf16): New. 19627 (vld2_dup_bf16): New. 19628 (vld2q_dup_bf16): New. 19629 (vld3_dup_bf16): New. 19630 (vld3q_dup_bf16): New. 19631 (vld4_dup_bf16): New. 19632 (vld4q_dup_bf16): New. 19633 * config/arm/arm_neon_builtins.def 19634 (vld2): Changed to VAR13 and added v4bf, v8bf 19635 (vld2_dup): Changed to VAR8 and added v4bf, v8bf 19636 (vld3): Changed to VAR13 and added v4bf, v8bf 19637 (vld3_dup): Changed to VAR8 and added v4bf, v8bf 19638 (vld4): Changed to VAR13 and added v4bf, v8bf 19639 (vld4_dup): Changed to VAR8 and added v4bf, v8bf 19640 * config/arm/iterators.md (VDXBF2): New iterator. 19641 *config/arm/neon.md (neon_vld2): Use new iterators. 19642 (neon_vld2_dup<mode): Use new iterators. 19643 (neon_vld3<mode>): Likewise. 19644 (neon_vld3qa<mode>): Likewise. 19645 (neon_vld3qb<mode>): Likewise. 19646 (neon_vld3_dup<mode>): Likewise. 19647 (neon_vld4<mode>): Likewise. 19648 (neon_vld4qa<mode>): Likewise. 19649 (neon_vld4qb<mode>): Likewise. 19650 (neon_vld4_dup<mode>): Likewise. 19651 (neon_vld2_dupv8bf): New. 19652 (neon_vld3_dupv8bf): Likewise. 19653 (neon_vld4_dupv8bf): Likewise. 19654 196552020-03-06 Delia Burduv <delia.burduv@arm.com> 19656 19657 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef. 19658 (bfloat16x8x2_t): New typedef. 19659 (bfloat16x4x3_t): New typedef. 19660 (bfloat16x8x3_t): New typedef. 19661 (bfloat16x4x4_t): New typedef. 19662 (bfloat16x8x4_t): New typedef. 19663 (vst2_bf16): New. 19664 (vst2q_bf16): New. 19665 (vst3_bf16): New. 19666 (vst3q_bf16): New. 19667 (vst4_bf16): New. 19668 (vst4q_bf16): New. 19669 * config/arm/arm-builtins.c (v2bf_UP): Define. 19670 (VAR13): New. 19671 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype. 19672 * config/arm/arm-modes.def (V2BF): New mode. 19673 * config/arm/arm-simd-builtin-types.def 19674 (Bfloat16x2_t): New entry. 19675 * config/arm/arm_neon_builtins.def 19676 (vst2): Changed to VAR13 and added v4bf, v8bf 19677 (vst3): Changed to VAR13 and added v4bf, v8bf 19678 (vst4): Changed to VAR13 and added v4bf, v8bf 19679 * config/arm/iterators.md (VDXBF): New iterator. 19680 (VQ2BF): New iterator. 19681 *config/arm/neon.md (neon_vst2<mode>): Used new iterators. 19682 (neon_vst2<mode>): Used new iterators. 19683 (neon_vst3<mode>): Used new iterators. 19684 (neon_vst3<mode>): Used new iterators. 19685 (neon_vst3qa<mode>): Used new iterators. 19686 (neon_vst3qb<mode>): Used new iterators. 19687 (neon_vst4<mode>): Used new iterators. 19688 (neon_vst4<mode>): Used new iterators. 19689 (neon_vst4qa<mode>): Used new iterators. 19690 (neon_vst4qb<mode>): Used new iterators. 19691 196922020-03-06 Delia Burduv <delia.burduv@arm.com> 19693 19694 * config/aarch64/aarch64-simd-builtins.def 19695 (bfcvtn): New built-in function. 19696 (bfcvtn_q): New built-in function. 19697 (bfcvtn2): New built-in function. 19698 (bfcvt): New built-in function. 19699 * config/aarch64/aarch64-simd.md 19700 (aarch64_bfcvtn<q><mode>): New pattern. 19701 (aarch64_bfcvtn2v8bf): New pattern. 19702 (aarch64_bfcvtbf): New pattern. 19703 * config/aarch64/arm_bf16.h (float32_t): New typedef. 19704 (vcvth_bf16_f32): New intrinsic. 19705 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic. 19706 (vcvtq_low_bf16_f32): New intrinsic. 19707 (vcvtq_high_bf16_f32): New intrinsic. 19708 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator. 19709 (UNSPEC_BFCVTN): New UNSPEC. 19710 (UNSPEC_BFCVTN2): New UNSPEC. 19711 (UNSPEC_BFCVT): New UNSPEC. 19712 * config/arm/types.md (bf_cvt): New type. 19713 197142020-03-06 Andreas Krebbel <krebbel@linux.ibm.com> 19715 19716 * config/s390/s390.md ("tabort"): Get rid of two consecutive 19717 blanks in format string. 19718 197192020-03-05 H.J. Lu <hongjiu.lu@intel.com> 19720 19721 PR target/89229 19722 PR target/89346 19723 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype. 19724 * config/i386/i386.c (ix86_get_ssemov): New function. 19725 (ix86_output_ssemov): Likewise. 19726 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call 19727 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL 19728 check. 19729 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV. 19730 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV. 19731 Remove ext_sse_reg_operand and TARGET_AVX512VL check. 19732 (*movti_internal): Likewise. 19733 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. 19734 197352020-03-05 Jeff Law <law@redhat.com> 19736 19737 PR tree-optimization/91890 19738 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument. 19739 Use gimple_or_expr_nonartificial_location. 19740 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds. 19741 Use gimple_or_expr_nonartificial_location. 19742 * gimple.c (gimple_or_expr_nonartificial_location): New function. 19743 * gimple.h (gimple_or_expr_nonartificial_location): Declare it. 19744 * tree-ssa-strlen.c (maybe_warn_overflow): Use 19745 gimple_or_expr_nonartificial_location. 19746 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise. 19747 (maybe_warn_pointless_strcmp): Likewise. 19748 197492020-03-05 Jakub Jelinek <jakub@redhat.com> 19750 19751 PR target/94046 19752 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of 19753 SRC and MASK arguments to __m128 from __m128d. 19754 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256 19755 from __m256d. 19756 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128 19757 from __m128d. 19758 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C 19759 argument to __m128i from __m128d. 19760 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from 19761 __m256d. 19762 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128. 19763 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from 19764 __m256. 19765 197662020-03-05 Delia Burduv <delia.burduv@arm.com> 19767 19768 * config/arm/arm_neon.h (vbfmmlaq_f32): New. 19769 (vbfmlalbq_f32): New. 19770 (vbfmlaltq_f32): New. 19771 (vbfmlalbq_lane_f32): New. 19772 (vbfmlaltq_lane_f32): New. 19773 (vbfmlalbq_laneq_f32): New. 19774 (vbfmlaltq_laneq_f32): New. 19775 * config/arm/arm_neon_builtins.def (vmmla): New. 19776 (vfmab): New. 19777 (vfmat): New. 19778 (vfmab_lane): New. 19779 (vfmat_lane): New. 19780 (vfmab_laneq): New. 19781 (vfmat_laneq): New. 19782 * config/arm/iterators.md (BF_MA): New int iterator. 19783 (bt): New int attribute. 19784 (VQXBF): Copy of VQX with V8BF. 19785 * config/arm/neon.md (neon_vmmlav8bf): New insn. 19786 (neon_vfma<bt>v8bf): New insn. 19787 (neon_vfma<bt>_lanev8bf): New insn. 19788 (neon_vfma<bt>_laneqv8bf): New expand. 19789 (neon_vget_high<mode>): Changed iterator to VQXBF. 19790 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC. 19791 (UNSPEC_BFMAB): New UNSPEC. 19792 (UNSPEC_BFMAT): New UNSPEC. 19793 197942020-03-05 Jakub Jelinek <jakub@redhat.com> 19795 19796 PR middle-end/93399 19797 * tree-pretty-print.h (pretty_print_string): Declare. 19798 * tree-pretty-print.c (pretty_print_string): Remove forward 19799 declaration, no longer static. Change nbytes parameter type 19800 from unsigned to size_t. 19801 * print-rtl.c (print_value) <case CONST_STRING>: Use 19802 pretty_print_string and for shrink way too long strings. 19803 198042020-03-05 Richard Biener <rguenther@suse.de> 19805 Jakub Jelinek <jakub@redhat.com> 19806 19807 PR tree-optimization/93582 19808 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR 19809 last operand as signed when looking for memset offset. Formatting 19810 fix. 19811 198122020-03-04 Andrew Pinski <apinski@marvell.com> 19813 19814 PR bootstrap/93962 19815 * value-prof.c (dump_histogram_value): Use std::abs. 19816 198172020-03-04 Martin Sebor <msebor@redhat.com> 19818 19819 PR tree-optimization/93986 19820 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int 19821 operands to the same precision widest_int to avoid ICEs. 19822 198232020-03-04 Bill Schmidt <wschmidt@linux.ibm.com> 19824 19825 PR target/87560 19826 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define. 19827 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry 19828 for OPTION_MASK_ALTIVEC. 19829 198302020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 19831 19832 * config.gcc: Include the glibc-stdint.h header for zTPF. 19833 198342020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 19835 19836 * config/s390/s390.c (s390_secondary_memory_needed): Disallow 19837 direct FPR-GPR copies. 19838 (s390_register_info_gprtofpr): Disallow GPR content to be saved in 19839 FPRs. 19840 198412020-03-04 Andreas Krebbel <krebbel@linux.ibm.com> 19842 19843 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new 19844 operands to the prologue_tpf expander. 19845 (s390_emit_epilogue): Likewise. 19846 (s390_option_override_internal): Do error checking and setup for 19847 the new options. 19848 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK) 19849 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET) 19850 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET) 19851 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions. 19852 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new 19853 operands for the check flag and the branch target. 19854 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check") 19855 ("mtpf-trace-hook-prologue-target") 19856 ("mtpf-trace-hook-epilogue-check") 19857 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New 19858 options. 19859 * doc/invoke.texi: Document -mtpf-trace-skip option. The other 19860 options are for debugging purposes and will not be documented 19861 here. 19862 198632020-03-04 Jakub Jelinek <jakub@redhat.com> 19864 19865 PR debug/93888 19866 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag. 19867 19868 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti 19869 argument. Change pd argument so that it can be modified. Turn 19870 constant non-CONSTRUCTOR store into non-constant if it is too large. 19871 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid 19872 overflows. 19873 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust 19874 callers. 19875 198762020-02-04 Richard Biener <rguenther@suse.de> 19877 19878 PR tree-optimization/93964 19879 * graphite-isl-ast-to-gimple.c 19880 (gcc_expression_from_isl_ast_expr_id): Add intermediate 19881 conversion for pointer to integer converts. 19882 * graphite-scop-detection.c (assign_parameter_index_in_region): 19883 Relax assert. 19884 198852020-03-04 Martin Liska <mliska@suse.cz> 19886 19887 PR c/93886 19888 PR c/93887 19889 * doc/invoke.texi: Clarify --help=language and --help=common 19890 interaction. 19891 198922020-03-04 Jakub Jelinek <jakub@redhat.com> 19893 19894 PR tree-optimization/94001 19895 * tree-tailcall.c (process_assignment): Before comparing op1 to 19896 *ass_var, verify *ass_var is non-NULL. 19897 198982020-03-04 Kito Cheng <kito.cheng@sifive.com> 19899 19900 PR target/93995 19901 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare 19902 the result of IOR. 19903 199042020-03-03 Dennis Zhang <dennis.zhang@arm.com> 19905 19906 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New. 19907 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New. 19908 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New. 19909 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New. 19910 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries. 19911 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise. 19912 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators. 19913 (V_bf_low, V_bf_cvt_m): New mode attributes. 19914 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New. 19915 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New. 19916 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New. 19917 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New 19918 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New. 19919 199202020-03-03 Jakub Jelinek <jakub@redhat.com> 19921 19922 PR tree-optimization/93582 19923 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument. 19924 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result 19925 members, initialize them in the constructor and if mask is non-NULL, 19926 artificially push_partial_def {} for the portions of the mask that 19927 contain zeros. 19928 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to 19929 val and return (void *)-1. Formatting fix. 19930 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization. 19931 Formatting fix. 19932 (vn_reference_lookup): Add mask argument. If non-NULL, don't call 19933 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return 19934 data.mask_result. 19935 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST 19936 mask. 19937 (visit_stmt): Formatting fix. 19938 199392020-03-03 Richard Biener <rguenther@suse.de> 19940 19941 PR tree-optimization/93946 19942 * alias.h (refs_same_for_tbaa_p): Declare. 19943 * alias.c (refs_same_for_tbaa_p): New function. 19944 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return 19945 zero. 19946 * tree-ssa-scopedtables.h 19947 (avail_exprs_stack::lookup_avail_expr): Add output argument 19948 giving access to the hashtable entry. 19949 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr): 19950 Likewise. 19951 * tree-ssa-dom.c: Include alias.h. 19952 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before 19953 removing redundant store. 19954 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member. 19955 (ao_ref_init_from_vn_reference): Adjust prototype. 19956 (vn_reference_lookup_pieces): Likewise. 19957 (vn_reference_insert_pieces): Likewise. 19958 * tree-ssa-sccvn.c: Track base alias set in addition to alias 19959 set everywhere. 19960 (eliminate_dom_walker::eliminate_stmt): Also check base alias 19961 set when removing redundant stores. 19962 (visit_reference_op_store): Likewise. 19963 * dse.c (record_store): Adjust valdity check for redundant 19964 store removal. 19965 199662020-03-03 Jakub Jelinek <jakub@redhat.com> 19967 19968 PR target/26877 19969 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder. 19970 19971 PR rtl-optimization/94002 19972 * explow.c (plus_constant): Punt if cst has VOIDmode and 19973 get_pool_mode is different from mode. 19974 199752020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 19976 19977 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an 19978 address has an offset which fits the scalling constraint for a 19979 load/store operation. 19980 (legitimate_scaled_address_p): Update use 19981 leigitimate_small_data_address_p. 19982 (arc_print_operand): Likewise. 19983 (arc_legitimate_address_p): Likewise. 19984 (legitimate_small_data_address_p): Likewise. 19985 199862020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 19987 19988 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate. 19989 (fnmasf4_fpu): Likewise. 19990 199912020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 19992 19993 * config/arc/arc.md (adddi3): Early expand the 64bit operation into 19994 32bit ops. 19995 (subdi3): Likewise. 19996 (adddi3_i): Remove pattern. 19997 (subdi3_i): Likewise. 19998 199992020-03-03 Claudiu Zissulescu <claziss@synopsys.com> 20000 20001 * config/arc/arc.md (eh_return): Add length info. 20002 200032020-03-02 David Malcolm <dmalcolm@redhat.com> 20004 20005 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New. 20006 200072020-03-02 David Malcolm <dmalcolm@redhat.com> 20008 20009 * doc/invoke.texi (Static Analyzer Options): Add 20010 -Wanalyzer-stale-setjmp-buffer to the list of options enabled 20011 by -fanalyzer. 20012 200132020-03-02 Uroš Bizjak <ubizjak@gmail.com> 20014 20015 PR target/93997 20016 * config/i386/i386.md (movstrict<mode>): Allow only 20017 registers with VALID_INT_MODE_P modes. 20018 200192020-03-02 Andrew Stubbs <ams@codesourcery.com> 20020 20021 * config/gcn/gcn-valu.md (dpp_move<mode>): New. 20022 (reduc_insn): Use 'U' and 'B' operand codes. 20023 (reduc_<reduc_op>_scal_<mode>): Allow all types. 20024 (reduc_<reduc_op>_scal_v64di): Delete. 20025 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types. 20026 (*plus_carry_dpp_shr_v64si): Change to ... 20027 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types. 20028 (mov_from_lane63_v64di): Change to ... 20029 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes. 20030 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size. 20031 Support UNSPEC_MOV_DPP_SHR output formats. 20032 (gcn_expand_reduc_scalar): Add "use_moves" reductions. 20033 Add "use_extends" reductions. 20034 (print_operand_address): Add 'I' and 'U' codes. 20035 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR. 20036 200372020-03-02 Martin Liska <mliska@suse.cz> 20038 20039 * lto-wrapper.c: Fix typo in comment about 20040 C++ standard version. 20041 200422020-03-01 Martin Sebor <msebor@redhat.com> 20043 20044 PR c++/92721 20045 * calls.c (init_attr_rdwr_indices): Correctly handle attribute. 20046 200472020-03-01 Martin Sebor <msebor@redhat.com> 20048 20049 PR middle-end/93829 20050 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that 20051 of a pointer in the outermost ADDR_EXPRs. 20052 200532020-02-28 Jeff Law <law@redhat.com> 20054 20055 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19. 20056 * config/v850/v850.c (v850_asm_trampoline_template): Update 20057 accordingly. 20058 200592020-02-28 Michael Meissner <meissner@linux.ibm.com> 20060 20061 PR target/93937 20062 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var): 20063 Delete insn. 20064 200652020-02-28 Martin Liska <mliska@suse.cz> 20066 20067 PR other/93965 20068 * configure.ac: Improve detection of ld_date by requiring 20069 either two dashes or none. 20070 * configure: Regenerate. 20071 200722020-02-28 Vladimir Makarov <vmakarov@redhat.com> 20073 20074 PR rtl-optimization/93564 20075 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we 20076 do not honor reg alloc order. 20077 200782020-02-27 Joel Hutton <Joel.Hutton@arm.com> 20079 20080 PR target/87612 20081 * config/aarch64/aarch64.c (aarch64_override_options): Fix 20082 misleading warning string. 20083 200842020-02-27 Martin Sebor <msebor@redhat.com> 20085 20086 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo. 20087 200882020-02-27 Michael Meissner <meissner@linux.ibm.com> 20089 20090 PR target/93932 20091 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator): 20092 Split the insn into two parts. This insn only does variable 20093 extract from a register. 20094 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do 20095 variable extract from memory. 20096 (vsx_extract_v4sf_var): Split the insn into two parts. This insn 20097 only does variable extract from a register. 20098 (vsx_extract_v4sf_var_load): New insn, do variable extract from 20099 memory. 20100 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn 20101 into two parts. This insn only does variable extract from a 20102 register. 20103 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn, 20104 do variable extract from memory. 20105 201062020-02-27 Martin Jambor <mjambor@suse.cz> 20107 Feng Xue <fxue@os.amperecomputing.com> 20108 20109 PR ipa/93707 20110 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with 20111 new function calls_same_node_or_its_all_contexts_clone_p. 20112 (cgraph_edge_brings_value_p): Use it. 20113 (cgraph_edge_brings_value_p): Likewise. 20114 (self_recursive_pass_through_p): Return false if caller is a clone. 20115 (self_recursive_agg_pass_through_p): Likewise. 20116 201172020-02-27 Jan Hubicka <hubicka@ucw.cz> 20118 20119 PR middle-end/92152 20120 * alias.c (ends_tbaa_access_path_p): Break out from ... 20121 (component_uses_parent_alias_set_from): ... here. 20122 * alias.h (ends_tbaa_access_path_p): Declare. 20123 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...; 20124 handle trailing arrays past end of tbaa access path. 20125 (aliasing_component_refs_p): ... here; likewise. 20126 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access 20127 path; disambiguate also past end of it. 20128 (nonoverlapping_component_refs_p): Use only TBAA segment of the access 20129 path. 20130 201312020-02-27 Mihail Ionescu <mihail.ionescu@arm.com> 20132 20133 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the 20134 beginning of the file. 20135 (vcreate_bf16, vcombine_bf16): New. 20136 (vdup_n_bf16, vdupq_n_bf16): New. 20137 (vdup_lane_bf16, vdup_laneq_bf16): New. 20138 (vdupq_lane_bf16, vdupq_laneq_bf16): New. 20139 (vduph_lane_bf16, vduph_laneq_bf16): New. 20140 (vset_lane_bf16, vsetq_lane_bf16): New. 20141 (vget_lane_bf16, vgetq_lane_bf16): New. 20142 (vget_high_bf16, vget_low_bf16): New. 20143 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. 20144 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. 20145 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. 20146 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. 20147 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. 20148 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. 20149 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. 20150 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. 20151 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. 20152 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. 20153 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New. 20154 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. 20155 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. 20156 (vreinterpretq_bf16_p128): New. 20157 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. 20158 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. 20159 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. 20160 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. 20161 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. 20162 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. 20163 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. 20164 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. 20165 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. 20166 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. 20167 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. 20168 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. 20169 (vreinterpretq_p128_bf16): New. 20170 * config/arm/arm_neon_builtins.def (VDX): Add V4BF. 20171 (V_elem): Likewise. 20172 (V_elem_l): Likewise. 20173 (VD_LANE): Likewise. 20174 (VQX) Add V8BF. 20175 (V_DOUBLE): Likewise. 20176 (VDQX): Add V4BF and V8BF. 20177 (V_two_elem, V_three_elem, V_four_elem): Likewise. 20178 (V_reg): Likewise. 20179 (V_HALF): Likewise. 20180 (V_double_vector_mode): Likewise. 20181 (V_cmp_result): Likewise. 20182 (V_uf_sclr): Likewise. 20183 (V_sz_elem): Likewise. 20184 (Is_d_reg): Likewise. 20185 (V_mode_nunits): Likewise. 20186 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16. 20187 201882020-02-27 Andrew Stubbs <ams@codesourcery.com> 20189 20190 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator. 20191 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE. 20192 (<expander><mode>3<exec>): Likewise. 20193 (<expander><mode>3): New. 20194 (v<expander><mode>3): New. 20195 (<expander><mode>3): New. 20196 (<expander><mode>3<exec>): Rename to ... 20197 (<expander>v64si3<exec>): ... this, and change modes to V64SI. 20198 * config/gcn/gcn.md (mnemonic): Use '%B' for not. 20199 202002020-02-27 Alexandre Oliva <oliva@adacore.com> 20201 20202 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave 20203 them alone on vx7. 20204 202052020-02-27 Richard Biener <rguenther@suse.de> 20206 20207 PR tree-optimization/93508 20208 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like 20209 non-_CHK variants. Valueize their length arguments. 20210 202112020-02-27 Richard Biener <rguenther@suse.de> 20212 20213 PR tree-optimization/93953 20214 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference 20215 to the hash-map entry. 20216 202172020-02-27 Andrew Stubbs <ams@codesourcery.com> 20218 20219 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs. 20220 202212020-02-27 Mark Williams <mwilliams@fb.com> 20222 20223 * dwarf2out.c (file_name_acquire): Call remap_debug_filename. 20224 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map, 20225 -ffile-prefix-map and -fmacro-prefix-map. 20226 * lto-streamer-out.c: Include file-prefix-map.h. 20227 (lto_output_location): Remap the file part of locations. 20228 202292020-02-27 Jakub Jelinek <jakub@redhat.com> 20230 20231 PR c/93949 20232 * gimplify.c (gimplify_init_constructor): Don't promote readonly 20233 DECL_REGISTER variables to TREE_STATIC. 20234 20235 PR tree-optimization/93582 20236 PR tree-optimization/93945 20237 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with 20238 non-zero INTEGER_CST second argument and ref->offset or ref->size 20239 not a multiple of BITS_PER_UNIT. 20240 202412020-02-27 Jonathan Wakely <jwakely@redhat.com> 20242 20243 * doc/install.texi (Binaries): Update description of BullFreeware. 20244 202452020-02-26 Sandra Loosemore <sandra@codesourcery.com> 20246 20247 PR c++/90467 20248 20249 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in 20250 C++ Language Options, Warning Options, and Static Analyzer 20251 Options lists. Document negative form of options enabled by 20252 default. Move some things around to more accurately sort 20253 warnings by category. 20254 (C++ Dialect Options, Warning Options, Static Analyzer 20255 Options): Document negative form of options when enabled by 20256 default. Move some things around to more accurately sort 20257 warnings by category. Add some missing index entries. 20258 Light copy-editing. 20259 202602020-02-26 Carl Love <cel@us.ibm.com> 20261 20262 PR target/91276 20263 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on 20264 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only 20265 for the vector unsigned short arguments. It is also listed as the 20266 name of the built-in for arguments vector unsigned short, 20267 vector unsigned int and vector unsigned long long built-ins. The 20268 name of the builtins for these arguments should be: 20269 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and 20270 __builtin_crypto_vpmsumd respectively. 20271 202722020-02-26 Richard Biener <rguenther@suse.de> 20273 20274 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count 20275 and load permutation. 20276 202772020-02-26 Richard Sandiford <richard.sandiford@arm.com> 20278 20279 PR middle-end/93843 20280 * optabs-tree.c (supportable_convert_operation): Reject types with 20281 scalar modes. 20282 202832020-02-26 David Malcolm <dmalcolm@redhat.com> 20284 20285 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o. 20286 202872020-02-26 Jakub Jelinek <jakub@redhat.com> 20288 20289 PR tree-optimization/93820 20290 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE 20291 argument to ALL_INTEGER_CST_P boolean. 20292 (imm_store_chain_info::try_coalesce_bswap): Adjust caller. 20293 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle 20294 adjacent INTEGER_CST store into merged_store->only_constants like 20295 overlapping one. 20296 202972020-02-25 Jakub Jelinek <jakub@redhat.com> 20298 20299 PR other/93912 20300 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity 20301 -> probability. 20302 * cfghooks.c (verify_flow_info): Likewise. 20303 * predict.c (combine_predictions_for_bb): Likewise. 20304 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo, 20305 sucessor -> successor. 20306 (find_traces_1_round): Fix comment typo, destinarion -> destination. 20307 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors -> 20308 successors. 20309 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump 20310 message typo, sucessors -> successors. 20311 203122020-02-25 Martin Sebor <msebor@redhat.com> 20313 20314 * doc/extend.texi (attribute access): Correct an example. 20315 203162020-02-25 Mihail Ionescu <mihail.ionescu@arm.com> 20317 20318 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types): 20319 Add simd_bf. 20320 (aarch64_init_simd_builtin_scalar_types): Register simd_bf. 20321 (VAR15, VAR16): New. 20322 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF. 20323 (VD): Enable for V4BF. 20324 (VDC): Likewise. 20325 (VQ): Enable for V8BF. 20326 (VQ2): Likewise. 20327 (VQ_NO2E): Likewise. 20328 (VDBL, Vdbl): Add V4BF. 20329 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF. 20330 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef. 20331 (bfloat16x8x2_t): Likewise. 20332 (bfloat16x4x3_t): Likewise. 20333 (bfloat16x8x3_t): Likewise. 20334 (bfloat16x4x4_t): Likewise. 20335 (bfloat16x8x4_t): Likewise. 20336 (vcombine_bf16): New. 20337 (vld1_bf16, vld1_bf16_x2): New. 20338 (vld1_bf16_x3, vld1_bf16_x4): New. 20339 (vld1q_bf16, vld1q_bf16_x2): New. 20340 (vld1q_bf16_x3, vld1q_bf16_x4): New. 20341 (vld1_lane_bf16): New. 20342 (vld1q_lane_bf16): New. 20343 (vld1_dup_bf16): New. 20344 (vld1q_dup_bf16): New. 20345 (vld2_bf16): New. 20346 (vld2q_bf16): New. 20347 (vld2_dup_bf16): New. 20348 (vld2q_dup_bf16): New. 20349 (vld3_bf16): New. 20350 (vld3q_bf16): New. 20351 (vld3_dup_bf16): New. 20352 (vld3q_dup_bf16): New. 20353 (vld4_bf16): New. 20354 (vld4q_bf16): New. 20355 (vld4_dup_bf16): New. 20356 (vld4q_dup_bf16): New. 20357 (vst1_bf16, vst1_bf16_x2): New. 20358 (vst1_bf16_x3, vst1_bf16_x4): New. 20359 (vst1q_bf16, vst1q_bf16_x2): New. 20360 (vst1q_bf16_x3, vst1q_bf16_x4): New. 20361 (vst1_lane_bf16): New. 20362 (vst1q_lane_bf16): New. 20363 (vst2_bf16): New. 20364 (vst2q_bf16): New. 20365 (vst3_bf16): New. 20366 (vst3q_bf16): New. 20367 (vst4_bf16): New. 20368 (vst4q_bf16): New. 20369 203702020-02-25 Mihail Ionescu <mihail.ionescu@arm.com> 20371 20372 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF. 20373 (VALL_F16): Likewise. 20374 (VALLDI_F16): Likewise. 20375 (Vtype): Likewise. 20376 (Vetype): Likewise. 20377 (vswap_width_name): Likewise. 20378 (VSWAP_WIDTH): Likewise. 20379 (Vel): Likewise. 20380 (VEL): Likewise. 20381 (q): Likewise. 20382 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New. 20383 (vget_lane_bf16, vgetq_lane_bf16): New. 20384 (vcreate_bf16): New. 20385 (vdup_n_bf16, vdupq_n_bf16): New. 20386 (vdup_lane_bf16, vdup_laneq_bf16): New. 20387 (vdupq_lane_bf16, vdupq_laneq_bf16): New. 20388 (vduph_lane_bf16, vduph_laneq_bf16): New. 20389 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. 20390 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. 20391 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. 20392 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. 20393 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. 20394 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. 20395 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. 20396 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. 20397 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. 20398 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. 20399 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New 20400 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New 20401 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. 20402 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. 20403 (vreinterpretq_bf16_p128): New. 20404 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. 20405 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. 20406 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. 20407 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. 20408 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. 20409 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. 20410 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. 20411 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. 20412 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. 20413 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. 20414 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. 20415 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. 20416 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New. 20417 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New. 20418 (vreinterpretq_p128_bf16): New. 20419 204202020-02-25 Dennis Zhang <dennis.zhang@arm.com> 20421 20422 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New 20423 (vbfdot_lane_f32, vbfdotq_laneq_f32): New. 20424 (vbfdot_laneq_f32, vbfdotq_lane_f32): New. 20425 * config/arm/arm_neon_builtins.def (vbfdot): New entry. 20426 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise. 20427 * config/arm/iterators.md (VSF2BF): New attribute. 20428 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry. 20429 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise. 20430 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise. 20431 204322020-02-25 Christophe Lyon <christophe.lyon@linaro.org> 20433 20434 * config/arm/arm.md (required_for_purecode): New attribute. 20435 (enabled): Handle required_for_purecode. 20436 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to 20437 work with -mpure-code. 20438 204392020-02-25 Jakub Jelinek <jakub@redhat.com> 20440 20441 PR rtl-optimization/93908 20442 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src 20443 with mask. 20444 204452019-02-25 Eric Botcazou <ebotcazou@adacore.com> 20446 20447 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode. 20448 204492020-02-25 Roman Zhuykov <zhroma@ispras.ru> 20450 20451 * doc/install.texi (--enable-checking): Adjust wording. 20452 204532020-02-25 Richard Biener <rguenther@suse.de> 20454 20455 PR tree-optimization/93868 20456 * tree-vect-slp.c (slp_copy_subtree): New function. 20457 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before 20458 re-arranging stmts in it. 20459 204602020-02-25 Jakub Jelinek <jakub@redhat.com> 20461 20462 PR middle-end/93874 20463 * passes.c (pass_manager::dump_passes): Create a cgraph node for the 20464 dummy function and remove it at the end. 20465 20466 PR translation/93864 20467 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo 20468 paramter -> parameter. 20469 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise. 20470 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise. 20471 204722020-02-24 Roman Zhuykov <zhroma@ispras.ru> 20473 20474 * doc/install.texi (--enable-checking): Properly document current 20475 behavior. 20476 (--enable-stage1-checking): Minor clarification about bootstrap. 20477 204782020-02-24 David Malcolm <dmalcolm@redhat.com> 20479 20480 PR analyzer/93032 20481 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that 20482 -fanalyzer-checker=taint is also required. 20483 (-fanalyzer-checker=): Note that providing this option enables the 20484 given checker, and doing so may be required for checkers that are 20485 disabled by default. 20486 204872020-02-24 David Malcolm <dmalcolm@redhat.com> 20488 20489 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows 20490 significant control flow events; add a "3" which shows all 20491 control flow events; the old "3" becomes "4". 20492 204932020-02-24 Jakub Jelinek <jakub@redhat.com> 20494 20495 PR tree-optimization/93582 20496 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider 20497 pd.offset and pd.size to be counted in bits rather than bytes, add 20498 support for maxsizei that is not a multiple of BITS_PER_UNIT and 20499 handle bitfield stores and loads. 20500 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with 20501 uncomparable quantities - bytes vs. bits. Allow push_partial_def 20502 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust 20503 pd.offset/pd.size to be counted in bits rather than bytes. 20504 Formatting fix. Rename shadowed len variable to buflen. 20505 205062020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> 20507 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org> 20508 20509 PR driver/47785 20510 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function. 20511 (driver::main): Call putenv_COLLECT_AS_OPTIONS. 20512 * opts-common.c (parse_options_from_collect_gcc_options): New function. 20513 (prepend_xassembler_to_collect_as_options): Likewise. 20514 * opts.h (parse_options_from_collect_gcc_options): Declare prototype. 20515 (prepend_xassembler_to_collect_as_options): Likewise. 20516 * lto-opts.c (lto_write_options): Stream assembler options 20517 in COLLECT_AS_OPTIONS. 20518 * lto-wrapper.c (xassembler_options_error): New static variable. 20519 (get_options_from_collect_gcc_options): Move parsing options code to 20520 parse_options_from_collect_gcc_options and call it. 20521 (merge_and_complain): Validate -Xassembler options. 20522 (append_compiler_options): Handle OPT_Xassembler. 20523 (run_gcc): Append command line -Xassembler options to 20524 collect_gcc_options. 20525 * doc/invoke.texi: Add documentation about using Xassembler 20526 options with LTO. 20527 205282020-02-24 Kito Cheng <kito.cheng@sifive.com> 20529 20530 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen 20531 for LTGT. 20532 (riscv_rtx_costs): Update cost model for LTGT. 20533 205342020-02-23 Vladimir Makarov <vmakarov@redhat.com> 20535 20536 PR rtl-optimization/93564 20537 * ira-color.c (struct update_cost_queue_elem): New member start. 20538 (queue_update_cost, get_next_update_cost): Add new arg start. 20539 (allocnos_conflict_p): New function. 20540 (update_costs_from_allocno): Add new arg conflict_cost_update_p. 20541 Add checking conflicts with allocnos_conflict_p. 20542 (update_costs_from_prefs, restore_costs_from_copies): Adjust 20543 update_costs_from_allocno calls. 20544 (update_conflict_hard_regno_costs): Add checking conflicts with 20545 allocnos_conflict_p. Adjust calls of queue_update_cost and 20546 get_next_update_cost. 20547 (assign_hard_reg): Adjust calls of queue_update_cost. Add 20548 debugging print. 20549 (bucket_allocno_compare_func): Restore previous version. 20550 205512020-02-21 John David Anglin <danglin@gcc.gnu.org> 20552 20553 * gcc/config/pa/pa.c (pa_function_value): Fix check for word and 20554 double-word size when handling aggregate return values. 20555 * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate 20556 that homogeneous SFmode and DFmode aggregates are passed and returned 20557 in general registers. 20558 205592020-02-21 Jakub Jelinek <jakub@redhat.com> 20560 20561 PR translation/93759 20562 * opts.c (print_filtered_help): Translate help before appending 20563 messages to it rather than after that. 20564 205652020-02-19 Richard Sandiford <richard.sandiford@arm.com> 20566 20567 PR rtl-optimization/PR92989 20568 * lra-lives.c (process_bb_lives): Restore the original order 20569 of the bb liveness update. Call make_hard_regno_dead for each 20570 register clobbered at the start of an EH receiver. 20571 205722020-02-18 Feng Xue <fxue@os.amperecomputing.com> 20573 20574 PR ipa/93763 20575 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as 20576 self-recursively generated. 20577 205782020-02-21 Iain Sandoe <iain@sandoe.co.uk> 20579 20580 PR target/93860 20581 * config/darwin-c.c (pop_field_alignment): Adjust quoting of 20582 error string. 20583 205842020-02-21 Mihail Ionescu <mihail.ionescu@arm.com> 20585 20586 * doc/sourcebuild.texi (arm_v8_1m_mve_ok): 20587 Document new target supports option. 20588 205892020-02-21 Dennis Zhang <dennis.zhang@arm.com> 20590 20591 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New. 20592 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New. 20593 * config/arm/iterators.md (MATMUL): New iterator. 20594 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US. 20595 (mmla_sfx): New attribute. 20596 * config/arm/neon.md (neon_<sup>mmlav16qi): New. 20597 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New. 20598 (UNSPEC_MATMUL_US): New. 20599 206002020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 20601 20602 * config/arm/arm.md: Prevent scalar shifts from being used when big 20603 endian is enabled. 20604 206052020-02-21 Jan Hubicka <hubicka@ucw.cz> 20606 Richard Biener <rguenther@suse.de> 20607 20608 PR tree-optimization/93586 20609 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk 20610 after mismatched array refs; do not sure type size information to 20611 recover from unmatched referneces with !flag_strict_aliasing_p. 20612 206132020-02-21 Andrew Stubbs <ams@codesourcery.com> 20614 20615 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ... 20616 (gather_load<mode>v64si): ... this and set operand 2 to V64SI. 20617 (scatter_store<mode>): Rename to ... 20618 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI. 20619 (scatter<mode>_exec): Delete. Move contents ... 20620 (mask_scatter_store<mode>): ... here, and rename that to ... 20621 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI. 20622 Remove mode conversion. 20623 (mask_gather_load<mode>): Rename to ... 20624 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI. 20625 Remove mode conversion. 20626 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion. 20627 206282020-02-21 Martin Jambor <mjambor@suse.cz> 20629 20630 PR tree-optimization/93845 20631 * tree-sra.c (verify_sra_access_forest): Only test access size of 20632 scalar types. 20633 206342020-02-21 Andrew Stubbs <ams@codesourcery.com> 20635 20636 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs. 20637 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber. 20638 (addv64di3_exec): Likewise. 20639 (subv64di3): Likewise. 20640 (subv64di3_exec): Likewise. 20641 (addv64di3_zext): Likewise. 20642 (addv64di3_zext_exec): Likewise. 20643 (addv64di3_zext_dup): Likewise. 20644 (addv64di3_zext_dup_exec): Likewise. 20645 (addv64di3_zext_dup2): Likewise. 20646 (addv64di3_zext_dup2_exec): Likewise. 20647 (addv64di3_sext_dup2): Likewise. 20648 (addv64di3_sext_dup2_exec): Likewise. 20649 (<expander>v64di3): Likewise. 20650 (<expander>v64di3_exec): Likewise. 20651 (*<reduc_op>_dpp_shr_v64di): Likewise. 20652 (*plus_carry_dpp_shr_v64di): Likewise. 20653 * config/gcn/gcn.md (adddi3): Likewise. 20654 (addptrdi3): Likewise. 20655 (<expander>di3): Likewise. 20656 206572020-02-21 Andrew Stubbs <ams@codesourcery.com> 20658 20659 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di. 20660 206612020-02-21 Richard Sandiford <richard.sandiford@arm.com> 20662 20663 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE 20664 support. Use aarch64_emit_mult instead of emitting multiplication 20665 instructions directly. 20666 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2) 20667 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders. 20668 206692020-02-21 Richard Sandiford <richard.sandiford@arm.com> 20670 20671 * config/aarch64/aarch64.c (aarch64_emit_mult): New function. 20672 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult 20673 instead of emitting multiplication instructions directly. 20674 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator. 20675 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>) 20676 (@aarch64_frecps<mode>): New expanders. 20677 206782020-02-21 Richard Sandiford <richard.sandiford@arm.com> 20679 20680 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate 20681 on and produce uint64_ts rather than ints. 20682 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts. 20683 (cpu_approx_modes): Change the fields from unsigned int to uint64_t. 20684 206852020-02-21 Richard Sandiford <richard.sandiford@arm.com> 20686 20687 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create 20688 an unused xmsk register when handling approximate rsqrt. 20689 206902020-02-21 Richard Sandiford <richard.sandiford@arm.com> 20691 20692 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted 20693 flag_finite_math_only condition. 20694 206952020-02-20 Uroš Bizjak <ubizjak@gmail.com> 20696 20697 PR target/93828 20698 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand 20699 to destination operand for shufps alternative. 20700 (*vec_extractv2si_1): Ditto. 20701 207022020-02-20 Peter Bergner <bergner@linux.ibm.com> 20703 20704 PR target/93658 20705 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX 20706 vector modes. 20707 207082020-02-20 Martin Liska <mliska@suse.cz> 20709 20710 PR translation/93831 20711 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode. 20712 207132020-02-20 Martin Liska <mliska@suse.cz> 20714 20715 PR translation/93830 20716 * common/config/avr/avr-common.c: Remote trailing "|". 20717 207182020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de> 20719 20720 * collect2.c (maybe_run_lto_and_relink): Fix typo in 20721 comment. 20722 207232020-02-19 Richard Sandiford <richard.sandiford@arm.com> 20724 20725 PR tree-optimization/93767 20726 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the 20727 access-size bias from the offset calculations for negative strides. 20728 207292020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de> 20730 20731 * collect2.c (c_file, o_file): Make const again. 20732 (ldout,lderrout, dump_ld_file): Remove. 20733 (tool_cleanup): Avoid calling not signal-safe functions. 20734 (maybe_run_lto_and_relink): Avoid possible signal handler 20735 access to unintialzed memory (lto_o_files). 20736 (main): Avoid leaking temp files in $TMPDIR. 20737 Initialize c_file/o_file with concat, which avoids exposing 20738 uninitialized memory to signal handler, which calls unlink(!). 20739 Avoid calling maybe_unlink when the main function returns, 20740 since the atexit handler is already doing this. 20741 * collect2.h (dump_ld_file, ldout, lderrout): Remove. 20742 207432020-02-19 Martin Jambor <mjambor@suse.cz> 20744 20745 PR tree-optimization/93776 20746 * tree-sra.c (create_access): Do not create zero size accesses. 20747 (get_access_for_expr): Do not search for zero sized accesses. 20748 207492020-02-19 Martin Jambor <mjambor@suse.cz> 20750 20751 PR tree-optimization/93667 20752 * tree-sra.c (scalarizable_type_p): Return false if record fields 20753 do not follow wach other. 20754 207552020-01-21 Kito Cheng <kito.cheng@sifive.com> 20756 20757 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x 20758 rather than fmv.x.s/fmv.s.x. 20759 207602020-02-18 James Greenhalgh <james.greenhalgh@arm.com> 20761 20762 * config/aarch64/aarch64-simd-builtins.def 20763 (intrinsic_vec_smult_lo_): New. 20764 (intrinsic_vec_umult_lo_): Likewise. 20765 (vec_widen_smult_hi_): Likewise. 20766 (vec_widen_umult_hi_): Likewise. 20767 * config/aarch64/aarch64-simd.md 20768 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New. 20769 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics. 20770 (vmull_high_s16): Likewise. 20771 (vmull_high_s32): Likewise. 20772 (vmull_high_u8): Likewise. 20773 (vmull_high_u16): Likewise. 20774 (vmull_high_u32): Likewise. 20775 (vmull_s8): Likewise. 20776 (vmull_s16): Likewise. 20777 (vmull_s32): Likewise. 20778 (vmull_u8): Likewise. 20779 (vmull_u16): Likewise. 20780 (vmull_u32): Likewise. 20781 207822020-02-18 Martin Liska <mliska@suse.cz> 20783 20784 * value-prof.c (stream_out_histogram_value): Restore LTO PGO 20785 bootstrap by missing removal of invalid sanity check. 20786 207872020-02-18 Martin Liska <mliska@suse.cz> 20788 20789 PR ipa/92518 20790 * ipa-icf-gimple.c (func_checker::compare_gimple_assign): 20791 Always compare LHS of gimple_assign. 20792 207932020-02-18 Martin Liska <mliska@suse.cz> 20794 20795 PR ipa/93583 20796 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute 20797 and return type of functions. 20798 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl): 20799 Drop MALLOC attribute for void functions. 20800 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop 20801 malloc_state for a new VOID clone. 20802 208032020-02-18 Martin Liska <mliska@suse.cz> 20804 20805 PR ipa/92924 20806 * common.opt: Add -fprofile-reproducibility. 20807 * doc/invoke.texi: Document it. 20808 * value-prof.c (dump_histogram_value): 20809 Document and support behavior for counters[0] 20810 being a negative value. 20811 (get_nth_most_common_value): Handle negative 20812 counters[0] in respect to flag_profile_reproducible. 20813 208142020-02-18 Jakub Jelinek <jakub@redhat.com> 20815 20816 PR ipa/93797 20817 * cgraph.c (verify_speculative_call): Use speculative_id instead of 20818 speculative_uid in messages. Remove trailing whitespace from error 20819 message. Use num_speculative_call_targets instead of 20820 num_speculative_targets in a message. 20821 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in 20822 edge messages and stmt instead of cal_stmt in reference message. 20823 20824 PR tree-optimization/93780 20825 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p 20826 before calling build_vector_type. 20827 (execute_update_addresses_taken): Likewise. 20828 20829 PR driver/93796 20830 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help 20831 typo, functoin -> function. 20832 * tree.c (free_lang_data_in_decl): Fix comment typo, 20833 functoin -> function. 20834 * ipa-visibility.c (cgraph_externally_visible_p): Likewise. 20835 208362020-02-17 David Malcolm <dmalcolm@redhat.com> 20837 20838 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs 20839 won't be printed. 20840 (print_option_information): Don't call get_option_url if URLs 20841 won't be printed. 20842 208432020-02-17 Alexandre Oliva <oliva@adacore.com> 20844 20845 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete 20846 handling of register_common-less targets. 20847 208482020-02-17 Martin Liska <mliska@suse.cz> 20849 20850 PR ipa/93760 20851 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar. 20852 208532020-02-17 Martin Liska <mliska@suse.cz> 20854 20855 PR translation/93755 20856 * config/rs6000/rs6000.c (rs6000_option_override_internal): 20857 Fix double quotes. 20858 208592020-02-17 Martin Liska <mliska@suse.cz> 20860 20861 PR other/93756 20862 * config/rx/elf.opt: Fix typo. 20863 208642020-02-17 Richard Biener <rguenther@suse.de> 20865 20866 PR c/86134 20867 * opts-global.c (print_ignored_options): Use inform and 20868 amend message. 20869 208702020-02-17 Jiufu Guo <guojiufu@linux.ibm.com> 20871 20872 PR target/93047 20873 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber. 20874 208752020-02-16 Uroš Bizjak <ubizjak@gmail.com> 20876 20877 PR target/93743 20878 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2. 20879 (atan2<mode>3): Update operand order in the call to gen_atan2xf3. 20880 208812020-02-15 Jason Merrill <jason@redhat.com> 20882 20883 * doc/invoke.texi (C Dialect Options): Add -std=c++20. 20884 208852020-02-15 Jakub Jelinek <jakub@redhat.com> 20886 20887 PR tree-optimization/93744 20888 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0, 20889 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A, 20890 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make 20891 sure @2 in the first and @1 in the other patterns has no side-effects. 20892 208932020-02-15 David Malcolm <dmalcolm@redhat.com> 20894 Bernd Edlinger <bernd.edlinger@hotmail.de> 20895 20896 PR 87488 20897 PR other/93168 20898 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define. 20899 * configure.ac (--with-diagnostics-urls): New configuration 20900 option, based on --with-diagnostics-color. 20901 (DIAGNOSTICS_URLS_DEFAULT): New define. 20902 * config.h: Regenerate. 20903 * configure: Regenerate. 20904 * diagnostic.c (diagnostic_urls_init): Handle -1 for 20905 DIAGNOSTICS_URLS_DEFAULT from configure-time 20906 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS 20907 and TERM_URLS environment variable. 20908 * diagnostic-url.h (diagnostic_url_format): New enum type. 20909 (diagnostic_urls_enabled_p): rename to... 20910 (determine_url_format): ... this, and change return type. 20911 * diagnostic-color.c (parse_env_vars_for_urls): New helper function. 20912 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal, 20913 the linux console, and mingw. 20914 (diagnostic_urls_enabled_p): rename to... 20915 (determine_url_format): ... this, and adjust. 20916 * pretty-print.h (pretty_printer::show_urls): rename to... 20917 (pretty_printer::url_format): ... this, and change to enum. 20918 * pretty-print.c (pretty_printer::pretty_printer, 20919 pp_begin_url, pp_end_url, test_urls): Adjust. 20920 * doc/install.texi (--with-diagnostics-urls): Document the new 20921 configuration option. 20922 (--with-diagnostics-color): Document the existing interaction 20923 with GCC_COLORS better. 20924 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS 20925 vindex reference. Update description of defaults based on the above. 20926 (-fdiagnostics-color): Update description of how -fdiagnostics-color 20927 interacts with GCC_COLORS. 20928 209292020-02-14 Eric Botcazou <ebotcazou@adacore.com> 20930 20931 PR target/93704 20932 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in 20933 conjunction with TARGET_GNU_TLS in early return. 20934 209352020-02-14 Alexander Monakov <amonakov@ispras.ru> 20936 20937 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if 20938 the mode is not wider than UNITS_PER_WORD. 20939 209402020-02-14 Martin Jambor <mjambor@suse.cz> 20941 20942 PR tree-optimization/93516 20943 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create 20944 access of the same type as the parent. 20945 (propagate_subaccesses_from_lhs): Likewise. 20946 209472020-02-14 Hongtao Liu <hongtao.liu@intel.com> 20948 20949 PR target/93724 20950 * config/i386/avx512vbmi2intrin.h 20951 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16, 20952 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32, 20953 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32, 20954 _m512_shrdi_epi64, _m512_mask_shrdi_epi64, 20955 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16, 20956 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16, 20957 _mm512_shldi_epi32, _mm512_mask_shldi_epi32, 20958 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64, 20959 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo 20960 of lacking a closing parenthesis. 20961 * config/i386/avx512vbmi2vlintrin.h 20962 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16, 20963 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32, 20964 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32, 20965 _m256_shrdi_epi64, _m256_mask_shrdi_epi64, 20966 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16, 20967 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16, 20968 _mm256_shldi_epi32, _mm256_mask_shldi_epi32, 20969 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64, 20970 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64, 20971 _mm_shrdi_epi16, _mm_mask_shrdi_epi16, 20972 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32, 20973 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32, 20974 _mm_shrdi_epi64, _mm_mask_shrdi_epi64, 20975 _m_maskz_shrdi_epi64, _mm_shldi_epi16, 20976 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16, 20977 _mm_shldi_epi32, _mm_mask_shldi_epi32, 20978 _mm_maskz_shldi_epi32, _mm_shldi_epi64, 20979 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto. 20980 209812020-02-13 H.J. Lu <hongjiu.lu@intel.com> 20982 20983 PR target/93656 20984 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at 20985 the target function entry. 20986 209872020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 20988 20989 * common/config/arc/arc-common.c (arc_option_optimization_table): 20990 Disable if-conversion step when optimized for size. 20991 209922020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 20993 20994 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and 20995 R12-R15 are always in ARCOMPACT16_REGS register class. 20996 * config/arc/arc.opt (mq-class): Deprecate. 20997 * config/arc/constraint.md ("q"): Remove dependency on mq-class 20998 option. 20999 * doc/invoke.texi (mq-class): Update text. 21000 * common/config/arc/arc-common.c (arc_option_optimization_table): 21001 Update list. 21002 210032020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 21004 21005 * config/arc/arc.c (arc_insn_cost): New function. 21006 (TARGET_INSN_COST): Define. 21007 * config/arc/arc.md (cost): New attribute. 21008 (add_n): Use arc_nonmemory_operand. 21009 (ashlsi3_insn): Likewise, also update constraints. 21010 (ashrsi3_insn): Likewise. 21011 (rotrsi3): Likewise. 21012 (add_shift): Likewise. 21013 * config/arc/predicates.md (arc_nonmemory_operand): New predicate. 21014 210152020-02-13 Claudiu Zissulescu <claziss@synopsys.com> 21016 21017 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi 21018 registers. 21019 (umulsidi_600): Likewise. 21020 210212020-02-13 Jakub Jelinek <jakub@redhat.com> 21022 21023 PR target/93696 21024 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8, 21025 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8, 21026 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8, 21027 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W, 21028 pass __A to the builtin followed by __W instead of __A followed by 21029 __B. 21030 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32, 21031 _mm512_mask_popcnt_epi64): Likewise. 21032 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32, 21033 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64, 21034 _mm256_mask_popcnt_epi64): Likewise. 21035 21036 PR tree-optimization/93582 21037 * fold-const.h (shift_bytes_in_array_left, 21038 shift_bytes_in_array_right): Declare. 21039 * fold-const.c (shift_bytes_in_array_left, 21040 shift_bytes_in_array_right): New function, moved from 21041 gimple-ssa-store-merging.c, no longer static. 21042 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move 21043 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left. 21044 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c. 21045 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of 21046 shift_bytes_in_array. 21047 (verify_shift_bytes_in_array): Rename to ... 21048 (verify_shift_bytes_in_array_left): ... this. Use 21049 shift_bytes_in_array_left instead of shift_bytes_in_array. 21050 (store_merging_c_tests): Call verify_shift_bytes_in_array_left 21051 instead of verify_shift_bytes_in_array. 21052 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr 21053 / native_interpret_expr where the store covers all needed bits, 21054 punt on PDP-endian, otherwise allow all involved offsets and sizes 21055 not to be byte-aligned. 21056 21057 PR target/93673 21058 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and 21059 use const_0_to_255_operand predicate instead of immediate_operand. 21060 (avx512dq_fpclass<mode><mask_scalar_merge_name>, 21061 avx512dq_vmfpclass<mode><mask_scalar_merge_name>, 21062 vgf2p8affineinvqb_<mode><mask_name>, 21063 vgf2p8affineqb_<mode><mask_name>): Drop mode from 21064 const_0_to_255_operand predicated operands. 21065 210662020-02-12 Jeff Law <law@redhat.com> 21067 21068 * config/h8300/h8300.md (comparison shortening peepholes): Use 21069 a mode iterator to merge the HImode and SImode peepholes. 21070 210712020-02-12 Jakub Jelinek <jakub@redhat.com> 21072 21073 PR middle-end/93663 21074 * real.c (is_even): Make static. Function comment fix. 21075 (is_halfway_below): Make static, don't assert R is not inf/nan, 21076 instead return false for those. Small formatting fixes. 21077 210782020-02-12 Martin Sebor <msebor@redhat.com> 21079 21080 PR middle-end/93646 21081 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename... 21082 (handle_builtin_stxncpy_strncat): ...to this. Change first argument. 21083 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation. 21084 (strlen_check_and_optimize_call): Adjust callee name. 21085 210862020-02-12 Jeff Law <law@redhat.com> 21087 21088 * config/h8300/h8300.md (comparison shortening peepholes): Drop 21089 (and (xor)) variant. Combine other two into single peephole. 21090 210912020-02-12 Wilco Dijkstra <wdijkstr@arm.com> 21092 21093 PR rtl-optimization/93565 21094 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs. 21095 210962020-02-12 Wilco Dijkstra <wdijkstr@arm.com> 21097 21098 * config/aarch64/aarch64-simd.md 21099 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern. 21100 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of 21101 generating separate ADDV and zero_extend patterns. 21102 * config/aarch64/iterators.md (VDQV_E): New iterator. 21103 211042020-02-12 Jeff Law <law@redhat.com> 21105 21106 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns, 21107 expanders, splits, etc. 21108 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise. 21109 (stpcpy_internal_<mode>, stpcpy splitter): Likewise. 21110 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise. 21111 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function. 21112 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise 21113 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused 21114 function prototype. 21115 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise. 21116 211172020-02-12 Jakub Jelinek <jakub@redhat.com> 21118 21119 PR target/93670 21120 * config/i386/sse.md (VI48F_256_DQ): New mode iterator. 21121 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove 21122 TARGET_AVX512DQ from condition. 21123 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition> 21124 instead of <mask_mode512bit_condition> in condition. If 21125 TARGET_AVX512DQ is false, emit vextract*64x4 instead of 21126 vextract*32x8. 21127 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition> 21128 from condition. 21129 211302020-02-12 Kewen Lin <linkw@gcc.gnu.org> 21131 21132 PR target/91052 21133 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn. 21134 211352020-02-12 Segher Boessenkool <segher@kernel.crashing.org> 21136 21137 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof 21138 where strlen is more legible. 21139 (rs6000_builtin_vectorized_libmass): Ditto. 21140 (rs6000_print_options_internal): Ditto. 21141 211422020-02-11 Martin Sebor <msebor@redhat.com> 21143 21144 PR tree-optimization/93683 21145 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set. 21146 211472020-02-11 Michael Meissner <meissner@linux.ibm.com> 21148 21149 * config/rs6000/predicates.md (cint34_operand): Rename the 21150 -mprefixed-addr option to be -mprefixed. 21151 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename 21152 the -mprefixed-addr option to be -mprefixed. 21153 (OTHER_FUTURE_MASKS): Likewise. 21154 (POWERPC_MASKS): Likewise. 21155 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename 21156 the -mprefixed-addr option to be -mprefixed. Change error 21157 messages to refer to -mprefixed. 21158 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be 21159 -mprefixed. 21160 (rs6000_legitimate_offset_address_p): Likewise. 21161 (rs6000_mode_dependent_address): Likewise. 21162 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be 21163 "-mprefixed" for target attributes and pragmas. 21164 (address_to_insn_form): Rename the -mprefixed-addr option to be 21165 -mprefixed. 21166 (rs6000_adjust_insn_length): Likewise. 21167 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the 21168 -mprefixed-addr option to be -mprefixed. 21169 (ASM_OUTPUT_OPCODE): Likewise. 21170 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the 21171 -mprefixed-addr option to be -mprefixed. 21172 * config/rs6000/rs6000.opt (-mprefixed): Rename the 21173 -mprefixed-addr option to be prefixed. Change the option from 21174 being undocumented to being documented. 21175 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the 21176 -mprefixed option. Update the -mpcrel documentation to mention 21177 -mprefixed. 21178 211792020-02-11 Hans-Peter Nilsson <hp@axis.com> 21180 21181 * ira-conflicts.c (print_hard_reg_set): Correct output for sets 21182 including FIRST_PSEUDO_REGISTER - 1. 21183 * ira-color.c (print_hard_reg_set): Ditto. 21184 211852020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> 21186 21187 * config/arm/arm-builtins.c (enum arm_type_qualifiers): 21188 (USTERNOP_QUALIFIERS): New define. 21189 (USMAC_LANE_QUADTUP_QUALIFIERS): New define. 21190 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define. 21191 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX. 21192 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index. 21193 * config/arm/arm_neon.h (vusdot_s32): New. 21194 (vusdot_lane_s32): New. 21195 (vusdotq_lane_s32): New. 21196 (vsudot_lane_s32): New. 21197 (vsudotq_lane_s32): New. 21198 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New. 21199 * config/arm/iterators.md (DOTPROD_I8MM): New. 21200 (sup, opsuffix): Add <us/su>. 21201 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New. 21202 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New. 21203 212042020-02-11 Richard Biener <rguenther@suse.de> 21205 21206 PR tree-optimization/93661 21207 PR tree-optimization/93662 21208 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard 21209 tree_to_poly_int64. 21210 * tree-sra.c (get_access_for_expr): Likewise. 21211 212122020-02-10 Jakub Jelinek <jakub@redhat.com> 21213 21214 PR target/93637 21215 * config/i386/sse.md (VI_256_AVX2): New mode iterator. 21216 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256. 21217 Change condition from TARGET_AVX2 to TARGET_AVX. 21218 212192020-02-10 Iain Sandoe <iain@sandoe.co.uk> 21220 21221 PR other/93641 21222 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last 21223 argument of strncmp. 21224 212252020-02-10 Hans-Peter Nilsson <hp@axis.com> 21226 21227 Try to generate zero-based comparisons. 21228 * config/cris/cris.c (cris_reduce_compare): New function. 21229 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype. 21230 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4") 21231 (cstore<mode>4"): Apply cris_reduce_compare in expanders. 21232 212332020-02-10 Richard Earnshaw <rearnsha@arm.com> 21234 21235 PR target/91913 21236 * config/arm/arm.md (movsi_compare0): Allow SP as a source register 21237 in Thumb state and also as a destination in Arm state. Add T16 21238 variants. 21239 212402020-02-10 Hans-Peter Nilsson <hp@axis.com> 21241 21242 * md.texi (Define Subst): Match closing paren in example. 21243 212442020-02-10 Jakub Jelinek <jakub@redhat.com> 21245 21246 PR target/58218 21247 PR other/93641 21248 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last 21249 arguments of strncmp. 21250 212512020-02-10 Feng Xue <fxue@os.amperecomputing.com> 21252 21253 PR ipa/93203 21254 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge 21255 but different source value. 21256 (adjust_callers_for_value_intersection): New function. 21257 (gather_edges_for_value): Adjust order of callers to let a 21258 non-self-recursive caller be the first element. 21259 (self_recursive_pass_through_p): Add a new parameter "simple", and 21260 check generalized self-recursive pass-through jump function. 21261 (self_recursive_agg_pass_through_p): Likewise. 21262 (find_more_scalar_values_for_callers_subset): Compute value from 21263 pass-through jump function for self-recursive. 21264 (intersect_with_plats): Cleanup previous implementation code for value 21265 itersection with self-recursive call edge. 21266 (intersect_with_agg_replacements): Likewise. 21267 (intersect_aggregates_with_edge): Deduce value from pass-through jump 21268 function for self-recursive call edge. Cleanup previous implementation 21269 code for value intersection with self-recursive call edge. 21270 (decide_whether_version_node): Remove dead callers and adjust order 21271 to let a non-self-recursive caller be the first element. 21272 212732020-02-09 Uroš Bizjak <ubizjak@gmail.com> 21274 21275 * recog.c: Move pass_split_before_sched2 code in front of 21276 pass_split_before_regstack. 21277 (pass_data_split_before_sched2): Rename pass to split3 from split4. 21278 (pass_data_split_before_regstack): Rename pass to split4 from split3. 21279 (rest_of_handle_split_before_sched2): Remove. 21280 (pass_split_before_sched2::execute): Unconditionally call 21281 split_all_insns. 21282 (enable_split_before_sched2): New function. 21283 (pass_split_before_sched2::gate): Use enable_split_before_sched2. 21284 (pass_split_before_regstack::gate): Ditto. 21285 * config/nds32/nds32.c (nds32_split_double_word_load_store_p): 21286 Update name check for renamed split4 pass. 21287 * config/sh/sh.c (register_sh_passes): Update pass insertion 21288 point for renamed split4 pass. 21289 212902020-02-09 Jakub Jelinek <jakub@redhat.com> 21291 21292 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote 21293 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid 21294 copying them around between host and target. 21295 212962020-02-08 Andrew Pinski <apinski@marvell.com> 21297 21298 PR target/91927 21299 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check 21300 STRICT_ALIGNMENT also. 21301 213022020-02-08 Jim Wilson <jimw@sifive.com> 21303 21304 PR target/93532 21305 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define. 21306 213072020-02-08 Uroš Bizjak <ubizjak@gmail.com> 21308 Jakub Jelinek <jakub@redhat.com> 21309 21310 PR target/65782 21311 * config/i386/i386.h (CALL_USED_REGISTERS): Make 21312 xmm16-xmm31 call-used even in 64-bit ms-abi. 21313 213142020-02-07 Dennis Zhang <dennis.zhang@arm.com> 21315 21316 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry. 21317 (simd_ummla, simd_usmmla): Likewise. 21318 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New. 21319 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New. 21320 (vusmmlaq_s32): New. 21321 213222020-02-07 Richard Biener <rguenther@suse.de> 21323 21324 PR middle-end/93519 21325 * tree-inline.c (fold_marked_statements): Do a PRE walk, 21326 skipping unreachable regions. 21327 (optimize_inline_calls): Skip folding stmts when we didn't 21328 inline. 21329 213302020-02-07 H.J. Lu <hongjiu.lu@intel.com> 21331 21332 PR target/85667 21333 * config/i386/i386.c (function_arg_ms_64): Add a type argument. 21334 Don't return aggregates with only SFmode and DFmode in SSE 21335 register. 21336 (ix86_function_arg): Pass arg.type to function_arg_ms_64. 21337 213382020-02-07 Jakub Jelinek <jakub@redhat.com> 21339 21340 PR target/93122 21341 * config/rs6000/rs6000-logue.c 21342 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn, 21343 if it fails, move rs into end_addr and retry. Add 21344 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or 21345 the insn pattern doesn't describe well what exactly happens to 21346 dwarf2cfi.c. 21347 21348 PR target/93594 21349 * config/i386/predicates.md (avx_identity_operand): Remove. 21350 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove. 21351 (avx_<castmode><avxsizesuffix>_<castmode>, 21352 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to 21353 a VEC_CONCAT of the operand and UNSPEC_CAST. 21354 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to 21355 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with 21356 UNSPEC_CAST. 21357 21358 PR target/93611 21359 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear 21360 recog_data.insn if distance_non_agu_define changed it. 21361 213622020-02-06 Michael Meissner <meissner@linux.ibm.com> 21363 21364 PR target/93569 21365 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 21366 we only had X-FORM (reg+reg) addressing for vectors. Also before 21367 ISA 3.0, we only had X-FORM addressing for scalars in the 21368 traditional Altivec registers. 21369 213702020-02-06 <zhongyunde@huawei.com> 21371 Vladimir Makarov <vmakarov@redhat.com> 21372 21373 PR rtl-optimization/93561 21374 * lra-assigns.c (spill_for): Check that tested hard regno is not out of 21375 hard register range. 21376 213772020-02-06 Richard Sandiford <richard.sandiford@arm.com> 21378 21379 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type 21380 attribute. 21381 213822020-02-06 Segher Boessenkool <segher@kernel.crashing.org> 21383 21384 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case 21385 where the low and the high 32 bits are equal to each other specially, 21386 with an rldimi instruction. 21387 213882020-02-06 Mihail Ionescu <mihail.ionescu@arm.com> 21389 21390 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main. 21391 213922020-02-06 Mihail Ionescu <mihail.ionescu@arm.com> 21393 21394 * config/arm/arm-tables.opt: Regenerate. 21395 213962020-02-06 Richard Sandiford <richard.sandiford@arm.com> 21397 21398 PR target/87763 21399 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare. 21400 * config/aarch64/aarch64.c (aarch64_movk_shift): New function. 21401 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern. 21402 214032020-02-06 Richard Sandiford <richard.sandiford@arm.com> 21404 21405 PR rtl-optimization/87763 21406 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern. 21407 214082020-02-06 Delia Burduv <delia.burduv@arm.com> 21409 21410 * config/aarch64/aarch64-simd-builtins.def 21411 (bfmlaq): New built-in function. 21412 (bfmlalb): New built-in function. 21413 (bfmlalt): New built-in function. 21414 (bfmlalb_lane): New built-in function. 21415 (bfmlalt_lane): New built-in function. 21416 * config/aarch64/aarch64-simd.md 21417 (aarch64_bfmmlaqv4sf): New pattern. 21418 (aarch64_bfmlal<bt>v4sf): New pattern. 21419 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern. 21420 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic. 21421 (vbfmlalbq_f32): New intrinsic. 21422 (vbfmlaltq_f32): New intrinsic. 21423 (vbfmlalbq_lane_f32): New intrinsic. 21424 (vbfmlaltq_lane_f32): New intrinsic. 21425 (vbfmlalbq_laneq_f32): New intrinsic. 21426 (vbfmlaltq_laneq_f32): New intrinsic. 21427 * config/aarch64/iterators.md (BF_MLA): New int iterator. 21428 (bt): New int attribute. 21429 214302020-02-06 Uroš Bizjak <ubizjak@gmail.com> 21431 21432 * config/i386/i386.md (*pushtf): Emit "#" instead of 21433 calling gcc_unreachable in insn output. 21434 (*pushxf): Ditto. 21435 (*pushdf): Ditto. 21436 (*pushsf_rex64): Ditto for alternatives other than 1. 21437 (*pushsf): Ditto for alternatives other than 1. 21438 214392020-02-06 Martin Liska <mliska@suse.cz> 21440 21441 PR gcov-profile/91971 21442 PR gcov-profile/93466 21443 * coverage.c (coverage_init): Revert mangling of 21444 path into filename. It can lead to huge filename length. 21445 Creation of subfolders seem more natural. 21446 214472020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com> 21448 21449 PR target/93300 21450 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New. 21451 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs. 21452 Use arm_block_arith_comp_libfuncs_for_mode for HFmode. 21453 214542020-02-06 Jakub Jelinek <jakub@redhat.com> 21455 21456 PR target/93594 21457 * config/i386/predicates.md (avx_identity_operand): New predicate. 21458 * config/i386/sse.md (*avx_vec_concat<mode>_1): New 21459 define_insn_and_split. 21460 21461 PR libgomp/93515 21462 * omp-low.c (use_pointer_for_field): For nested constructs, also 21463 look for map clauses on target construct. 21464 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily 21465 taskreg_nesting_level. 21466 21467 PR libgomp/93515 21468 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding 21469 shared clause, call omp_notice_variable on outer context if any. 21470 214712020-02-05 Jason Merrill <jason@redhat.com> 21472 21473 PR c++/92003 21474 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has 21475 non-zero address even if weak and not yet defined. 21476 214772020-02-05 Martin Sebor <msebor@redhat.com> 21478 21479 PR tree-optimization/92765 21480 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL. 21481 * tree-ssa-strlen.c (compute_string_length): Remove. 21482 (determine_min_objsize): Remove. 21483 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic. 21484 Avoid using type size as the upper bound on string length. 21485 (handle_builtin_string_cmp): Add an argument. Adjust. 21486 (strlen_check_and_optimize_call): Pass additional argument to 21487 handle_builtin_string_cmp. 21488 214892020-02-05 Uroš Bizjak <ubizjak@gmail.com> 21490 21491 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove. 21492 (*pushdi2_rex64 peephole2): Unconditionally split after 21493 epilogue_completed. 21494 (*ashl<mode>3_doubleword): Ditto. 21495 (*<shift_insn><mode>3_doubleword): Ditto. 21496 214972020-02-05 Michael Meissner <meissner@linux.ibm.com> 21498 21499 PR target/93568 21500 * config/rs6000/rs6000.c (get_vector_offset): Fix 21501 215022020-02-05 Andrew Stubbs <ams@codesourcery.com> 21503 21504 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space. 21505 215062020-02-05 David Malcolm <dmalcolm@redhat.com> 21507 21508 * doc/analyzer.texi 21509 (Special Functions for Debugging the Analyzer): Update description 21510 of __analyzer_dump_exploded_nodes. 21511 215122020-02-05 Jakub Jelinek <jakub@redhat.com> 21513 21514 PR target/92190 21515 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only 21516 include sets and not clobbers in the vzeroupper pattern. 21517 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that 21518 the parallel has 17 (64-bit) or 9 (32-bit) elts. 21519 (*avx_vzeroupper_1): New define_insn_and_split. 21520 21521 PR target/92190 21522 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets, 21523 don't run when !optimize. 21524 (pass_split_before_regstack::gate): For STACK_REGS targets, run even 21525 when !optimize. 21526 215272020-02-05 Richard Biener <rguenther@suse.de> 21528 21529 PR middle-end/90648 21530 * genmatch.c (dt_node::gen_kids_1): Emit number of argument 21531 checks before matching calls. 21532 215332020-02-05 Jakub Jelinek <jakub@redhat.com> 21534 21535 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up 21536 function comment typo. 21537 21538 PR middle-end/93555 21539 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or 21540 simd_clone_create failed when i == 0, adjust clone->nargs by 21541 clone->inbranch. 21542 215432020-02-05 Martin Liska <mliska@suse.cz> 21544 21545 PR c++/92717 21546 * doc/invoke.texi: Document that one should 21547 not combine ASLR and -fpch. 21548 215492020-02-04 Richard Biener <rguenther@suse.de> 21550 21551 PR tree-optimization/93538 21552 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr. 21553 215542020-02-04 Richard Biener <rguenther@suse.de> 21555 21556 PR tree-optimization/91123 21557 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method. 21558 (vn_walk_cb_data::last_vuse): New member. 21559 (vn_walk_cb_data::saved_operands): Likewsie. 21560 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands. 21561 (vn_walk_cb_data::push_partial_def): Use finish. 21562 (vn_reference_lookup_2): Update last_vuse and use finish if 21563 we've saved operands. 21564 (vn_reference_lookup_3): Use finish and update calls to 21565 push_partial_defs everywhere. When translating through 21566 memcpy or aggregate copies save off operands and alias-set. 21567 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE 21568 operation for redundant store removal. 21569 215702020-02-04 Richard Biener <rguenther@suse.de> 21571 21572 PR tree-optimization/92819 21573 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid 21574 generating more stmts than before. 21575 215762020-02-04 Martin Liska <mliska@suse.cz> 21577 21578 * config/arm/arm.c (arm_gen_far_branch): Move the function 21579 outside of selftests. 21580 215812020-02-03 Michael Meissner <meissner@linux.ibm.com> 21582 21583 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper 21584 function to adjust PC-relative vector addresses. 21585 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to 21586 handle vectors with PC-relative addresses. 21587 215882020-02-03 Michael Meissner <meissner@linux.ibm.com> 21589 21590 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward 21591 reference. 21592 (hard_reg_and_mode_to_addr_mask): Delete. 21593 (rs6000_adjust_vec_address): If the original vector address 21594 was REG+REG or REG+OFFSET and the element is not zero, do the add 21595 of the elements in the original address before adding the offset 21596 for the vector element. Use address_to_insn_form to validate the 21597 address using the register being loaded, rather than guessing 21598 whether the address is a DS-FORM or DQ-FORM address. 21599 216002020-02-03 Michael Meissner <meissner@linux.ibm.com> 21601 21602 * config/rs6000/rs6000.c (get_vector_offset): New helper function 21603 to calculate the offset in memory from the start of a vector of a 21604 particular element. Add code to keep the element number in 21605 bounds if the element number is variable. 21606 (rs6000_adjust_vec_address): Move calculation of offset of the 21607 vector element to get_vector_offset. 21608 (rs6000_split_vec_extract_var): Do not do the initial AND of 21609 element here, move the code to get_vector_offset. 21610 216112020-02-03 Michael Meissner <meissner@linux.ibm.com> 21612 21613 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some 21614 gcc_asserts. 21615 216162020-02-03 Segher Boessenkool <segher@kernel.crashing.org> 21617 21618 * config/rs6000/constraints.md: Improve documentation. 21619 216202020-02-03 Richard Earnshaw <rearnsha@arm.com> 21621 21622 PR target/93548 21623 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md) 21624 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change. 21625 216262020-02-03 Andrew Stubbs <ams@codesourcery.com> 21627 21628 * config.gcc: Remove "carrizo" support. 21629 * config/gcn/gcn-opts.h (processor_type): Likewise. 21630 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise. 21631 * config/gcn/gcn.opt (gpu_type): Likewise. 21632 * config/gcn/t-omp-device: Likewise. 21633 216342020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com> 21635 21636 PR target/91816 21637 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype. 21638 * config/arm/arm.c (arm_gen_far_branch): New function 21639 arm_gen_far_branch. 21640 * config/arm/arm.md: Update b<cond> for Thumb2 range checks. 21641 216422020-02-03 Julian Brown <julian@codesourcery.com> 21643 Tobias Burnus <tobias@codesourcery.com> 21644 21645 * doc/invoke.texi: Update mention of OpenACC version to 2.6. 21646 216472020-02-03 Jakub Jelinek <jakub@redhat.com> 21648 21649 PR target/93533 21650 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit 21651 valid RTL to sum up the lowest and second lowest bytes of the popcnt 21652 result. 21653 216542020-02-02 Vladimir Makarov <vmakarov@redhat.com> 21655 21656 PR rtl-optimization/91333 21657 * ira-color.c (struct allocno_color_data): Add member 21658 hard_reg_prefs. 21659 (init_allocno_threads): Set the member up. 21660 (bucket_allocno_compare_func): Add compare hard reg 21661 prefs. 21662 216632020-01-31 Sandra Loosemore <sandra@codesourcery.com> 21664 21665 nios2: Support for GOT-relative DW_EH_PE_datarel encoding. 21666 21667 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION. 21668 * config.in: Regenerated. 21669 * configure: Regenerated. 21670 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling 21671 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION. 21672 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New. 21673 216742020-02-01 Andrew Burgess <andrew.burgess@embecosm.com> 21675 21676 * configure: Regenerate. 21677 216782020-01-31 Vladimir Makarov <vmakarov@redhat.com> 21679 21680 PR rtl-optimization/91333 21681 * ira-color.c (bucket_allocno_compare_func): Move conflict hard 21682 reg preferences comparison up. 21683 216842020-01-31 Richard Sandiford <richard.sandiford@arm.com> 21685 21686 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro. 21687 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to 21688 aarch64-sve-builtins-base.h. 21689 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to 21690 aarch64-sve-builtins-base.cc. 21691 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane) 21692 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 21693 (svcvtnt): Declare. 21694 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane) 21695 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 21696 (svcvtnt): New functions. 21697 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane) 21698 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) 21699 (svcvtnt): New functions. 21700 (svcvt): Add a form that converts f32 to bf16. 21701 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat) 21702 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n): 21703 Declare. 21704 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type): 21705 Treat B as bfloat16_t. 21706 (ternary_bfloat_lane_base): New class. 21707 (ternary_bfloat_def): Likewise. 21708 (ternary_bfloat): New shape. 21709 (ternary_bfloat_lane_def): New class. 21710 (ternary_bfloat_lane): New shape. 21711 (ternary_bfloat_lanex2_def): New class. 21712 (ternary_bfloat_lanex2): New shape. 21713 (ternary_bfloat_opt_n_def): New class. 21714 (ternary_bfloat_opt_n): New shape. 21715 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro. 21716 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf) 21717 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns. 21718 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>) 21719 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise. 21720 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise. 21721 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise. 21722 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key 21723 the pattern off the narrow mode instead of the wider one. 21724 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator. 21725 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs. 21726 (sve_fp_op): Handle them. 21727 (SVE_BFLOAT_TERNARY_LONG): New int itertor. 21728 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise. 21729 217302020-01-31 Richard Sandiford <richard.sandiford@arm.com> 21731 21732 * config/aarch64/arm_sve.h: Include arm_bf16.h. 21733 * config/aarch64/aarch64-modes.def (BF): Move definition before 21734 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF. 21735 (SVE_MODES): Handle BF modes. 21736 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle 21737 BF modes. 21738 (aarch64_full_sve_mode): Likewise. 21739 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF 21740 and VNx32BF. 21741 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF. 21742 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore) 21743 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count) 21744 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the 21745 new SVE BF modes. 21746 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New 21747 type_class_index. 21748 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro. 21749 (TYPES_all_data): Add bf16. 21750 (TYPES_reinterpret1, TYPES_reinterpret): Likewise. 21751 (register_tuple_type): Increase buffer size. 21752 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type. 21753 (bf16): New type suffix. 21754 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv) 21755 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax) 21756 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr): 21757 Change type from all_data to all_arith. 21758 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp) 21759 (svminp): Likewise. 21760 217612020-01-31 Dennis Zhang <dennis.zhang@arm.com> 21762 Matthew Malcomson <matthew.malcomson@arm.com> 21763 Richard Sandiford <richard.sandiford@arm.com> 21764 21765 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension. 21766 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define 21767 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and 21768 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define 21769 __ARM_FEATURE_MATMUL_FP64. 21770 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16) 21771 (sve): Add AARCH64_FL_F32MM to the list of extensions that should 21772 be disabled at the same time. 21773 (f32mm): New extension. 21774 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro. 21775 (AARCH64_FL_F64MM): Bump to the next bit up. 21776 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM) 21777 (TARGET_SVE_F64MM): New macros. 21778 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator. 21779 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL) 21780 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q) 21781 (UNSPEC_ZIP2Q): New unspeccs. 21782 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators. 21783 (optab, sur, perm_insn): Handle the new unspecs. 21784 (sve_fp_op): Handle UNSPEC_FMMLA. Resort. 21785 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use 21786 TARGET_SVE_F64MM instead of separate tests. 21787 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern. 21788 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise. 21789 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise. 21790 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise. 21791 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise. 21792 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro. 21793 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it. 21794 (TYPES_s_signed): New macro. 21795 (TYPES_s_integer): Use it. 21796 (TYPES_d_float): New macro. 21797 (TYPES_d_data): Use it. 21798 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare. 21799 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq) 21800 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise. 21801 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class. 21802 (svmmla): New shape. 21803 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3 21804 template parameters. 21805 (ternary_resize2_lane_base): Likewise. 21806 (ternary_resize2_base): New class. 21807 (ternary_qq_lane_base): Likewise. 21808 (ternary_intq_uintq_lane_def): Likewise. 21809 (ternary_intq_uintq_lane): New shape. 21810 (ternary_intq_uintq_opt_n_def): New class 21811 (ternary_intq_uintq_opt_n): New shape. 21812 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base. 21813 (ternary_uintq_intq_def): New class. 21814 (ternary_uintq_intq): New shape. 21815 (ternary_uintq_intq_lane_def): New class. 21816 (ternary_uintq_intq_lane): New shape. 21817 (ternary_uintq_intq_opt_n_def): New class. 21818 (ternary_uintq_intq_opt_n): New shape. 21819 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot) 21820 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla) 21821 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare. 21822 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl): 21823 Generalize to... 21824 (svdotprod_lane_impl): ...this new class. 21825 (svmmla_impl, svusdot_impl): New classes. 21826 (svdot_lane): Update to use svdotprod_lane_impl. 21827 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot) 21828 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New 21829 functions. 21830 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base 21831 function, with no types defined. 21832 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New 21833 AARCH64_FL_I8MM functions. 21834 (svmmla): New AARCH64_FL_F32MM function. 21835 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6. 21836 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New 21837 AARCH64_FL_F64MM function. 21838 (REQUIRED_EXTENSIONS): 21839 218402020-01-31 Andrew Stubbs <ams@codesourcery.com> 21841 21842 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each 21843 alternative only. 21844 218452020-01-31 Uroš Bizjak <ubizjak@gmail.com> 21846 21847 * config/i386/i386.md (*movoi_internal_avx): Do not check for 21848 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling. 21849 (*movti_internal): Do not check for 21850 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. 21851 (*movtf_internal): Move check for TARGET_SSE2 and size optimization 21852 just after check for TARGET_AVX. 21853 (*movdf_internal): Ditto. 21854 * config/i386/mmx.md (*mov<mode>_internal): Do not check for 21855 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. 21856 * config/i386/sse.md (mov<mode>_internal): Only check 21857 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check 21858 for TARGET_SSE2 and size optimization just after check for TARGET_AVX. 21859 (<sse>_andnot<mode>3<mask_name>): Move check for 21860 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX. 21861 (<code><mode>3<mask_name>): Ditto. 21862 (*andnot<mode>3): Ditto. 21863 (*andnottf3): Ditto. 21864 (*<code><mode>3): Ditto. 21865 (*<code>tf3): Ditto. 21866 (*andnot<VI:mode>3): Remove 21867 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling. 21868 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto. 21869 (*<code><VI12_AVX_AVX512F:mode>3): Ditto. 21870 (sse4_1_blendv<ssemodesuffix>): Ditto. 21871 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): 21872 Explain that tune applies to 128bit instructions only. 21873 218742020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com> 21875 21876 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count 21877 to definition of hsa_kernel_description. Parse assembly to find SGPR 21878 and VGPR count of kernel and store in hsa_kernel_description. 21879 218802020-01-31 Tamar Christina <tamar.christina@arm.com> 21881 21882 PR rtl-optimization/91838 21883 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case 21884 to truncate if allowed or reject combination. 21885 218862020-01-31 Andrew Stubbs <ams@codesourcery.com> 21887 21888 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step. 21889 (find_inv_vars_cb): Likewise. 21890 218912020-01-31 David Malcolm <dmalcolm@redhat.com> 21892 21893 * calls.c (special_function_p): Split out the check for DECL_NAME 21894 being non-NULL and fndecl being extern at file scope into a 21895 new maybe_special_function_p and call it. Drop check for fndecl 21896 being non-NULL that was after a usage of DECL_NAME (fndecl). 21897 * tree.h (maybe_special_function_p): New inline function. 21898 218992020-01-30 Andrew Stubbs <ams@codesourcery.com> 21900 21901 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ... 21902 (mask_gather_load<mode>): ... here, and zero-initialize the 21903 destination. 21904 (maskload<mode>di): Zero-initialize the destination. 21905 * config/gcn/gcn.c: 21906 219072020-01-30 David Malcolm <dmalcolm@redhat.com> 21908 21909 PR analyzer/93356 21910 * doc/analyzer.texi (Limitations): Note that constraints on 21911 floating-point values are currently ignored. 21912 219132020-01-30 Jakub Jelinek <jakub@redhat.com> 21914 21915 PR lto/93384 21916 * symtab.c (symtab_node::noninterposable_alias): If localalias 21917 already exists, but is not usable, append numbers after it until 21918 a unique name is found. Formatting fix. 21919 21920 PR middle-end/93505 21921 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range 21922 rotate counts. 21923 219242020-01-30 Andrew Stubbs <ams@codesourcery.com> 21925 21926 * config/gcn/gcn.c (print_operand): Handle LTGT. 21927 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt. 21928 219292020-01-30 Richard Biener <rguenther@suse.de> 21930 21931 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST 21932 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE. 21933 219342020-01-30 John David Anglin <danglin@gcc.gnu.org> 21935 21936 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers 21937 without a DECL in .data.rel.ro.local. 21938 219392020-01-30 Jakub Jelinek <jakub@redhat.com> 21940 21941 PR target/93494 21942 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4 21943 returned. 21944 21945 PR target/91824 21946 * config/i386/sse.md 21947 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ... 21948 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use 21949 any_extend code iterator instead of always zero_extend. 21950 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ... 21951 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this. 21952 Use any_extend code iterator instead of always zero_extend. 21953 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ... 21954 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this. 21955 Use any_extend code iterator instead of always zero_extend. 21956 (*sse2_pmovmskb_ext): New define_insn. 21957 (*sse2_pmovmskb_ext_lt): New define_insn_and_split. 21958 21959 PR target/91824 21960 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split. 21961 (*popcountsi2_zext_falsedep): New define_insn. 21962 219632020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 21964 21965 * config.in: Regenerated. 21966 * configure: Regenerated. 21967 219682020-01-29 Tobias Burnus <tobias@codesourcery.com> 21969 21970 PR bootstrap/93409 21971 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as 21972 LLVM's assembler changed the default in version 9. 21973 219742020-01-24 Jeff Law <law@redhat.com> 21975 21976 PR tree-optimization/89689 21977 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure. 21978 219792020-01-29 Richard Sandiford <richard.sandiford@arm.com> 21980 21981 Revert: 21982 21983 2020-01-28 Richard Sandiford <richard.sandiford@arm.com> 21984 21985 PR rtl-optimization/87763 21986 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract 21987 simplification to handle subregs as well as bare regs. 21988 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 21989 219902020-01-29 Joel Hutton <Joel.Hutton@arm.com> 21991 21992 PR target/93221 21993 * ira.c (ira): Revert use of simplified LRA algorithm. 21994 219952020-01-29 Martin Jambor <mjambor@suse.cz> 21996 21997 PR tree-optimization/92706 21998 * tree-sra.c (struct access): Fields first_link, last_link, 21999 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link, 22000 next_rhs_queued and grp_rhs_queued respectively, new fields 22001 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued. 22002 (struct assign_link): Field next renamed to next_rhs, new field 22003 next_lhs. Updated comment. 22004 (work_queue_head): Renamed to rhs_work_queue_head. 22005 (lhs_work_queue_head): New variable. 22006 (add_link_to_lhs): New function. 22007 (relink_to_new_repr): Also relink LHS lists. 22008 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue. 22009 (add_access_to_lhs_work_queue): New function. 22010 (pop_access_from_work_queue): Renamed to 22011 pop_access_from_rhs_work_queue. 22012 (pop_access_from_lhs_work_queue): New function. 22013 (build_accesses_from_assign): Also add links to LHS lists and to LHS 22014 work_queue. 22015 (child_would_conflict_in_lacc): Renamed to 22016 child_would_conflict_in_acc. Adjusted parameter names. 22017 (create_artificial_child_access): New parameter set_grp_read, use it. 22018 (subtree_mark_written_and_enqueue): Renamed to 22019 subtree_mark_written_and_rhs_enqueue. 22020 (propagate_subaccesses_across_link): Renamed to 22021 propagate_subaccesses_from_rhs. 22022 (propagate_subaccesses_from_lhs): New function. 22023 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to 22024 RHSs. 22025 220262020-01-29 Martin Jambor <mjambor@suse.cz> 22027 22028 PR tree-optimization/92706 22029 * tree-sra.c (struct access): Adjust comment of 22030 grp_total_scalarization. 22031 (find_access_in_subtree): Look for single children spanning an entire 22032 access. 22033 (scalarizable_type_p): Allow register accesses, adjust callers. 22034 (completely_scalarize): Remove function. 22035 (scalarize_elem): Likewise. 22036 (create_total_scalarization_access): Likewise. 22037 (sort_and_splice_var_accesses): Do not track total scalarization 22038 flags. 22039 (analyze_access_subtree): New parameter totally, adjust to new meaning 22040 of grp_total_scalarization. 22041 (analyze_access_trees): Pass new parameter to analyze_access_subtree. 22042 (can_totally_scalarize_forest_p): New function. 22043 (create_total_scalarization_access): Likewise. 22044 (create_total_access_and_reshape): Likewise. 22045 (total_should_skip_creating_access): Likewise. 22046 (totally_scalarize_subtree): Likewise. 22047 (analyze_all_variable_accesses): Perform total scalarization after 22048 subaccess propagation using the new functions above. 22049 (initialize_constant_pool_replacements): Output initializers by 22050 traversing the access tree. 22051 220522020-01-29 Martin Jambor <mjambor@suse.cz> 22053 22054 * tree-sra.c (verify_sra_access_forest): New function. 22055 (verify_all_sra_access_forests): Likewise. 22056 (create_artificial_child_access): Set parent. 22057 (analyze_all_variable_accesses): Call the verifier. 22058 220592020-01-28 Jan Hubicka <hubicka@ucw.cz> 22060 22061 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge 22062 if called on indirect edge. 22063 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of 22064 speculative call if needed. 22065 220662020-01-29 Richard Biener <rguenther@suse.de> 22067 22068 PR tree-optimization/93428 22069 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load 22070 permutation when the load node is created. 22071 (vect_analyze_slp_instance): Re-use it here. 22072 220732020-01-28 Jan Hubicka <hubicka@ucw.cz> 22074 22075 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning. 22076 220772020-01-28 Vladimir Makarov <vmakarov@redhat.com> 22078 22079 PR rtl-optimization/93272 22080 * ira-lives.c (process_out_of_region_eh_regs): New function. 22081 (process_bb_node_lives): Call it. 22082 220832020-01-28 Jan Hubicka <hubicka@ucw.cz> 22084 22085 * coverage.c (read_counts_file): Make error message lowercase. 22086 220872020-01-28 Jan Hubicka <hubicka@ucw.cz> 22088 22089 * profile-count.c (profile_quality_display_names): Fix ordering. 22090 220912020-01-28 Jan Hubicka <hubicka@ucw.cz> 22092 22093 PR lto/93318 22094 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site 22095 hash only when edge is first within the sequence. 22096 (cgraph_edge::set_call_stmt): Update handling of speculative calls. 22097 (symbol_table::create_edge): Do not set target_prob. 22098 (cgraph_edge::remove_caller): Watch for speculative calls when updating 22099 the call site hash. 22100 (cgraph_edge::make_speculative): Drop target_prob parameter. 22101 (cgraph_edge::speculative_call_info): Remove. 22102 (cgraph_edge::first_speculative_call_target): New member function. 22103 (update_call_stmt_hash_for_removing_direct_edge): New function. 22104 (cgraph_edge::resolve_speculation): Rewrite to new API. 22105 (cgraph_edge::speculative_call_for_target): New member function. 22106 (cgraph_edge::make_direct): Rewrite to new API; fix handling of 22107 multiple speculation targets. 22108 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating 22109 of profile. 22110 (verify_speculative_call): Verify that targets form an interval. 22111 * cgraph.h (cgraph_edge::speculative_call_info): Remove. 22112 (cgraph_edge::first_speculative_call_target): New member function. 22113 (cgraph_edge::next_speculative_call_target): New member function. 22114 (cgraph_edge::speculative_call_target_ref): New member function. 22115 (cgraph_edge;:speculative_call_indirect_edge): New member funtion. 22116 (cgraph_edge): Remove target_prob. 22117 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): 22118 Fix handling of speculative calls. 22119 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals. 22120 * ipa-fnsummary.c (analyze_function_body): Likewise. 22121 * ipa-inline.c (speculation_useful_p): Use new speculative call API. 22122 * ipa-profile.c (dump_histogram): Fix formating. 22123 (ipa_profile_generate_summary): Watch for overflows. 22124 (ipa_profile): Do not require probablity to be 1/2; update to new API. 22125 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API. 22126 (update_indirect_edges_after_inlining): Update to new API. 22127 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call 22128 profiles. 22129 * profile-count.h: (profile_probability::adjusted): New. 22130 * tree-inline.c (copy_bb): Update to new speculative call API; fix 22131 updating of profile. 22132 * value-prof.c (gimple_ic_transform): Rename to ... 22133 (dump_ic_profile): ... this one; update dumping. 22134 (stream_in_histogram_value): Fix formating. 22135 (gimple_value_profile_transformations): Update. 22136 221372020-01-28 H.J. Lu <hongjiu.lu@intel.com> 22138 22139 PR target/91461 22140 * config/i386/i386.md (*movoi_internal_avx): Remove 22141 TARGET_SSE_TYPELESS_STORES check. 22142 (*movti_internal): Prefer TARGET_AVX over 22143 TARGET_SSE_TYPELESS_STORES. 22144 (*movtf_internal): Likewise. 22145 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over 22146 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check 22147 from TARGET_SSE_TYPELESS_STORES. 22148 221492020-01-28 David Malcolm <dmalcolm@redhat.com> 22150 22151 * diagnostic-core.h (warning_at): Rename overload to... 22152 (warning_meta): ...this. 22153 (emit_diagnostic_valist): Delete decl of overload taking 22154 diagnostic_metadata. 22155 * diagnostic.c (emit_diagnostic_valist): Likewise for defn. 22156 (warning_at): Rename overload taking diagnostic_metadata to... 22157 (warning_meta): ...this. 22158 221592020-01-28 Richard Biener <rguenther@suse.de> 22160 22161 PR tree-optimization/93439 22162 * tree-parloops.c (create_loop_fn): Move clique bookkeeping... 22163 * tree-cfg.c (move_sese_region_to_fn): ... here. 22164 (verify_types_in_gimple_reference): Verify used cliques are 22165 tracked. 22166 221672020-01-28 H.J. Lu <hongjiu.lu@intel.com> 22168 22169 PR target/91399 22170 * config/i386/i386-options.c (set_ix86_tune_features): Add an 22171 argument of a pointer to struct gcc_options and pass it to 22172 parse_mtune_ctrl_str. 22173 (ix86_function_specific_restore): Pass opts to 22174 set_ix86_tune_features. 22175 (ix86_option_override_internal): Likewise. 22176 (parse_mtune_ctrl_str): Add an argument of a pointer to struct 22177 gcc_options and use it for x_ix86_tune_ctrl_string. 22178 221792020-01-28 Richard Sandiford <richard.sandiford@arm.com> 22180 22181 PR rtl-optimization/87763 22182 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract 22183 simplification to handle subregs as well as bare regs. 22184 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 22185 221862020-01-28 Richard Sandiford <richard.sandiford@arm.com> 22187 22188 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully 22189 for reduction chains that (now) include a call. 22190 221912020-01-28 Richard Sandiford <richard.sandiford@arm.com> 22192 22193 PR tree-optimization/92822 22194 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling 22195 out the don't-care elements of a vector whose significant elements 22196 are duplicates, make the don't-care elements duplicates too. 22197 221982020-01-28 Richard Sandiford <richard.sandiford@arm.com> 22199 22200 PR tree-optimization/93434 22201 * tree-predcom.c (split_data_refs_to_components): Record which 22202 components have had aliasing loads removed. Prevent store-store 22203 commoning for all such components. 22204 222052020-01-28 Jakub Jelinek <jakub@redhat.com> 22206 22207 PR target/93418 22208 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not 22209 -1 or is_vshift is true, use new_vector with number of elts npatterns 22210 rather than new_unary_operation. 22211 22212 PR tree-optimization/93454 22213 * gimple-fold.c (fold_array_ctor_reference): Perform 22214 elt_size.to_uhwi () just once, instead of calling it in every 22215 iteration. Punt if that value is above size of the temporary 22216 buffer. Decrease third native_encode_expr argument when 22217 bufoff + elt_sz is above size of buf. 22218 222192020-01-27 Joseph Myers <joseph@codesourcery.com> 22220 22221 * config/mips/mips.c (mips_declare_object_name) 22222 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object. 22223 222242020-01-27 Martin Liska <mliska@suse.cz> 22225 22226 PR gcov-profile/93403 22227 * tree-profile.c (gimple_init_gcov_profiler): Generate 22228 both __gcov_indirect_call_profiler_v4 and 22229 __gcov_indirect_call_profiler_v4_atomic. 22230 222312020-01-27 Richard Sandiford <richard.sandiford@arm.com> 22232 22233 PR target/92822 22234 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New 22235 expander. 22236 (@aarch64_split_simd_mov<mode>): Use it. 22237 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative. 22238 Leave the vec_extract patterns to handle 2-element vectors. 22239 (aarch64_simd_mov_from_<mode>high): Likewise. 22240 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander. 22241 (vec_extractv2dfv1df): Likewise. 22242 222432020-01-27 Richard Sandiford <richard.sandiford@arm.com> 22244 22245 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match 22246 jump conditions for *compare_condjump<GPI:mode>. 22247 222482020-01-27 David Malcolm <dmalcolm@redhat.com> 22249 22250 PR analyzer/93276 22251 * digraph.cc (test_edge::test_edge): Specify template for base 22252 class initializer. 22253 222542020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 22255 22256 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost. 22257 222582020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 22259 22260 * config/arc/arc-protos.h (gen_mlo): Remove. 22261 (gen_mhi): Likewise. 22262 * config/arc/arc.c (AUX_MULHI): Define. 22263 (arc_must_save_reister): Special handling for r58/59. 22264 (arc_compute_frame_size): Consider mlo/mhi registers. 22265 (arc_save_callee_saves): Emit fp/sp move only when emit_move 22266 paramter is true. 22267 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from 22268 mlo/mhi name selection. 22269 (arc_restore_callee_saves): Don't early restore blink when ISR. 22270 (arc_expand_prologue): Add mlo/mhi saving. 22271 (arc_expand_epilogue): Add mlo/mhi restoring. 22272 (gen_mlo): Remove. 22273 (gen_mhi): Remove. 22274 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register 22275 numbering when MUL64 option is used. 22276 (DWARF2_FRAME_REG_OUT): Define. 22277 * config/arc/arc.md (arc600_stall): New pattern. 22278 (VUNSPEC_ARC_ARC600_STALL): Define. 22279 (mulsi64): Use correct mlo/mhi registers. 22280 (mulsi_600): Clean it up. 22281 * config/arc/predicates.md (mlo_operand): Remove any dependency on 22282 TARGET_BIG_ENDIAN. 22283 (mhi_operand): Likewise. 22284 222852020-01-27 Claudiu Zissulescu <claziss@synopsys.com> 22286 Petro Karashchenko <petro.karashchenko@ring.com> 22287 22288 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct 22289 attributes if needed. 22290 (prepare_move_operands): Generate special unspec instruction for 22291 direct access. 22292 (arc_isuncached_mem_p): Propagate uncached attribute to each 22293 structure member. 22294 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define. 22295 (VUNSPEC_ARC_STDI): Likewise. 22296 (ALLI): New mode iterator. 22297 (mALLI): New mode attribute. 22298 (lddi): New instruction pattern. 22299 (stdi): Likewise. 22300 (stdidi_split): Split instruction for architectures which are not 22301 supporting ll64 option. 22302 (lddidi_split): Likewise. 22303 223042020-01-27 Richard Sandiford <richard.sandiford@arm.com> 22305 22306 PR rtl-optimization/92989 22307 * lra-lives.c (process_bb_lives): Update the live-in set before 22308 processing additional clobbers. 22309 223102020-01-27 Richard Sandiford <richard.sandiford@arm.com> 22311 22312 PR rtl-optimization/93170 22313 * cselib.c (cselib_invalidate_regno_val): New function, split out 22314 from... 22315 (cselib_invalidate_regno): ...here. 22316 (cselib_invalidated_by_call_p): New function. 22317 (cselib_process_insn): Iterate over all the hard-register entries in 22318 REG_VALUES and invalidate any that cross call-clobbered registers. 22319 223202020-01-27 Richard Sandiford <richard.sandiford@arm.com> 22321 22322 * dojump.c (split_comparison): Use HONOR_NANS rather than 22323 HONOR_SNANS when splitting LTGT. 22324 223252020-01-27 Martin Liska <mliska@suse.cz> 22326 22327 PR driver/91220 22328 * opts.c (print_filtered_help): Exclude language-specific 22329 options from --help=common unless enabled in all FEs. 22330 223312020-01-27 Martin Liska <mliska@suse.cz> 22332 22333 * opts.c (print_help): Exclude params from 22334 all except --help=param. 22335 223362020-01-27 Martin Liska <mliska@suse.cz> 22337 22338 PR target/93274 22339 * config/i386/i386-features.c (make_resolver_func): 22340 Align the code with ppc64 target implementation. 22341 Do not generate a unique name for resolver function. 22342 223432020-01-27 Richard Biener <rguenther@suse.de> 22344 22345 PR tree-optimization/93397 22346 * tree-vect-slp.c (vect_analyze_slp_instance): Delay 22347 converted reduction chain SLP graph adjustment. 22348 223492020-01-26 Marek Polacek <polacek@redhat.com> 22350 22351 PR sanitizer/93436 22352 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on 22353 null DECL_NAME. 22354 223552020-01-26 Jason Merrill <jason@redhat.com> 22356 22357 PR c++/92601 22358 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING 22359 of complete types. 22360 223612020-01-26 Darius Galis <darius.galis@cyberthorstudios.com> 22362 22363 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint 22364 (rx_setmem): Likewise. 22365 223662020-01-26 Jakub Jelinek <jakub@redhat.com> 22367 22368 PR target/93412 22369 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword): 22370 Use nonimmediate_operand instead of x86_64_hilo_general_operand and 22371 drop <di> from constraint of last operand. 22372 22373 PR target/93430 22374 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for 22375 TARGET_AVX2 and V4DFmode not in the split condition, but in the 22376 pattern condition, though allow { 0, 0, 0, 0 } broadcast always. 22377 223782020-01-25 Feng Xue <fxue@os.amperecomputing.com> 22379 22380 PR ipa/93166 22381 * ipa-cp.c (get_info_about_necessary_edges): Remove value 22382 check assertion. 22383 223842020-01-24 Jeff Law <law@redhat.com> 22385 22386 PR tree-optimization/92788 22387 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX 22388 not EDGE_ABNORMAL. 22389 223902020-01-24 Jakub Jelinek <jakub@redhat.com> 22391 22392 PR target/93395 22393 * config/i386/sse.md (*avx_vperm_broadcast_v4sf, 22394 *avx_vperm_broadcast_<mode>, 22395 <sse2_avx_avx512f>_vpermil<mode><mask_name>, 22396 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>): 22397 Move before avx2_perm<mode>/avx512f_perm<mode>. 22398 22399 PR target/93376 22400 * simplify-rtx.c (simplify_const_unary_operation, 22401 simplify_const_binary_operation): Punt for mode precision above 22402 MAX_BITSIZE_MODE_ANY_INT. 22403 224042020-01-24 Andrew Pinski <apinski@marvell.com> 22405 22406 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change 22407 alu.shift_reg to 0. 22408 224092020-01-24 Jeff Law <law@redhat.com> 22410 22411 PR target/13721 22412 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg 22413 for REGs. Call output_operand_lossage to get more reasonable 22414 diagnostics. 22415 224162020-01-24 Andrew Stubbs <ams@codesourcery.com> 22417 22418 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use 22419 gcn_fp_compare_operator. 22420 (vec_cmpu<mode>di): Use gcn_compare_operator. 22421 (vec_cmp<u>v64qidi): Use gcn_compare_operator. 22422 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator. 22423 (vec_cmpu<mode>di_exec): Use gcn_compare_operator. 22424 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator. 22425 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator. 22426 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator. 22427 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use 22428 gcn_fp_compare_operator. 22429 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use 22430 gcn_fp_compare_operator. 22431 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use 22432 gcn_fp_compare_operator. 22433 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use 22434 gcn_fp_compare_operator. 22435 224362020-01-24 Maciej W. Rozycki <macro@wdc.com> 22437 22438 * doc/install.texi (Cross-Compiler-Specific Options): Document 22439 `--with-toolexeclibdir' option. 22440 224412020-01-24 Hans-Peter Nilsson <hp@axis.com> 22442 22443 * target.def (flags_regnum): Also mention effect on delay slot filling. 22444 * doc/tm.texi: Regenerate. 22445 224462020-01-23 Jeff Law <law@redhat.com> 22447 22448 PR translation/90162 22449 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text. 22450 224512020-01-23 Mikael Tillenius <mti-1@tillenius.com> 22452 22453 PR target/92269 22454 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of 22455 profiling label 22456 224572020-01-23 Jakub Jelinek <jakub@redhat.com> 22458 22459 PR rtl-optimization/93402 22460 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust 22461 USE insns. 22462 224632020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 22464 22465 * config.in: Regenerated. 22466 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1 22467 for TARGET_LIBC_GNUSTACK. 22468 * configure: Regenerated. 22469 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is 22470 found to be 2.31 or greater. 22471 224722020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com> 22473 22474 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 22475 TARGET_SOFT_FLOAT. 22476 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ... 22477 (mips_asm_file_end): New function. Delegate to 22478 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true. 22479 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0. 22480 224812020-01-23 Jakub Jelinek <jakub@redhat.com> 22482 22483 PR target/93376 22484 * config/i386/i386-modes.def (POImode): New mode. 22485 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160. 22486 * config/i386/i386.md (DPWI): New mode attribute. 22487 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>. 22488 (QWI): Rename to... 22489 (QPWI): ... this. Use POI instead of OI for TImode. 22490 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1, 22491 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI> 22492 instead of <QWI>. 22493 224942020-01-23 Richard Sandiford <richard.sandiford@arm.com> 22495 22496 PR target/93341 22497 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New 22498 unspec. 22499 (speculation_tracker_rev): New pattern. 22500 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation): 22501 Use speculation_tracker_rev to track the inverse condition. 22502 225032020-01-23 Richard Biener <rguenther@suse.de> 22504 22505 PR tree-optimization/93381 22506 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take 22507 alias-set of the def as argument and record the first one. 22508 (vn_walk_cb_data::first_set): New member. 22509 (vn_reference_lookup_3): Pass the alias-set of the current def 22510 to push_partial_def. Fix alias-set used in the aggregate copy 22511 case. 22512 (vn_reference_lookup): Consistently set *last_vuse_ptr. 22513 * real.c (clear_significand_below): Fix out-of-bound access. 22514 225152020-01-23 Jakub Jelinek <jakub@redhat.com> 22516 22517 PR target/93346 22518 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3): 22519 New define_insn patterns. 22520 225212020-01-23 Richard Sandiford <richard.sandiford@arm.com> 22522 22523 * doc/sourcebuild.texi (check-function-bodies): Add an 22524 optional target/xfail selector. 22525 225262020-01-23 Richard Sandiford <richard.sandiford@arm.com> 22527 22528 PR rtl-optimization/93124 22529 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to 22530 bare USE and CLOBBER insns. 22531 225322020-01-22 Andrew Pinski <apinski@marvell.com> 22533 22534 * config/arc/arc.c (output_short_suffix): Check insn for nullness. 22535 225362020-01-22 David Malcolm <dmalcolm@redhat.com> 22537 22538 PR analyzer/93307 22539 * gdbinit.in (break-on-saved-diagnostic): Update for move of 22540 diagnostic_manager into "ana" namespace. 22541 * selftest-run-tests.c (selftest::run_tests): Update for move of 22542 selftest::run_analyzer_selftests to 22543 ana::selftest::run_analyzer_selftests. 22544 225452020-01-22 Richard Sandiford <richard.sandiford@arm.com> 22546 22547 * cfgexpand.c (union_stack_vars): Update the size. 22548 225492020-01-22 Richard Biener <rguenther@suse.de> 22550 22551 PR tree-optimization/93381 22552 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting 22553 throughout, handle all conversions the same. 22554 225552020-01-22 Jakub Jelinek <jakub@redhat.com> 22556 22557 PR target/93335 22558 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use 22559 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate 22560 predicate, not whenever it is CONST_INT. Otherwise, force_reg it. 22561 Call force_reg on high_in2 unconditionally. 22562 225632020-01-22 Martin Liska <mliska@suse.cz> 22564 22565 PR tree-optimization/92924 22566 * profile.c (compute_value_histograms): Divide 22567 all counter values. 22568 225692020-01-22 Jakub Jelinek <jakub@redhat.com> 22570 22571 PR target/91298 22572 * output.h (assemble_name_resolve): Declare. 22573 * varasm.c (assemble_name_resolve): New function. 22574 (assemble_name): Use it. 22575 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define. 22576 225772020-01-22 Joseph Myers <joseph@codesourcery.com> 22578 22579 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to 22580 update_web_docs_git instead of update_web_docs_svn. 22581 225822020-01-21 Andrew Pinski <apinski@marvell.com> 22583 22584 PR target/9311 22585 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0 22586 as PTR mode. Have operand 1 as being modeless, it can be P mode. 22587 (*tlsgd_small_<mode>): Likewise. 22588 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately) 22589 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode 22590 register. Convert that register back to dest using convert_mode. 22591 225922020-01-21 Jim Wilson <jimw@sifive.com> 22593 22594 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL 22595 instead of XINT. 22596 225972020-01-21 H.J. Lu <hongjiu.lu@intel.com> 22598 Uros Bizjak <ubizjak@gmail.com> 22599 22600 PR target/93319 22601 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode 22602 with ptr_mode. 22603 (legitimize_tls_address): Do GNU2 TLS address computation in 22604 ptr_mode and zero-extend result to Pmode. 22605 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace 22606 :P with :PTR and Pmode with ptr_mode. 22607 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise. 22608 (*tls_dynamic_gnu2_call_64_<mode>): Likewise. 22609 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise. 22610 226112020-01-21 Jakub Jelinek <jakub@redhat.com> 22612 22613 PR target/93333 22614 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify 22615 the last two operands are CONST_INT_P before using them as such. 22616 226172020-01-21 Richard Sandiford <richard.sandiford@arm.com> 22618 22619 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name 22620 to get the integer element types. 22621 226222020-01-21 Richard Sandiford <richard.sandiford@arm.com> 22623 22624 * config/aarch64/aarch64-sve-builtins.h 22625 (function_expander::convert_to_pmode): Declare. 22626 * config/aarch64/aarch64-sve-builtins.cc 22627 (function_expander::convert_to_pmode): New function. 22628 (function_expander::get_contiguous_base): Use it. 22629 (function_expander::prepare_gather_address_operands): Likewise. 22630 * config/aarch64/aarch64-sve-builtins-sve2.cc 22631 (svwhilerw_svwhilewr_impl::expand): Likewise. 22632 226332020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com> 22634 22635 PR target/92424 22636 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set 22637 cfun->machine->label_is_assembled. 22638 (aarch64_print_patchable_function_entry): New. 22639 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define. 22640 * config/aarch64/aarch64.h (struct machine_function): New field, 22641 label_is_assembled. 22642 226432020-01-21 David Malcolm <dmalcolm@redhat.com> 22644 22645 PR ipa/93315 22646 * ipa-profile.c (ipa_profile): Delete call_sums and set it to 22647 NULL on exit. 22648 226492020-01-18 Jan Hubicka <hubicka@ucw.cz> 22650 22651 PR lto/93318 22652 * cgraph.c (cgraph_edge::resolve_speculation, 22653 cgraph_edge::redirect_call_stmt_to_callee): Fix update of 22654 call_stmt_site_hash. 22655 226562020-01-21 Martin Liska <mliska@suse.cz> 22657 22658 * config/rs6000/rs6000.c (common_mode_defined): Remove 22659 unused variable. 22660 226612020-01-21 Richard Biener <rguenther@suse.de> 22662 22663 PR tree-optimization/92328 22664 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve 22665 type when value-numbering same-sized store by inserting a 22666 VIEW_CONVERT_EXPR. 22667 (eliminate_dom_walker::eliminate_stmt): When eliminating 22668 a redundant store handle bit-reinterpretation of the same value. 22669 226702020-01-21 Andrew Pinski <apinski@marvel.com> 22671 22672 PR tree-opt/93321 22673 * tree-into-ssa.c (prepare_block_for_update_1): Split out 22674 from ... 22675 (prepare_block_for_update): This. Use a worklist instead of 22676 recursing. 22677 226782020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 22679 22680 * gcc/config/arm/arm.c (clear_operation_p): 22681 Initialise last_regno, skip first iteration 22682 based on the first_set value and use ints instead 22683 of the unnecessary HOST_WIDE_INTs. 22684 226852020-01-21 Jakub Jelinek <jakub@redhat.com> 22686 22687 PR target/93073 22688 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for 22689 compare_mode other than SFmode or DFmode. 22690 226912020-01-21 Kito Cheng <kito.cheng@sifive.com> 22692 22693 PR target/93304 22694 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New. 22695 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New. 22696 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined. 22697 226982020-01-20 Wilco Dijkstra <wdijkstr@arm.com> 22699 22700 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4. 22701 227022020-01-20 Andrew Pinski <apinski@marvell.com> 22703 22704 PR middle-end/93242 22705 * targhooks.c (default_print_patchable_function_entry): Use 22706 output_asm_insn to emit the nop instruction. 22707 227082020-01-20 Fangrui Song <maskray@google.com> 22709 22710 PR middle-end/93194 22711 * targhooks.c (default_print_patchable_function_entry): Align to 22712 POINTER_SIZE. 22713 227142020-01-20 H.J. Lu <hongjiu.lu@intel.com> 22715 22716 PR target/93319 22717 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to 22718 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode. 22719 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ... 22720 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P. 22721 (*tls_dynamic_gnu2_lea_64): Renamed to ... 22722 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P. 22723 Remove the {q} suffix from lea. 22724 (*tls_dynamic_gnu2_call_64): Renamed to ... 22725 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P. 22726 (*tls_dynamic_gnu2_combine_64): Renamed to ... 22727 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P. 22728 Pass Pmode to gen_tls_dynamic_gnu2_64. 22729 227302020-01-20 Wilco Dijkstra <wdijkstr@arm.com> 22731 22732 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1. 22733 227342020-01-20 Richard Sandiford <richard.sandiford@arm.com> 22735 22736 * config/aarch64/aarch64-sve-builtins-base.cc 22737 (svld1ro_impl::memory_vector_mode): Remove parameter name. 22738 227392020-01-20 Richard Biener <rguenther@suse.de> 22740 22741 PR debug/92763 22742 * dwarf2out.c (prune_unused_types): Unconditionally mark 22743 called function DIEs. 22744 227452020-01-20 Martin Liska <mliska@suse.cz> 22746 22747 PR tree-optimization/93199 22748 * tree-eh.c (struct leh_state): Add 22749 new field outer_non_cleanup. 22750 (cleanup_is_dead_in): Pass leh_state instead 22751 of eh_region. Add a checking that state->outer_non_cleanup 22752 points to outer non-clean up region. 22753 (lower_try_finally): Record outer_non_cleanup 22754 for this_state. 22755 (lower_catch): Likewise. 22756 (lower_eh_filter): Likewise. 22757 (lower_eh_must_not_throw): Likewise. 22758 (lower_cleanup): Likewise. 22759 227602020-01-20 Richard Biener <rguenther@suse.de> 22761 22762 PR tree-optimization/93094 22763 * tree-vectorizer.h (vect_loop_versioning): Adjust. 22764 (vect_transform_loop): Likewise. 22765 * tree-vectorizer.c (try_vectorize_loop_1): Pass down 22766 loop_vectorized_call to vect_transform_loop. 22767 * tree-vect-loop.c (vect_transform_loop): Pass down 22768 loop_vectorized_call to vect_loop_versioning. 22769 * tree-vect-loop-manip.c (vect_loop_versioning): Use 22770 the earlier discovered loop_vectorized_call. 22771 227722020-01-19 Eric S. Raymond <esr@thyrsus.com> 22773 22774 * doc/contribute.texi: Update for SVN -> Git transition. 22775 * doc/install.texi: Likewise. 22776 227772020-01-18 Jan Hubicka <hubicka@ucw.cz> 22778 22779 PR lto/93318 22780 * cgraph.c (cgraph_edge::make_speculative): Increase number of 22781 speculative targets. 22782 (verify_speculative_call): New function 22783 (cgraph_node::verify_node): Use it. 22784 * ipa-profile.c (ipa_profile): Fix formating; do not set number of 22785 speculations. 22786 227872020-01-18 Jan Hubicka <hubicka@ucw.cz> 22788 22789 PR lto/93318 22790 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting. 22791 (cgraph_edge::make_direct): Remove all indirect targets. 22792 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct.. 22793 (cgraph_node::verify_node): Verify that only one call_stmt or 22794 lto_stmt_uid is set. 22795 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or 22796 lto_stmt_uid. 22797 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt. 22798 (lto_output_ref): Simplify streaming of stmt. 22799 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid. 22800 228012020-01-18 Tamar Christina <tamar.christina@arm.com> 22802 22803 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode): 22804 Mark parameter unused. 22805 228062020-01-18 Hans-Peter Nilsson <hp@axis.com> 22807 22808 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux* 22809 228102019-01-18 Gerald Pfeifer <gerald@pfeifer.com> 22811 22812 * varpool.c (ctor_useable_for_folding_p): Fix grammar. 22813 228142020-01-18 Iain Sandoe <iain@sandoe.co.uk> 22815 22816 * Makefile.in: Add coroutine-passes.o. 22817 * builtin-types.def (BT_CONST_SIZE): New. 22818 (BT_FN_BOOL_PTR): New. 22819 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New. 22820 * builtins.def (DEF_COROUTINE_BUILTIN): New. 22821 * coroutine-builtins.def: New file. 22822 * coroutine-passes.cc: New file. 22823 * function.h (struct GTY function): Add a bit to indicate that the 22824 function is a coroutine component. 22825 * internal-fn.c (expand_CO_FRAME): New. 22826 (expand_CO_YIELD): New. 22827 (expand_CO_SUSPN): New. 22828 (expand_CO_ACTOR): New. 22829 * internal-fn.def (CO_ACTOR): New. 22830 (CO_YIELD): New. 22831 (CO_SUSPN): New. 22832 (CO_FRAME): New. 22833 * passes.def: Add pass_coroutine_lower_builtins, 22834 pass_coroutine_early_expand_ifns. 22835 * tree-pass.h (make_pass_coroutine_lower_builtins): New. 22836 (make_pass_coroutine_early_expand_ifns): New. 22837 * doc/invoke.texi: Document the fcoroutines command line 22838 switch. 22839 228402020-01-18 Jakub Jelinek <jakub@redhat.com> 22841 22842 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable. 22843 22844 PR target/93312 22845 * config/arm/arm.c (clear_operation_p): Don't use REGNO until 22846 after checking the argument is a REG. Don't use REGNO (reg) 22847 again to set last_regno, reuse regno variable instead. 22848 228492020-01-17 David Malcolm <dmalcolm@redhat.com> 22850 22851 * doc/analyzer.texi (Limitations): Add note about NaN. 22852 228532020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 22854 Sudakshina Das <sudi.das@arm.com> 22855 22856 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg 22857 and valid immediate. 22858 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. 22859 (lshrdi3): Generate thumb2_lsrl for valid immediates. 22860 * config/arm/constraints.md (Pg): New. 22861 * config/arm/predicates.md (long_shift_imm): New. 22862 (arm_reg_or_long_shift_imm): Likewise. 22863 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. 22864 (thumb2_lsll): Likewise. 22865 (thumb2_lsrl): New. 22866 228672020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 22868 Sudakshina Das <sudi.das@arm.com> 22869 22870 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE. 22871 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE. 22872 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd 22873 register pairs for doubleword quantities for ARMv8.1M-Mainline. 22874 * config/arm/thumb2.md (thumb2_asrl): New. 22875 (thumb2_lsll): Likewise. 22876 228772020-01-17 Jakub Jelinek <jakub@redhat.com> 22878 22879 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove 22880 unused variable. 22881 228822020-01-17 Alexander Monakov <amonakov@ispras.ru> 22883 22884 * gdbinit.in (help-gcc-hooks): New command. 22885 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc, 22886 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update 22887 documentation. 22888 228892020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 22890 22891 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the 22892 correct target macro. 22893 228942020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 22895 22896 * config/aarch64/aarch64-protos.h 22897 (aarch64_sve_ld1ro_operand_p): New. 22898 * config/aarch64/aarch64-sve-builtins-base.cc 22899 (class load_replicate): New. 22900 (class svld1ro_impl): New. 22901 (class svld1rq_impl): Change to inherit from load_replicate. 22902 (svld1ro): New sve intrinsic function base. 22903 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro): 22904 New DEF_SVE_FUNCTION. 22905 * config/aarch64/aarch64-sve-builtins-base.h 22906 (svld1ro): New decl. 22907 * config/aarch64/aarch64-sve-builtins.cc 22908 (function_expander::add_mem_operand): Modify assert to allow 22909 OImode. 22910 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New 22911 pattern. 22912 * config/aarch64/aarch64.c 22913 (aarch64_sve_ld1rq_operand_p): Implement in terms of ... 22914 (aarch64_sve_ld1rq_ld1ro_operand_p): This. 22915 (aarch64_sve_ld1ro_operand_p): New. 22916 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec. 22917 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New. 22918 * config/aarch64/predicates.md 22919 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New. 22920 229212020-01-17 Matthew Malcomson <matthew.malcomson@arm.com> 22922 22923 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64): 22924 Introduce this ACLE specified predefined macro. 22925 * config/aarch64/aarch64-option-extensions.def (f64mm): New. 22926 (fp): Disabling this disables f64mm. 22927 (simd): Disabling this disables f64mm. 22928 (fp16): Disabling this disables f64mm. 22929 (sve): Disabling this disables f64mm. 22930 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New. 22931 (AARCH64_ISA_F64MM): New. 22932 (TARGET_F64MM): New. 22933 * doc/invoke.texi (f64mm): Document new option. 22934 229352020-01-17 Wilco Dijkstra <wdijkstr@arm.com> 22936 22937 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion. 22938 (neoversen1_tunings): Likewise. 22939 229402020-01-17 Wilco Dijkstra <wdijkstr@arm.com> 22941 22942 PR target/92692 22943 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap) 22944 Add assert to ensure prolog has been emitted. 22945 (aarch64_split_atomic_op): Likewise. 22946 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>) 22947 Use epilogue_completed rather than reload_completed. 22948 (aarch64_atomic_exchange<mode>): Likewise. 22949 (aarch64_atomic_<atomic_optab><mode>): Likewise. 22950 (atomic_nand<mode>): Likewise. 22951 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise. 22952 (atomic_fetch_nand<mode>): Likewise. 22953 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise. 22954 (atomic_nand_fetch<mode>): Likewise. 22955 229562020-01-17 Richard Sandiford <richard.sandiford@arm.com> 22957 22958 PR target/93133 22959 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false 22960 for FP modes. 22961 (REVERSE_CONDITION): Delete. 22962 * config/aarch64/iterators.md (CC_ONLY): New mode iterator. 22963 (CCFP_CCFPE): Likewise. 22964 (e): New mode attribute. 22965 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to... 22966 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC. 22967 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into... 22968 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern. 22969 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern. 22970 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise. 22971 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update 22972 name of generator from gen_ccmpdi to gen_ccmpccdi. 22973 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse 22974 the previous comparison but aren't able to, use the new ccmp_rev 22975 patterns instead. 22976 229772020-01-17 Richard Sandiford <richard.sandiford@arm.com> 22978 22979 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather 22980 than testing directly for INTEGER_CST. 22981 (gimplify_target_expr, gimplify_omp_depend): Likewise. 22982 229832020-01-17 Jakub Jelinek <jakub@redhat.com> 22984 22985 PR tree-optimization/93292 22986 * tree-vect-stmts.c (vectorizable_comparison): Punt also if 22987 get_vectype_for_scalar_type returns NULL. 22988 229892020-01-16 Jan Hubicka <hubicka@ucw.cz> 22990 22991 * params.opt (-param=max-predicted-iterations): Increase range from 0. 22992 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations. 22993 229942020-01-16 Jan Hubicka <hubicka@ucw.cz> 22995 22996 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of 22997 dump. 22998 * params.opt: (max-predicted-iterations): Set bounds. 22999 * predict.c (real_almost_one, real_br_prob_base, 23000 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove. 23001 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic 23002 probabilities; do not truncate to reg_br_prob_bases. 23003 (estimate_loops_at_level): Pass max_cyclic_prob. 23004 (estimate_loops): Compute max_cyclic_prob. 23005 (estimate_bb_frequencies): Do not initialize real_*; update calculation 23006 of back edge prob. 23007 * profile-count.c (profile_probability::to_sreal): New. 23008 * profile-count.h (class sreal): Move up in file. 23009 (profile_probability::to_sreal): Declare. 23010 230112020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23012 23013 * config/arm/arm.c 23014 (arm_invalid_conversion): New function for target hook. 23015 (arm_invalid_unary_op): New function for target hook. 23016 (arm_invalid_binary_op): New function for target hook. 23017 230182020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23019 23020 * config.gcc: Add arm_bf16.h. 23021 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment. 23022 (arm_simd_builtin_std_type): Add BFmode. 23023 (arm_init_simd_builtin_types): Define element types for vector types. 23024 (arm_init_bf16_types): New function. 23025 (arm_init_builtins): Add arm_init_bf16_types function call. 23026 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes. 23027 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF. 23028 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode. 23029 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements. 23030 (arm_vector_mode_supported_p): Add V4BF, V8BF. 23031 (arm_mangle_type): Add __bf16. 23032 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE, 23033 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node, 23034 arm_bf16_ptr_type_node. 23035 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and 23036 define_split between ARM registers. 23037 * config/arm/arm_bf16.h: New file. 23038 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types. 23039 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New. 23040 (VQXMOV): Add V8BF. 23041 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns. 23042 * config/arm/vfp.md: Add BFmode to movhf patterns. 23043 230442020-01-16 Mihail Ionescu <mihail.ionescu@arm.com> 23045 Andre Vieira <andre.simoesdiasvieira@arm.com> 23046 23047 * config/arm/arm-cpus.in (mve, mve_float): New features. 23048 (dsp, mve, mve.fp): New options. 23049 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define. 23050 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M. 23051 * doc/invoke.texi: Document the armv8.1-m mve and dps options. 23052 230532020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23054 Thomas Preud'homme <thomas.preudhomme@arm.com> 23055 23056 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to 23057 Armv8-M Mainline. 23058 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove 23059 error for using -mcmse when targeting Armv8.1-M Mainline. 23060 230612020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23062 Thomas Preud'homme <thomas.preudhomme@arm.com> 23063 23064 * config/arm/arm.md (nonsecure_call_internal): Do not force memory 23065 address in r4 when targeting Armv8.1-M Mainline. 23066 (nonsecure_call_value_internal): Likewise. 23067 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address 23068 a register match_operand again. Emit BLXNS when targeting 23069 Armv8.1-M Mainline. 23070 (nonsecure_call_value_reg_thumb2): Likewise. 23071 230722020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23073 Thomas Preud'homme <thomas.preudhomme@arm.com> 23074 23075 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early. 23076 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear 23077 variable as true when floating-point ABI is not hard. Replace 23078 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear. 23079 Generate VLSTM and VLLDM instruction respectively before and 23080 after a function call to cmse_nonsecure_call function. 23081 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec. 23082 (VUNSPEC_VLLDM): Likewise. 23083 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn. 23084 (lazy_load_multiple_insn): Likewise. 23085 230862020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23087 Thomas Preud'homme <thomas.preudhomme@arm.com> 23088 23089 * config/arm/arm.c (vfp_emit_fstmd): Declare early. 23090 (arm_emit_vfp_multi_reg_pop): Likewise. 23091 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP 23092 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and 23093 restore callee-saved VFP registers. 23094 230952020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23096 Thomas Preud'homme <thomas.preudhomme@arm.com> 23097 23098 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early. 23099 (cmse_nonsecure_call_clear_caller_saved): Rename into ... 23100 (cmse_nonsecure_call_inline_register_clear): This. Save and clear 23101 callee-saved GPRs as well as clear ip register before doing a nonsecure 23102 call then restore callee-saved GPRs after it when targeting 23103 Armv8.1-M Mainline. 23104 (arm_reorg): Adapt to function rename. 23105 231062020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23107 Thomas Preud'homme <thomas.preudhomme@arm.com> 23108 23109 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype. 23110 * config/arm/arm.c (clear_operation_p): Extend to be able to check a 23111 clear_vfp_multiple pattern based on a new vfp parameter. 23112 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when 23113 targeting Armv8.1-M Mainline. 23114 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers 23115 unconditionally when targeting Armv8.1-M Mainline architecture. Check 23116 whether VFP registers are available before looking call_used_regs for a 23117 VFP register. 23118 * config/arm/predicates.md (clear_multiple_operation): Adapt to change 23119 of prototype of clear_operation_p. 23120 (clear_vfp_multiple_operation): New predicate. 23121 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec. 23122 * config/arm/vfp.md (clear_vfp_multiple): New define_insn. 23123 231242020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23125 Thomas Preud'homme <thomas.preudhomme@arm.com> 23126 23127 * config/arm/arm-protos.h (clear_operation_p): Declare. 23128 * config/arm/arm.c (clear_operation_p): New function. 23129 (cmse_clear_registers): Generate clear_multiple instruction pattern if 23130 targeting Armv8.1-M Mainline or successor. 23131 (output_return_instruction): Only output APSR register clearing if 23132 Armv8.1-M Mainline instructions not available. 23133 (thumb_exit): Likewise. 23134 * config/arm/predicates.md (clear_multiple_operation): New predicate. 23135 * config/arm/thumb2.md (clear_apsr): New define_insn. 23136 (clear_multiple): Likewise. 23137 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec. 23138 231392020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23140 Thomas Preud'homme <thomas.preudhomme@arm.com> 23141 23142 * config/arm/arm.c (fp_sysreg_names): Declare and define. 23143 (use_return_insn): Also return false for Armv8.1-M Mainline. 23144 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M 23145 Mainline instructions are available. 23146 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS 23147 when targeting Armv8.1-M Mainline Security Extensions. 23148 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M 23149 Mainline entry function. 23150 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if 23151 targeting Armv8.1-M Mainline or successor. 23152 (arm_expand_epilogue): Fix indentation of caller-saved register 23153 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline 23154 entry function. 23155 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro. 23156 (FP_SYSREGS): Likewise. 23157 (enum vfp_sysregs_encoding): Define enum. 23158 (fp_sysreg_names): Declare. 23159 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec. 23160 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn. 23161 (pop_fpsysreg_insn): Likewise. 23162 231632020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 23164 Thomas Preud'homme <thomas.preudhomme@arm.com> 23165 23166 * config/arm/arm-cpus.in (armv8_1m_main): New feature. 23167 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k, 23168 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve, 23169 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a, 23170 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent. 23171 (ARMv8_1m_main): New feature group. 23172 (armv8.1-m.main): New architecture. 23173 * config/arm/arm-tables.opt: Regenerate. 23174 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize. 23175 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main. 23176 (arm_options_perform_arch_sanity_checks): Error out when targeting 23177 Armv8.1-M Mainline Security Extensions. 23178 * config/arm/arm.h (arm_arch8_1m_main): Declare. 23179 231802020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23181 23182 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot, 23183 aarch64_bfdot_lane, aarch64_bfdot_laneq): New. 23184 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane, 23185 aarch64_bfdot_laneq): New. 23186 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32, 23187 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32, 23188 vbfdotq_laneq_f32): New. 23189 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype, 23190 VBFMLA_W, VBF): New. 23191 (isquadop): Add V4BF, V8BF. 23192 231932020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23194 23195 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers): 23196 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS, 23197 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP. 23198 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX. 23199 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index. 23200 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane, 23201 usdot_laneq, sudot_lane,sudot_laneq): New. 23202 * config/aarch64/aarch64-simd.md (aarch64_usdot): New. 23203 (aarch64_<sur>dot_lane): New. 23204 * config/aarch64/arm_neon.h (vusdot_s32): New. 23205 (vusdotq_s32): New. 23206 (vusdot_lane_s32): New. 23207 (vsudot_lane_s32): New. 23208 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator. 23209 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs. 23210 232112020-01-16 Martin Liska <mliska@suse.cz> 23212 23213 * value-prof.c (dump_histogram_value): Fix 23214 obvious spacing issue. 23215 232162020-01-16 Andrew Pinski <apinski@marvell.com> 23217 23218 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for 23219 !storage_order_barrier_p. 23220 232212020-01-16 Andrew Pinski <apinski@marvell.com> 23222 23223 * sched-int.h (_dep): Add unused bit-field field for the padding. 23224 * sched-deps.c (init_dep_1): Init unused field. 23225 232262020-01-16 Andrew Pinski <apinski@marvell.com> 23227 23228 * optabs.h (create_expand_operand): Initialize target field also. 23229 232302020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 23231 23232 PR tree-optimization/92429 23233 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter. 23234 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to 23235 control folding. 23236 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing 23237 tree. 23238 232392020-01-16 Richard Sandiford <richard.sandiford@arm.com> 23240 23241 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply 23242 aarch64_sve_int_mode to each mode. 23243 232442020-01-15 David Malcolm <dmalcolm@redhat.com> 23245 23246 * doc/analyzer.texi (Overview): Add note about 23247 -fdump-ipa-analyzer. 23248 232492020-01-15 Wilco Dijkstra <wdijkstr@arm.com> 23250 23251 PR tree-optimization/93231 23252 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check 23253 input_type is unsigned. Use tree_to_shwi for shift constant. 23254 Check CST_STRING element size is CHAR_TYPE_SIZE bits. 23255 (simplify_count_trailing_zeroes): Add test to handle known non-zero 23256 inputs more efficiently. 23257 232582020-01-15 Uroš Bizjak <ubizjak@gmail.com> 23259 23260 * config/i386/i386.md (*movsf_internal): Do not require 23261 SSE2 ISA for alternatives 14 and 15. 23262 232632020-01-15 Richard Biener <rguenther@suse.de> 23264 23265 PR middle-end/93273 23266 * tree-eh.c (sink_clobbers): If we already visited the destination 23267 block do not defer insertion. 23268 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for 23269 the purpose of defered insertion. 23270 232712020-01-15 Jakub Jelinek <jakub@redhat.com> 23272 23273 * BASE-VER: Bump to 10.0.1. 23274 232752020-01-15 Richard Sandiford <richard.sandiford@arm.com> 23276 23277 PR tree-optimization/93247 23278 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access 23279 type of the stmt that we're going to vectorize. 23280 232812020-01-15 Richard Sandiford <richard.sandiford@arm.com> 23282 23283 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a 23284 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent 23285 type from the lhs. 23286 232872020-01-15 Martin Liska <mliska@suse.cz> 23288 23289 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow 23290 2 calls of streamer_read_hwi in a function call. 23291 232922020-01-15 Richard Biener <rguenther@suse.de> 23293 23294 * alias.c (record_alias_subset): Avoid redundant work when 23295 subset is already recorded. 23296 232972020-01-14 David Malcolm <dmalcolm@redhat.com> 23298 23299 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of 23300 the analyzer options provide CWE identifiers. 23301 233022020-01-14 David Malcolm <dmalcolm@redhat.com> 23303 23304 * tree-diagnostic-path.cc (path_summary::event_range::print): 23305 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers 23306 using get_pure_location. 23307 233082020-01-15 Jakub Jelinek <jakub@redhat.com> 23309 23310 PR tree-optimization/93262 23311 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins, 23312 perform head trimming only if the last argument is constant, 23313 either all ones, or larger or equal to head trim, in the latter 23314 case decrease the last argument by head_trim. 23315 23316 PR tree-optimization/93249 23317 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h. 23318 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to 23319 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't 23320 perform head trim unless we can prove there are no '\0' chars 23321 from the source among the first head_trim chars. 23322 233232020-01-14 David Malcolm <dmalcolm@redhat.com> 23324 23325 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o. 23326 233272020-01-15 Jakub Jelinek <jakub@redhat.com> 23328 23329 PR target/93009 23330 * config/i386/sse.md 23331 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1, 23332 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1, 23333 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1, 23334 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use 23335 just a single alternative instead of two, make operands 1 and 2 23336 commutative. 23337 233382020-01-14 Jan Hubicka <hubicka@ucw.cz> 23339 23340 PR lto/91576 23341 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and 23342 TYPE_MODE. 23343 233442020-01-14 David Malcolm <dmalcolm@redhat.com> 23345 23346 * Makefile.in (lang_opt_files): Add analyzer.opt. 23347 (ANALYZER_OBJS): New. 23348 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o, 23349 tristate.o and ANALYZER_OBJS. 23350 (TEXI_GCCINT_FILES): Add analyzer.texi. 23351 * common.opt (-fanalyzer): New driver option. 23352 * config.in: Regenerate. 23353 * configure: Regenerate. 23354 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option. 23355 (gccdepdir): Also create depdir for "analyzer" subdir. 23356 * digraph.cc: New file. 23357 * digraph.h: New file. 23358 * doc/analyzer.texi: New file. 23359 * doc/gccint.texi ("Static Analyzer") New menu item. 23360 (analyzer.texi): Include it. 23361 * doc/invoke.texi ("Static Analyzer Options"): New list and new section. 23362 ("Warning Options"): Add static analysis warnings to the list. 23363 (-Wno-analyzer-double-fclose): New option. 23364 (-Wno-analyzer-double-free): New option. 23365 (-Wno-analyzer-exposure-through-output-file): New option. 23366 (-Wno-analyzer-file-leak): New option. 23367 (-Wno-analyzer-free-of-non-heap): New option. 23368 (-Wno-analyzer-malloc-leak): New option. 23369 (-Wno-analyzer-possible-null-argument): New option. 23370 (-Wno-analyzer-possible-null-dereference): New option. 23371 (-Wno-analyzer-null-argument): New option. 23372 (-Wno-analyzer-null-dereference): New option. 23373 (-Wno-analyzer-stale-setjmp-buffer): New option. 23374 (-Wno-analyzer-tainted-array-index): New option. 23375 (-Wno-analyzer-use-after-free): New option. 23376 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option. 23377 (-Wno-analyzer-use-of-uninitialized-value): New option. 23378 (-Wanalyzer-too-complex): New option. 23379 (-fanalyzer-call-summaries): New warning. 23380 (-fanalyzer-checker=): New warning. 23381 (-fanalyzer-fine-grained): New warning. 23382 (-fno-analyzer-state-merge): New warning. 23383 (-fno-analyzer-state-purge): New warning. 23384 (-fanalyzer-transitivity): New warning. 23385 (-fanalyzer-verbose-edges): New warning. 23386 (-fanalyzer-verbose-state-changes): New warning. 23387 (-fanalyzer-verbosity=): New warning. 23388 (-fdump-analyzer): New warning. 23389 (-fdump-analyzer-callgraph): New warning. 23390 (-fdump-analyzer-exploded-graph): New warning. 23391 (-fdump-analyzer-exploded-nodes): New warning. 23392 (-fdump-analyzer-exploded-nodes-2): New warning. 23393 (-fdump-analyzer-exploded-nodes-3): New warning. 23394 (-fdump-analyzer-supergraph): New warning. 23395 * doc/sourcebuild.texi (dg-require-dot): New. 23396 (dg-check-dot): New. 23397 * gdbinit.in (break-on-saved-diagnostic): New command. 23398 * graphviz.cc: New file. 23399 * graphviz.h: New file. 23400 * ordered-hash-map-tests.cc: New file. 23401 * ordered-hash-map.h: New file. 23402 * passes.def (pass_analyzer): Add before 23403 pass_ipa_whole_program_visibility. 23404 * selftest-run-tests.c (selftest::run_tests): Call 23405 selftest::ordered_hash_map_tests_cc_tests. 23406 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New 23407 decl. 23408 * shortest-paths.h: New file. 23409 * timevar.def (TV_ANALYZER): New timevar. 23410 (TV_ANALYZER_SUPERGRAPH): Likewise. 23411 (TV_ANALYZER_STATE_PURGE): Likewise. 23412 (TV_ANALYZER_PLAN): Likewise. 23413 (TV_ANALYZER_SCC): Likewise. 23414 (TV_ANALYZER_WORKLIST): Likewise. 23415 (TV_ANALYZER_DUMP): Likewise. 23416 (TV_ANALYZER_DIAGNOSTICS): Likewise. 23417 (TV_ANALYZER_SHORTEST_PATHS): Likewise. 23418 * tree-pass.h (make_pass_analyzer): New decl. 23419 * tristate.cc: New file. 23420 * tristate.h: New file. 23421 234222020-01-14 Uroš Bizjak <ubizjak@gmail.com> 23423 23424 PR target/93254 23425 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for 23426 alternatives 9 and 10. 23427 234282020-01-14 David Malcolm <dmalcolm@redhat.com> 23429 23430 * attribs.c (excl_hash_traits::empty_zero_p): New static constant. 23431 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise. 23432 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise. 23433 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest. 23434 (selftest::hash_map_tests_c_tests): Call it. 23435 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p): 23436 New static constant, using the value of = H::empty_zero_p. 23437 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value 23438 from default_hash_traits <Value>. 23439 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value 23440 from Traits. 23441 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise. 23442 * hash-table.h (hash_table::alloc_entries): Guard the loop of 23443 calls to mark_empty with !Descriptor::empty_zero_p. 23444 (hash_table::empty_slow): Conditionalize the memset call with a 23445 check that Descriptor::empty_zero_p; otherwise, loop through the 23446 entries calling mark_empty on them. 23447 * hash-traits.h (int_hash::empty_zero_p): New static constant. 23448 (pointer_hash::empty_zero_p): Likewise. 23449 (pair_hash::empty_zero_p): Likewise. 23450 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p): 23451 Likewise. 23452 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise. 23453 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise. 23454 * profile.c (location_triplet_hash::empty_zero_p): Likewise. 23455 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise. 23456 (sanopt_tree_couple_hash::empty_zero_p): Likewise. 23457 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise. 23458 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise. 23459 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise. 23460 * tree-vectorizer.h 23461 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p): 23462 Likewise. 23463 234642020-01-14 Kewen Lin <linkw@gcc.gnu.org> 23465 23466 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return, 23467 fix typo on return value. 23468 234692020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com> 23470 23471 PR ipa/69678 23472 * cgraph.c (symbol_table::create_edge): Init speculative_id and 23473 target_prob. 23474 (cgraph_edge::make_speculative): Add param for setting speculative_id 23475 and target_prob. 23476 (cgraph_edge::speculative_call_info): Update comments and find reference 23477 by speculative_id for multiple indirect targets. 23478 (cgraph_edge::resolve_speculation): Decrease the speculations 23479 for indirect edge, drop it's speculative if not direct target 23480 left. Update comments. 23481 (cgraph_edge::redirect_call_stmt_to_callee): Likewise. 23482 (cgraph_node::dump): Print num_speculative_call_targets. 23483 (cgraph_node::verify_node): Don't report error if speculative 23484 edge not include statement. 23485 (cgraph_edge::num_speculative_call_targets_p): New function. 23486 * cgraph.h (int common_target_id): Remove. 23487 (int common_target_probability): Remove. 23488 (num_speculative_call_targets): New variable. 23489 (make_speculative): Add param for setting speculative_id. 23490 (cgraph_edge::num_speculative_call_targets_p): New declare. 23491 (target_prob): New variable. 23492 (speculative_id): New variable. 23493 * ipa-fnsummary.c (analyze_function_body): Create and duplicate 23494 call summaries for multiple speculative call targets. 23495 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id. 23496 * ipa-profile.c (struct speculative_call_target): New struct. 23497 (class speculative_call_summary): New class. 23498 (class speculative_call_summaries): New class. 23499 (call_sums): New variable. 23500 (ipa_profile_generate_summary): Generate indirect multiple targets summaries. 23501 (ipa_profile_write_edge_summary): New function. 23502 (ipa_profile_write_summary): Stream out indirect multiple targets summaries. 23503 (ipa_profile_dump_all_summaries): New function. 23504 (ipa_profile_read_edge_summary): New function. 23505 (ipa_profile_read_summary_section): New function. 23506 (ipa_profile_read_summary): Stream in indirect multiple targets summaries. 23507 (ipa_profile): Generate num_speculative_call_targets from 23508 profile summaries. 23509 * ipa-ref.h (speculative_id): New variable. 23510 * ipa-utils.c (ipa_merge_profiles): Update with target_prob. 23511 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and 23512 common_target_probability. Stream out speculative_id and 23513 num_speculative_call_targets. 23514 (input_edge): Likewise. 23515 * predict.c (dump_prediction): Remove edges count assert to be 23516 precise. 23517 * symtab.c (symtab_node::create_reference): Init speculative_id. 23518 (symtab_node::clone_references): Clone speculative_id. 23519 (symtab_node::clone_referring): Clone speculative_id. 23520 (symtab_node::clone_reference): Clone speculative_id. 23521 (symtab_node::clear_stmts_in_references): Clear speculative_id. 23522 * tree-inline.c (copy_bb): Duplicate all the speculative edges 23523 if indirect call contains multiple speculative targets. 23524 * value-prof.h (check_ic_target): Remove. 23525 * value-prof.c (gimple_value_profile_transformations): 23526 Use void function gimple_ic_transform. 23527 * value-prof.c (gimple_ic_transform): Handle topn case. 23528 Fix comment typos. Change it to a void function. 23529 235302020-01-13 Andrew Pinski <apinski@marvell.com> 23531 23532 * config/aarch64/aarch64-cores.def (octeontx2): New define. 23533 (octeontx2t98): New define. 23534 (octeontx2t96): New define. 23535 (octeontx2t93): New define. 23536 (octeontx2f95): New define. 23537 (octeontx2f95n): New define. 23538 (octeontx2f95mm): New define. 23539 * config/aarch64/aarch64-tune.md: Regenerate. 23540 * doc/invoke.texi (-mcpu=): Document the new cpu types. 23541 235422020-01-13 Jason Merrill <jason@redhat.com> 23543 23544 PR c++/33799 - destroy return value if local cleanup throws. 23545 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR. 23546 235472020-01-13 Martin Liska <mliska@suse.cz> 23548 23549 * ipa-cp.c (get_max_overall_size): Use newly 23550 renamed param param_ipa_cp_unit_growth. 23551 * params.opt: Remove legacy param name. 23552 235532020-01-13 Martin Sebor <msebor@redhat.com> 23554 23555 PR tree-optimization/93213 23556 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul 23557 stores to be eliminated. 23558 235592020-01-13 Martin Liska <mliska@suse.cz> 23560 23561 * opts.c (print_help): Do not print CL_PARAM 23562 and CL_WARNING for CL_OPTIMIZATION. 23563 235642020-01-13 Jonathan Wakely <jwakely@redhat.com> 23565 23566 PR driver/92757 23567 * doc/invoke.texi (Warning Options): Add caveat about some warnings 23568 depending on optimization settings. 23569 235702020-01-13 Jakub Jelinek <jakub@redhat.com> 23571 23572 PR tree-optimization/90838 23573 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use 23574 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro 23575 argument rather than to initialize temporary for targets that 23576 don't use the mode argument at all. Initialize ctzval to avoid 23577 warning at -O0. 23578 235792020-01-10 Thomas Schwinge <thomas@codesourcery.com> 23580 23581 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition. 23582 * tree-core.h: Document it. 23583 * gimplify.c (gimplify_omp_workshare): Set it. 23584 * omp-low.c (lower_omp_target): Use it. 23585 * tree-pretty-print.c (dump_omp_clause): Print it. 23586 23587 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>: 23588 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'. 23589 235902020-01-10 David Malcolm <dmalcolm@redhat.com> 23591 23592 * Makefile.in (OBJS): Add tree-diagnostic-path.o. 23593 * common.opt (fdiagnostics-path-format=): New option. 23594 (diagnostic_path_format): New enum. 23595 (fdiagnostics-show-path-depths): New option. 23596 * coretypes.h (diagnostic_event_id_t): New forward decl. 23597 * diagnostic-color.c (color_dict): Add "path". 23598 * diagnostic-event-id.h: New file. 23599 * diagnostic-format-json.cc (json_from_expanded_location): Make 23600 non-static. 23601 (json_end_diagnostic): Call context->make_json_for_path if it 23602 exists and the diagnostic has a path. 23603 (diagnostic_output_format_init): Clear context->print_path. 23604 * diagnostic-path.h: New file. 23605 * diagnostic-show-locus.c (colorizer::set_range): Special-case 23606 when printing a run of events in a diagnostic_path so that they 23607 all get the same color. 23608 (layout::m_diagnostic_path_p): New field. 23609 (layout::layout): Initialize it. 23610 (layout::print_any_labels): Don't colorize the label text for an 23611 event in a diagnostic_path. 23612 (gcc_rich_location::add_location_if_nearby): Add 23613 "restrict_to_current_line_spans" and "label" params. Pass the 23614 former to layout.maybe_add_location_range; pass the latter 23615 when calling add_range. 23616 * diagnostic.c: Include "diagnostic-path.h". 23617 (diagnostic_initialize): Initialize context->path_format and 23618 context->show_path_depths. 23619 (diagnostic_show_any_path): New function. 23620 (diagnostic_path::interprocedural_p): New function. 23621 (diagnostic_report_diagnostic): Call diagnostic_show_any_path. 23622 (simple_diagnostic_path::num_events): New function. 23623 (simple_diagnostic_path::get_event): New function. 23624 (simple_diagnostic_path::add_event): New function. 23625 (simple_diagnostic_event::simple_diagnostic_event): New ctor. 23626 (simple_diagnostic_event::~simple_diagnostic_event): New dtor. 23627 (debug): New overload taking a diagnostic_path *. 23628 * diagnostic.def (DK_DIAGNOSTIC_PATH): New. 23629 * diagnostic.h (enum diagnostic_path_format): New enum. 23630 (json::value): New forward decl. 23631 (diagnostic_context::path_format): New field. 23632 (diagnostic_context::show_path_depths): New field. 23633 (diagnostic_context::print_path): New callback field. 23634 (diagnostic_context::make_json_for_path): New callback field. 23635 (diagnostic_show_any_path): New decl. 23636 (json_from_expanded_location): New decl. 23637 * doc/invoke.texi (-fdiagnostics-path-format=): New option. 23638 (-fdiagnostics-show-path-depths): New option. 23639 (-fdiagnostics-color): Add "path" to description of default 23640 GCC_COLORS; describe it. 23641 (-fdiagnostics-format=json): Document how diagnostic paths are 23642 represented in the JSON output format. 23643 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby): 23644 Add optional params "restrict_to_current_line_spans" and "label". 23645 * opts.c (common_handle_option): Handle 23646 OPT_fdiagnostics_path_format_ and 23647 OPT_fdiagnostics_show_path_depths. 23648 * pretty-print.c: Include "diagnostic-event-id.h". 23649 (pp_format): Implement "%@" format code for printing 23650 diagnostic_event_id_t *. 23651 (selftest::test_pp_format): Add tests for "%@". 23652 * selftest-run-tests.c (selftest::run_tests): Call 23653 selftest::tree_diagnostic_path_cc_tests. 23654 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl. 23655 * toplev.c (general_init): Initialize global_dc->path_format and 23656 global_dc->show_path_depths. 23657 * tree-diagnostic-path.cc: New file. 23658 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make 23659 non-static. Drop "diagnostic" param in favor of storing the 23660 original value of "where" and re-using it. 23661 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of 23662 maybe_unwind_expanded_macro_loc. 23663 (tree_diagnostics_defaults): Initialize context->print_path and 23664 context->make_json_for_path. 23665 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New 23666 decl. 23667 (default_tree_make_json_for_path): New decl. 23668 (maybe_unwind_expanded_macro_loc): New decl. 23669 236702020-01-10 Jakub Jelinek <jakub@redhat.com> 23671 23672 PR tree-optimization/93210 23673 * fold-const.h (native_encode_initializer, 23674 can_native_interpret_type_p): Declare. 23675 * fold-const.c (native_encode_string): Fix up handling with off != -1, 23676 simplify. 23677 (native_encode_initializer): New function, moved from dwarf2out.c. 23678 Adjust to native_encode_expr compatible arguments, including dry-run 23679 and partial extraction modes. Don't handle STRING_CST. 23680 (can_native_interpret_type_p): No longer static. 23681 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify 23682 offset / BITS_PER_UNIT fits into int and don't call it if 23683 can_native_interpret_type_p fails. If suboff is NULL and for 23684 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with 23685 native_encode_initializer. 23686 (fold_const_aggregate_ref_1): Formatting fix. 23687 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c. 23688 (tree_add_const_value_attribute): Adjust caller. 23689 23690 PR tree-optimization/90838 23691 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use 23692 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of 23693 CTZ_DEFINED_VALUE_AT_ZERO. 23694 236952020-01-10 Vladimir Makarov <vmakarov@redhat.com> 23696 23697 PR inline-asm/93027 23698 * lra-constraints.c (match_reload): Permit input operands have the 23699 same mode as output while other input operands have a different 23700 mode. 23701 237022020-01-10 Wilco Dijkstra <wdijkstr@arm.com> 23703 23704 PR tree-optimization/90838 23705 * tree-ssa-forwprop.c (check_ctz_array): Add new function. 23706 (check_ctz_string): Likewise. 23707 (optimize_count_trailing_zeroes): Likewise. 23708 (simplify_count_trailing_zeroes): Likewise. 23709 (pass_forwprop::execute): Try ctz simplification. 23710 * match.pd: Add matching for ctz idioms. 23711 237122020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23713 23714 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function 23715 for target hook. 23716 (aarch64_invalid_unary_op): New function for target hook. 23717 (aarch64_invalid_binary_op): New function for target hook. 23718 237192020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> 23720 23721 * config.gcc: Add arm_bf16.h. 23722 * config/aarch64/aarch64-builtins.c 23723 (aarch64_simd_builtin_std_type): Add BFmode. 23724 (aarch64_init_simd_builtin_types): Define element types for vector 23725 types. 23726 (aarch64_init_bf16_types): New function. 23727 (aarch64_general_init_builtins): Add arm_init_bf16_types function call. 23728 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector 23729 modes. 23730 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types. 23731 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move 23732 patterns. 23733 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF. 23734 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF. 23735 * config/aarch64/aarch64.c 23736 (aarch64_classify_vector_mode): Add support for BF types. 23737 (aarch64_gimplify_va_arg_expr): Add support for BF types. 23738 (aarch64_vq_mode): Add support for BF types. 23739 (aarch64_simd_container_mode): Add support for BF types. 23740 (aarch64_mangle_type): Add support for BF scalar type. 23741 * config/aarch64/aarch64.md: Add BFmode to movhf pattern. 23742 * config/aarch64/arm_bf16.h: New file. 23743 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types. 23744 * config/aarch64/iterators.md: Add BF types to mode attributes. 23745 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New. 23746 237472020-01-10 Jason Merrill <jason@redhat.com> 23748 23749 PR c++/93173 - incorrect tree sharing. 23750 * gimplify.c (copy_if_shared): No longer static. 23751 * gimplify.h: Declare it. 23752 237532020-01-10 Richard Sandiford <richard.sandiford@arm.com> 23754 23755 * doc/invoke.texi (-msve-vector-bits=): Document that 23756 -msve-vector-bits=128 now generates VL-specific code for 23757 little-endian targets. 23758 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use 23759 build_vector_type_for_mode to construct the data vector types. 23760 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate 23761 VL-specific code for -msve-vector-bits=128 on little-endian targets. 23762 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes 23763 for 128-bit vectors. 23764 237652020-01-10 Richard Sandiford <richard.sandiford@arm.com> 23766 23767 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask 23768 invocation. 23769 237702020-01-10 Richard Sandiford <richard.sandiford@arm.com> 23771 23772 * config/aarch64/aarch64-builtins.c 23773 (aarch64_builtin_vectorized_function): Check for specific vector modes, 23774 rather than checking the number of elements and the element mode. 23775 237762020-01-10 Richard Sandiford <richard.sandiford@arm.com> 23777 23778 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use 23779 get_related_vectype_for_scalar_type rather than build_vector_type 23780 to create the index type for a conditional reduction. 23781 237822020-01-10 Richard Sandiford <richard.sandiford@arm.com> 23783 23784 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF 23785 for any type of gather or scatter, including strided accesses. 23786 237872020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com> 23788 23789 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function 23790 comment. 23791 237922020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com> 23793 23794 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use 23795 get_dr_vinfo_offset 23796 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init 23797 parameter and its use to reset DR_OFFSET's. 23798 (vect_transform_loop): Remove orig_drs_init argument. 23799 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset 23800 member of dr_vec_info rather than the offset of the associated 23801 data_reference's innermost_loop_behavior. 23802 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference. 23803 (vect_do_peeling): Remove orig_drs_init parameter and its construction. 23804 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with 23805 get_dr_vinfo_offset. 23806 (vectorizable_store): Likewise. 23807 (vectorizable_load): Likewise. 23808 238092020-01-10 Richard Biener <rguenther@suse.de> 23810 23811 * gimple-ssa-store-merging 23812 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info. 23813 238142020-01-10 Martin Liska <mliska@suse.cz> 23815 23816 PR ipa/93217 23817 * ipa-inline-analysis.c (offline_size): Make proper parenthesis 23818 encapsulation that was there before r280040. 23819 238202020-01-10 Richard Biener <rguenther@suse.de> 23821 23822 PR middle-end/93199 23823 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL 23824 sequences to avoid walking them again for secondary opportunities. 23825 (pass_lower_eh_dispatch::execute): Instead actually insert 23826 them here. 23827 238282020-01-10 Richard Biener <rguenther@suse.de> 23829 23830 PR middle-end/93199 23831 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible. 23832 (cleanup_all_empty_eh): Walk landing pads in reverse order to 23833 avoid quadraticness. 23834 238352020-01-10 Martin Jambor <mjambor@suse.cz> 23836 23837 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization. 23838 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it 23839 to get param_ipa_sra_max_replacements. 23840 (param_splitting_across_edge): Pass the caller to 23841 pull_accesses_from_callee. 23842 238432020-01-10 Martin Jambor <mjambor@suse.cz> 23844 23845 * params.opt (param_ipcp_unit_growth): Mark as Optimization. 23846 * ipa-cp.c (max_new_size): Removed. 23847 (orig_overall_size): New variable. 23848 (get_max_overall_size): New function. 23849 (estimate_local_effects): Use it. Adjust dump. 23850 (decide_about_value): Likewise. 23851 (ipcp_propagate_stage): Do not calculate max_new_size, just store 23852 orig_overall_size. Adjust dump. 23853 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size. 23854 238552020-01-10 Martin Jambor <mjambor@suse.cz> 23856 23857 * params.opt (param_ipa_max_agg_items): Mark as Optimization 23858 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use 23859 instead of param_ipa_max_agg_items. 23860 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from 23861 optimization info for the callee. 23862 238632020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com> 23864 23865 * lto-streamer-in.c (input_function): Remove streamed-in inline debug 23866 markers if debug_inline_points is false. 23867 238682020-01-09 Richard Sandiford <richard.sandiford@arm.com> 23869 23870 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to 23871 extra_objs. 23872 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on 23873 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and 23874 aarch64-sve-builtins-sve2.h. 23875 (aarch64-sve-builtins-sve2.o): New rule. 23876 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro. 23877 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise. 23878 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise. 23879 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise. 23880 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle 23881 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and 23882 TARGET_SVE2_SM4. 23883 * config/aarch64/aarch64-sve.md: Update comments with SVE2 23884 instructions that are handled here. 23885 (@cond_asrd<mode>): Generalize to... 23886 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this. 23887 (*cond_asrd<mode>_2): Generalize to... 23888 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this. 23889 (*cond_asrd<mode>_z): Generalize to... 23890 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this. 23891 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec. 23892 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise. 23893 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise. 23894 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New 23895 pattern. 23896 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) 23897 (@aarch64_scatter_stnt<mode>): Likewise. 23898 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>) 23899 (@aarch64_mul_lane_<mode>): Likewise. 23900 (@aarch64_sve_suqadd<mode>_const): Likewise. 23901 (*<sur>h<addsub><mode>): Generalize to... 23902 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this 23903 new pattern. 23904 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander. 23905 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern. 23906 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise. 23907 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise. 23908 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise. 23909 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise. 23910 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise. 23911 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise. 23912 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander. 23913 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern. 23914 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise. 23915 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise. 23916 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise. 23917 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>) 23918 (@aarch64_sve_add_mul_lane_<mode>): Likewise. 23919 (@aarch64_sve_sub_mul_lane_<mode>): Likewise. 23920 (@aarch64_sve2_xar<mode>): Likewise. 23921 (@aarch64_sve2_bcax<mode>): Likewise. 23922 (*aarch64_sve2_eor3<mode>): Rename to... 23923 (@aarch64_sve2_eor3<mode>): ...this. 23924 (@aarch64_sve2_bsl<mode>): New expander. 23925 (@aarch64_sve2_nbsl<mode>): Likewise. 23926 (@aarch64_sve2_bsl1n<mode>): Likewise. 23927 (@aarch64_sve2_bsl2n<mode>): Likewise. 23928 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise. 23929 (*aarch64_sve2_sra<mode>): Add MOVPRFX support. 23930 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern. 23931 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise. 23932 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander. 23933 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern. 23934 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise. 23935 (<su>mull<bt><Vwide>): Generalize to... 23936 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new 23937 pattern. 23938 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>) 23939 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>) 23940 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>) 23941 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 23942 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>) 23943 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 23944 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>) 23945 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 23946 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>) 23947 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>) 23948 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns. 23949 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>) 23950 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise. 23951 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise. 23952 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise. 23953 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise. 23954 (<SHRNB:r>shrnb<mode>): Generalize to... 23955 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this 23956 new pattern. 23957 (<SHRNT:r>shrnt<mode>): Generalize to... 23958 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this 23959 new pattern. 23960 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern. 23961 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise. 23962 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander. 23963 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern. 23964 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise. 23965 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise. 23966 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise. 23967 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise. 23968 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise. 23969 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise. 23970 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise. 23971 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander. 23972 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern. 23973 (@aarch64_sve2_cvtnt<mode>): Likewise. 23974 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise. 23975 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander. 23976 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern. 23977 (@aarch64_sve2_cvtxnt<mode>): Likewise. 23978 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise. 23979 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander. 23980 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern. 23981 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise. 23982 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander. 23983 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern. 23984 (@aarch64_sve2_pmul<mode>): Likewise. 23985 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise. 23986 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise. 23987 (@aarch64_sve2_tbl2<mode>): Likewise. 23988 (@aarch64_sve2_tbx<mode>): Likewise. 23989 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise. 23990 (@aarch64_sve2_histcnt<mode>): Likewise. 23991 (@aarch64_sve2_histseg<mode>): Likewise. 23992 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise. 23993 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise. 23994 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise. 23995 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise. 23996 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise. 23997 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise. 23998 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise. 23999 (<su>mulh<r>s<mode>3): Update after above pattern name changes. 24000 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY) 24001 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI) 24002 (SVE2_PMULL_PAIR_I): New mode iterators. 24003 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP) 24004 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT) 24005 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA) 24006 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT) 24007 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT) 24008 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP) 24009 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT) 24010 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP) 24011 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH) 24012 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR) 24013 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT) 24014 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB) 24015 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT) 24016 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP) 24017 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT) 24018 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90) 24019 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB) 24020 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB) 24021 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB) 24022 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB) 24023 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT) 24024 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB) 24025 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT) 24026 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT) 24027 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT) 24028 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT) 24029 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT) 24030 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs. 24031 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT) 24032 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS) 24033 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move 24034 further down file. 24035 (VNARROW, Ventype): New mode attributes. 24036 (Vewtype): Handle VNx2DI. Fix typo in comment. 24037 (VDOUBLE): New mode attribute. 24038 (sve_lane_con): Handle VNx8HI. 24039 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2. 24040 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus. 24041 (sve_int_op, sve_int_op_rev): Handle the above codes. 24042 (sve_pred_int_rhs2_operand): Likewise. 24043 (MULLBT, SHRNB, SHRNT): Delete. 24044 (SVE_INT_SHIFT_IMM): New int iterator. 24045 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI 24046 and UNSPEC_WHILEHS for TARGET_SVE2. 24047 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT) 24048 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG) 24049 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB) 24050 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR) 24051 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators. 24052 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise. 24053 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD) 24054 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise. 24055 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA) 24056 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG) 24057 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise. 24058 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE) 24059 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE) 24060 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise. 24061 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise. 24062 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise. 24063 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise. 24064 (optab): Handle the new unspecs. 24065 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB 24066 and UNSPEC_RSHRNT. 24067 (lr): Handle the new unspecs. 24068 (bt): Delete. 24069 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs. 24070 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op) 24071 (sve_int_qsub_op): New int attributes. 24072 (sve_fp_op, rot): Handle the new unspecs. 24073 * config/aarch64/aarch64-sve-builtins.h 24074 (function_resolver::require_matching_pointer_type): Declare. 24075 (function_resolver::resolve_unary): Add an optional boolean argument. 24076 (function_resolver::finish_opt_n_resolution): Add an optional 24077 type_suffix_index argument. 24078 (gimple_folder::redirect_call): Declare. 24079 (gimple_expander::prepare_gather_address_operands): Add an optional 24080 bool parameter. 24081 * config/aarch64/aarch64-sve-builtins.cc: Include 24082 aarch64-sve-builtins-sve2.h. 24083 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros. 24084 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise. 24085 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise. 24086 (TYPES_hsd_integer): Use TYPES_hsd_signed. 24087 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros. 24088 (TYPES_s_unsigned): Likewise. 24089 (TYPES_s_integer): Use TYPES_s_unsigned. 24090 (TYPES_sd_signed, TYPES_sd_unsigned): New macros. 24091 (TYPES_sd_integer): Use them. 24092 (TYPES_d_unsigned): New macro. 24093 (TYPES_d_integer): Use it. 24094 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros. 24095 (TYPES_cvt_narrow): Likewise. 24096 (DEF_SVE_TYPES_ARRAY): Include the new types macros above. 24097 (preds_mx): New variable. 24098 (function_builder::add_overloaded_function): Allow the new feature 24099 set to be more restrictive than the original one. 24100 (function_resolver::infer_pointer_type): Remove qualifiers from 24101 the pointer type before printing it. 24102 (function_resolver::require_matching_pointer_type): New function. 24103 (function_resolver::resolve_sv_displacement): Handle functions 24104 that don't support 32-bit vector indices or svint32_t vector offsets. 24105 (function_resolver::finish_opt_n_resolution): Take the inferred type 24106 as a separate argument. 24107 (function_resolver::resolve_unary): Optionally treat all forms in 24108 the same way as normal merging functions. 24109 (gimple_folder::redirect_call): New function. 24110 (function_expander::prepare_gather_address_operands): Add an argument 24111 that says whether scaled forms are available. If they aren't, 24112 handle scaling of vector indices and don't add the extension and 24113 scaling operands. 24114 (function_expander::map_to_unspecs): If aarch64_sve isn't available, 24115 fall back to using cond_* instead. 24116 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function): 24117 Split out the member variables into... 24118 (rtx_code_function_base): ...this new base class. 24119 (rtx_code_function_rotated): Inherit rtx_code_function_base. 24120 (unspec_based_function): Split out the member variables into... 24121 (unspec_based_function_base): ...this new base class. 24122 (unspec_based_function_rotated): Inherit unspec_based_function_base. 24123 (unspec_based_function_exact_insn): New class. 24124 (unspec_based_add_function, unspec_based_add_lane_function) 24125 (unspec_based_lane_function, unspec_based_pred_function) 24126 (unspec_based_qadd_function, unspec_based_qadd_lane_function) 24127 (unspec_based_qsub_function, unspec_based_qsub_lane_function) 24128 (unspec_based_sub_function, unspec_based_sub_lane_function): New 24129 typedefs. 24130 (unspec_based_fused_function): New class. 24131 (unspec_based_mla_function, unspec_based_mls_function): New typedefs. 24132 (unspec_based_fused_lane_function): New class. 24133 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New 24134 typedefs. 24135 (CODE_FOR_MODE1): New macro. 24136 (fixed_insn_function): New class. 24137 (while_comparison): Likewise. 24138 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane) 24139 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n) 24140 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr) 24141 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted) 24142 (load_gather_sv_restricted, shift_left_imm_long): Declare. 24143 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise. 24144 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise. 24145 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted) 24146 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane) 24147 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate) 24148 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint) 24149 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt) 24150 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise. 24151 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication): 24152 Also add an initial argument for unary_convert_narrowt, regardless 24153 of the predication type. 24154 (build_32_64): Allow loads and stores to specify MODE_none. 24155 (build_sv_index64, build_sv_uint_offset): New functions. 24156 (long_type_suffix): New function. 24157 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes. 24158 (binary_imm_long_base, load_gather_sv_base): Likewise. 24159 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise. 24160 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise. 24161 (unary_narrowb_base, unary_narrowt_base): Likewise. 24162 (binary_long_lane_def, binary_long_lane): New shape. 24163 (binary_long_opt_n_def, binary_long_opt_n): Likewise. 24164 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise. 24165 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise. 24166 (binary_to_uint_def, binary_to_uint): Likewise. 24167 (binary_wide_def, binary_wide): Likewise. 24168 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise. 24169 (compare_def, compare): Likewise. 24170 (compare_ptr_def, compare_ptr): Likewise. 24171 (load_ext_gather_index_restricted_def, 24172 load_ext_gather_index_restricted): Likewise. 24173 (load_ext_gather_offset_restricted_def, 24174 load_ext_gather_offset_restricted): Likewise. 24175 (load_gather_sv_def): Inherit from load_gather_sv_base. 24176 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape. 24177 (shift_left_imm_def, shift_left_imm): Likewise. 24178 (shift_left_imm_long_def, shift_left_imm_long): Likewise. 24179 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise. 24180 (store_scatter_index_restricted_def, 24181 store_scatter_index_restricted): Likewise. 24182 (store_scatter_offset_restricted_def, 24183 store_scatter_offset_restricted): Likewise. 24184 (tbl_tuple_def, tbl_tuple): Likewise. 24185 (ternary_long_lane_def, ternary_long_lane): Likewise. 24186 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise. 24187 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base. 24188 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape 24189 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base. 24190 (ternary_qq_rotate_def, ternary_qq_rotate): New shape. 24191 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise. 24192 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise. 24193 (ternary_uint_def, ternary_uint): Likewise. 24194 (unary_convert): Fix typo in comment. 24195 (unary_convert_narrowt_def, unary_convert_narrowt): New shape. 24196 (unary_long_def, unary_long): Likewise. 24197 (unary_narrowb_def, unary_narrowb): Likewise. 24198 (unary_narrowt_def, unary_narrowt): Likewise. 24199 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise. 24200 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise. 24201 (unary_to_int_def, unary_to_int): Likewise. 24202 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla) 24203 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions. 24204 (svasrd_impl): Delete. 24205 (svcadd_impl::expand): Handle integer operations too. 24206 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the 24207 new functions to derive the unspec numbers. 24208 (svmla_svmls_lane_impl): Replace with... 24209 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle 24210 integer operations too. 24211 (svwhile_impl): Rename to... 24212 (svwhilelx_impl): ...this and inherit from while_comparison. 24213 (svasrd): Use unspec_based_function. 24214 (svmla_lane): Use svmla_lane_impl. 24215 (svmls_lane): Use svmls_lane_impl. 24216 (svrecpe, svrsqrte): Handle unsigned integer operations too. 24217 (svwhilele, svwhilelt): Use svwhilelx_impl. 24218 * config/aarch64/aarch64-sve-builtins-sve2.h: New file. 24219 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. 24220 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. 24221 * config/aarch64/aarch64-sve-builtins.def: Include 24222 aarch64-sve-builtins-sve2.def. 24223 242242020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24225 24226 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p) 24227 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument. 24228 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p) 24229 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar 24230 immediates as well as vector ones. 24231 * config/aarch64/predicates.md (aarch64_sve_arith_immediate) 24232 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate) 24233 (aarch64_sve_qsub_immediate): Update calls accordingly. 24234 242352020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24236 24237 * config/aarch64/aarch64-sve2.md: Add banner comments. 24238 (<su>mulh<r>s<mode>3): Move further up file. 24239 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>) 24240 (*aarch64_sve2_sra<mode>): Move further down file. 24241 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. 24242 242432020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24244 24245 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW 24246 and UNSPEC_WHILEWR. 24247 (while_optab_cmp): Handle them. 24248 * config/aarch64/aarch64-sve.md 24249 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public 24250 and add a "@" marker. 24251 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it 24252 instead of gen_aarch64_sve2_while_ptest. 24253 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete. 24254 242552020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24256 24257 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... 24258 (UNSPEC_WHILELE): ...this. 24259 (UNSPEC_WHILE_LO): Rename to... 24260 (UNSPEC_WHILELO): ...this. 24261 (UNSPEC_WHILE_LS): Rename to... 24262 (UNSPEC_WHILELS): ...this. 24263 (UNSPEC_WHILE_LT): Rename to... 24264 (UNSPEC_WHILELT): ...this. 24265 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. 24266 (cmp_op, while_optab_cmp): Likewise. 24267 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. 24268 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. 24269 (svwhilelt): Likewise. 24270 242712020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24272 24273 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete. 24274 (unary_to_uint): Define. 24275 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def) 24276 (unary_count): Rename to... 24277 (unary_to_uint_def, unary_to_uint): ...this. 24278 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly. 24279 242802020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24281 24282 * config/aarch64/aarch64-sve-builtins-functions.h 24283 (code_for_mode_function): New class. 24284 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros. 24285 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl) 24286 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete. 24287 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0. 24288 (svmul_lane, svtmad): Use CODE_FOR_MODE0. 24289 242902020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24291 24292 * config/aarch64/iterators.md (addsub): New code attribute. 24293 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>): 24294 Re-express as... 24295 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change 24296 in the asm string and attributes. Fix indentation. 24297 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>): 24298 Re-express as... 24299 (@aarch64_sve_<optab><mode>): ...this. 24300 * config/aarch64/aarch64-sve-builtins.h 24301 (function_expander::expand_signed_unpred_op): Delete. 24302 * config/aarch64/aarch64-sve-builtins.cc 24303 (function_expander::expand_signed_unpred_op): Likewise. 24304 (function_expander::map_to_rtx_codes): If the optab isn't defined, 24305 try using code_for_aarch64_sve instead. 24306 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete. 24307 (svqsub_impl): Likewise. 24308 (svqadd, svqsub): Use rtx_code_function instead. 24309 243102020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24311 24312 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete. 24313 (HADDSUB, sur, addsub): Remove them. 24314 243152020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24316 24317 * tree-nrv.c (pass_return_slot::execute): Handle all internal 24318 functions the same way, rather than singling out those that 24319 aren't mapped directly to optabs. 24320 243212020-01-09 Richard Sandiford <richard.sandiford@arm.com> 24322 24323 * target.def (compatible_vector_types_p): New target hook. 24324 * hooks.h (hook_bool_const_tree_const_tree_true): Declare. 24325 * hooks.c (hook_bool_const_tree_const_tree_true): New function. 24326 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook. 24327 * doc/tm.texi: Regenerate. 24328 * gimple-expr.c: Include target.h. 24329 (useless_type_conversion_p): Use targetm.compatible_vector_types_p. 24330 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New 24331 function. 24332 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define. 24333 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred): 24334 Use the original predicate if it already has a suitable type. 24335 243362020-01-09 Martin Jambor <mjambor@suse.cz> 24337 24338 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct, 24339 resolve_speculation and redirect_call_stmt_to_callee static. Change 24340 return type of set_call_stmt to cgraph_edge *. 24341 * auto-profile.c (afdo_indirect_call): Adjust call to 24342 redirect_call_stmt_to_callee. 24343 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *, 24344 make the this pointer explicit, adjust self-recursive calls and the 24345 call top make_direct. Return the resulting edge. 24346 (cgraph_edge::remove): Make this pointer explicit. 24347 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove. 24348 (cgraph_edge::make_direct): Likewise, adjust call to 24349 resolve_speculation. 24350 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust 24351 call to set_call_stmt. 24352 (cgraph_update_edges_for_call_stmt_node): Update call to 24353 set_call_stmt and remove. 24354 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): 24355 Renamed edge to master_edge. Adjusted calls to set_call_stmt. 24356 (cgraph_node::create_edge_including_clones): Moved "first" definition 24357 of edge to the block where it was used. Adjusted calls to 24358 set_call_stmt. 24359 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to 24360 cgraph_edge::remove. 24361 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to 24362 make_direct and redirect_call_stmt_to_callee. 24363 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to 24364 resolve_speculation and make_direct. 24365 * ipa-inline-transform.c (inline_transform): Adjust call to 24366 redirect_call_stmt_to_callee. 24367 (check_speculations_1):: Adjust call to resolve_speculation. 24368 * ipa-inline.c (resolve_noninline_speculation): Adjust call to 24369 resolve-speculation. 24370 (inline_small_functions): Adjust call to resolve_speculation. 24371 (ipa_inline): Likewise. 24372 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to 24373 make_direct. 24374 * ipa-visibility.c (function_and_variable_visibility): Make iteration 24375 safe with regards to edge removal, adjust calls to 24376 redirect_call_stmt_to_callee. 24377 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct 24378 and redirect_call_stmt_to_callee. 24379 * multiple_target.c (create_dispatcher_calls): Adjust call to 24380 redirect_call_stmt_to_callee 24381 (redirect_to_specific_clone): Likewise. 24382 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph): 24383 Adjust calls to cgraph_edge::remove. 24384 * tree-inline.c (copy_bb): Adjust call to set_call_stmt. 24385 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee. 24386 (expand_call_inline): Adjust call to cgraph_edge::remove. 24387 243882020-01-09 Martin Liska <mliska@suse.cz> 24389 24390 * params.opt: Set Optimization for 24391 param_max_speculative_devirt_maydefs. 24392 243932020-01-09 Martin Sebor <msebor@redhat.com> 24394 24395 PR middle-end/93200 24396 PR fortran/92956 24397 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type. 24398 243992020-01-09 Martin Liska <mliska@suse.cz> 24400 24401 * auto-profile.c (auto_profile): Use opt_for_fn 24402 for a parameter. 24403 * ipa-cp.c (ipcp_lattice::add_value): Likewise. 24404 (propagate_vals_across_arith_jfunc): Likewise. 24405 (hint_time_bonus): Likewise. 24406 (incorporate_penalties): Likewise. 24407 (good_cloning_opportunity_p): Likewise. 24408 (perform_estimation_of_a_value): Likewise. 24409 (estimate_local_effects): Likewise. 24410 (ipcp_propagate_stage): Likewise. 24411 * ipa-fnsummary.c (decompose_param_expr): Likewise. 24412 (set_switch_stmt_execution_predicate): Likewise. 24413 (analyze_function_body): Likewise. 24414 * ipa-inline-analysis.c (offline_size): Likewise. 24415 * ipa-inline.c (early_inliner): Likewise. 24416 * ipa-prop.c (ipa_analyze_node): Likewise. 24417 (ipcp_transform_function): Likewise. 24418 * ipa-sra.c (process_scan_results): Likewise. 24419 (ipa_sra_summarize_function): Likewise. 24420 * params.opt: Rename ipcp-unit-growth to 24421 ipa-cp-unit-growth. Add Optimization for various 24422 IPA-related parameters. 24423 244242020-01-09 Richard Biener <rguenther@suse.de> 24425 24426 PR middle-end/93054 24427 * gimplify.c (gimplify_expr): Deal with NOP definitions. 24428 244292020-01-09 Richard Biener <rguenther@suse.de> 24430 24431 PR tree-optimization/93040 24432 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit. 24433 244342020-01-09 Georg-Johann Lay <avr@gjlay.de> 24435 24436 * common/config/avr/avr-common.c (avr_option_optimization_table) 24437 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early. 24438 244392020-01-09 Martin Liska <mliska@suse.cz> 24440 24441 * cgraphclones.c (symbol_table::materialize_all_clones): 24442 Use cgraph_node::dump_name. 24443 244442020-01-09 Jakub Jelinek <jakub@redhat.com> 24445 24446 PR inline-asm/93202 24447 * config/riscv/riscv.c (riscv_print_operand_reloc): Use 24448 output_operand_lossage instead of gcc_unreachable. 24449 * doc/md.texi (riscv f constraint): Fix typo. 24450 24451 PR target/93141 24452 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of 24453 SWI. Use <general_hilo_operand> instead of <general_operand>. Use 24454 CONST_SCALAR_INT_P instead of CONST_INT_P. 24455 (*subv<mode>4_1): Rename to ... 24456 (subv<mode>4_1): ... this. 24457 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New 24458 define_insn_and_split patterns. 24459 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn 24460 patterns. 24461 244622020-01-08 David Malcolm <dmalcolm@redhat.com> 24463 24464 * vec.c (class selftest::count_dtor): New class. 24465 (selftest::test_auto_delete_vec): New test. 24466 (selftest::vec_c_tests): Call it. 24467 * vec.h (class auto_delete_vec): New class template. 24468 (auto_delete_vec<T>::~auto_delete_vec): New dtor. 24469 244702020-01-08 David Malcolm <dmalcolm@redhat.com> 24471 24472 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap. 24473 244742020-01-08 Jim Wilson <jimw@sifive.com> 24475 24476 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out 24477 use of TLS_MODEL_LOCAL_EXEC when not pic. 24478 244792020-01-08 David Malcolm <dmalcolm@redhat.com> 24480 24481 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix 24482 memory leak. 24483 244842020-01-08 Jakub Jelinek <jakub@redhat.com> 24485 24486 PR target/93187 24487 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2, 24488 *stack_protect_set_3 peephole2): Also check that the second 24489 insns source is general_operand. 24490 24491 PR target/93174 24492 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand 24493 predicate for output operand instead of register_operand. 24494 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with 24495 memory destination and non-memory operands[2]. 24496 244972020-01-08 Martin Liska <mliska@suse.cz> 24498 24499 * cgraph.c (cgraph_node::dump): Use ::dump_name or 24500 ::dump_asm_name instead of (::name or ::asm_name). 24501 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise. 24502 * cgraphunit.c (walk_polymorphic_call_targets): Likewise. 24503 (analyze_functions): Likewise. 24504 (expand_all_functions): Likewise. 24505 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise. 24506 (propagate_bits_across_jump_function): Likewise. 24507 (dump_profile_updates): Likewise. 24508 (ipcp_store_bits_results): Likewise. 24509 (ipcp_store_vr_results): Likewise. 24510 * ipa-devirt.c (dump_targets): Likewise. 24511 * ipa-fnsummary.c (analyze_function_body): Likewise. 24512 * ipa-hsa.c (check_warn_node_versionable): Likewise. 24513 (process_hsa_functions): Likewise. 24514 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise. 24515 (set_alias_uids): Likewise. 24516 * ipa-inline-transform.c (save_inline_function_body): Likewise. 24517 * ipa-inline.c (recursive_inlining): Likewise. 24518 (inline_to_all_callers_1): Likewise. 24519 (ipa_inline): Likewise. 24520 * ipa-profile.c (ipa_propagate_frequency_1): Likewise. 24521 (ipa_propagate_frequency): Likewise. 24522 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise. 24523 (remove_described_reference): Likewise. 24524 * ipa-pure-const.c (worse_state): Likewise. 24525 (check_retval_uses): Likewise. 24526 (analyze_function): Likewise. 24527 (propagate_pure_const): Likewise. 24528 (propagate_nothrow): Likewise. 24529 (dump_malloc_lattice): Likewise. 24530 (propagate_malloc): Likewise. 24531 (pass_local_pure_const::execute): Likewise. 24532 * ipa-visibility.c (optimize_weakref): Likewise. 24533 (function_and_variable_visibility): Likewise. 24534 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise. 24535 (ipa_discover_variable_flags): Likewise. 24536 * lto-streamer-out.c (output_function): Likewise. 24537 (output_constructor): Likewise. 24538 * tree-inline.c (copy_bb): Likewise. 24539 * tree-ssa-structalias.c (ipa_pta_execute): Likewise. 24540 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise. 24541 245422020-01-08 Richard Biener <rguenther@suse.de> 24543 24544 PR middle-end/93199 24545 * tree-eh.c (sink_clobbers): Update virtual operands for 24546 the first and last stmt only. Add a dry-run capability. 24547 (pass_lower_eh_dispatch::execute): Perform clobber sinking 24548 after CFG manipulations and in RPO order to catch all 24549 secondary opportunities reliably. 24550 245512020-01-08 Georg-Johann Lay <avr@gjlay.de> 24552 24553 PR target/93182 24554 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 24555 245562019-01-08 Richard Biener <rguenther@suse.de> 24557 24558 PR middle-end/93199 24559 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified. 24560 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust 24561 virtual operand, also updating SSA use. 24562 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction): 24563 Update stmt after resetting virtual operand. 24564 (tree_loop_interchange::move_code_to_inner_loop): Likewise. 24565 * gimple-iterator.c (gsi_remove): When not removing the stmt 24566 permanently do not delink immediate uses or mark the stmt modified. 24567 245682020-01-08 Martin Liska <mliska@suse.cz> 24569 24570 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name. 24571 (ipa_call_context::estimate_size_and_time): Likewise. 24572 (inline_analyze_function): Likewise. 24573 245742020-01-08 Martin Liska <mliska@suse.cz> 24575 24576 * cgraph.c (cgraph_node::dump): Use systematically 24577 dump_asm_name. 24578 245792020-01-08 Georg-Johann Lay <avr@gjlay.de> 24580 24581 Add -nodevicespecs option for avr. 24582 24583 PR target/93182 24584 * config/avr/avr.opt (-nodevicespecs): New driver option. 24585 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue 24586 "-specs=device-specs/..." if that option is not set. 24587 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 24588 245892020-01-08 Georg-Johann Lay <avr@gjlay.de> 24590 24591 Implement 64-bit double functions for avr. 24592 24593 PR target/92055 24594 * config.gcc (tm_defines) [target=avr]: Support --with-libf7, 24595 --with-double-comparison. 24596 * doc/install.texi: Document them. 24597 * config/avr/avr-c.c (avr_cpu_cpp_builtins) 24598 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS> 24599 <WITH_DOUBLE_COMPARISON>: New built-in defines. 24600 * doc/invoke.texi (AVR Built-in Macros): Document them. 24601 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New. 24602 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function. 24603 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro. 24604 246052020-01-08 Richard Earnshaw <rearnsha@arm.com> 24606 24607 PR target/93188 24608 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match 24609 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants 24610 when only building rm-profile multilibs. 24611 246122020-01-08 Feng Xue <fxue@os.amperecomputing.com> 24613 24614 PR ipa/93084 24615 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate 24616 lattice for a value to check. 24617 (propagate_vals_across_arith_jfunc): Add an assertion to ensure 24618 finite propagation in self-recursive scc. 24619 246202020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com> 24621 24622 * ipa-inline.c (caller_growth_limits): Restore the AND. 24623 246242020-01-07 Andrew Stubbs <ams@codesourcery.com> 24625 24626 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator. 24627 (VEC_ALLREG_ALT): New iterator. 24628 (VEC_ALLREG_INT_MODE): New iterator. 24629 (VCMP_MODE): New iterator. 24630 (VCMP_MODE_INT): New iterator. 24631 (vec_cmpu<mode>di): Use VCMP_MODE_INT. 24632 (vec_cmp<u>v64qidi): New define_expand. 24633 (vec_cmp<mode>di_exec): Use VCMP_MODE. 24634 (vec_cmpu<mode>di_exec): New define_expand. 24635 (vec_cmp<u>v64qidi_exec): New define_expand. 24636 (vec_cmp<mode>di_dup): Use VCMP_MODE. 24637 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE. 24638 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ... 24639 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this. 24640 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ... 24641 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this. 24642 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ... 24643 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this. 24644 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ... 24645 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to 24646 this. 24647 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes. 24648 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend. 24649 246502020-01-07 Andrew Stubbs <ams@codesourcery.com> 24651 24652 * config/gcn/constraints.md (DA): Update description and match. 24653 (DB): Likewise. 24654 (Db): New constraint. 24655 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second 24656 parameter. 24657 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter. 24658 Implement 'Db' mixed immediate type. 24659 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints. 24660 (addcv64si3_dup<exec_vcc>): Delete. 24661 (subcv64si3<exec_vcc>): Rework constraints. 24662 (addv64di3): Rework constraints. 24663 (addv64di3_exec): Rework constraints. 24664 (subv64di3): Rework constraints. 24665 (addv64di3_dup): Delete. 24666 (addv64di3_dup_exec): Delete. 24667 (addv64di3_zext): Rework constraints. 24668 (addv64di3_zext_exec): Rework constraints. 24669 (addv64di3_zext_dup): Rework constraints. 24670 (addv64di3_zext_dup_exec): Rework constraints. 24671 (addv64di3_zext_dup2): Rework constraints. 24672 (addv64di3_zext_dup2_exec): Rework constraints. 24673 (addv64di3_sext_dup2): Rework constraints. 24674 (addv64di3_sext_dup2_exec): Rework constraints. 24675 246762020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com> 24677 24678 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented 24679 existing target checks. 24680 246812020-01-07 Richard Biener <rguenther@suse.de> 24682 24683 * doc/install.texi: Bump minimal supported MPC version. 24684 246852020-01-07 Richard Sandiford <richard.sandiford@arm.com> 24686 24687 * langhooks-def.h (lhd_simulate_enum_decl): Declare. 24688 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it. 24689 * langhooks.c: Include stor-layout.h. 24690 (lhd_simulate_enum_decl): New function. 24691 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call 24692 handle_arm_sve_h for the LTO frontend. 24693 (register_vector_type): Cope with null returns from pushdecl. 24694 246952020-01-07 Richard Sandiford <richard.sandiford@arm.com> 24696 24697 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p) 24698 (aarch64_sve::nvectors_if_data_type): Replace with... 24699 (aarch64_sve::builtin_type_p): ...this. 24700 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h. 24701 (find_vector_type): Delete. 24702 (add_sve_type_attribute): New function. 24703 (lookup_sve_type_attribute): Likewise. 24704 (register_builtin_types): Add an "SVE type" attribute to each type. 24705 (register_tuple_type): Likewise. 24706 (svbool_type_p, nvectors_if_data_type): Delete. 24707 (mangle_builtin_type): Use lookup_sve_type_attribute. 24708 (builtin_type_p): Likewise. Add an overload that returns the 24709 number of constituent vector and predicate registers. 24710 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete. 24711 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p 24712 instead of aarch64_sve_argument_p. 24713 (aarch64_takes_arguments_in_sve_regs_p): Likewise. 24714 (aarch64_pass_by_reference): Likewise. 24715 (aarch64_function_value_1): Likewise. 24716 (aarch64_return_in_memory): Likewise. 24717 (aarch64_layout_arg): Likewise. 24718 247192020-01-07 Jakub Jelinek <jakub@redhat.com> 24720 24721 PR tree-optimization/93156 24722 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second 24723 least significant bit is always clear. 24724 24725 PR tree-optimization/93118 24726 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new 24727 simplifier with two intermediate conversions. 24728 247292020-01-07 Martin Liska <mliska@suse.cz> 24730 24731 * params.opt: Add Optimization for various parameters. 24732 247332020-01-07 Martin Liska <mliska@suse.cz> 24734 24735 PR ipa/83411 24736 * doc/extend.texi: Explain cloning for target_clone 24737 attribute. 24738 247392020-01-07 Martin Liska <mliska@suse.cz> 24740 24741 PR tree-optimization/92860 24742 * common.opt: Make in Optimization option 24743 as it is affected by -O0, which is an Optimization 24744 option. 24745 * tree-inline.c (tree_inlinable_function_p): 24746 Use opt_for_fn for warn_inline. 24747 (expand_call_inline): Likewise. 24748 247492020-01-07 Martin Liska <mliska@suse.cz> 24750 24751 PR tree-optimization/92860 24752 * common.opt: Make flag_ree as optimization 24753 attribute. 24754 247552020-01-07 Martin Liska <mliska@suse.cz> 24756 24757 PR optimization/92860 24758 * params.opt: Mark param_min_crossjump_insns with Optimization 24759 keyword. 24760 247612020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com> 24762 24763 * ipa-inline-analysis.c (estimate_growth): Fix typo. 24764 * ipa-inline.c (caller_growth_limits): Use OR instead of AND. 24765 247662020-01-06 Michael Meissner <meissner@linux.ibm.com> 24767 24768 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New 24769 helper function to return the valid addressing formats for a given 24770 hard register and mode. 24771 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask. 24772 24773 * config/rs6000/constraints.md (Q constraint): Update 24774 documentation. 24775 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint 24776 documentation. 24777 24778 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator): 24779 Use 'Q' for doing vector extract from memory. 24780 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from 24781 memory. 24782 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for 24783 doing vector extract from memory. 24784 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector 24785 extract from memory. 24786 24787 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support 24788 for the offset being 34-bits when -mcpu=future is used. 24789 247902020-01-06 John David Anglin <danglin@gcc.gnu.org> 24791 24792 * config/pa/pa.md: Revert change to use ordered_comparison_operator 24793 instead of cmpib_comparison_operator in cmpib patterns. 24794 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal 24795 of cmpib_comparison_operator. Revise comment. 24796 247972020-01-06 Richard Sandiford <richard.sandiford@arm.com> 24798 24799 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts 24800 in an IFN_DIV_POW2 node to be equal. 24801 248022020-01-06 Richard Sandiford <richard.sandiford@arm.com> 24803 24804 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to... 24805 (vect_check_scalar_mask): ...this. 24806 (vectorizable_store, vectorizable_load): Update call accordingly. 24807 (vectorizable_call): Use vect_check_scalar_mask to check the mask 24808 argument in calls to conditional internal functions. 24809 248102020-01-06 Andrew Stubbs <ams@codesourcery.com> 24811 24812 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for 24813 '0' matching inputs. 24814 (subv64di3_exec): Likewise. 24815 248162020-01-06 Bryan Stenson <bryan@siliconvortex.com> 24817 24818 * config/mips/mips.c (vr4130_align_insns): Fix typo. 24819 * doc/md.texi (movstr): Likewise. 24820 248212020-01-06 Andrew Stubbs <ams@codesourcery.com> 24822 24823 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early 24824 clobber. 24825 248262020-01-06 Richard Sandiford <richard.sandiford@arm.com> 24827 24828 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md): 24829 Depend on... 24830 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents 24831 to a temporary file and use move-if-change to update the real 24832 file where necessary. 24833 248342020-01-06 Richard Sandiford <richard.sandiford@arm.com> 24835 24836 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl 24837 rather than Upa for CPY /M. 24838 248392020-01-06 Andrew Stubbs <ams@codesourcery.com> 24840 24841 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline 24842 immediate. 24843 248442020-01-06 Martin Liska <mliska@suse.cz> 24845 24846 PR tree-optimization/92860 24847 * params.opt: Mark param_max_combine_insns with Optimization 24848 keyword. 24849 248502020-01-05 Jakub Jelinek <jakub@redhat.com> 24851 24852 PR target/93141 24853 * config/i386/i386.md (SWIDWI): New mode iterator. 24854 (DWI, dwi): Add TImode variants. 24855 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use 24856 <general_hilo_operand> instead of <general_operand>. Use 24857 CONST_SCALAR_INT_P instead of CONST_INT_P. 24858 (*addv<mode>4_1): Rename to ... 24859 (addv<mode>4_1): ... this. 24860 (QWI): New mode attribute. 24861 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New 24862 define_insn_and_split patterns. 24863 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn 24864 patterns. 24865 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use 24866 <general_hilo_operand> instead of <general_operand>. 24867 (*addcarry<mode>_1): New define_insn. 24868 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split. 24869 248702020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru> 24871 24872 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm): 24873 Use "call" instead of "set". 24874 248752020-01-03 Martin Jambor <mjambor@suse.cz> 24876 24877 PR ipa/92917 24878 * ipa-cp.c (print_all_lattices): Skip functions without info. 24879 248802020-01-03 Jakub Jelinek <jakub@redhat.com> 24881 24882 PR target/93089 24883 * config/i386/i386-options.c (ix86_simd_clone_adjust): If 24884 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd' 24885 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512 24886 for 'e' simd clones. 24887 24888 PR target/93089 24889 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave 24890 entry. 24891 (mprefer-vector-width=): Add Save. 24892 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print 24893 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment. 24894 (ix86_debug_options, ix86_function_specific_print): Adjust 24895 ix86_target_string callers. 24896 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=. 24897 (ix86_valid_target_attribute_tree): Likewise. 24898 * config/i386/i386-options.h (ix86_target_string): Add PVW argument. 24899 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust 24900 ix86_target_string caller. 24901 24902 PR target/93110 24903 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of 24904 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode 24905 instead of gen_int_shift_amount + convert_modes. 24906 24907 PR rtl-optimization/93088 24908 * loop-iv.c (find_single_def_src): Punt after looking through 24909 128 reg copies for regs with single definitions. Move definitions 24910 to first uses. 24911 249122020-01-02 Dennis Zhang <dennis.zhang@arm.com> 24913 24914 * config/arm/arm-c.c (arm_cpu_builtins): Define 24915 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC, 24916 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and 24917 __ARM_BF16_FORMAT_ALTERNATIVE when enabled. 24918 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features. 24919 * config/arm/arm-tables.opt: Regenerated. 24920 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize 24921 arm_arch_i8mm and arm_arch_bf16 when enabled. 24922 * config/arm/arm.h (TARGET_I8MM): New macro. 24923 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. 24924 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a. 24925 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a. 24926 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a. 24927 (v8_6_a_simd_variants): New. 24928 (v8_*_a_simd_variants): Add i8mm and bf16. 24929 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. 24930 249312020-01-02 Jakub Jelinek <jakub@redhat.com> 24932 24933 PR ipa/93087 24934 * predict.c (compute_function_frequency): Don't call 24935 warn_function_cold on functions that already have cold attribute. 24936 249372020-01-01 John David Anglin <danglin@gcc.gnu.org> 24938 24939 PR target/67834 24940 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to 24941 COMDAT group function labels in .data.rel.ro.local section. 24942 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define. 24943 24944 PR target/93111 24945 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of 24946 comparison_operator in B and S integer comparisons. Likewise, use 24947 ordered_comparison_operator instead of cmpib_comparison_operator in 24948 cmpib patterns. 24949 * config/pa/predicates.md (cmpib_comparison_operator): Remove. 24950 249512020-01-01 Jakub Jelinek <jakub@redhat.com> 24952 24953 Update copyright years. 24954 24955 * gcc.c (process_command): Update copyright notice dates. 24956 * gcov-dump.c (print_version): Ditto. 24957 * gcov.c (print_version): Ditto. 24958 * gcov-tool.c (print_version): Ditto. 24959 * gengtype.c (create_file): Ditto. 24960 * doc/cpp.texi: Bump @copying's copyright year. 24961 * doc/cppinternals.texi: Ditto. 24962 * doc/gcc.texi: Ditto. 24963 * doc/gccint.texi: Ditto. 24964 * doc/gcov.texi: Ditto. 24965 * doc/install.texi: Ditto. 24966 * doc/invoke.texi: Ditto. 24967 249682020-01-01 Jan Hubicka <hubicka@ucw.cz> 24969 24970 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall 24971 summary. 24972 249732020-01-01 Jakub Jelinek <jakub@redhat.com> 24974 24975 PR tree-optimization/93098 24976 * match.pd (popcount): For shift amounts, use integer_onep 24977 or wi::to_widest () == cst instead of tree_to_uhwi () == cst 24978 tests. Make sure that precision is power of two larger than or equal 24979 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro 24980 instead of ULL suffixed constants. Formatting fixes. 24981 24982Copyright (C) 2020 Free Software Foundation, Inc. 24983 24984Copying and distribution of this file, with or without modification, 24985are permitted in any medium without royalty provided the copyright 24986notice and this notice are preserved. 24987