1cef8759bSmrg /* This file is automatically generated. DO NOT EDIT! */ 2*627f7eb2Smrg /* Generated from: NetBSD: mknative-gcc,v 1.108 2020/09/05 10:58:08 mrg Exp */ 3cef8759bSmrg /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */ 4cef8759bSmrg 5cef8759bSmrg /* -*- buffer-read-only: t -*- 6cef8759bSmrg Generated automatically by parsecpu.awk from arm-cpus.in. 7cef8759bSmrg Do not edit. 8cef8759bSmrg 9*627f7eb2Smrg Copyright (C) 2011-2019 Free Software Foundation, Inc. 10cef8759bSmrg 11cef8759bSmrg This file is part of GCC. 12cef8759bSmrg 13cef8759bSmrg GCC is free software; you can redistribute it and/or modify 14cef8759bSmrg it under the terms of the GNU General Public License as 15cef8759bSmrg published by the Free Software Foundation; either version 3, 16cef8759bSmrg or (at your option) any later version. 17cef8759bSmrg 18cef8759bSmrg GCC is distributed in the hope that it will be useful, 19cef8759bSmrg but WITHOUT ANY WARRANTY; without even the implied warranty of 20cef8759bSmrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21cef8759bSmrg GNU General Public License for more details. 22cef8759bSmrg 23cef8759bSmrg You should have received a copy of the GNU General Public 24cef8759bSmrg License along with GCC; see the file COPYING3. If not see 25cef8759bSmrg <http://www.gnu.org/licenses/>. */ 26cef8759bSmrg 27*627f7eb2Smrg static const cpu_alias cpu_aliastab_strongarm[] = { 28*627f7eb2Smrg { "strongarm110", true}, 29*627f7eb2Smrg { "strongarm1100", false}, 30*627f7eb2Smrg { "strongarm1110", false}, 31*627f7eb2Smrg { NULL, false} 32*627f7eb2Smrg }; 33*627f7eb2Smrg 34*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm7tdmi[] = { 35*627f7eb2Smrg { "arm7tdmi-s", true}, 36*627f7eb2Smrg { NULL, false} 37*627f7eb2Smrg }; 38*627f7eb2Smrg 39*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm710t[] = { 40*627f7eb2Smrg { "arm720t", true}, 41*627f7eb2Smrg { "arm740t", true}, 42*627f7eb2Smrg { NULL, false} 43*627f7eb2Smrg }; 44*627f7eb2Smrg 45*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm920t[] = { 46*627f7eb2Smrg { "arm920", true}, 47*627f7eb2Smrg { "arm922t", true}, 48*627f7eb2Smrg { "arm940t", true}, 49*627f7eb2Smrg { "ep9312", true}, 50*627f7eb2Smrg { NULL, false} 51*627f7eb2Smrg }; 52*627f7eb2Smrg 53*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm10tdmi[] = { 54*627f7eb2Smrg { "arm1020t", true}, 55*627f7eb2Smrg { NULL, false} 56*627f7eb2Smrg }; 57*627f7eb2Smrg 58cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm9e[] = { 59cef8759bSmrg { 60cef8759bSmrg "nofp", true, false, 61cef8759bSmrg { 62cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 63cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 64cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 65cef8759bSmrg } 66cef8759bSmrg }, 67cef8759bSmrg { NULL, false, false, {isa_nobit}} 68cef8759bSmrg }; 69cef8759bSmrg 70*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm9e[] = { 71*627f7eb2Smrg { "arm946e-s", true}, 72*627f7eb2Smrg { "arm966e-s", true}, 73*627f7eb2Smrg { "arm968e-s", true}, 74*627f7eb2Smrg { NULL, false} 75cef8759bSmrg }; 76cef8759bSmrg 77cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm10e[] = { 78cef8759bSmrg { 79cef8759bSmrg "nofp", true, false, 80cef8759bSmrg { 81cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 82cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 83cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 84cef8759bSmrg } 85cef8759bSmrg }, 86cef8759bSmrg { NULL, false, false, {isa_nobit}} 87cef8759bSmrg }; 88cef8759bSmrg 89*627f7eb2Smrg static const cpu_alias cpu_aliastab_arm10e[] = { 90*627f7eb2Smrg { "arm1020e", true}, 91*627f7eb2Smrg { "arm1022e", true}, 92*627f7eb2Smrg { NULL, false} 93cef8759bSmrg }; 94cef8759bSmrg 95cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm926ejs[] = { 96cef8759bSmrg { 97cef8759bSmrg "nofp", true, false, 98cef8759bSmrg { 99cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 100cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 101cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 102cef8759bSmrg } 103cef8759bSmrg }, 104cef8759bSmrg { NULL, false, false, {isa_nobit}} 105cef8759bSmrg }; 106cef8759bSmrg 107cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { 108cef8759bSmrg { 109cef8759bSmrg "nofp", true, false, 110cef8759bSmrg { 111cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 112cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 113cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 114cef8759bSmrg } 115cef8759bSmrg }, 116cef8759bSmrg { NULL, false, false, {isa_nobit}} 117cef8759bSmrg }; 118cef8759bSmrg 119cef8759bSmrg static const cpu_arch_extension cpu_opttab_genericv7a[] = { 120cef8759bSmrg { 121cef8759bSmrg "mp", false, false, 122cef8759bSmrg { 123cef8759bSmrg isa_bit_mp, isa_nobit 124cef8759bSmrg } 125cef8759bSmrg }, 126cef8759bSmrg { 127cef8759bSmrg "sec", false, false, 128cef8759bSmrg { 129cef8759bSmrg isa_bit_sec, isa_nobit 130cef8759bSmrg } 131cef8759bSmrg }, 132cef8759bSmrg { 133cef8759bSmrg "vfpv3-d16", false, false, 134cef8759bSmrg { 135cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 136cef8759bSmrg } 137cef8759bSmrg }, 138cef8759bSmrg { 139cef8759bSmrg "vfpv3", false, false, 140cef8759bSmrg { 141cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 142cef8759bSmrg isa_nobit 143cef8759bSmrg } 144cef8759bSmrg }, 145cef8759bSmrg { 146cef8759bSmrg "vfpv3-d16-fp16", false, false, 147cef8759bSmrg { 148cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 149cef8759bSmrg isa_nobit 150cef8759bSmrg } 151cef8759bSmrg }, 152cef8759bSmrg { 153cef8759bSmrg "vfpv3-fp16", false, false, 154cef8759bSmrg { 155cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 156cef8759bSmrg isa_bit_fp_dbl, isa_nobit 157cef8759bSmrg } 158cef8759bSmrg }, 159cef8759bSmrg { 160cef8759bSmrg "vfpv4-d16", false, false, 161cef8759bSmrg { 162cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 163cef8759bSmrg isa_bit_fp_dbl, isa_nobit 164cef8759bSmrg } 165cef8759bSmrg }, 166cef8759bSmrg { 167cef8759bSmrg "vfpv4", false, false, 168cef8759bSmrg { 169cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 170cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 171cef8759bSmrg } 172cef8759bSmrg }, 173cef8759bSmrg { 174cef8759bSmrg "simd", false, false, 175cef8759bSmrg { 176cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 177cef8759bSmrg isa_bit_fp_dbl, isa_nobit 178cef8759bSmrg } 179cef8759bSmrg }, 180cef8759bSmrg { 181cef8759bSmrg "neon-fp16", false, false, 182cef8759bSmrg { 183cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 184cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 185cef8759bSmrg } 186cef8759bSmrg }, 187cef8759bSmrg { 188cef8759bSmrg "neon-vfpv4", false, false, 189cef8759bSmrg { 190cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 191cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 192cef8759bSmrg } 193cef8759bSmrg }, 194cef8759bSmrg { 195cef8759bSmrg "nosimd", true, false, 196cef8759bSmrg { 197cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 198cef8759bSmrg isa_bit_crypto, isa_nobit 199cef8759bSmrg } 200cef8759bSmrg }, 201cef8759bSmrg { 202cef8759bSmrg "nofp", true, false, 203cef8759bSmrg { 204cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 205cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 206cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 207cef8759bSmrg } 208cef8759bSmrg }, 209cef8759bSmrg { 210cef8759bSmrg "neon", false, true, 211cef8759bSmrg { 212cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 213cef8759bSmrg isa_bit_fp_dbl, isa_nobit 214cef8759bSmrg } 215cef8759bSmrg }, 216cef8759bSmrg { 217cef8759bSmrg "neon-vfpv3", false, true, 218cef8759bSmrg { 219cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 220cef8759bSmrg isa_bit_fp_dbl, isa_nobit 221cef8759bSmrg } 222cef8759bSmrg }, 223cef8759bSmrg { NULL, false, false, {isa_nobit}} 224cef8759bSmrg }; 225cef8759bSmrg 226cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa5[] = { 227cef8759bSmrg { 228cef8759bSmrg "nosimd", true, false, 229cef8759bSmrg { 230cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 231cef8759bSmrg isa_bit_crypto, isa_nobit 232cef8759bSmrg } 233cef8759bSmrg }, 234cef8759bSmrg { 235cef8759bSmrg "nofp", true, false, 236cef8759bSmrg { 237cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 238cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 239cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 240cef8759bSmrg } 241cef8759bSmrg }, 242cef8759bSmrg { NULL, false, false, {isa_nobit}} 243cef8759bSmrg }; 244cef8759bSmrg 245cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa7[] = { 246cef8759bSmrg { 247cef8759bSmrg "nosimd", true, false, 248cef8759bSmrg { 249cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 250cef8759bSmrg isa_bit_crypto, isa_nobit 251cef8759bSmrg } 252cef8759bSmrg }, 253cef8759bSmrg { 254cef8759bSmrg "nofp", true, false, 255cef8759bSmrg { 256cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 257cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 258cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 259cef8759bSmrg } 260cef8759bSmrg }, 261cef8759bSmrg { NULL, false, false, {isa_nobit}} 262cef8759bSmrg }; 263cef8759bSmrg 264cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa8[] = { 265cef8759bSmrg { 266cef8759bSmrg "nofp", true, false, 267cef8759bSmrg { 268cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 269cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 270cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 271cef8759bSmrg } 272cef8759bSmrg }, 273cef8759bSmrg { NULL, false, false, {isa_nobit}} 274cef8759bSmrg }; 275cef8759bSmrg 276cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa9[] = { 277cef8759bSmrg { 278cef8759bSmrg "nosimd", true, false, 279cef8759bSmrg { 280cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 281cef8759bSmrg isa_bit_crypto, isa_nobit 282cef8759bSmrg } 283cef8759bSmrg }, 284cef8759bSmrg { 285cef8759bSmrg "nofp", true, false, 286cef8759bSmrg { 287cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 288cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 289cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 290cef8759bSmrg } 291cef8759bSmrg }, 292cef8759bSmrg { NULL, false, false, {isa_nobit}} 293cef8759bSmrg }; 294cef8759bSmrg 295cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa12[] = { 296cef8759bSmrg { 297cef8759bSmrg "nofp", true, false, 298cef8759bSmrg { 299cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 300cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 301cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 302cef8759bSmrg } 303cef8759bSmrg }, 304cef8759bSmrg { NULL, false, false, {isa_nobit}} 305cef8759bSmrg }; 306cef8759bSmrg 307cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa15[] = { 308cef8759bSmrg { 309cef8759bSmrg "nofp", true, false, 310cef8759bSmrg { 311cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 312cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 313cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 314cef8759bSmrg } 315cef8759bSmrg }, 316cef8759bSmrg { NULL, false, false, {isa_nobit}} 317cef8759bSmrg }; 318cef8759bSmrg 319cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa17[] = { 320cef8759bSmrg { 321cef8759bSmrg "nofp", true, false, 322cef8759bSmrg { 323cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 324cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 325cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 326cef8759bSmrg } 327cef8759bSmrg }, 328cef8759bSmrg { NULL, false, false, {isa_nobit}} 329cef8759bSmrg }; 330cef8759bSmrg 331cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr5[] = { 332cef8759bSmrg { 333cef8759bSmrg "nofp.dp", true, false, 334cef8759bSmrg { 335cef8759bSmrg isa_bit_fp_dbl, isa_nobit 336cef8759bSmrg } 337cef8759bSmrg }, 338cef8759bSmrg { 339cef8759bSmrg "nofp", true, false, 340cef8759bSmrg { 341cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 342cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 343cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 344cef8759bSmrg } 345cef8759bSmrg }, 346cef8759bSmrg { NULL, false, false, {isa_nobit}} 347cef8759bSmrg }; 348cef8759bSmrg 349cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr7[] = { 350cef8759bSmrg { 351cef8759bSmrg "nofp.dp", true, false, 352cef8759bSmrg { 353cef8759bSmrg isa_bit_fp_dbl, isa_nobit 354cef8759bSmrg } 355cef8759bSmrg }, 356cef8759bSmrg { 357cef8759bSmrg "nofp", true, false, 358cef8759bSmrg { 359cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 360cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 361cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 362cef8759bSmrg } 363cef8759bSmrg }, 364cef8759bSmrg { NULL, false, false, {isa_nobit}} 365cef8759bSmrg }; 366cef8759bSmrg 367cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr8[] = { 368cef8759bSmrg { 369cef8759bSmrg "nofp.dp", true, false, 370cef8759bSmrg { 371cef8759bSmrg isa_bit_fp_dbl, isa_nobit 372cef8759bSmrg } 373cef8759bSmrg }, 374cef8759bSmrg { 375cef8759bSmrg "nofp", true, false, 376cef8759bSmrg { 377cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 378cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 379cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 380cef8759bSmrg } 381cef8759bSmrg }, 382cef8759bSmrg { NULL, false, false, {isa_nobit}} 383cef8759bSmrg }; 384cef8759bSmrg 385cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm7[] = { 386cef8759bSmrg { 387cef8759bSmrg "nofp.dp", true, false, 388cef8759bSmrg { 389cef8759bSmrg isa_bit_fp_dbl, isa_nobit 390cef8759bSmrg } 391cef8759bSmrg }, 392cef8759bSmrg { 393cef8759bSmrg "nofp", true, false, 394cef8759bSmrg { 395cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 396cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 397cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 398cef8759bSmrg } 399cef8759bSmrg }, 400cef8759bSmrg { NULL, false, false, {isa_nobit}} 401cef8759bSmrg }; 402cef8759bSmrg 403cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm4[] = { 404cef8759bSmrg { 405cef8759bSmrg "nofp", true, false, 406cef8759bSmrg { 407cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 408cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 409cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 410cef8759bSmrg } 411cef8759bSmrg }, 412cef8759bSmrg { NULL, false, false, {isa_nobit}} 413cef8759bSmrg }; 414cef8759bSmrg 415cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { 416cef8759bSmrg { 417cef8759bSmrg "nofp", true, false, 418cef8759bSmrg { 419cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 420cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 421cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 422cef8759bSmrg } 423cef8759bSmrg }, 424cef8759bSmrg { NULL, false, false, {isa_nobit}} 425cef8759bSmrg }; 426cef8759bSmrg 427cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { 428cef8759bSmrg { 429cef8759bSmrg "nofp", true, false, 430cef8759bSmrg { 431cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 432cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 433cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 434cef8759bSmrg } 435cef8759bSmrg }, 436cef8759bSmrg { NULL, false, false, {isa_nobit}} 437cef8759bSmrg }; 438cef8759bSmrg 439cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa32[] = { 440cef8759bSmrg { 441cef8759bSmrg "crypto", false, false, 442cef8759bSmrg { 443cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 444cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 445cef8759bSmrg isa_bit_fp_dbl, isa_nobit 446cef8759bSmrg } 447cef8759bSmrg }, 448cef8759bSmrg { 449cef8759bSmrg "nofp", true, false, 450cef8759bSmrg { 451cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 452cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 453cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 454cef8759bSmrg } 455cef8759bSmrg }, 456cef8759bSmrg { NULL, false, false, {isa_nobit}} 457cef8759bSmrg }; 458cef8759bSmrg 459cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa35[] = { 460cef8759bSmrg { 461cef8759bSmrg "crypto", false, false, 462cef8759bSmrg { 463cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 464cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 465cef8759bSmrg isa_bit_fp_dbl, isa_nobit 466cef8759bSmrg } 467cef8759bSmrg }, 468cef8759bSmrg { 469cef8759bSmrg "nofp", true, false, 470cef8759bSmrg { 471cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 472cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 473cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 474cef8759bSmrg } 475cef8759bSmrg }, 476cef8759bSmrg { NULL, false, false, {isa_nobit}} 477cef8759bSmrg }; 478cef8759bSmrg 479cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa53[] = { 480cef8759bSmrg { 481cef8759bSmrg "crypto", false, false, 482cef8759bSmrg { 483cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 484cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 485cef8759bSmrg isa_bit_fp_dbl, isa_nobit 486cef8759bSmrg } 487cef8759bSmrg }, 488cef8759bSmrg { 489cef8759bSmrg "nofp", true, false, 490cef8759bSmrg { 491cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 492cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 493cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 494cef8759bSmrg } 495cef8759bSmrg }, 496cef8759bSmrg { NULL, false, false, {isa_nobit}} 497cef8759bSmrg }; 498cef8759bSmrg 499cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa57[] = { 500cef8759bSmrg { 501cef8759bSmrg "crypto", false, false, 502cef8759bSmrg { 503cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 504cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 505cef8759bSmrg isa_bit_fp_dbl, isa_nobit 506cef8759bSmrg } 507cef8759bSmrg }, 508cef8759bSmrg { NULL, false, false, {isa_nobit}} 509cef8759bSmrg }; 510cef8759bSmrg 511cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa72[] = { 512cef8759bSmrg { 513cef8759bSmrg "crypto", false, false, 514cef8759bSmrg { 515cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 516cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 517cef8759bSmrg isa_bit_fp_dbl, isa_nobit 518cef8759bSmrg } 519cef8759bSmrg }, 520cef8759bSmrg { NULL, false, false, {isa_nobit}} 521cef8759bSmrg }; 522cef8759bSmrg 523cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73[] = { 524cef8759bSmrg { 525cef8759bSmrg "crypto", false, false, 526cef8759bSmrg { 527cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 528cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 529cef8759bSmrg isa_bit_fp_dbl, isa_nobit 530cef8759bSmrg } 531cef8759bSmrg }, 532cef8759bSmrg { NULL, false, false, {isa_nobit}} 533cef8759bSmrg }; 534cef8759bSmrg 535cef8759bSmrg static const cpu_arch_extension cpu_opttab_exynosm1[] = { 536cef8759bSmrg { 537cef8759bSmrg "crypto", false, false, 538cef8759bSmrg { 539cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 540cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 541cef8759bSmrg isa_bit_fp_dbl, isa_nobit 542cef8759bSmrg } 543cef8759bSmrg }, 544cef8759bSmrg { NULL, false, false, {isa_nobit}} 545cef8759bSmrg }; 546cef8759bSmrg 547cef8759bSmrg static const cpu_arch_extension cpu_opttab_xgene1[] = { 548cef8759bSmrg { 549cef8759bSmrg "crypto", false, false, 550cef8759bSmrg { 551cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 552cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 553cef8759bSmrg isa_bit_fp_dbl, isa_nobit 554cef8759bSmrg } 555cef8759bSmrg }, 556cef8759bSmrg { NULL, false, false, {isa_nobit}} 557cef8759bSmrg }; 558cef8759bSmrg 559cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { 560cef8759bSmrg { 561cef8759bSmrg "crypto", false, false, 562cef8759bSmrg { 563cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 564cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 565cef8759bSmrg isa_bit_fp_dbl, isa_nobit 566cef8759bSmrg } 567cef8759bSmrg }, 568cef8759bSmrg { NULL, false, false, {isa_nobit}} 569cef8759bSmrg }; 570cef8759bSmrg 571cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { 572cef8759bSmrg { 573cef8759bSmrg "crypto", false, false, 574cef8759bSmrg { 575cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 576cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 577cef8759bSmrg isa_bit_fp_dbl, isa_nobit 578cef8759bSmrg } 579cef8759bSmrg }, 580cef8759bSmrg { NULL, false, false, {isa_nobit}} 581cef8759bSmrg }; 582cef8759bSmrg 583cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { 584cef8759bSmrg { 585cef8759bSmrg "crypto", false, false, 586cef8759bSmrg { 587cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 588cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 589cef8759bSmrg isa_bit_fp_dbl, isa_nobit 590cef8759bSmrg } 591cef8759bSmrg }, 592cef8759bSmrg { NULL, false, false, {isa_nobit}} 593cef8759bSmrg }; 594cef8759bSmrg 595cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { 596cef8759bSmrg { 597cef8759bSmrg "crypto", false, false, 598cef8759bSmrg { 599cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 600cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 601cef8759bSmrg isa_bit_fp_dbl, isa_nobit 602cef8759bSmrg } 603cef8759bSmrg }, 604cef8759bSmrg { NULL, false, false, {isa_nobit}} 605cef8759bSmrg }; 606cef8759bSmrg 607cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa55[] = { 608cef8759bSmrg { 609cef8759bSmrg "crypto", false, false, 610cef8759bSmrg { 611cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 612cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 613cef8759bSmrg isa_bit_fp_dbl, isa_nobit 614cef8759bSmrg } 615cef8759bSmrg }, 616cef8759bSmrg { 617cef8759bSmrg "nofp", true, false, 618cef8759bSmrg { 619cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 620cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 621cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 622cef8759bSmrg } 623cef8759bSmrg }, 624cef8759bSmrg { NULL, false, false, {isa_nobit}} 625cef8759bSmrg }; 626cef8759bSmrg 627cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa75[] = { 628cef8759bSmrg { 629cef8759bSmrg "crypto", false, false, 630cef8759bSmrg { 631cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 632cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 633cef8759bSmrg isa_bit_fp_dbl, isa_nobit 634cef8759bSmrg } 635cef8759bSmrg }, 636cef8759bSmrg { NULL, false, false, {isa_nobit}} 637cef8759bSmrg }; 638cef8759bSmrg 639*627f7eb2Smrg static const cpu_arch_extension cpu_opttab_cortexa76[] = { 640*627f7eb2Smrg { 641*627f7eb2Smrg "crypto", false, false, 642*627f7eb2Smrg { 643*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 644*627f7eb2Smrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 645*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 646*627f7eb2Smrg } 647*627f7eb2Smrg }, 648*627f7eb2Smrg { NULL, false, false, {isa_nobit}} 649*627f7eb2Smrg }; 650*627f7eb2Smrg 651*627f7eb2Smrg static const cpu_arch_extension cpu_opttab_neoversen1[] = { 652*627f7eb2Smrg { 653*627f7eb2Smrg "crypto", false, false, 654*627f7eb2Smrg { 655*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 656*627f7eb2Smrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 657*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 658*627f7eb2Smrg } 659*627f7eb2Smrg }, 660*627f7eb2Smrg { NULL, false, false, {isa_nobit}} 661*627f7eb2Smrg }; 662*627f7eb2Smrg 663*627f7eb2Smrg static const cpu_alias cpu_aliastab_neoversen1[] = { 664*627f7eb2Smrg { "ares", false}, 665*627f7eb2Smrg { NULL, false} 666*627f7eb2Smrg }; 667*627f7eb2Smrg 668cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = { 669cef8759bSmrg { 670cef8759bSmrg "crypto", false, false, 671cef8759bSmrg { 672cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 673cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 674cef8759bSmrg isa_bit_fp_dbl, isa_nobit 675cef8759bSmrg } 676cef8759bSmrg }, 677cef8759bSmrg { NULL, false, false, {isa_nobit}} 678cef8759bSmrg }; 679cef8759bSmrg 680*627f7eb2Smrg static const cpu_arch_extension cpu_opttab_cortexa76cortexa55[] = { 681*627f7eb2Smrg { 682*627f7eb2Smrg "crypto", false, false, 683*627f7eb2Smrg { 684*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 685*627f7eb2Smrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 686*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 687*627f7eb2Smrg } 688*627f7eb2Smrg }, 689*627f7eb2Smrg { NULL, false, false, {isa_nobit}} 690*627f7eb2Smrg }; 691*627f7eb2Smrg 692cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm33[] = { 693cef8759bSmrg { 694cef8759bSmrg "nofp", true, false, 695cef8759bSmrg { 696cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 697cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 698cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 699cef8759bSmrg } 700cef8759bSmrg }, 701cef8759bSmrg { 702cef8759bSmrg "nodsp", true, false, 703cef8759bSmrg { 704cef8759bSmrg isa_bit_armv7em, isa_nobit 705cef8759bSmrg } 706cef8759bSmrg }, 707cef8759bSmrg { NULL, false, false, {isa_nobit}} 708cef8759bSmrg }; 709cef8759bSmrg 710cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr52[] = { 711cef8759bSmrg { 712cef8759bSmrg "nofp.dp", true, false, 713cef8759bSmrg { 714cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 715cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 716cef8759bSmrg } 717cef8759bSmrg }, 718cef8759bSmrg { NULL, false, false, {isa_nobit}} 719cef8759bSmrg }; 720cef8759bSmrg 721cef8759bSmrg const cpu_option all_cores[] = 722cef8759bSmrg { 723cef8759bSmrg { 724cef8759bSmrg { 725cef8759bSmrg "arm8", 726cef8759bSmrg NULL, 727cef8759bSmrg { 728*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 729cef8759bSmrg } 730cef8759bSmrg }, 731*627f7eb2Smrg NULL, 732cef8759bSmrg TARGET_ARCH_armv4 733cef8759bSmrg }, 734cef8759bSmrg { 735cef8759bSmrg { 736cef8759bSmrg "arm810", 737cef8759bSmrg NULL, 738cef8759bSmrg { 739*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 740cef8759bSmrg } 741cef8759bSmrg }, 742*627f7eb2Smrg NULL, 743cef8759bSmrg TARGET_ARCH_armv4 744cef8759bSmrg }, 745cef8759bSmrg { 746cef8759bSmrg { 747cef8759bSmrg "strongarm", 748cef8759bSmrg NULL, 749cef8759bSmrg { 750*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 751cef8759bSmrg } 752cef8759bSmrg }, 753*627f7eb2Smrg cpu_aliastab_strongarm, 754cef8759bSmrg TARGET_ARCH_armv4 755cef8759bSmrg }, 756cef8759bSmrg { 757cef8759bSmrg { 758cef8759bSmrg "fa526", 759cef8759bSmrg NULL, 760cef8759bSmrg { 761*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 762cef8759bSmrg } 763cef8759bSmrg }, 764*627f7eb2Smrg NULL, 765cef8759bSmrg TARGET_ARCH_armv4 766cef8759bSmrg }, 767cef8759bSmrg { 768cef8759bSmrg { 769cef8759bSmrg "fa626", 770cef8759bSmrg NULL, 771cef8759bSmrg { 772*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 773cef8759bSmrg } 774cef8759bSmrg }, 775*627f7eb2Smrg NULL, 776cef8759bSmrg TARGET_ARCH_armv4 777cef8759bSmrg }, 778cef8759bSmrg { 779cef8759bSmrg { 780cef8759bSmrg "arm7tdmi", 781cef8759bSmrg NULL, 782cef8759bSmrg { 783*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 784cef8759bSmrg } 785cef8759bSmrg }, 786*627f7eb2Smrg cpu_aliastab_arm7tdmi, 787cef8759bSmrg TARGET_ARCH_armv4t 788cef8759bSmrg }, 789cef8759bSmrg { 790cef8759bSmrg { 791cef8759bSmrg "arm710t", 792cef8759bSmrg NULL, 793cef8759bSmrg { 794*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 795cef8759bSmrg } 796cef8759bSmrg }, 797*627f7eb2Smrg cpu_aliastab_arm710t, 798cef8759bSmrg TARGET_ARCH_armv4t 799cef8759bSmrg }, 800cef8759bSmrg { 801cef8759bSmrg { 802cef8759bSmrg "arm9", 803cef8759bSmrg NULL, 804cef8759bSmrg { 805*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 806cef8759bSmrg } 807cef8759bSmrg }, 808*627f7eb2Smrg NULL, 809cef8759bSmrg TARGET_ARCH_armv4t 810cef8759bSmrg }, 811cef8759bSmrg { 812cef8759bSmrg { 813cef8759bSmrg "arm9tdmi", 814cef8759bSmrg NULL, 815cef8759bSmrg { 816*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 817cef8759bSmrg } 818cef8759bSmrg }, 819cef8759bSmrg NULL, 820cef8759bSmrg TARGET_ARCH_armv4t 821cef8759bSmrg }, 822cef8759bSmrg { 823cef8759bSmrg { 824cef8759bSmrg "arm920t", 825cef8759bSmrg NULL, 826cef8759bSmrg { 827*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 828cef8759bSmrg } 829cef8759bSmrg }, 830*627f7eb2Smrg cpu_aliastab_arm920t, 831cef8759bSmrg TARGET_ARCH_armv4t 832cef8759bSmrg }, 833cef8759bSmrg { 834cef8759bSmrg { 835cef8759bSmrg "arm10tdmi", 836cef8759bSmrg NULL, 837cef8759bSmrg { 838*627f7eb2Smrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 839*627f7eb2Smrg isa_nobit 840cef8759bSmrg } 841cef8759bSmrg }, 842*627f7eb2Smrg cpu_aliastab_arm10tdmi, 843cef8759bSmrg TARGET_ARCH_armv5t 844cef8759bSmrg }, 845cef8759bSmrg { 846cef8759bSmrg { 847cef8759bSmrg "arm9e", 848cef8759bSmrg cpu_opttab_arm9e, 849cef8759bSmrg { 850*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 851*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 852cef8759bSmrg } 853cef8759bSmrg }, 854*627f7eb2Smrg cpu_aliastab_arm9e, 855cef8759bSmrg TARGET_ARCH_armv5te 856cef8759bSmrg }, 857cef8759bSmrg { 858cef8759bSmrg { 859cef8759bSmrg "arm10e", 860cef8759bSmrg cpu_opttab_arm10e, 861cef8759bSmrg { 862*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 863*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 864cef8759bSmrg } 865cef8759bSmrg }, 866*627f7eb2Smrg cpu_aliastab_arm10e, 867cef8759bSmrg TARGET_ARCH_armv5te 868cef8759bSmrg }, 869cef8759bSmrg { 870cef8759bSmrg { 871cef8759bSmrg "xscale", 872cef8759bSmrg NULL, 873cef8759bSmrg { 874*627f7eb2Smrg isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, isa_bit_armv5t, 875*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 876cef8759bSmrg } 877cef8759bSmrg }, 878*627f7eb2Smrg NULL, 879cef8759bSmrg TARGET_ARCH_armv5te 880cef8759bSmrg }, 881cef8759bSmrg { 882cef8759bSmrg { 883cef8759bSmrg "iwmmxt", 884cef8759bSmrg NULL, 885cef8759bSmrg { 886*627f7eb2Smrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 887*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 888cef8759bSmrg } 889cef8759bSmrg }, 890*627f7eb2Smrg NULL, 891cef8759bSmrg TARGET_ARCH_iwmmxt 892cef8759bSmrg }, 893cef8759bSmrg { 894cef8759bSmrg { 895cef8759bSmrg "iwmmxt2", 896cef8759bSmrg NULL, 897cef8759bSmrg { 898*627f7eb2Smrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 899*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 900*627f7eb2Smrg isa_nobit 901cef8759bSmrg } 902cef8759bSmrg }, 903*627f7eb2Smrg NULL, 904cef8759bSmrg TARGET_ARCH_iwmmxt2 905cef8759bSmrg }, 906cef8759bSmrg { 907cef8759bSmrg { 908cef8759bSmrg "fa606te", 909cef8759bSmrg NULL, 910cef8759bSmrg { 911*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 912*627f7eb2Smrg isa_bit_notm, isa_nobit 913cef8759bSmrg } 914cef8759bSmrg }, 915*627f7eb2Smrg NULL, 916cef8759bSmrg TARGET_ARCH_armv5te 917cef8759bSmrg }, 918cef8759bSmrg { 919cef8759bSmrg { 920cef8759bSmrg "fa626te", 921cef8759bSmrg NULL, 922cef8759bSmrg { 923*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 924*627f7eb2Smrg isa_bit_notm, isa_nobit 925cef8759bSmrg } 926cef8759bSmrg }, 927*627f7eb2Smrg NULL, 928cef8759bSmrg TARGET_ARCH_armv5te 929cef8759bSmrg }, 930cef8759bSmrg { 931cef8759bSmrg { 932cef8759bSmrg "fmp626", 933cef8759bSmrg NULL, 934cef8759bSmrg { 935*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 936*627f7eb2Smrg isa_bit_notm, isa_nobit 937cef8759bSmrg } 938cef8759bSmrg }, 939*627f7eb2Smrg NULL, 940cef8759bSmrg TARGET_ARCH_armv5te 941cef8759bSmrg }, 942cef8759bSmrg { 943cef8759bSmrg { 944cef8759bSmrg "fa726te", 945cef8759bSmrg NULL, 946cef8759bSmrg { 947*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 948*627f7eb2Smrg isa_bit_notm, isa_nobit 949cef8759bSmrg } 950cef8759bSmrg }, 951*627f7eb2Smrg NULL, 952cef8759bSmrg TARGET_ARCH_armv5te 953cef8759bSmrg }, 954cef8759bSmrg { 955cef8759bSmrg { 956cef8759bSmrg "arm926ej-s", 957cef8759bSmrg cpu_opttab_arm926ejs, 958cef8759bSmrg { 959*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 960*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 961cef8759bSmrg } 962cef8759bSmrg }, 963*627f7eb2Smrg NULL, 964cef8759bSmrg TARGET_ARCH_armv5tej 965cef8759bSmrg }, 966cef8759bSmrg { 967cef8759bSmrg { 968cef8759bSmrg "arm1026ej-s", 969cef8759bSmrg cpu_opttab_arm1026ejs, 970cef8759bSmrg { 971*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 972*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 973cef8759bSmrg } 974cef8759bSmrg }, 975*627f7eb2Smrg NULL, 976cef8759bSmrg TARGET_ARCH_armv5tej 977cef8759bSmrg }, 978cef8759bSmrg { 979cef8759bSmrg { 980cef8759bSmrg "arm1136j-s", 981cef8759bSmrg NULL, 982cef8759bSmrg { 983*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 984*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 985cef8759bSmrg } 986cef8759bSmrg }, 987*627f7eb2Smrg NULL, 988cef8759bSmrg TARGET_ARCH_armv6j 989cef8759bSmrg }, 990cef8759bSmrg { 991cef8759bSmrg { 992cef8759bSmrg "arm1136jf-s", 993cef8759bSmrg NULL, 994cef8759bSmrg { 995*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 996*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 997*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 998cef8759bSmrg } 999cef8759bSmrg }, 1000*627f7eb2Smrg NULL, 1001cef8759bSmrg TARGET_ARCH_armv6j 1002cef8759bSmrg }, 1003cef8759bSmrg { 1004cef8759bSmrg { 1005cef8759bSmrg "arm1176jz-s", 1006cef8759bSmrg NULL, 1007cef8759bSmrg { 1008*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1009*627f7eb2Smrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 1010*627f7eb2Smrg isa_bit_armv6k, isa_nobit 1011cef8759bSmrg } 1012cef8759bSmrg }, 1013*627f7eb2Smrg NULL, 1014cef8759bSmrg TARGET_ARCH_armv6kz 1015cef8759bSmrg }, 1016cef8759bSmrg { 1017cef8759bSmrg { 1018cef8759bSmrg "arm1176jzf-s", 1019cef8759bSmrg NULL, 1020cef8759bSmrg { 1021*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1022*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, 1023*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1024cef8759bSmrg } 1025cef8759bSmrg }, 1026*627f7eb2Smrg NULL, 1027cef8759bSmrg TARGET_ARCH_armv6kz 1028cef8759bSmrg }, 1029cef8759bSmrg { 1030cef8759bSmrg { 1031cef8759bSmrg "mpcorenovfp", 1032cef8759bSmrg NULL, 1033cef8759bSmrg { 1034*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1035*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 1036*627f7eb2Smrg isa_nobit 1037cef8759bSmrg } 1038cef8759bSmrg }, 1039*627f7eb2Smrg NULL, 1040cef8759bSmrg TARGET_ARCH_armv6k 1041cef8759bSmrg }, 1042cef8759bSmrg { 1043cef8759bSmrg { 1044cef8759bSmrg "mpcore", 1045cef8759bSmrg NULL, 1046cef8759bSmrg { 1047*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1048*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 1049*627f7eb2Smrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1050cef8759bSmrg } 1051cef8759bSmrg }, 1052*627f7eb2Smrg NULL, 1053cef8759bSmrg TARGET_ARCH_armv6k 1054cef8759bSmrg }, 1055cef8759bSmrg { 1056cef8759bSmrg { 1057cef8759bSmrg "arm1156t2-s", 1058cef8759bSmrg NULL, 1059cef8759bSmrg { 1060*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1061*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 1062*627f7eb2Smrg isa_nobit 1063cef8759bSmrg } 1064cef8759bSmrg }, 1065*627f7eb2Smrg NULL, 1066cef8759bSmrg TARGET_ARCH_armv6t2 1067cef8759bSmrg }, 1068cef8759bSmrg { 1069cef8759bSmrg { 1070cef8759bSmrg "arm1156t2f-s", 1071cef8759bSmrg NULL, 1072cef8759bSmrg { 1073*627f7eb2Smrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1074*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, 1075*627f7eb2Smrg isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1076cef8759bSmrg } 1077cef8759bSmrg }, 1078*627f7eb2Smrg NULL, 1079cef8759bSmrg TARGET_ARCH_armv6t2 1080cef8759bSmrg }, 1081cef8759bSmrg { 1082cef8759bSmrg { 1083cef8759bSmrg "cortex-m1", 1084cef8759bSmrg NULL, 1085cef8759bSmrg { 1086*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1087*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1088cef8759bSmrg } 1089cef8759bSmrg }, 1090*627f7eb2Smrg NULL, 1091cef8759bSmrg TARGET_ARCH_armv6s_m 1092cef8759bSmrg }, 1093cef8759bSmrg { 1094cef8759bSmrg { 1095cef8759bSmrg "cortex-m0", 1096cef8759bSmrg NULL, 1097cef8759bSmrg { 1098*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1099*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1100cef8759bSmrg } 1101cef8759bSmrg }, 1102*627f7eb2Smrg NULL, 1103cef8759bSmrg TARGET_ARCH_armv6s_m 1104cef8759bSmrg }, 1105cef8759bSmrg { 1106cef8759bSmrg { 1107cef8759bSmrg "cortex-m0plus", 1108cef8759bSmrg NULL, 1109cef8759bSmrg { 1110*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1111*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1112cef8759bSmrg } 1113cef8759bSmrg }, 1114*627f7eb2Smrg NULL, 1115cef8759bSmrg TARGET_ARCH_armv6s_m 1116cef8759bSmrg }, 1117cef8759bSmrg { 1118cef8759bSmrg { 1119cef8759bSmrg "cortex-m1.small-multiply", 1120cef8759bSmrg NULL, 1121cef8759bSmrg { 1122*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1123*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1124cef8759bSmrg } 1125cef8759bSmrg }, 1126*627f7eb2Smrg NULL, 1127cef8759bSmrg TARGET_ARCH_armv6s_m 1128cef8759bSmrg }, 1129cef8759bSmrg { 1130cef8759bSmrg { 1131cef8759bSmrg "cortex-m0.small-multiply", 1132cef8759bSmrg NULL, 1133cef8759bSmrg { 1134*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1135*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1136cef8759bSmrg } 1137cef8759bSmrg }, 1138*627f7eb2Smrg NULL, 1139cef8759bSmrg TARGET_ARCH_armv6s_m 1140cef8759bSmrg }, 1141cef8759bSmrg { 1142cef8759bSmrg { 1143cef8759bSmrg "cortex-m0plus.small-multiply", 1144cef8759bSmrg NULL, 1145cef8759bSmrg { 1146*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1147*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1148cef8759bSmrg } 1149cef8759bSmrg }, 1150*627f7eb2Smrg NULL, 1151cef8759bSmrg TARGET_ARCH_armv6s_m 1152cef8759bSmrg }, 1153cef8759bSmrg { 1154cef8759bSmrg { 1155cef8759bSmrg "generic-armv7-a", 1156cef8759bSmrg cpu_opttab_genericv7a, 1157cef8759bSmrg { 1158*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1159*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1160*627f7eb2Smrg isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 1161*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 1162cef8759bSmrg } 1163cef8759bSmrg }, 1164*627f7eb2Smrg NULL, 1165cef8759bSmrg TARGET_ARCH_armv7_a 1166cef8759bSmrg }, 1167cef8759bSmrg { 1168cef8759bSmrg { 1169cef8759bSmrg "cortex-a5", 1170cef8759bSmrg cpu_opttab_cortexa5, 1171cef8759bSmrg { 1172*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1173*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1174*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1175*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1176*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1177cef8759bSmrg } 1178cef8759bSmrg }, 1179*627f7eb2Smrg NULL, 1180cef8759bSmrg TARGET_ARCH_armv7_a 1181cef8759bSmrg }, 1182cef8759bSmrg { 1183cef8759bSmrg { 1184cef8759bSmrg "cortex-a7", 1185cef8759bSmrg cpu_opttab_cortexa7, 1186cef8759bSmrg { 1187cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1188*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1189*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1190*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1191*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1192*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1193cef8759bSmrg } 1194cef8759bSmrg }, 1195*627f7eb2Smrg NULL, 1196cef8759bSmrg TARGET_ARCH_armv7ve 1197cef8759bSmrg }, 1198cef8759bSmrg { 1199cef8759bSmrg { 1200cef8759bSmrg "cortex-a8", 1201cef8759bSmrg cpu_opttab_cortexa8, 1202cef8759bSmrg { 1203*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1204*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1205*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1206*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_sec, 1207*627f7eb2Smrg isa_nobit 1208cef8759bSmrg } 1209cef8759bSmrg }, 1210*627f7eb2Smrg NULL, 1211cef8759bSmrg TARGET_ARCH_armv7_a 1212cef8759bSmrg }, 1213cef8759bSmrg { 1214cef8759bSmrg { 1215cef8759bSmrg "cortex-a9", 1216cef8759bSmrg cpu_opttab_cortexa9, 1217cef8759bSmrg { 1218*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1219*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1220*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1221*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1222*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1223cef8759bSmrg } 1224cef8759bSmrg }, 1225*627f7eb2Smrg NULL, 1226cef8759bSmrg TARGET_ARCH_armv7_a 1227cef8759bSmrg }, 1228cef8759bSmrg { 1229cef8759bSmrg { 1230cef8759bSmrg "cortex-a12", 1231cef8759bSmrg cpu_opttab_cortexa12, 1232cef8759bSmrg { 1233cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1234*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1235*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1236*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1237*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1238*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1239cef8759bSmrg } 1240cef8759bSmrg }, 1241*627f7eb2Smrg NULL, 1242cef8759bSmrg TARGET_ARCH_armv7ve 1243cef8759bSmrg }, 1244cef8759bSmrg { 1245cef8759bSmrg { 1246cef8759bSmrg "cortex-a15", 1247cef8759bSmrg cpu_opttab_cortexa15, 1248cef8759bSmrg { 1249cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1250*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1251*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1252*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1253*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1254*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1255cef8759bSmrg } 1256cef8759bSmrg }, 1257*627f7eb2Smrg NULL, 1258cef8759bSmrg TARGET_ARCH_armv7ve 1259cef8759bSmrg }, 1260cef8759bSmrg { 1261cef8759bSmrg { 1262cef8759bSmrg "cortex-a17", 1263cef8759bSmrg cpu_opttab_cortexa17, 1264cef8759bSmrg { 1265cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1266*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1267*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1268*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1269*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1270*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1271cef8759bSmrg } 1272cef8759bSmrg }, 1273*627f7eb2Smrg NULL, 1274cef8759bSmrg TARGET_ARCH_armv7ve 1275cef8759bSmrg }, 1276cef8759bSmrg { 1277cef8759bSmrg { 1278cef8759bSmrg "cortex-r4", 1279cef8759bSmrg NULL, 1280cef8759bSmrg { 1281*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1282*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 1283*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 1284cef8759bSmrg } 1285cef8759bSmrg }, 1286*627f7eb2Smrg NULL, 1287cef8759bSmrg TARGET_ARCH_armv7_r 1288cef8759bSmrg }, 1289cef8759bSmrg { 1290cef8759bSmrg { 1291cef8759bSmrg "cortex-r4f", 1292cef8759bSmrg NULL, 1293cef8759bSmrg { 1294*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1295*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1296*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 1297*627f7eb2Smrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1298cef8759bSmrg } 1299cef8759bSmrg }, 1300*627f7eb2Smrg NULL, 1301cef8759bSmrg TARGET_ARCH_armv7_r 1302cef8759bSmrg }, 1303cef8759bSmrg { 1304cef8759bSmrg { 1305cef8759bSmrg "cortex-r5", 1306cef8759bSmrg cpu_opttab_cortexr5, 1307cef8759bSmrg { 1308*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1309*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1310*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1311*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1312cef8759bSmrg } 1313cef8759bSmrg }, 1314*627f7eb2Smrg NULL, 1315cef8759bSmrg TARGET_ARCH_armv7_r 1316cef8759bSmrg }, 1317cef8759bSmrg { 1318cef8759bSmrg { 1319cef8759bSmrg "cortex-r7", 1320cef8759bSmrg cpu_opttab_cortexr7, 1321cef8759bSmrg { 1322*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1323*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1324*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1325*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1326*627f7eb2Smrg isa_nobit 1327cef8759bSmrg } 1328cef8759bSmrg }, 1329*627f7eb2Smrg NULL, 1330cef8759bSmrg TARGET_ARCH_armv7_r 1331cef8759bSmrg }, 1332cef8759bSmrg { 1333cef8759bSmrg { 1334cef8759bSmrg "cortex-r8", 1335cef8759bSmrg cpu_opttab_cortexr8, 1336cef8759bSmrg { 1337*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1338*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1339*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1340*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1341*627f7eb2Smrg isa_nobit 1342cef8759bSmrg } 1343cef8759bSmrg }, 1344*627f7eb2Smrg NULL, 1345cef8759bSmrg TARGET_ARCH_armv7_r 1346cef8759bSmrg }, 1347cef8759bSmrg { 1348cef8759bSmrg { 1349cef8759bSmrg "cortex-m7", 1350cef8759bSmrg cpu_opttab_cortexm7, 1351cef8759bSmrg { 1352*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1353*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1354cef8759bSmrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5, 1355*627f7eb2Smrg isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_thumb2, isa_bit_fp16conv, 1356*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 1357cef8759bSmrg } 1358cef8759bSmrg }, 1359*627f7eb2Smrg NULL, 1360cef8759bSmrg TARGET_ARCH_armv7e_m 1361cef8759bSmrg }, 1362cef8759bSmrg { 1363cef8759bSmrg { 1364cef8759bSmrg "cortex-m4", 1365cef8759bSmrg cpu_opttab_cortexm4, 1366cef8759bSmrg { 1367*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1368*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1369cef8759bSmrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv, 1370*627f7eb2Smrg isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 1371cef8759bSmrg } 1372cef8759bSmrg }, 1373*627f7eb2Smrg NULL, 1374cef8759bSmrg TARGET_ARCH_armv7e_m 1375cef8759bSmrg }, 1376cef8759bSmrg { 1377cef8759bSmrg { 1378cef8759bSmrg "cortex-m3", 1379cef8759bSmrg NULL, 1380cef8759bSmrg { 1381*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8, 1382*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, 1383*627f7eb2Smrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 1384cef8759bSmrg } 1385cef8759bSmrg }, 1386*627f7eb2Smrg NULL, 1387cef8759bSmrg TARGET_ARCH_armv7_m 1388cef8759bSmrg }, 1389cef8759bSmrg { 1390cef8759bSmrg { 1391cef8759bSmrg "marvell-pj4", 1392cef8759bSmrg NULL, 1393cef8759bSmrg { 1394*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1395*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 1396*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 1397*627f7eb2Smrg isa_nobit 1398cef8759bSmrg } 1399cef8759bSmrg }, 1400*627f7eb2Smrg NULL, 1401cef8759bSmrg TARGET_ARCH_armv7_a 1402cef8759bSmrg }, 1403cef8759bSmrg { 1404cef8759bSmrg { 1405cef8759bSmrg "cortex-a15.cortex-a7", 1406cef8759bSmrg cpu_opttab_cortexa15cortexa7, 1407cef8759bSmrg { 1408cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1409*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1410*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1411*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1412*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1413*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1414cef8759bSmrg } 1415cef8759bSmrg }, 1416*627f7eb2Smrg NULL, 1417cef8759bSmrg TARGET_ARCH_armv7ve 1418cef8759bSmrg }, 1419cef8759bSmrg { 1420cef8759bSmrg { 1421cef8759bSmrg "cortex-a17.cortex-a7", 1422cef8759bSmrg cpu_opttab_cortexa17cortexa7, 1423cef8759bSmrg { 1424cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1425*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1426*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1427*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1428*627f7eb2Smrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1429*627f7eb2Smrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1430cef8759bSmrg } 1431cef8759bSmrg }, 1432*627f7eb2Smrg NULL, 1433cef8759bSmrg TARGET_ARCH_armv7ve 1434cef8759bSmrg }, 1435cef8759bSmrg { 1436cef8759bSmrg { 1437cef8759bSmrg "cortex-a32", 1438cef8759bSmrg cpu_opttab_cortexa32, 1439cef8759bSmrg { 1440cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1441*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1442*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1443cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1444*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1445*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1446*627f7eb2Smrg isa_bit_sec, isa_nobit 1447cef8759bSmrg } 1448cef8759bSmrg }, 1449*627f7eb2Smrg NULL, 1450cef8759bSmrg TARGET_ARCH_armv8_a 1451cef8759bSmrg }, 1452cef8759bSmrg { 1453cef8759bSmrg { 1454cef8759bSmrg "cortex-a35", 1455cef8759bSmrg cpu_opttab_cortexa35, 1456cef8759bSmrg { 1457cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1458*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1459*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1460cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1461*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1462*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1463*627f7eb2Smrg isa_bit_sec, isa_nobit 1464cef8759bSmrg } 1465cef8759bSmrg }, 1466*627f7eb2Smrg NULL, 1467cef8759bSmrg TARGET_ARCH_armv8_a 1468cef8759bSmrg }, 1469cef8759bSmrg { 1470cef8759bSmrg { 1471cef8759bSmrg "cortex-a53", 1472cef8759bSmrg cpu_opttab_cortexa53, 1473cef8759bSmrg { 1474cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1475*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1476*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1477cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1478*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1479*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1480*627f7eb2Smrg isa_bit_sec, isa_nobit 1481cef8759bSmrg } 1482cef8759bSmrg }, 1483*627f7eb2Smrg NULL, 1484cef8759bSmrg TARGET_ARCH_armv8_a 1485cef8759bSmrg }, 1486cef8759bSmrg { 1487cef8759bSmrg { 1488cef8759bSmrg "cortex-a57", 1489cef8759bSmrg cpu_opttab_cortexa57, 1490cef8759bSmrg { 1491cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1492*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1493*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1494cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1495*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1496*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1497*627f7eb2Smrg isa_bit_sec, isa_nobit 1498cef8759bSmrg } 1499cef8759bSmrg }, 1500*627f7eb2Smrg NULL, 1501cef8759bSmrg TARGET_ARCH_armv8_a 1502cef8759bSmrg }, 1503cef8759bSmrg { 1504cef8759bSmrg { 1505cef8759bSmrg "cortex-a72", 1506cef8759bSmrg cpu_opttab_cortexa72, 1507cef8759bSmrg { 1508cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1509*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1510*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1511cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1512*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1513*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1514*627f7eb2Smrg isa_bit_sec, isa_nobit 1515cef8759bSmrg } 1516cef8759bSmrg }, 1517*627f7eb2Smrg NULL, 1518cef8759bSmrg TARGET_ARCH_armv8_a 1519cef8759bSmrg }, 1520cef8759bSmrg { 1521cef8759bSmrg { 1522cef8759bSmrg "cortex-a73", 1523cef8759bSmrg cpu_opttab_cortexa73, 1524cef8759bSmrg { 1525cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1526*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1527*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1528cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1529*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1530*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1531*627f7eb2Smrg isa_bit_sec, isa_nobit 1532cef8759bSmrg } 1533cef8759bSmrg }, 1534*627f7eb2Smrg NULL, 1535cef8759bSmrg TARGET_ARCH_armv8_a 1536cef8759bSmrg }, 1537cef8759bSmrg { 1538cef8759bSmrg { 1539cef8759bSmrg "exynos-m1", 1540cef8759bSmrg cpu_opttab_exynosm1, 1541cef8759bSmrg { 1542cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1543*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1544*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1545cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1546*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1547*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1548*627f7eb2Smrg isa_bit_sec, isa_nobit 1549cef8759bSmrg } 1550cef8759bSmrg }, 1551*627f7eb2Smrg NULL, 1552cef8759bSmrg TARGET_ARCH_armv8_a 1553cef8759bSmrg }, 1554cef8759bSmrg { 1555cef8759bSmrg { 1556cef8759bSmrg "xgene1", 1557cef8759bSmrg cpu_opttab_xgene1, 1558cef8759bSmrg { 1559cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1560*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1561*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1562cef8759bSmrg isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, 1563*627f7eb2Smrg isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, 1564*627f7eb2Smrg isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, 1565*627f7eb2Smrg isa_nobit 1566cef8759bSmrg } 1567cef8759bSmrg }, 1568*627f7eb2Smrg NULL, 1569cef8759bSmrg TARGET_ARCH_armv8_a 1570cef8759bSmrg }, 1571cef8759bSmrg { 1572cef8759bSmrg { 1573cef8759bSmrg "cortex-a57.cortex-a53", 1574cef8759bSmrg cpu_opttab_cortexa57cortexa53, 1575cef8759bSmrg { 1576cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1577*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1578*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1579cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1580*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1581*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1582*627f7eb2Smrg isa_bit_sec, isa_nobit 1583cef8759bSmrg } 1584cef8759bSmrg }, 1585*627f7eb2Smrg NULL, 1586cef8759bSmrg TARGET_ARCH_armv8_a 1587cef8759bSmrg }, 1588cef8759bSmrg { 1589cef8759bSmrg { 1590cef8759bSmrg "cortex-a72.cortex-a53", 1591cef8759bSmrg cpu_opttab_cortexa72cortexa53, 1592cef8759bSmrg { 1593cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1594*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1595*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1596cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1597*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1598*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1599*627f7eb2Smrg isa_bit_sec, isa_nobit 1600cef8759bSmrg } 1601cef8759bSmrg }, 1602*627f7eb2Smrg NULL, 1603cef8759bSmrg TARGET_ARCH_armv8_a 1604cef8759bSmrg }, 1605cef8759bSmrg { 1606cef8759bSmrg { 1607cef8759bSmrg "cortex-a73.cortex-a35", 1608cef8759bSmrg cpu_opttab_cortexa73cortexa35, 1609cef8759bSmrg { 1610cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1611*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1612*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1613cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1614*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1615*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1616*627f7eb2Smrg isa_bit_sec, isa_nobit 1617cef8759bSmrg } 1618cef8759bSmrg }, 1619*627f7eb2Smrg NULL, 1620cef8759bSmrg TARGET_ARCH_armv8_a 1621cef8759bSmrg }, 1622cef8759bSmrg { 1623cef8759bSmrg { 1624cef8759bSmrg "cortex-a73.cortex-a53", 1625cef8759bSmrg cpu_opttab_cortexa73cortexa53, 1626cef8759bSmrg { 1627cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1628*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1629*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1630cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1631*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1632*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1633*627f7eb2Smrg isa_bit_sec, isa_nobit 1634cef8759bSmrg } 1635cef8759bSmrg }, 1636*627f7eb2Smrg NULL, 1637cef8759bSmrg TARGET_ARCH_armv8_a 1638cef8759bSmrg }, 1639cef8759bSmrg { 1640cef8759bSmrg { 1641cef8759bSmrg "cortex-a55", 1642cef8759bSmrg cpu_opttab_cortexa55, 1643cef8759bSmrg { 1644cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1645*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1646*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1647*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1648*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1649*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1650*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1651*627f7eb2Smrg isa_bit_sec, isa_nobit 1652cef8759bSmrg } 1653cef8759bSmrg }, 1654*627f7eb2Smrg NULL, 1655cef8759bSmrg TARGET_ARCH_armv8_2_a 1656cef8759bSmrg }, 1657cef8759bSmrg { 1658cef8759bSmrg { 1659cef8759bSmrg "cortex-a75", 1660cef8759bSmrg cpu_opttab_cortexa75, 1661cef8759bSmrg { 1662cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1663*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1664*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1665*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1666*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1667*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1668*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1669*627f7eb2Smrg isa_bit_sec, isa_nobit 1670cef8759bSmrg } 1671cef8759bSmrg }, 1672*627f7eb2Smrg NULL, 1673*627f7eb2Smrg TARGET_ARCH_armv8_2_a 1674*627f7eb2Smrg }, 1675*627f7eb2Smrg { 1676*627f7eb2Smrg { 1677*627f7eb2Smrg "cortex-a76", 1678*627f7eb2Smrg cpu_opttab_cortexa76, 1679*627f7eb2Smrg { 1680*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1681*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1682*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1683*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1684*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1685*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1686*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1687*627f7eb2Smrg isa_bit_sec, isa_nobit 1688*627f7eb2Smrg } 1689*627f7eb2Smrg }, 1690*627f7eb2Smrg NULL, 1691*627f7eb2Smrg TARGET_ARCH_armv8_2_a 1692*627f7eb2Smrg }, 1693*627f7eb2Smrg { 1694*627f7eb2Smrg { 1695*627f7eb2Smrg "neoverse-n1", 1696*627f7eb2Smrg cpu_opttab_neoversen1, 1697*627f7eb2Smrg { 1698*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1699*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1700*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1701*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1702*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1703*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1704*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1705*627f7eb2Smrg isa_bit_sec, isa_nobit 1706*627f7eb2Smrg } 1707*627f7eb2Smrg }, 1708*627f7eb2Smrg cpu_aliastab_neoversen1, 1709cef8759bSmrg TARGET_ARCH_armv8_2_a 1710cef8759bSmrg }, 1711cef8759bSmrg { 1712cef8759bSmrg { 1713cef8759bSmrg "cortex-a75.cortex-a55", 1714cef8759bSmrg cpu_opttab_cortexa75cortexa55, 1715cef8759bSmrg { 1716cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1717*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1718*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1719*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1720*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1721*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1722*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1723*627f7eb2Smrg isa_bit_sec, isa_nobit 1724cef8759bSmrg } 1725cef8759bSmrg }, 1726*627f7eb2Smrg NULL, 1727*627f7eb2Smrg TARGET_ARCH_armv8_2_a 1728*627f7eb2Smrg }, 1729*627f7eb2Smrg { 1730*627f7eb2Smrg { 1731*627f7eb2Smrg "cortex-a76.cortex-a55", 1732*627f7eb2Smrg cpu_opttab_cortexa76cortexa55, 1733*627f7eb2Smrg { 1734*627f7eb2Smrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1735*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1736*627f7eb2Smrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1737*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1738*627f7eb2Smrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1739*627f7eb2Smrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1740*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1741*627f7eb2Smrg isa_bit_sec, isa_nobit 1742*627f7eb2Smrg } 1743*627f7eb2Smrg }, 1744*627f7eb2Smrg NULL, 1745cef8759bSmrg TARGET_ARCH_armv8_2_a 1746cef8759bSmrg }, 1747cef8759bSmrg { 1748cef8759bSmrg { 1749cef8759bSmrg "cortex-m23", 1750cef8759bSmrg NULL, 1751cef8759bSmrg { 1752*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1753*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 1754*627f7eb2Smrg isa_bit_tdiv, isa_nobit 1755cef8759bSmrg } 1756cef8759bSmrg }, 1757*627f7eb2Smrg NULL, 1758cef8759bSmrg TARGET_ARCH_armv8_m_base 1759cef8759bSmrg }, 1760cef8759bSmrg { 1761cef8759bSmrg { 1762cef8759bSmrg "cortex-m33", 1763cef8759bSmrg cpu_opttab_cortexm33, 1764cef8759bSmrg { 1765*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1766*627f7eb2Smrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1767*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_cmse, 1768*627f7eb2Smrg isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, isa_bit_thumb2, 1769*627f7eb2Smrg isa_bit_fp16conv, isa_nobit 1770cef8759bSmrg } 1771cef8759bSmrg }, 1772*627f7eb2Smrg NULL, 1773cef8759bSmrg TARGET_ARCH_armv8_m_main 1774cef8759bSmrg }, 1775cef8759bSmrg { 1776cef8759bSmrg { 1777cef8759bSmrg "cortex-r52", 1778cef8759bSmrg cpu_opttab_cortexr52, 1779cef8759bSmrg { 1780cef8759bSmrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1781*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1782*627f7eb2Smrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1783cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1784*627f7eb2Smrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1785*627f7eb2Smrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1786*627f7eb2Smrg isa_bit_sec, isa_nobit 1787cef8759bSmrg } 1788cef8759bSmrg }, 1789*627f7eb2Smrg NULL, 1790cef8759bSmrg TARGET_ARCH_armv8_r 1791cef8759bSmrg }, 1792*627f7eb2Smrg {{NULL, NULL, {isa_nobit}}, NULL, TARGET_ARCH_arm_none} 1793cef8759bSmrg }; 1794cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv5te[] = { 1795cef8759bSmrg { 1796cef8759bSmrg "fp", false, false, 1797cef8759bSmrg { 1798cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1799cef8759bSmrg } 1800cef8759bSmrg }, 1801cef8759bSmrg { 1802cef8759bSmrg "nofp", true, false, 1803cef8759bSmrg { 1804cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1805cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1806cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1807cef8759bSmrg } 1808cef8759bSmrg }, 1809cef8759bSmrg { 1810cef8759bSmrg "vfpv2", false, true, 1811cef8759bSmrg { 1812cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1813cef8759bSmrg } 1814cef8759bSmrg }, 1815cef8759bSmrg { NULL, false, false, {isa_nobit}} 1816cef8759bSmrg }; 1817cef8759bSmrg 1818cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv5tej[] = { 1819cef8759bSmrg { 1820cef8759bSmrg "fp", false, false, 1821cef8759bSmrg { 1822cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1823cef8759bSmrg } 1824cef8759bSmrg }, 1825cef8759bSmrg { 1826cef8759bSmrg "nofp", true, false, 1827cef8759bSmrg { 1828cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1829cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1830cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1831cef8759bSmrg } 1832cef8759bSmrg }, 1833cef8759bSmrg { 1834cef8759bSmrg "vfpv2", false, true, 1835cef8759bSmrg { 1836cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1837cef8759bSmrg } 1838cef8759bSmrg }, 1839cef8759bSmrg { NULL, false, false, {isa_nobit}} 1840cef8759bSmrg }; 1841cef8759bSmrg 1842cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6[] = { 1843cef8759bSmrg { 1844cef8759bSmrg "fp", false, false, 1845cef8759bSmrg { 1846cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1847cef8759bSmrg } 1848cef8759bSmrg }, 1849cef8759bSmrg { 1850cef8759bSmrg "nofp", true, false, 1851cef8759bSmrg { 1852cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1853cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1854cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1855cef8759bSmrg } 1856cef8759bSmrg }, 1857cef8759bSmrg { 1858cef8759bSmrg "vfpv2", false, true, 1859cef8759bSmrg { 1860cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1861cef8759bSmrg } 1862cef8759bSmrg }, 1863cef8759bSmrg { NULL, false, false, {isa_nobit}} 1864cef8759bSmrg }; 1865cef8759bSmrg 1866cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6j[] = { 1867cef8759bSmrg { 1868cef8759bSmrg "fp", false, false, 1869cef8759bSmrg { 1870cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1871cef8759bSmrg } 1872cef8759bSmrg }, 1873cef8759bSmrg { 1874cef8759bSmrg "nofp", true, false, 1875cef8759bSmrg { 1876cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1877cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1878cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1879cef8759bSmrg } 1880cef8759bSmrg }, 1881cef8759bSmrg { 1882cef8759bSmrg "vfpv2", false, true, 1883cef8759bSmrg { 1884cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1885cef8759bSmrg } 1886cef8759bSmrg }, 1887cef8759bSmrg { NULL, false, false, {isa_nobit}} 1888cef8759bSmrg }; 1889cef8759bSmrg 1890cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6k[] = { 1891cef8759bSmrg { 1892cef8759bSmrg "fp", false, false, 1893cef8759bSmrg { 1894cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1895cef8759bSmrg } 1896cef8759bSmrg }, 1897cef8759bSmrg { 1898cef8759bSmrg "nofp", true, false, 1899cef8759bSmrg { 1900cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1901cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1902cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1903cef8759bSmrg } 1904cef8759bSmrg }, 1905cef8759bSmrg { 1906cef8759bSmrg "vfpv2", false, true, 1907cef8759bSmrg { 1908cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1909cef8759bSmrg } 1910cef8759bSmrg }, 1911cef8759bSmrg { NULL, false, false, {isa_nobit}} 1912cef8759bSmrg }; 1913cef8759bSmrg 1914cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6z[] = { 1915cef8759bSmrg { 1916cef8759bSmrg "fp", false, false, 1917cef8759bSmrg { 1918cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1919cef8759bSmrg } 1920cef8759bSmrg }, 1921cef8759bSmrg { 1922cef8759bSmrg "nofp", true, false, 1923cef8759bSmrg { 1924cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1925cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1926cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1927cef8759bSmrg } 1928cef8759bSmrg }, 1929cef8759bSmrg { 1930cef8759bSmrg "vfpv2", false, true, 1931cef8759bSmrg { 1932cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1933cef8759bSmrg } 1934cef8759bSmrg }, 1935cef8759bSmrg { NULL, false, false, {isa_nobit}} 1936cef8759bSmrg }; 1937cef8759bSmrg 1938cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6kz[] = { 1939cef8759bSmrg { 1940cef8759bSmrg "fp", false, false, 1941cef8759bSmrg { 1942cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1943cef8759bSmrg } 1944cef8759bSmrg }, 1945cef8759bSmrg { 1946cef8759bSmrg "nofp", true, false, 1947cef8759bSmrg { 1948cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1949cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1950cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1951cef8759bSmrg } 1952cef8759bSmrg }, 1953cef8759bSmrg { 1954cef8759bSmrg "vfpv2", false, true, 1955cef8759bSmrg { 1956cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1957cef8759bSmrg } 1958cef8759bSmrg }, 1959cef8759bSmrg { NULL, false, false, {isa_nobit}} 1960cef8759bSmrg }; 1961cef8759bSmrg 1962cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6zk[] = { 1963cef8759bSmrg { 1964cef8759bSmrg "fp", false, false, 1965cef8759bSmrg { 1966cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1967cef8759bSmrg } 1968cef8759bSmrg }, 1969cef8759bSmrg { 1970cef8759bSmrg "nofp", true, false, 1971cef8759bSmrg { 1972cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1973cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1974cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1975cef8759bSmrg } 1976cef8759bSmrg }, 1977cef8759bSmrg { 1978cef8759bSmrg "vfpv2", false, true, 1979cef8759bSmrg { 1980cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1981cef8759bSmrg } 1982cef8759bSmrg }, 1983cef8759bSmrg { NULL, false, false, {isa_nobit}} 1984cef8759bSmrg }; 1985cef8759bSmrg 1986cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6t2[] = { 1987cef8759bSmrg { 1988cef8759bSmrg "fp", false, false, 1989cef8759bSmrg { 1990cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1991cef8759bSmrg } 1992cef8759bSmrg }, 1993cef8759bSmrg { 1994cef8759bSmrg "nofp", true, false, 1995cef8759bSmrg { 1996cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1997cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1998cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1999cef8759bSmrg } 2000cef8759bSmrg }, 2001cef8759bSmrg { 2002cef8759bSmrg "vfpv2", false, true, 2003cef8759bSmrg { 2004cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2005cef8759bSmrg } 2006cef8759bSmrg }, 2007cef8759bSmrg { NULL, false, false, {isa_nobit}} 2008cef8759bSmrg }; 2009cef8759bSmrg 2010cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7[] = { 2011cef8759bSmrg { 2012cef8759bSmrg "fp", false, false, 2013cef8759bSmrg { 2014cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2015cef8759bSmrg } 2016cef8759bSmrg }, 2017cef8759bSmrg { 2018cef8759bSmrg "nofp", true, false, 2019cef8759bSmrg { 2020cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2021cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2022cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2023cef8759bSmrg } 2024cef8759bSmrg }, 2025cef8759bSmrg { 2026cef8759bSmrg "vfpv3-d16", false, true, 2027cef8759bSmrg { 2028cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2029cef8759bSmrg } 2030cef8759bSmrg }, 2031cef8759bSmrg { NULL, false, false, {isa_nobit}} 2032cef8759bSmrg }; 2033cef8759bSmrg 2034cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7_a[] = { 2035cef8759bSmrg { 2036cef8759bSmrg "mp", false, false, 2037cef8759bSmrg { 2038cef8759bSmrg isa_bit_mp, isa_nobit 2039cef8759bSmrg } 2040cef8759bSmrg }, 2041cef8759bSmrg { 2042cef8759bSmrg "sec", false, false, 2043cef8759bSmrg { 2044cef8759bSmrg isa_bit_sec, isa_nobit 2045cef8759bSmrg } 2046cef8759bSmrg }, 2047cef8759bSmrg { 2048cef8759bSmrg "fp", false, false, 2049cef8759bSmrg { 2050cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2051cef8759bSmrg } 2052cef8759bSmrg }, 2053cef8759bSmrg { 2054cef8759bSmrg "vfpv3", false, false, 2055cef8759bSmrg { 2056cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2057cef8759bSmrg isa_nobit 2058cef8759bSmrg } 2059cef8759bSmrg }, 2060cef8759bSmrg { 2061cef8759bSmrg "vfpv3-d16-fp16", false, false, 2062cef8759bSmrg { 2063cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2064cef8759bSmrg isa_nobit 2065cef8759bSmrg } 2066cef8759bSmrg }, 2067cef8759bSmrg { 2068cef8759bSmrg "vfpv3-fp16", false, false, 2069cef8759bSmrg { 2070cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2071cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2072cef8759bSmrg } 2073cef8759bSmrg }, 2074cef8759bSmrg { 2075cef8759bSmrg "vfpv4-d16", false, false, 2076cef8759bSmrg { 2077cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2078cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2079cef8759bSmrg } 2080cef8759bSmrg }, 2081cef8759bSmrg { 2082cef8759bSmrg "vfpv4", false, false, 2083cef8759bSmrg { 2084cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2085cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2086cef8759bSmrg } 2087cef8759bSmrg }, 2088cef8759bSmrg { 2089cef8759bSmrg "simd", false, false, 2090cef8759bSmrg { 2091cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2092cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2093cef8759bSmrg } 2094cef8759bSmrg }, 2095cef8759bSmrg { 2096cef8759bSmrg "neon-fp16", false, false, 2097cef8759bSmrg { 2098cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2099cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2100cef8759bSmrg } 2101cef8759bSmrg }, 2102cef8759bSmrg { 2103cef8759bSmrg "neon-vfpv4", false, false, 2104cef8759bSmrg { 2105cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2106cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2107cef8759bSmrg } 2108cef8759bSmrg }, 2109cef8759bSmrg { 2110cef8759bSmrg "nosimd", true, false, 2111cef8759bSmrg { 2112cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2113cef8759bSmrg isa_bit_crypto, isa_nobit 2114cef8759bSmrg } 2115cef8759bSmrg }, 2116cef8759bSmrg { 2117cef8759bSmrg "nofp", true, false, 2118cef8759bSmrg { 2119cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2120cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2121cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2122cef8759bSmrg } 2123cef8759bSmrg }, 2124cef8759bSmrg { 2125cef8759bSmrg "vfpv3-d16", false, true, 2126cef8759bSmrg { 2127cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2128cef8759bSmrg } 2129cef8759bSmrg }, 2130cef8759bSmrg { 2131cef8759bSmrg "neon", false, true, 2132cef8759bSmrg { 2133cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2134cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2135cef8759bSmrg } 2136cef8759bSmrg }, 2137cef8759bSmrg { 2138cef8759bSmrg "neon-vfpv3", false, true, 2139cef8759bSmrg { 2140cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2141cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2142cef8759bSmrg } 2143cef8759bSmrg }, 2144cef8759bSmrg { NULL, false, false, {isa_nobit}} 2145cef8759bSmrg }; 2146cef8759bSmrg 2147cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7ve[] = { 2148cef8759bSmrg { 2149cef8759bSmrg "vfpv3-d16", false, false, 2150cef8759bSmrg { 2151cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2152cef8759bSmrg } 2153cef8759bSmrg }, 2154cef8759bSmrg { 2155cef8759bSmrg "vfpv3", false, false, 2156cef8759bSmrg { 2157cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2158cef8759bSmrg isa_nobit 2159cef8759bSmrg } 2160cef8759bSmrg }, 2161cef8759bSmrg { 2162cef8759bSmrg "vfpv3-d16-fp16", false, false, 2163cef8759bSmrg { 2164cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2165cef8759bSmrg isa_nobit 2166cef8759bSmrg } 2167cef8759bSmrg }, 2168cef8759bSmrg { 2169cef8759bSmrg "vfpv3-fp16", false, false, 2170cef8759bSmrg { 2171cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2172cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2173cef8759bSmrg } 2174cef8759bSmrg }, 2175cef8759bSmrg { 2176cef8759bSmrg "fp", false, false, 2177cef8759bSmrg { 2178cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2179cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2180cef8759bSmrg } 2181cef8759bSmrg }, 2182cef8759bSmrg { 2183cef8759bSmrg "vfpv4", false, false, 2184cef8759bSmrg { 2185cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2186cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2187cef8759bSmrg } 2188cef8759bSmrg }, 2189cef8759bSmrg { 2190cef8759bSmrg "neon", false, false, 2191cef8759bSmrg { 2192cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2193cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2194cef8759bSmrg } 2195cef8759bSmrg }, 2196cef8759bSmrg { 2197cef8759bSmrg "neon-fp16", false, false, 2198cef8759bSmrg { 2199cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2200cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2201cef8759bSmrg } 2202cef8759bSmrg }, 2203cef8759bSmrg { 2204cef8759bSmrg "simd", false, false, 2205cef8759bSmrg { 2206cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2207cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2208cef8759bSmrg } 2209cef8759bSmrg }, 2210cef8759bSmrg { 2211cef8759bSmrg "nosimd", true, false, 2212cef8759bSmrg { 2213cef8759bSmrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2214cef8759bSmrg isa_bit_crypto, isa_nobit 2215cef8759bSmrg } 2216cef8759bSmrg }, 2217cef8759bSmrg { 2218cef8759bSmrg "nofp", true, false, 2219cef8759bSmrg { 2220cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2221cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2222cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2223cef8759bSmrg } 2224cef8759bSmrg }, 2225cef8759bSmrg { 2226cef8759bSmrg "vfpv4-d16", false, true, 2227cef8759bSmrg { 2228cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2229cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2230cef8759bSmrg } 2231cef8759bSmrg }, 2232cef8759bSmrg { 2233cef8759bSmrg "neon-vfpv3", false, true, 2234cef8759bSmrg { 2235cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2236cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2237cef8759bSmrg } 2238cef8759bSmrg }, 2239cef8759bSmrg { 2240cef8759bSmrg "neon-vfpv4", false, true, 2241cef8759bSmrg { 2242cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2243cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2244cef8759bSmrg } 2245cef8759bSmrg }, 2246cef8759bSmrg { NULL, false, false, {isa_nobit}} 2247cef8759bSmrg }; 2248cef8759bSmrg 2249cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7_r[] = { 2250cef8759bSmrg { 2251cef8759bSmrg "fp.sp", false, false, 2252cef8759bSmrg { 2253cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2254cef8759bSmrg } 2255cef8759bSmrg }, 2256cef8759bSmrg { 2257cef8759bSmrg "fp", false, false, 2258cef8759bSmrg { 2259cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2260cef8759bSmrg } 2261cef8759bSmrg }, 2262cef8759bSmrg { 2263cef8759bSmrg "vfpv3xd-fp16", false, false, 2264cef8759bSmrg { 2265cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 2266cef8759bSmrg } 2267cef8759bSmrg }, 2268cef8759bSmrg { 2269cef8759bSmrg "vfpv3-d16-fp16", false, false, 2270cef8759bSmrg { 2271cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2272cef8759bSmrg isa_nobit 2273cef8759bSmrg } 2274cef8759bSmrg }, 2275cef8759bSmrg { 2276cef8759bSmrg "idiv", false, false, 2277cef8759bSmrg { 2278cef8759bSmrg isa_bit_adiv, isa_nobit 2279cef8759bSmrg } 2280cef8759bSmrg }, 2281cef8759bSmrg { 2282cef8759bSmrg "nofp", true, false, 2283cef8759bSmrg { 2284cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2285cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2286cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2287cef8759bSmrg } 2288cef8759bSmrg }, 2289cef8759bSmrg { 2290cef8759bSmrg "noidiv", true, false, 2291cef8759bSmrg { 2292cef8759bSmrg isa_bit_adiv, isa_nobit 2293cef8759bSmrg } 2294cef8759bSmrg }, 2295cef8759bSmrg { 2296cef8759bSmrg "vfpv3xd", false, true, 2297cef8759bSmrg { 2298cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2299cef8759bSmrg } 2300cef8759bSmrg }, 2301cef8759bSmrg { 2302cef8759bSmrg "vfpv3-d16", false, true, 2303cef8759bSmrg { 2304cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2305cef8759bSmrg } 2306cef8759bSmrg }, 2307cef8759bSmrg { NULL, false, false, {isa_nobit}} 2308cef8759bSmrg }; 2309cef8759bSmrg 2310cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { 2311cef8759bSmrg { 2312cef8759bSmrg "fp", false, false, 2313cef8759bSmrg { 2314cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2315cef8759bSmrg isa_nobit 2316cef8759bSmrg } 2317cef8759bSmrg }, 2318cef8759bSmrg { 2319cef8759bSmrg "fpv5", false, false, 2320cef8759bSmrg { 2321cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2322cef8759bSmrg isa_bit_fp16conv, isa_nobit 2323cef8759bSmrg } 2324cef8759bSmrg }, 2325cef8759bSmrg { 2326cef8759bSmrg "fp.dp", false, false, 2327cef8759bSmrg { 2328cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2329cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2330cef8759bSmrg } 2331cef8759bSmrg }, 2332cef8759bSmrg { 2333cef8759bSmrg "nofp", true, false, 2334cef8759bSmrg { 2335cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2336cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2337cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2338cef8759bSmrg } 2339cef8759bSmrg }, 2340cef8759bSmrg { 2341cef8759bSmrg "vfpv4-sp-d16", false, true, 2342cef8759bSmrg { 2343cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2344cef8759bSmrg isa_nobit 2345cef8759bSmrg } 2346cef8759bSmrg }, 2347cef8759bSmrg { 2348cef8759bSmrg "fpv5-d16", false, true, 2349cef8759bSmrg { 2350cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2351cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2352cef8759bSmrg } 2353cef8759bSmrg }, 2354cef8759bSmrg { NULL, false, false, {isa_nobit}} 2355cef8759bSmrg }; 2356cef8759bSmrg 2357cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_a[] = { 2358cef8759bSmrg { 2359cef8759bSmrg "crc", false, false, 2360cef8759bSmrg { 2361cef8759bSmrg isa_bit_crc32, isa_nobit 2362cef8759bSmrg } 2363cef8759bSmrg }, 2364cef8759bSmrg { 2365cef8759bSmrg "simd", false, false, 2366cef8759bSmrg { 2367cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2368cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2369cef8759bSmrg isa_nobit 2370cef8759bSmrg } 2371cef8759bSmrg }, 2372cef8759bSmrg { 2373cef8759bSmrg "crypto", false, false, 2374cef8759bSmrg { 2375cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2376cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2377cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2378cef8759bSmrg } 2379cef8759bSmrg }, 2380cef8759bSmrg { 2381cef8759bSmrg "nocrypto", true, false, 2382cef8759bSmrg { 2383cef8759bSmrg isa_bit_crypto, isa_nobit 2384cef8759bSmrg } 2385cef8759bSmrg }, 2386cef8759bSmrg { 2387cef8759bSmrg "nofp", true, false, 2388cef8759bSmrg { 2389cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2390cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2391cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2392cef8759bSmrg } 2393cef8759bSmrg }, 2394*627f7eb2Smrg { 2395*627f7eb2Smrg "sb", false, false, 2396*627f7eb2Smrg { 2397*627f7eb2Smrg isa_bit_sb, isa_nobit 2398*627f7eb2Smrg } 2399*627f7eb2Smrg }, 2400*627f7eb2Smrg { 2401*627f7eb2Smrg "predres", false, false, 2402*627f7eb2Smrg { 2403*627f7eb2Smrg isa_bit_predres, isa_nobit 2404*627f7eb2Smrg } 2405*627f7eb2Smrg }, 2406cef8759bSmrg { NULL, false, false, {isa_nobit}} 2407cef8759bSmrg }; 2408cef8759bSmrg 2409cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { 2410cef8759bSmrg { 2411cef8759bSmrg "simd", false, false, 2412cef8759bSmrg { 2413cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2414cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2415cef8759bSmrg isa_nobit 2416cef8759bSmrg } 2417cef8759bSmrg }, 2418cef8759bSmrg { 2419cef8759bSmrg "crypto", false, false, 2420cef8759bSmrg { 2421cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2422cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2423cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2424cef8759bSmrg } 2425cef8759bSmrg }, 2426cef8759bSmrg { 2427cef8759bSmrg "nocrypto", true, false, 2428cef8759bSmrg { 2429cef8759bSmrg isa_bit_crypto, isa_nobit 2430cef8759bSmrg } 2431cef8759bSmrg }, 2432cef8759bSmrg { 2433cef8759bSmrg "nofp", true, false, 2434cef8759bSmrg { 2435cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2436cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2437cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2438cef8759bSmrg } 2439cef8759bSmrg }, 2440*627f7eb2Smrg { 2441*627f7eb2Smrg "sb", false, false, 2442*627f7eb2Smrg { 2443*627f7eb2Smrg isa_bit_sb, isa_nobit 2444*627f7eb2Smrg } 2445*627f7eb2Smrg }, 2446*627f7eb2Smrg { 2447*627f7eb2Smrg "predres", false, false, 2448*627f7eb2Smrg { 2449*627f7eb2Smrg isa_bit_predres, isa_nobit 2450*627f7eb2Smrg } 2451*627f7eb2Smrg }, 2452cef8759bSmrg { NULL, false, false, {isa_nobit}} 2453cef8759bSmrg }; 2454cef8759bSmrg 2455cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { 2456cef8759bSmrg { 2457cef8759bSmrg "simd", false, false, 2458cef8759bSmrg { 2459cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2460cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2461cef8759bSmrg isa_nobit 2462cef8759bSmrg } 2463cef8759bSmrg }, 2464cef8759bSmrg { 2465cef8759bSmrg "fp16", false, false, 2466cef8759bSmrg { 2467cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2468cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2469cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2470cef8759bSmrg } 2471cef8759bSmrg }, 2472cef8759bSmrg { 2473cef8759bSmrg "fp16fml", false, false, 2474cef8759bSmrg { 2475cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2476cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2477cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2478cef8759bSmrg } 2479cef8759bSmrg }, 2480cef8759bSmrg { 2481cef8759bSmrg "crypto", false, false, 2482cef8759bSmrg { 2483cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2484cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2485cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2486cef8759bSmrg } 2487cef8759bSmrg }, 2488cef8759bSmrg { 2489cef8759bSmrg "nocrypto", true, false, 2490cef8759bSmrg { 2491cef8759bSmrg isa_bit_crypto, isa_nobit 2492cef8759bSmrg } 2493cef8759bSmrg }, 2494cef8759bSmrg { 2495cef8759bSmrg "nofp", true, false, 2496cef8759bSmrg { 2497cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2498cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2499cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2500cef8759bSmrg } 2501cef8759bSmrg }, 2502cef8759bSmrg { 2503cef8759bSmrg "dotprod", false, false, 2504cef8759bSmrg { 2505cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2506cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2507cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2508cef8759bSmrg } 2509cef8759bSmrg }, 2510*627f7eb2Smrg { 2511*627f7eb2Smrg "sb", false, false, 2512*627f7eb2Smrg { 2513*627f7eb2Smrg isa_bit_sb, isa_nobit 2514*627f7eb2Smrg } 2515*627f7eb2Smrg }, 2516*627f7eb2Smrg { 2517*627f7eb2Smrg "predres", false, false, 2518*627f7eb2Smrg { 2519*627f7eb2Smrg isa_bit_predres, isa_nobit 2520*627f7eb2Smrg } 2521*627f7eb2Smrg }, 2522cef8759bSmrg { NULL, false, false, {isa_nobit}} 2523cef8759bSmrg }; 2524cef8759bSmrg 2525cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = { 2526cef8759bSmrg { 2527cef8759bSmrg "simd", false, false, 2528cef8759bSmrg { 2529cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2530cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2531cef8759bSmrg isa_nobit 2532cef8759bSmrg } 2533cef8759bSmrg }, 2534cef8759bSmrg { 2535cef8759bSmrg "fp16", false, false, 2536cef8759bSmrg { 2537cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2538cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2539cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2540cef8759bSmrg } 2541cef8759bSmrg }, 2542cef8759bSmrg { 2543cef8759bSmrg "fp16fml", false, false, 2544cef8759bSmrg { 2545cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2546cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2547cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2548cef8759bSmrg } 2549cef8759bSmrg }, 2550cef8759bSmrg { 2551cef8759bSmrg "crypto", false, false, 2552cef8759bSmrg { 2553cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2554cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2555cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2556cef8759bSmrg } 2557cef8759bSmrg }, 2558cef8759bSmrg { 2559cef8759bSmrg "nocrypto", true, false, 2560cef8759bSmrg { 2561cef8759bSmrg isa_bit_crypto, isa_nobit 2562cef8759bSmrg } 2563cef8759bSmrg }, 2564cef8759bSmrg { 2565cef8759bSmrg "nofp", true, false, 2566cef8759bSmrg { 2567cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2568cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2569cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2570cef8759bSmrg } 2571cef8759bSmrg }, 2572cef8759bSmrg { 2573cef8759bSmrg "dotprod", false, false, 2574cef8759bSmrg { 2575cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2576cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2577cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2578cef8759bSmrg } 2579cef8759bSmrg }, 2580*627f7eb2Smrg { 2581*627f7eb2Smrg "sb", false, false, 2582*627f7eb2Smrg { 2583*627f7eb2Smrg isa_bit_sb, isa_nobit 2584*627f7eb2Smrg } 2585*627f7eb2Smrg }, 2586*627f7eb2Smrg { 2587*627f7eb2Smrg "predres", false, false, 2588*627f7eb2Smrg { 2589*627f7eb2Smrg isa_bit_predres, isa_nobit 2590*627f7eb2Smrg } 2591*627f7eb2Smrg }, 2592cef8759bSmrg { NULL, false, false, {isa_nobit}} 2593cef8759bSmrg }; 2594cef8759bSmrg 2595cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = { 2596cef8759bSmrg { 2597cef8759bSmrg "simd", false, false, 2598cef8759bSmrg { 2599cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2600cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2601cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2602cef8759bSmrg } 2603cef8759bSmrg }, 2604cef8759bSmrg { 2605cef8759bSmrg "fp16", false, false, 2606cef8759bSmrg { 2607cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2608cef8759bSmrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2609cef8759bSmrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2610cef8759bSmrg } 2611cef8759bSmrg }, 2612cef8759bSmrg { 2613cef8759bSmrg "crypto", false, false, 2614cef8759bSmrg { 2615cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2616cef8759bSmrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2617cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2618cef8759bSmrg } 2619cef8759bSmrg }, 2620cef8759bSmrg { 2621cef8759bSmrg "nocrypto", true, false, 2622cef8759bSmrg { 2623cef8759bSmrg isa_bit_crypto, isa_nobit 2624cef8759bSmrg } 2625cef8759bSmrg }, 2626cef8759bSmrg { 2627cef8759bSmrg "nofp", true, false, 2628cef8759bSmrg { 2629cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2630cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2631cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2632cef8759bSmrg } 2633cef8759bSmrg }, 2634*627f7eb2Smrg { 2635*627f7eb2Smrg "sb", false, false, 2636*627f7eb2Smrg { 2637*627f7eb2Smrg isa_bit_sb, isa_nobit 2638*627f7eb2Smrg } 2639*627f7eb2Smrg }, 2640*627f7eb2Smrg { 2641*627f7eb2Smrg "predres", false, false, 2642*627f7eb2Smrg { 2643*627f7eb2Smrg isa_bit_predres, isa_nobit 2644*627f7eb2Smrg } 2645*627f7eb2Smrg }, 2646*627f7eb2Smrg { NULL, false, false, {isa_nobit}} 2647*627f7eb2Smrg }; 2648*627f7eb2Smrg 2649*627f7eb2Smrg static const struct cpu_arch_extension arch_opttab_armv8_5_a[] = { 2650*627f7eb2Smrg { 2651*627f7eb2Smrg "simd", false, false, 2652*627f7eb2Smrg { 2653*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2654*627f7eb2Smrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2655*627f7eb2Smrg isa_bit_fp_dbl, isa_nobit 2656*627f7eb2Smrg } 2657*627f7eb2Smrg }, 2658*627f7eb2Smrg { 2659*627f7eb2Smrg "fp16", false, false, 2660*627f7eb2Smrg { 2661*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2662*627f7eb2Smrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2663*627f7eb2Smrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2664*627f7eb2Smrg } 2665*627f7eb2Smrg }, 2666*627f7eb2Smrg { 2667*627f7eb2Smrg "crypto", false, false, 2668*627f7eb2Smrg { 2669*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2670*627f7eb2Smrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2671*627f7eb2Smrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2672*627f7eb2Smrg } 2673*627f7eb2Smrg }, 2674*627f7eb2Smrg { 2675*627f7eb2Smrg "nocrypto", true, false, 2676*627f7eb2Smrg { 2677*627f7eb2Smrg isa_bit_crypto, isa_nobit 2678*627f7eb2Smrg } 2679*627f7eb2Smrg }, 2680*627f7eb2Smrg { 2681*627f7eb2Smrg "nofp", true, false, 2682*627f7eb2Smrg { 2683*627f7eb2Smrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2684*627f7eb2Smrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2685*627f7eb2Smrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2686*627f7eb2Smrg } 2687*627f7eb2Smrg }, 2688cef8759bSmrg { NULL, false, false, {isa_nobit}} 2689cef8759bSmrg }; 2690cef8759bSmrg 2691cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { 2692cef8759bSmrg { 2693cef8759bSmrg "dsp", false, false, 2694cef8759bSmrg { 2695cef8759bSmrg isa_bit_armv7em, isa_nobit 2696cef8759bSmrg } 2697cef8759bSmrg }, 2698cef8759bSmrg { 2699cef8759bSmrg "fp", false, false, 2700cef8759bSmrg { 2701cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2702cef8759bSmrg isa_bit_fp16conv, isa_nobit 2703cef8759bSmrg } 2704cef8759bSmrg }, 2705cef8759bSmrg { 2706cef8759bSmrg "fp.dp", false, false, 2707cef8759bSmrg { 2708cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2709cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2710cef8759bSmrg } 2711cef8759bSmrg }, 2712cef8759bSmrg { 2713cef8759bSmrg "nofp", true, false, 2714cef8759bSmrg { 2715cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2716cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2717cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2718cef8759bSmrg } 2719cef8759bSmrg }, 2720cef8759bSmrg { 2721cef8759bSmrg "nodsp", true, false, 2722cef8759bSmrg { 2723cef8759bSmrg isa_bit_armv7em, isa_nobit 2724cef8759bSmrg } 2725cef8759bSmrg }, 2726cef8759bSmrg { NULL, false, false, {isa_nobit}} 2727cef8759bSmrg }; 2728cef8759bSmrg 2729cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_r[] = { 2730cef8759bSmrg { 2731cef8759bSmrg "crc", false, false, 2732cef8759bSmrg { 2733cef8759bSmrg isa_bit_crc32, isa_nobit 2734cef8759bSmrg } 2735cef8759bSmrg }, 2736cef8759bSmrg { 2737cef8759bSmrg "fp.sp", false, false, 2738cef8759bSmrg { 2739cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2740cef8759bSmrg isa_bit_fp16conv, isa_nobit 2741cef8759bSmrg } 2742cef8759bSmrg }, 2743cef8759bSmrg { 2744cef8759bSmrg "simd", false, false, 2745cef8759bSmrg { 2746cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2747cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2748cef8759bSmrg isa_nobit 2749cef8759bSmrg } 2750cef8759bSmrg }, 2751cef8759bSmrg { 2752cef8759bSmrg "crypto", false, false, 2753cef8759bSmrg { 2754cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2755cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2756cef8759bSmrg isa_bit_fp_dbl, isa_nobit 2757cef8759bSmrg } 2758cef8759bSmrg }, 2759cef8759bSmrg { 2760cef8759bSmrg "nocrypto", true, false, 2761cef8759bSmrg { 2762cef8759bSmrg isa_bit_crypto, isa_nobit 2763cef8759bSmrg } 2764cef8759bSmrg }, 2765cef8759bSmrg { 2766cef8759bSmrg "nofp", true, false, 2767cef8759bSmrg { 2768cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2769cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2770cef8759bSmrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2771cef8759bSmrg } 2772cef8759bSmrg }, 2773cef8759bSmrg { NULL, false, false, {isa_nobit}} 2774cef8759bSmrg }; 2775cef8759bSmrg 2776cef8759bSmrg const arch_option all_architectures[] = 2777cef8759bSmrg { 2778cef8759bSmrg { 2779cef8759bSmrg "armv4", 2780cef8759bSmrg NULL, 2781cef8759bSmrg { 2782*627f7eb2Smrg isa_bit_armv4, isa_bit_notm, isa_nobit 2783cef8759bSmrg }, 2784cef8759bSmrg "4", BASE_ARCH_4, 2785cef8759bSmrg 0, 2786cef8759bSmrg TARGET_CPU_arm7tdmi, 2787cef8759bSmrg }, 2788cef8759bSmrg { 2789cef8759bSmrg "armv4t", 2790cef8759bSmrg NULL, 2791cef8759bSmrg { 2792*627f7eb2Smrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 2793cef8759bSmrg }, 2794cef8759bSmrg "4T", BASE_ARCH_4T, 2795cef8759bSmrg 0, 2796cef8759bSmrg TARGET_CPU_arm7tdmi, 2797cef8759bSmrg }, 2798cef8759bSmrg { 2799cef8759bSmrg "armv5t", 2800cef8759bSmrg NULL, 2801cef8759bSmrg { 2802*627f7eb2Smrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 2803*627f7eb2Smrg isa_nobit 2804cef8759bSmrg }, 2805cef8759bSmrg "5T", BASE_ARCH_5T, 2806cef8759bSmrg 0, 2807cef8759bSmrg TARGET_CPU_arm10tdmi, 2808cef8759bSmrg }, 2809cef8759bSmrg { 2810cef8759bSmrg "armv5te", 2811cef8759bSmrg arch_opttab_armv5te, 2812cef8759bSmrg { 2813*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2814*627f7eb2Smrg isa_bit_notm, isa_nobit 2815cef8759bSmrg }, 2816cef8759bSmrg "5TE", BASE_ARCH_5TE, 2817cef8759bSmrg 0, 2818cef8759bSmrg TARGET_CPU_arm1026ejs, 2819cef8759bSmrg }, 2820cef8759bSmrg { 2821cef8759bSmrg "armv5tej", 2822cef8759bSmrg arch_opttab_armv5tej, 2823cef8759bSmrg { 2824*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2825*627f7eb2Smrg isa_bit_notm, isa_nobit 2826cef8759bSmrg }, 2827cef8759bSmrg "5TEJ", BASE_ARCH_5TEJ, 2828cef8759bSmrg 0, 2829cef8759bSmrg TARGET_CPU_arm1026ejs, 2830cef8759bSmrg }, 2831cef8759bSmrg { 2832cef8759bSmrg "armv6", 2833cef8759bSmrg arch_opttab_armv6, 2834cef8759bSmrg { 2835*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2836*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2837cef8759bSmrg }, 2838cef8759bSmrg "6", BASE_ARCH_6, 2839cef8759bSmrg 0, 2840cef8759bSmrg TARGET_CPU_arm1136js, 2841cef8759bSmrg }, 2842cef8759bSmrg { 2843cef8759bSmrg "armv6j", 2844cef8759bSmrg arch_opttab_armv6j, 2845cef8759bSmrg { 2846*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2847*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2848cef8759bSmrg }, 2849cef8759bSmrg "6J", BASE_ARCH_6J, 2850cef8759bSmrg 0, 2851cef8759bSmrg TARGET_CPU_arm1136js, 2852cef8759bSmrg }, 2853cef8759bSmrg { 2854cef8759bSmrg "armv6k", 2855cef8759bSmrg arch_opttab_armv6k, 2856cef8759bSmrg { 2857*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2858*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 2859*627f7eb2Smrg isa_nobit 2860cef8759bSmrg }, 2861cef8759bSmrg "6K", BASE_ARCH_6K, 2862cef8759bSmrg 0, 2863cef8759bSmrg TARGET_CPU_mpcore, 2864cef8759bSmrg }, 2865cef8759bSmrg { 2866cef8759bSmrg "armv6z", 2867cef8759bSmrg arch_opttab_armv6z, 2868cef8759bSmrg { 2869*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2870*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2871cef8759bSmrg }, 2872cef8759bSmrg "6Z", BASE_ARCH_6Z, 2873cef8759bSmrg 0, 2874cef8759bSmrg TARGET_CPU_arm1176jzs, 2875cef8759bSmrg }, 2876cef8759bSmrg { 2877cef8759bSmrg "armv6kz", 2878cef8759bSmrg arch_opttab_armv6kz, 2879cef8759bSmrg { 2880*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2881*627f7eb2Smrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2882*627f7eb2Smrg isa_bit_armv6k, isa_nobit 2883cef8759bSmrg }, 2884cef8759bSmrg "6KZ", BASE_ARCH_6KZ, 2885cef8759bSmrg 0, 2886cef8759bSmrg TARGET_CPU_arm1176jzs, 2887cef8759bSmrg }, 2888cef8759bSmrg { 2889cef8759bSmrg "armv6zk", 2890cef8759bSmrg arch_opttab_armv6zk, 2891cef8759bSmrg { 2892*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2893*627f7eb2Smrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2894*627f7eb2Smrg isa_bit_armv6k, isa_nobit 2895cef8759bSmrg }, 2896cef8759bSmrg "6KZ", BASE_ARCH_6KZ, 2897cef8759bSmrg 0, 2898cef8759bSmrg TARGET_CPU_arm1176jzs, 2899cef8759bSmrg }, 2900cef8759bSmrg { 2901cef8759bSmrg "armv6t2", 2902cef8759bSmrg arch_opttab_armv6t2, 2903cef8759bSmrg { 2904*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2905*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 2906*627f7eb2Smrg isa_nobit 2907cef8759bSmrg }, 2908cef8759bSmrg "6T2", BASE_ARCH_6T2, 2909cef8759bSmrg 0, 2910cef8759bSmrg TARGET_CPU_arm1156t2s, 2911cef8759bSmrg }, 2912cef8759bSmrg { 2913cef8759bSmrg "armv6-m", 2914cef8759bSmrg NULL, 2915cef8759bSmrg { 2916*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2917*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 2918cef8759bSmrg }, 2919cef8759bSmrg "6M", BASE_ARCH_6M, 2920cef8759bSmrg 'M', 2921cef8759bSmrg TARGET_CPU_cortexm1, 2922cef8759bSmrg }, 2923cef8759bSmrg { 2924cef8759bSmrg "armv6s-m", 2925cef8759bSmrg NULL, 2926cef8759bSmrg { 2927*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2928*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_nobit 2929cef8759bSmrg }, 2930cef8759bSmrg "6M", BASE_ARCH_6M, 2931cef8759bSmrg 'M', 2932cef8759bSmrg TARGET_CPU_cortexm1, 2933cef8759bSmrg }, 2934cef8759bSmrg { 2935cef8759bSmrg "armv7", 2936cef8759bSmrg arch_opttab_armv7, 2937cef8759bSmrg { 2938*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2939*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2940*627f7eb2Smrg isa_nobit 2941cef8759bSmrg }, 2942cef8759bSmrg "7", BASE_ARCH_7, 2943cef8759bSmrg 0, 2944cef8759bSmrg TARGET_CPU_cortexa8, 2945cef8759bSmrg }, 2946cef8759bSmrg { 2947cef8759bSmrg "armv7-a", 2948cef8759bSmrg arch_opttab_armv7_a, 2949cef8759bSmrg { 2950*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2951*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2952*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_nobit 2953cef8759bSmrg }, 2954cef8759bSmrg "7A", BASE_ARCH_7A, 2955cef8759bSmrg 'A', 2956cef8759bSmrg TARGET_CPU_cortexa8, 2957cef8759bSmrg }, 2958cef8759bSmrg { 2959cef8759bSmrg "armv7ve", 2960cef8759bSmrg arch_opttab_armv7ve, 2961cef8759bSmrg { 2962*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 2963*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 2964*627f7eb2Smrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 2965*627f7eb2Smrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 2966cef8759bSmrg }, 2967cef8759bSmrg "7A", BASE_ARCH_7A, 2968cef8759bSmrg 'A', 2969cef8759bSmrg TARGET_CPU_cortexa8, 2970cef8759bSmrg }, 2971cef8759bSmrg { 2972cef8759bSmrg "armv7-r", 2973cef8759bSmrg arch_opttab_armv7_r, 2974cef8759bSmrg { 2975*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2976*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2977*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 2978cef8759bSmrg }, 2979cef8759bSmrg "7R", BASE_ARCH_7R, 2980cef8759bSmrg 'R', 2981cef8759bSmrg TARGET_CPU_cortexr4, 2982cef8759bSmrg }, 2983cef8759bSmrg { 2984cef8759bSmrg "armv7-m", 2985cef8759bSmrg NULL, 2986cef8759bSmrg { 2987*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2988*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2989*627f7eb2Smrg isa_bit_thumb2, isa_nobit 2990cef8759bSmrg }, 2991cef8759bSmrg "7M", BASE_ARCH_7M, 2992cef8759bSmrg 'M', 2993cef8759bSmrg TARGET_CPU_cortexm3, 2994cef8759bSmrg }, 2995cef8759bSmrg { 2996cef8759bSmrg "armv7e-m", 2997cef8759bSmrg arch_opttab_armv7e_m, 2998cef8759bSmrg { 2999*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3000*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, 3001*627f7eb2Smrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3002cef8759bSmrg }, 3003cef8759bSmrg "7EM", BASE_ARCH_7EM, 3004cef8759bSmrg 'M', 3005cef8759bSmrg TARGET_CPU_cortexm4, 3006cef8759bSmrg }, 3007cef8759bSmrg { 3008cef8759bSmrg "armv8-a", 3009cef8759bSmrg arch_opttab_armv8_a, 3010cef8759bSmrg { 3011*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3012*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3013*627f7eb2Smrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3014*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3015*627f7eb2Smrg isa_nobit 3016cef8759bSmrg }, 3017cef8759bSmrg "8A", BASE_ARCH_8A, 3018cef8759bSmrg 'A', 3019cef8759bSmrg TARGET_CPU_cortexa53, 3020cef8759bSmrg }, 3021cef8759bSmrg { 3022cef8759bSmrg "armv8.1-a", 3023cef8759bSmrg arch_opttab_armv8_1_a, 3024cef8759bSmrg { 3025*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3026*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3027cef8759bSmrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3028*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3029*627f7eb2Smrg isa_bit_mp, isa_bit_sec, isa_nobit 3030cef8759bSmrg }, 3031cef8759bSmrg "8A", BASE_ARCH_8A, 3032cef8759bSmrg 'A', 3033cef8759bSmrg TARGET_CPU_cortexa53, 3034cef8759bSmrg }, 3035cef8759bSmrg { 3036cef8759bSmrg "armv8.2-a", 3037cef8759bSmrg arch_opttab_armv8_2_a, 3038cef8759bSmrg { 3039*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3040*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3041*627f7eb2Smrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3042*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3043*627f7eb2Smrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 3044cef8759bSmrg }, 3045cef8759bSmrg "8A", BASE_ARCH_8A, 3046cef8759bSmrg 'A', 3047cef8759bSmrg TARGET_CPU_cortexa53, 3048cef8759bSmrg }, 3049cef8759bSmrg { 3050cef8759bSmrg "armv8.3-a", 3051cef8759bSmrg arch_opttab_armv8_3_a, 3052cef8759bSmrg { 3053*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3054*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3055cef8759bSmrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3056*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3057*627f7eb2Smrg isa_bit_armv8_2, isa_bit_armv8_3, isa_bit_mp, isa_bit_sec, 3058*627f7eb2Smrg isa_nobit 3059cef8759bSmrg }, 3060cef8759bSmrg "8A", BASE_ARCH_8A, 3061cef8759bSmrg 'A', 3062cef8759bSmrg TARGET_CPU_cortexa53, 3063cef8759bSmrg }, 3064cef8759bSmrg { 3065cef8759bSmrg "armv8.4-a", 3066cef8759bSmrg arch_opttab_armv8_4_a, 3067cef8759bSmrg { 3068*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3069*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3070*627f7eb2Smrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3071*627f7eb2Smrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3072*627f7eb2Smrg isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp, 3073*627f7eb2Smrg isa_bit_sec, isa_nobit 3074*627f7eb2Smrg }, 3075*627f7eb2Smrg "8A", BASE_ARCH_8A, 3076*627f7eb2Smrg 'A', 3077*627f7eb2Smrg TARGET_CPU_cortexa53, 3078*627f7eb2Smrg }, 3079*627f7eb2Smrg { 3080*627f7eb2Smrg "armv8.5-a", 3081*627f7eb2Smrg arch_opttab_armv8_5_a, 3082*627f7eb2Smrg { 3083*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3084*627f7eb2Smrg isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3085*627f7eb2Smrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 3086*627f7eb2Smrg isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3087cef8759bSmrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 3088*627f7eb2Smrg isa_bit_mp, isa_bit_armv8_5, isa_bit_sec, isa_bit_predres, 3089*627f7eb2Smrg isa_nobit 3090cef8759bSmrg }, 3091cef8759bSmrg "8A", BASE_ARCH_8A, 3092cef8759bSmrg 'A', 3093cef8759bSmrg TARGET_CPU_cortexa53, 3094cef8759bSmrg }, 3095cef8759bSmrg { 3096cef8759bSmrg "armv8-m.base", 3097cef8759bSmrg NULL, 3098cef8759bSmrg { 3099*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3100*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 3101*627f7eb2Smrg isa_bit_tdiv, isa_nobit 3102cef8759bSmrg }, 3103cef8759bSmrg "8M_BASE", BASE_ARCH_8M_BASE, 3104cef8759bSmrg 'M', 3105cef8759bSmrg TARGET_CPU_cortexm23, 3106cef8759bSmrg }, 3107cef8759bSmrg { 3108cef8759bSmrg "armv8-m.main", 3109cef8759bSmrg arch_opttab_armv8_m_main, 3110cef8759bSmrg { 3111*627f7eb2Smrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3112*627f7eb2Smrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_cmse, 3113*627f7eb2Smrg isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3114cef8759bSmrg }, 3115cef8759bSmrg "8M_MAIN", BASE_ARCH_8M_MAIN, 3116cef8759bSmrg 'M', 3117cef8759bSmrg TARGET_CPU_cortexm7, 3118cef8759bSmrg }, 3119cef8759bSmrg { 3120cef8759bSmrg "armv8-r", 3121cef8759bSmrg arch_opttab_armv8_r, 3122cef8759bSmrg { 3123*627f7eb2Smrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3124*627f7eb2Smrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3125*627f7eb2Smrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3126*627f7eb2Smrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3127*627f7eb2Smrg isa_nobit 3128cef8759bSmrg }, 3129cef8759bSmrg "8R", BASE_ARCH_8R, 3130cef8759bSmrg 'R', 3131cef8759bSmrg TARGET_CPU_cortexr52, 3132cef8759bSmrg }, 3133cef8759bSmrg { 3134cef8759bSmrg "iwmmxt", 3135cef8759bSmrg NULL, 3136cef8759bSmrg { 3137*627f7eb2Smrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3138*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 3139cef8759bSmrg }, 3140cef8759bSmrg "5TE", BASE_ARCH_5TE, 3141cef8759bSmrg 0, 3142cef8759bSmrg TARGET_CPU_iwmmxt, 3143cef8759bSmrg }, 3144cef8759bSmrg { 3145cef8759bSmrg "iwmmxt2", 3146cef8759bSmrg NULL, 3147cef8759bSmrg { 3148*627f7eb2Smrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3149*627f7eb2Smrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 3150*627f7eb2Smrg isa_nobit 3151cef8759bSmrg }, 3152cef8759bSmrg "5TE", BASE_ARCH_5TE, 3153cef8759bSmrg 0, 3154cef8759bSmrg TARGET_CPU_iwmmxt2, 3155cef8759bSmrg }, 3156cef8759bSmrg {{NULL, NULL, {isa_nobit}}, 3157cef8759bSmrg NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none} 3158cef8759bSmrg }; 3159cef8759bSmrg 3160cef8759bSmrg const arm_fpu_desc all_fpus[] = 3161cef8759bSmrg { 3162cef8759bSmrg { 3163cef8759bSmrg "vfp", 3164cef8759bSmrg { 3165cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3166cef8759bSmrg } 3167cef8759bSmrg }, 3168cef8759bSmrg { 3169cef8759bSmrg "vfpv2", 3170cef8759bSmrg { 3171cef8759bSmrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3172cef8759bSmrg } 3173cef8759bSmrg }, 3174cef8759bSmrg { 3175cef8759bSmrg "vfpv3", 3176cef8759bSmrg { 3177cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3178cef8759bSmrg isa_nobit 3179cef8759bSmrg } 3180cef8759bSmrg }, 3181cef8759bSmrg { 3182cef8759bSmrg "vfpv3-fp16", 3183cef8759bSmrg { 3184cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 3185cef8759bSmrg isa_bit_fp_dbl, isa_nobit 3186cef8759bSmrg } 3187cef8759bSmrg }, 3188cef8759bSmrg { 3189cef8759bSmrg "vfpv3-d16", 3190cef8759bSmrg { 3191cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 3192cef8759bSmrg } 3193cef8759bSmrg }, 3194cef8759bSmrg { 3195cef8759bSmrg "vfpv3-d16-fp16", 3196cef8759bSmrg { 3197cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 3198cef8759bSmrg isa_nobit 3199cef8759bSmrg } 3200cef8759bSmrg }, 3201cef8759bSmrg { 3202cef8759bSmrg "vfpv3xd", 3203cef8759bSmrg { 3204cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 3205cef8759bSmrg } 3206cef8759bSmrg }, 3207cef8759bSmrg { 3208cef8759bSmrg "vfpv3xd-fp16", 3209cef8759bSmrg { 3210cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 3211cef8759bSmrg } 3212cef8759bSmrg }, 3213cef8759bSmrg { 3214cef8759bSmrg "neon", 3215cef8759bSmrg { 3216cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3217cef8759bSmrg isa_bit_fp_dbl, isa_nobit 3218cef8759bSmrg } 3219cef8759bSmrg }, 3220cef8759bSmrg { 3221cef8759bSmrg "neon-vfpv3", 3222cef8759bSmrg { 3223cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3224cef8759bSmrg isa_bit_fp_dbl, isa_nobit 3225cef8759bSmrg } 3226cef8759bSmrg }, 3227cef8759bSmrg { 3228cef8759bSmrg "neon-fp16", 3229cef8759bSmrg { 3230cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3231cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3232cef8759bSmrg } 3233cef8759bSmrg }, 3234cef8759bSmrg { 3235cef8759bSmrg "vfpv4", 3236cef8759bSmrg { 3237cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 3238cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3239cef8759bSmrg } 3240cef8759bSmrg }, 3241cef8759bSmrg { 3242cef8759bSmrg "neon-vfpv4", 3243cef8759bSmrg { 3244cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3245cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3246cef8759bSmrg } 3247cef8759bSmrg }, 3248cef8759bSmrg { 3249cef8759bSmrg "vfpv4-d16", 3250cef8759bSmrg { 3251cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3252cef8759bSmrg isa_bit_fp_dbl, isa_nobit 3253cef8759bSmrg } 3254cef8759bSmrg }, 3255cef8759bSmrg { 3256cef8759bSmrg "fpv4-sp-d16", 3257cef8759bSmrg { 3258cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3259cef8759bSmrg isa_nobit 3260cef8759bSmrg } 3261cef8759bSmrg }, 3262cef8759bSmrg { 3263cef8759bSmrg "fpv5-sp-d16", 3264cef8759bSmrg { 3265cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3266cef8759bSmrg isa_bit_fp16conv, isa_nobit 3267cef8759bSmrg } 3268cef8759bSmrg }, 3269cef8759bSmrg { 3270cef8759bSmrg "fpv5-d16", 3271cef8759bSmrg { 3272cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3273cef8759bSmrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3274cef8759bSmrg } 3275cef8759bSmrg }, 3276cef8759bSmrg { 3277cef8759bSmrg "fp-armv8", 3278cef8759bSmrg { 3279cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3280cef8759bSmrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3281cef8759bSmrg } 3282cef8759bSmrg }, 3283cef8759bSmrg { 3284cef8759bSmrg "neon-fp-armv8", 3285cef8759bSmrg { 3286cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3287cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 3288cef8759bSmrg isa_nobit 3289cef8759bSmrg } 3290cef8759bSmrg }, 3291cef8759bSmrg { 3292cef8759bSmrg "crypto-neon-fp-armv8", 3293cef8759bSmrg { 3294cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3295cef8759bSmrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 3296cef8759bSmrg isa_bit_fp_dbl, isa_nobit 3297cef8759bSmrg } 3298cef8759bSmrg }, 3299cef8759bSmrg { 3300cef8759bSmrg "vfp3", 3301cef8759bSmrg { 3302cef8759bSmrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3303cef8759bSmrg isa_nobit 3304cef8759bSmrg } 3305cef8759bSmrg }, 3306cef8759bSmrg }; 3307